1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/seq_buf.h> 30 #include <linux/string_helpers.h> 31 32 #include <drm/display/drm_dp_helper.h> 33 #include <drm/display/drm_scdc_helper.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_privacy_screen_consumer.h> 36 #include <drm/intel/step.h> 37 38 #include "icl_dsi.h" 39 #include "intel_alpm.h" 40 #include "intel_audio.h" 41 #include "intel_audio_regs.h" 42 #include "intel_backlight.h" 43 #include "intel_combo_phy.h" 44 #include "intel_combo_phy_regs.h" 45 #include "intel_connector.h" 46 #include "intel_crtc.h" 47 #include "intel_cx0_phy.h" 48 #include "intel_cx0_phy_regs.h" 49 #include "intel_ddi.h" 50 #include "intel_ddi_buf_trans.h" 51 #include "intel_de.h" 52 #include "intel_display_power.h" 53 #include "intel_display_regs.h" 54 #include "intel_display_types.h" 55 #include "intel_display_utils.h" 56 #include "intel_display_wa.h" 57 #include "intel_dkl_phy.h" 58 #include "intel_dkl_phy_regs.h" 59 #include "intel_dp.h" 60 #include "intel_dp_aux.h" 61 #include "intel_dp_link_training.h" 62 #include "intel_dp_mst.h" 63 #include "intel_dp_test.h" 64 #include "intel_dp_tunnel.h" 65 #include "intel_dpio_phy.h" 66 #include "intel_dsi.h" 67 #include "intel_encoder.h" 68 #include "intel_fdi.h" 69 #include "intel_fifo_underrun.h" 70 #include "intel_gmbus.h" 71 #include "intel_hdcp.h" 72 #include "intel_hdmi.h" 73 #include "intel_hotplug.h" 74 #include "intel_hti.h" 75 #include "intel_lspcon.h" 76 #include "intel_lt_phy.h" 77 #include "intel_mg_phy_regs.h" 78 #include "intel_modeset_lock.h" 79 #include "intel_panel.h" 80 #include "intel_pfit.h" 81 #include "intel_pps.h" 82 #include "intel_psr.h" 83 #include "intel_quirks.h" 84 #include "intel_snps_phy.h" 85 #include "intel_tc.h" 86 #include "intel_vdsc.h" 87 #include "intel_vdsc_regs.h" 88 #include "intel_vrr.h" 89 #include "skl_scaler.h" 90 #include "skl_universal_plane.h" 91 92 struct intel_dpll; 93 94 static const u8 index_to_dp_signal_levels[] = { 95 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 96 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 97 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 98 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 99 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 100 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 101 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 102 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 103 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 104 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 105 }; 106 107 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 108 const struct intel_ddi_buf_trans *trans) 109 { 110 int level; 111 112 level = intel_bios_hdmi_level_shift(encoder->devdata); 113 if (level < 0) 114 level = trans->hdmi_default_entry; 115 116 return level; 117 } 118 119 static bool has_buf_trans_select(struct intel_display *display) 120 { 121 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 122 } 123 124 static bool has_iboost(struct intel_display *display) 125 { 126 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 127 } 128 129 /* 130 * Starting with Haswell, DDI port buffers must be programmed with correct 131 * values in advance. This function programs the correct values for 132 * DP/eDP/FDI use cases. 133 */ 134 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 135 const struct intel_crtc_state *crtc_state) 136 { 137 struct intel_display *display = to_intel_display(encoder); 138 u32 iboost_bit = 0; 139 int i, n_entries; 140 enum port port = encoder->port; 141 const struct intel_ddi_buf_trans *trans; 142 143 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 144 if (drm_WARN_ON_ONCE(display->drm, !trans)) 145 return; 146 147 /* If we're boosting the current, set bit 31 of trans1 */ 148 if (has_iboost(display) && 149 intel_bios_dp_boost_level(encoder->devdata)) 150 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 151 152 for (i = 0; i < n_entries; i++) { 153 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 154 trans->entries[i].hsw.trans1 | iboost_bit); 155 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 156 trans->entries[i].hsw.trans2); 157 } 158 } 159 160 /* 161 * Starting with Haswell, DDI port buffers must be programmed with correct 162 * values in advance. This function programs the correct values for 163 * HDMI/DVI use cases. 164 */ 165 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 166 const struct intel_crtc_state *crtc_state) 167 { 168 struct intel_display *display = to_intel_display(encoder); 169 int level = intel_ddi_level(encoder, crtc_state, 0); 170 u32 iboost_bit = 0; 171 int n_entries; 172 enum port port = encoder->port; 173 const struct intel_ddi_buf_trans *trans; 174 175 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 176 if (drm_WARN_ON_ONCE(display->drm, !trans)) 177 return; 178 179 /* If we're boosting the current, set bit 31 of trans1 */ 180 if (has_iboost(display) && 181 intel_bios_hdmi_boost_level(encoder->devdata)) 182 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 183 184 /* Entry 9 is for HDMI: */ 185 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 186 trans->entries[level].hsw.trans1 | iboost_bit); 187 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 188 trans->entries[level].hsw.trans2); 189 } 190 191 static intel_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 192 { 193 if (DISPLAY_VER(display) >= 14) 194 return XELPDP_PORT_BUF_CTL1(display, port); 195 else 196 return DDI_BUF_CTL(port); 197 } 198 199 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 200 { 201 /* 202 * Bspec's platform specific timeouts: 203 * MTL+ : 100 us 204 * BXT : fixed 16 us 205 * HSW-ADL: 8 us 206 * 207 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 208 */ 209 if (display->platform.broxton) { 210 udelay(16); 211 return; 212 } 213 214 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 215 if (intel_de_wait_for_set_ms(display, intel_ddi_buf_status_reg(display, port), 216 DDI_BUF_IS_IDLE, 10)) 217 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 218 port_name(port)); 219 } 220 221 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 222 { 223 struct intel_display *display = to_intel_display(encoder); 224 enum port port = encoder->port; 225 226 /* 227 * Bspec's platform specific timeouts: 228 * MTL+ : 10000 us 229 * DG2 : 1200 us 230 * TGL-ADL combo PHY: 1000 us 231 * TGL-ADL TypeC PHY: 3000 us 232 * HSW-ICL : fixed 518 us 233 */ 234 if (DISPLAY_VER(display) < 10) { 235 usleep_range(518, 1000); 236 return; 237 } 238 239 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 240 if (intel_de_wait_for_clear_ms(display, intel_ddi_buf_status_reg(display, port), 241 DDI_BUF_IS_IDLE, 10)) 242 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 243 port_name(port)); 244 } 245 246 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) 247 { 248 switch (pll->info->id) { 249 case DPLL_ID_WRPLL1: 250 return PORT_CLK_SEL_WRPLL1; 251 case DPLL_ID_WRPLL2: 252 return PORT_CLK_SEL_WRPLL2; 253 case DPLL_ID_SPLL: 254 return PORT_CLK_SEL_SPLL; 255 case DPLL_ID_LCPLL_810: 256 return PORT_CLK_SEL_LCPLL_810; 257 case DPLL_ID_LCPLL_1350: 258 return PORT_CLK_SEL_LCPLL_1350; 259 case DPLL_ID_LCPLL_2700: 260 return PORT_CLK_SEL_LCPLL_2700; 261 default: 262 MISSING_CASE(pll->info->id); 263 return PORT_CLK_SEL_NONE; 264 } 265 } 266 267 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 268 const struct intel_crtc_state *crtc_state) 269 { 270 const struct intel_dpll *pll = crtc_state->intel_dpll; 271 int clock = crtc_state->port_clock; 272 const enum intel_dpll_id id = pll->info->id; 273 274 switch (id) { 275 default: 276 /* 277 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 278 * here, so do warn if this get passed in 279 */ 280 MISSING_CASE(id); 281 return DDI_CLK_SEL_NONE; 282 case DPLL_ID_ICL_TBTPLL: 283 switch (clock) { 284 case 162000: 285 return DDI_CLK_SEL_TBT_162; 286 case 270000: 287 return DDI_CLK_SEL_TBT_270; 288 case 540000: 289 return DDI_CLK_SEL_TBT_540; 290 case 810000: 291 return DDI_CLK_SEL_TBT_810; 292 default: 293 MISSING_CASE(clock); 294 return DDI_CLK_SEL_NONE; 295 } 296 case DPLL_ID_ICL_MGPLL1: 297 case DPLL_ID_ICL_MGPLL2: 298 case DPLL_ID_ICL_MGPLL3: 299 case DPLL_ID_ICL_MGPLL4: 300 case DPLL_ID_TGL_MGPLL5: 301 case DPLL_ID_TGL_MGPLL6: 302 return DDI_CLK_SEL_MG; 303 } 304 } 305 306 static u32 ddi_buf_phy_link_rate(int port_clock) 307 { 308 switch (port_clock) { 309 case 162000: 310 return DDI_BUF_PHY_LINK_RATE(0); 311 case 216000: 312 return DDI_BUF_PHY_LINK_RATE(4); 313 case 243000: 314 return DDI_BUF_PHY_LINK_RATE(5); 315 case 270000: 316 return DDI_BUF_PHY_LINK_RATE(1); 317 case 324000: 318 return DDI_BUF_PHY_LINK_RATE(6); 319 case 432000: 320 return DDI_BUF_PHY_LINK_RATE(7); 321 case 540000: 322 return DDI_BUF_PHY_LINK_RATE(2); 323 case 810000: 324 return DDI_BUF_PHY_LINK_RATE(3); 325 default: 326 MISSING_CASE(port_clock); 327 return DDI_BUF_PHY_LINK_RATE(0); 328 } 329 } 330 331 static int dp_phy_lane_stagger_delay(int port_clock) 332 { 333 /* 334 * Return the number of symbol clocks delay used to stagger the 335 * assertion/desassertion of the port lane enables. The target delay 336 * time is 100 ns or greater, return the number of symbols specific to 337 * the provided port_clock (aka link clock) corresponding to this delay 338 * time, i.e. so that 339 * 340 * number_of_symbols * duration_of_one_symbol >= 100 ns 341 * 342 * The delay must be applied only on TypeC DP outputs, for everything else 343 * the delay must be set to 0. 344 * 345 * Return the number of link symbols per 100 ns: 346 * port_clock (10 kHz) -> bits / 100 us 347 * / symbol_size -> symbols / 100 us 348 * / 1000 -> symbols / 100 ns 349 */ 350 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 351 } 352 353 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 354 const struct intel_crtc_state *crtc_state) 355 { 356 struct intel_display *display = to_intel_display(encoder); 357 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 358 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 359 360 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 361 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 362 DDI_BUF_TRANS_SELECT(0); 363 364 if (dig_port->lane_reversal) 365 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 366 if (dig_port->ddi_a_4_lanes) 367 intel_dp->DP |= DDI_A_4_LANES; 368 369 if (DISPLAY_VER(display) >= 14) { 370 if (intel_dp_is_uhbr(crtc_state)) 371 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 372 else 373 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 374 } 375 376 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 377 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 378 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 379 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 380 } 381 382 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 383 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 384 385 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 386 } 387 } 388 389 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 390 { 391 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 392 393 switch (val) { 394 case DDI_CLK_SEL_NONE: 395 return 0; 396 case DDI_CLK_SEL_TBT_162: 397 return 162000; 398 case DDI_CLK_SEL_TBT_270: 399 return 270000; 400 case DDI_CLK_SEL_TBT_540: 401 return 540000; 402 case DDI_CLK_SEL_TBT_810: 403 return 810000; 404 default: 405 MISSING_CASE(val); 406 return 0; 407 } 408 } 409 410 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 411 { 412 /* CRT dotclock is determined via other means */ 413 if (pipe_config->has_pch_encoder) 414 return; 415 416 pipe_config->hw.adjusted_mode.crtc_clock = 417 intel_crtc_dotclock(pipe_config); 418 } 419 420 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 421 const struct drm_connector_state *conn_state) 422 { 423 struct intel_display *display = to_intel_display(crtc_state); 424 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 425 u32 temp; 426 427 if (!intel_crtc_has_dp_encoder(crtc_state)) 428 return; 429 430 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 431 432 temp = DP_MSA_MISC_SYNC_CLOCK; 433 434 switch (crtc_state->pipe_bpp) { 435 case 18: 436 temp |= DP_MSA_MISC_6_BPC; 437 break; 438 case 24: 439 temp |= DP_MSA_MISC_8_BPC; 440 break; 441 case 30: 442 temp |= DP_MSA_MISC_10_BPC; 443 break; 444 case 36: 445 temp |= DP_MSA_MISC_12_BPC; 446 break; 447 default: 448 MISSING_CASE(crtc_state->pipe_bpp); 449 break; 450 } 451 452 /* nonsense combination */ 453 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 454 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 455 456 if (crtc_state->limited_color_range) 457 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 458 459 /* 460 * As per DP 1.2 spec section 2.3.4.3 while sending 461 * YCBCR 444 signals we should program MSA MISC1/0 fields with 462 * colorspace information. 463 */ 464 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 465 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 466 467 /* 468 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 469 * of Color Encoding Format and Content Color Gamut] while sending 470 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 471 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 472 * Only set the delegation bit when the content needs it and 473 * the sink advertises support. 474 */ 475 if (intel_dp_needs_vsc_colorimetry(crtc_state, conn_state)) 476 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 477 478 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 479 temp); 480 } 481 482 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 483 { 484 if (master_transcoder == TRANSCODER_EDP) 485 return 0; 486 else 487 return master_transcoder + 1; 488 } 489 490 static void 491 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 492 bool enable) 493 { 494 struct intel_display *display = to_intel_display(crtc_state); 495 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 496 u32 val = 0; 497 498 if (!HAS_DP20(display)) 499 return; 500 501 if (enable && intel_dp_is_uhbr(crtc_state)) 502 val = TRANS_DP2_128B132B_CHANNEL_CODING; 503 504 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 505 } 506 507 /* 508 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 509 * 510 * Only intended to be used by intel_ddi_enable_transcoder_func() and 511 * intel_ddi_config_transcoder_func(). 512 */ 513 static u32 514 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 515 const struct intel_crtc_state *crtc_state) 516 { 517 struct intel_display *display = to_intel_display(crtc_state); 518 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 519 enum pipe pipe = crtc->pipe; 520 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 521 enum port port = encoder->port; 522 u32 temp; 523 524 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 525 temp = TRANS_DDI_FUNC_ENABLE; 526 if (DISPLAY_VER(display) >= 12) 527 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 528 else 529 temp |= TRANS_DDI_SELECT_PORT(port); 530 531 switch (crtc_state->pipe_bpp) { 532 default: 533 MISSING_CASE(crtc_state->pipe_bpp); 534 fallthrough; 535 case 18: 536 temp |= TRANS_DDI_BPC_6; 537 break; 538 case 24: 539 temp |= TRANS_DDI_BPC_8; 540 break; 541 case 30: 542 temp |= TRANS_DDI_BPC_10; 543 break; 544 case 36: 545 temp |= TRANS_DDI_BPC_12; 546 break; 547 } 548 549 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 550 temp |= TRANS_DDI_PVSYNC; 551 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 552 temp |= TRANS_DDI_PHSYNC; 553 554 if (cpu_transcoder == TRANSCODER_EDP) { 555 switch (pipe) { 556 default: 557 MISSING_CASE(pipe); 558 fallthrough; 559 case PIPE_A: 560 /* On Haswell, can only use the always-on power well for 561 * eDP when not using the panel fitter, and when not 562 * using motion blur mitigation (which we don't 563 * support). */ 564 if (crtc_state->pch_pfit.force_thru) 565 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 566 else 567 temp |= TRANS_DDI_EDP_INPUT_A_ON; 568 break; 569 case PIPE_B: 570 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 571 break; 572 case PIPE_C: 573 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 574 break; 575 } 576 } 577 578 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 579 if (crtc_state->has_hdmi_sink) 580 temp |= TRANS_DDI_MODE_SELECT_HDMI; 581 else 582 temp |= TRANS_DDI_MODE_SELECT_DVI; 583 584 if (crtc_state->hdmi_scrambling) 585 temp |= TRANS_DDI_HDMI_SCRAMBLING; 586 if (crtc_state->hdmi_high_tmds_clock_ratio) 587 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 588 if (DISPLAY_VER(display) >= 14) 589 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 590 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 591 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 592 temp |= (crtc_state->fdi_lanes - 1) << 1; 593 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 594 intel_dp_is_uhbr(crtc_state)) { 595 if (intel_dp_is_uhbr(crtc_state)) 596 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 597 else 598 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 599 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 600 601 if (DISPLAY_VER(display) >= 12) { 602 enum transcoder master; 603 604 master = crtc_state->mst_master_transcoder; 605 if (drm_WARN_ON(display->drm, 606 master == INVALID_TRANSCODER)) 607 master = TRANSCODER_A; 608 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 609 } 610 } else { 611 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 612 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 613 } 614 615 if (IS_DISPLAY_VER(display, 8, 10) && 616 crtc_state->master_transcoder != INVALID_TRANSCODER) { 617 u8 master_select = 618 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 619 620 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 621 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 622 } 623 624 return temp; 625 } 626 627 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 628 const struct intel_crtc_state *crtc_state) 629 { 630 struct intel_display *display = to_intel_display(crtc_state); 631 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 632 633 if (DISPLAY_VER(display) >= 11) { 634 enum transcoder master_transcoder = crtc_state->master_transcoder; 635 u32 ctl2 = 0; 636 637 if (master_transcoder != INVALID_TRANSCODER) { 638 u8 master_select = 639 bdw_trans_port_sync_master_select(master_transcoder); 640 641 ctl2 |= PORT_SYNC_MODE_ENABLE | 642 PORT_SYNC_MODE_MASTER_SELECT(master_select); 643 } 644 645 intel_de_write(display, 646 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 647 ctl2); 648 } 649 650 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 651 intel_ddi_transcoder_func_reg_val_get(encoder, 652 crtc_state)); 653 } 654 655 /* 656 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 657 * bit for the DDI function and enables the DP2 configuration. Called for all 658 * transcoder types. 659 */ 660 void 661 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 662 const struct intel_crtc_state *crtc_state) 663 { 664 struct intel_display *display = to_intel_display(crtc_state); 665 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 666 u32 ctl; 667 668 intel_ddi_config_transcoder_dp2(crtc_state, true); 669 670 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 671 ctl &= ~TRANS_DDI_FUNC_ENABLE; 672 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 673 ctl); 674 } 675 676 /* 677 * Disable the DDI function and port syncing. 678 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 679 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 680 * transcoders these are done later in intel_ddi_post_disable_dp(). 681 */ 682 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 683 { 684 struct intel_display *display = to_intel_display(crtc_state); 685 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 686 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 687 u32 ctl; 688 689 if (DISPLAY_VER(display) >= 11) 690 intel_de_write(display, 691 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 692 0); 693 694 ctl = intel_de_read(display, 695 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 696 697 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 698 699 ctl &= ~TRANS_DDI_FUNC_ENABLE; 700 701 if (IS_DISPLAY_VER(display, 8, 10)) 702 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 703 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 704 705 if (DISPLAY_VER(display) >= 12) { 706 if (!intel_dp_mst_is_master_trans(crtc_state)) { 707 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 708 TRANS_DDI_MODE_SELECT_MASK); 709 } 710 } else { 711 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 712 } 713 714 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 715 ctl); 716 717 if (intel_dp_mst_is_slave_trans(crtc_state)) 718 intel_ddi_config_transcoder_dp2(crtc_state, false); 719 720 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 721 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 722 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 723 /* Quirk time at 100ms for reliable operation */ 724 msleep(100); 725 } 726 } 727 728 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 729 enum transcoder cpu_transcoder, 730 bool enable, u32 hdcp_mask) 731 { 732 struct intel_display *display = to_intel_display(intel_encoder); 733 struct ref_tracker *wakeref; 734 int ret = 0; 735 736 wakeref = intel_display_power_get_if_enabled(display, 737 intel_encoder->power_domain); 738 if (drm_WARN_ON(display->drm, !wakeref)) 739 return -ENXIO; 740 741 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 742 hdcp_mask, enable ? hdcp_mask : 0); 743 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 744 return ret; 745 } 746 747 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 748 { 749 struct intel_display *display = to_intel_display(intel_connector); 750 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 751 int type = intel_connector->base.connector_type; 752 enum port port = encoder->port; 753 enum transcoder cpu_transcoder; 754 struct ref_tracker *wakeref; 755 enum pipe pipe = 0; 756 u32 ddi_mode; 757 bool ret; 758 759 wakeref = intel_display_power_get_if_enabled(display, 760 encoder->power_domain); 761 if (!wakeref) 762 return false; 763 764 /* Note: This returns false for DP MST primary encoders. */ 765 if (!encoder->get_hw_state(encoder, &pipe)) { 766 ret = false; 767 goto out; 768 } 769 770 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 771 cpu_transcoder = TRANSCODER_EDP; 772 else 773 cpu_transcoder = (enum transcoder) pipe; 774 775 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 776 TRANS_DDI_MODE_SELECT_MASK; 777 778 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 779 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 780 ret = type == DRM_MODE_CONNECTOR_HDMIA; 781 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 782 ret = type == DRM_MODE_CONNECTOR_VGA; 783 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 784 ret = type == DRM_MODE_CONNECTOR_eDP || 785 type == DRM_MODE_CONNECTOR_DisplayPort; 786 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 787 /* 788 * encoder->get_hw_state() should have bailed out on MST. This 789 * must be SST and non-eDP. 790 */ 791 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 792 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 793 /* encoder->get_hw_state() should have bailed out on MST. */ 794 ret = false; 795 } else { 796 ret = false; 797 } 798 799 out: 800 intel_display_power_put(display, encoder->power_domain, wakeref); 801 802 return ret; 803 } 804 805 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 806 u8 *pipe_mask, bool *is_dp_mst) 807 { 808 struct intel_display *display = to_intel_display(encoder); 809 enum port port = encoder->port; 810 struct ref_tracker *wakeref; 811 enum pipe p; 812 u32 tmp; 813 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 814 815 *pipe_mask = 0; 816 *is_dp_mst = false; 817 818 wakeref = intel_display_power_get_if_enabled(display, 819 encoder->power_domain); 820 if (!wakeref) 821 return; 822 823 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 824 if (!(tmp & DDI_BUF_CTL_ENABLE)) 825 goto out; 826 827 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 828 tmp = intel_de_read(display, 829 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 830 831 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 832 default: 833 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 834 fallthrough; 835 case TRANS_DDI_EDP_INPUT_A_ON: 836 case TRANS_DDI_EDP_INPUT_A_ONOFF: 837 *pipe_mask = BIT(PIPE_A); 838 break; 839 case TRANS_DDI_EDP_INPUT_B_ONOFF: 840 *pipe_mask = BIT(PIPE_B); 841 break; 842 case TRANS_DDI_EDP_INPUT_C_ONOFF: 843 *pipe_mask = BIT(PIPE_C); 844 break; 845 } 846 847 goto out; 848 } 849 850 for_each_pipe(display, p) { 851 enum transcoder cpu_transcoder = (enum transcoder)p; 852 u32 port_mask, ddi_select, ddi_mode; 853 struct ref_tracker *trans_wakeref; 854 855 trans_wakeref = intel_display_power_get_if_enabled(display, 856 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 857 if (!trans_wakeref) 858 continue; 859 860 if (DISPLAY_VER(display) >= 12) { 861 port_mask = TGL_TRANS_DDI_PORT_MASK; 862 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 863 } else { 864 port_mask = TRANS_DDI_PORT_MASK; 865 ddi_select = TRANS_DDI_SELECT_PORT(port); 866 } 867 868 tmp = intel_de_read(display, 869 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 870 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 871 trans_wakeref); 872 873 if ((tmp & port_mask) != ddi_select) 874 continue; 875 876 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 877 878 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 879 mst_pipe_mask |= BIT(p); 880 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 881 dp128b132b_pipe_mask |= BIT(p); 882 883 *pipe_mask |= BIT(p); 884 } 885 886 if (!*pipe_mask) 887 drm_dbg_kms(display->drm, 888 "No pipe for [ENCODER:%d:%s] found\n", 889 encoder->base.base.id, encoder->base.name); 890 891 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 892 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 893 894 /* 895 * If we don't have 8b/10b MST, but have more than one 896 * transcoder in 128b/132b mode, we know it must be 128b/132b 897 * MST. 898 * 899 * Otherwise, we fall back to checking the current MST 900 * state. It's not accurate for hardware takeover at probe, but 901 * we don't expect MST to have been enabled at that point, and 902 * can assume it's SST. 903 */ 904 if (hweight8(dp128b132b_pipe_mask) > 1 || 905 intel_dp_mst_active_streams(intel_dp)) 906 mst_pipe_mask = dp128b132b_pipe_mask; 907 } 908 909 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 910 drm_dbg_kms(display->drm, 911 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 912 encoder->base.base.id, encoder->base.name, 913 *pipe_mask); 914 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 915 } 916 917 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 918 drm_dbg_kms(display->drm, 919 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 920 encoder->base.base.id, encoder->base.name, 921 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 922 else 923 *is_dp_mst = mst_pipe_mask; 924 925 out: 926 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 927 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 928 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 929 BXT_PHY_LANE_POWERDOWN_ACK | 930 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 931 drm_err(display->drm, 932 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 933 encoder->base.base.id, encoder->base.name, tmp); 934 } 935 936 intel_display_power_put(display, encoder->power_domain, wakeref); 937 } 938 939 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 940 enum pipe *pipe) 941 { 942 u8 pipe_mask; 943 bool is_mst; 944 945 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 946 947 if (is_mst || !pipe_mask) 948 return false; 949 950 *pipe = ffs(pipe_mask) - 1; 951 952 return true; 953 } 954 955 static enum intel_display_power_domain 956 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 957 const struct intel_crtc_state *crtc_state) 958 { 959 struct intel_display *display = to_intel_display(dig_port); 960 961 /* 962 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 963 * DC states enabled at the same time, while for driver initiated AUX 964 * transfers we need the same AUX IOs to be powered but with DC states 965 * disabled. Accordingly use the AUX_IO_<port> power domain here which 966 * leaves DC states enabled. 967 * 968 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 969 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 970 * well, so we can acquire a wider AUX_<port> power domain reference 971 * instead of a specific AUX_IO_<port> reference without powering up any 972 * extra wells. 973 */ 974 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 975 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 976 else if (DISPLAY_VER(display) < 14 && 977 (intel_crtc_has_dp_encoder(crtc_state) || 978 intel_encoder_is_tc(&dig_port->base))) 979 return intel_aux_power_domain(dig_port); 980 else 981 return POWER_DOMAIN_INVALID; 982 } 983 984 static void 985 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 986 const struct intel_crtc_state *crtc_state) 987 { 988 struct intel_display *display = to_intel_display(dig_port); 989 enum intel_display_power_domain domain = 990 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 991 992 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 993 994 if (domain == POWER_DOMAIN_INVALID) 995 return; 996 997 dig_port->aux_wakeref = intel_display_power_get(display, domain); 998 } 999 1000 static void 1001 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 1002 const struct intel_crtc_state *crtc_state) 1003 { 1004 struct intel_display *display = to_intel_display(dig_port); 1005 enum intel_display_power_domain domain = 1006 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1007 struct ref_tracker *wf; 1008 1009 wf = fetch_and_zero(&dig_port->aux_wakeref); 1010 if (!wf) 1011 return; 1012 1013 intel_display_power_put(display, domain, wf); 1014 } 1015 1016 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1017 struct intel_crtc_state *crtc_state) 1018 { 1019 struct intel_display *display = to_intel_display(encoder); 1020 struct intel_digital_port *dig_port; 1021 1022 /* 1023 * TODO: Add support for MST encoders. Atm, the following should never 1024 * happen since fake-MST encoders don't set their get_power_domains() 1025 * hook. 1026 */ 1027 if (drm_WARN_ON(display->drm, 1028 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1029 return; 1030 1031 dig_port = enc_to_dig_port(encoder); 1032 1033 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1034 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1035 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1036 dig_port->ddi_io_power_domain); 1037 } 1038 1039 main_link_aux_power_domain_get(dig_port, crtc_state); 1040 } 1041 1042 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1043 const struct intel_crtc_state *crtc_state) 1044 { 1045 struct intel_display *display = to_intel_display(crtc_state); 1046 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1047 enum phy phy = intel_encoder_to_phy(encoder); 1048 u32 val; 1049 1050 if (cpu_transcoder == TRANSCODER_EDP) 1051 return; 1052 1053 if (DISPLAY_VER(display) >= 13) 1054 val = TGL_TRANS_CLK_SEL_PORT(phy); 1055 else if (DISPLAY_VER(display) >= 12) 1056 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1057 else 1058 val = TRANS_CLK_SEL_PORT(encoder->port); 1059 1060 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1061 } 1062 1063 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1064 { 1065 struct intel_display *display = to_intel_display(crtc_state); 1066 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1067 u32 val; 1068 1069 if (cpu_transcoder == TRANSCODER_EDP) 1070 return; 1071 1072 if (DISPLAY_VER(display) >= 12) 1073 val = TGL_TRANS_CLK_SEL_DISABLED; 1074 else 1075 val = TRANS_CLK_SEL_DISABLED; 1076 1077 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1078 } 1079 1080 static void _skl_ddi_set_iboost(struct intel_display *display, 1081 enum port port, u8 iboost) 1082 { 1083 u32 tmp; 1084 1085 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1086 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1087 if (iboost) 1088 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1089 else 1090 tmp |= BALANCE_LEG_DISABLE(port); 1091 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1092 } 1093 1094 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1095 const struct intel_crtc_state *crtc_state, 1096 int level) 1097 { 1098 struct intel_display *display = to_intel_display(encoder); 1099 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1100 u8 iboost; 1101 1102 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1103 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1104 else 1105 iboost = intel_bios_dp_boost_level(encoder->devdata); 1106 1107 if (iboost == 0) { 1108 const struct intel_ddi_buf_trans *trans; 1109 int n_entries; 1110 1111 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1112 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1113 return; 1114 1115 iboost = trans->entries[level].hsw.i_boost; 1116 } 1117 1118 /* Make sure that the requested I_boost is valid */ 1119 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1120 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1121 return; 1122 } 1123 1124 _skl_ddi_set_iboost(display, encoder->port, iboost); 1125 1126 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1127 _skl_ddi_set_iboost(display, PORT_E, iboost); 1128 } 1129 1130 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1131 const struct intel_crtc_state *crtc_state) 1132 { 1133 struct intel_display *display = to_intel_display(intel_dp); 1134 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1135 int n_entries; 1136 1137 intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1138 1139 if (drm_WARN_ON(display->drm, n_entries < 1)) 1140 n_entries = 1; 1141 if (drm_WARN_ON(display->drm, 1142 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1143 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1144 1145 return index_to_dp_signal_levels[n_entries - 1] & 1146 DP_TRAIN_VOLTAGE_SWING_MASK; 1147 } 1148 1149 /* 1150 * We assume that the full set of pre-emphasis values can be 1151 * used on all DDI platforms. Should that change we need to 1152 * rethink this code. 1153 */ 1154 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1155 { 1156 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1157 } 1158 1159 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1160 int lane) 1161 { 1162 if (crtc_state->port_clock > 600000) 1163 return 0; 1164 1165 if (crtc_state->lane_count == 4) 1166 return lane >= 1 ? LOADGEN_SELECT : 0; 1167 else 1168 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1169 } 1170 1171 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1172 const struct intel_crtc_state *crtc_state) 1173 { 1174 struct intel_display *display = to_intel_display(encoder); 1175 const struct intel_ddi_buf_trans *trans; 1176 enum phy phy = intel_encoder_to_phy(encoder); 1177 int n_entries, ln; 1178 u32 val; 1179 1180 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1181 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1182 return; 1183 1184 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1185 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1186 1187 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1188 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1189 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1190 intel_dp->hobl_active ? val : 0); 1191 } 1192 1193 /* Set PORT_TX_DW5 */ 1194 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1195 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1196 COEFF_POLARITY | CURSOR_PROGRAM | 1197 TAP2_DISABLE | TAP3_DISABLE); 1198 val |= SCALING_MODE_SEL(0x2); 1199 val |= RTERM_SELECT(0x6); 1200 val |= TAP3_DISABLE; 1201 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1202 1203 /* Program PORT_TX_DW2 */ 1204 for (ln = 0; ln < 4; ln++) { 1205 int level = intel_ddi_level(encoder, crtc_state, ln); 1206 1207 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1208 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1209 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1210 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1211 RCOMP_SCALAR(0x98)); 1212 } 1213 1214 /* Program PORT_TX_DW4 */ 1215 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1216 for (ln = 0; ln < 4; ln++) { 1217 int level = intel_ddi_level(encoder, crtc_state, ln); 1218 1219 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1220 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1221 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1222 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1223 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1224 } 1225 1226 /* Program PORT_TX_DW7 */ 1227 for (ln = 0; ln < 4; ln++) { 1228 int level = intel_ddi_level(encoder, crtc_state, ln); 1229 1230 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1231 N_SCALAR_MASK, 1232 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1233 } 1234 } 1235 1236 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1237 const struct intel_crtc_state *crtc_state) 1238 { 1239 struct intel_display *display = to_intel_display(encoder); 1240 enum phy phy = intel_encoder_to_phy(encoder); 1241 u32 val; 1242 int ln; 1243 1244 /* 1245 * 1. If port type is eDP or DP, 1246 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1247 * else clear to 0b. 1248 */ 1249 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1250 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1251 val &= ~COMMON_KEEPER_EN; 1252 else 1253 val |= COMMON_KEEPER_EN; 1254 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1255 1256 /* 2. Program loadgen select */ 1257 /* 1258 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1259 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1260 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1261 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1262 */ 1263 for (ln = 0; ln < 4; ln++) { 1264 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1265 LOADGEN_SELECT, 1266 icl_combo_phy_loadgen_select(crtc_state, ln)); 1267 } 1268 1269 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1270 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1271 0, SUS_CLOCK_CONFIG); 1272 1273 /* 4. Clear training enable to change swing values */ 1274 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1275 val &= ~TX_TRAINING_EN; 1276 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1277 1278 /* 5. Program swing and de-emphasis */ 1279 icl_ddi_combo_vswing_program(encoder, crtc_state); 1280 1281 /* 6. Set training enable to trigger update */ 1282 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1283 val |= TX_TRAINING_EN; 1284 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1285 } 1286 1287 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1288 const struct intel_crtc_state *crtc_state) 1289 { 1290 struct intel_display *display = to_intel_display(encoder); 1291 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1292 const struct intel_ddi_buf_trans *trans; 1293 int n_entries, ln; 1294 1295 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1296 return; 1297 1298 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1299 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1300 return; 1301 1302 for (ln = 0; ln < 2; ln++) { 1303 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1304 CRI_USE_FS32, 0); 1305 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1306 CRI_USE_FS32, 0); 1307 } 1308 1309 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1310 for (ln = 0; ln < 2; ln++) { 1311 int level; 1312 1313 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1314 1315 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1316 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1317 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1318 1319 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1320 1321 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1322 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1323 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1324 } 1325 1326 /* Program MG_TX_DRVCTRL with values from vswing table */ 1327 for (ln = 0; ln < 2; ln++) { 1328 int level; 1329 1330 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1331 1332 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1333 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1334 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1335 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1336 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1337 CRI_TXDEEMPH_OVERRIDE_EN); 1338 1339 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1340 1341 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1342 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1343 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1344 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1345 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1346 CRI_TXDEEMPH_OVERRIDE_EN); 1347 1348 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1349 } 1350 1351 /* 1352 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1353 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1354 * values from table for which TX1 and TX2 enabled. 1355 */ 1356 for (ln = 0; ln < 2; ln++) { 1357 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1358 CFG_LOW_RATE_LKREN_EN, 1359 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1360 } 1361 1362 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1363 for (ln = 0; ln < 2; ln++) { 1364 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1365 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1366 CFG_AMI_CK_DIV_OVERRIDE_EN, 1367 crtc_state->port_clock > 500000 ? 1368 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1369 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1370 1371 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1372 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1373 CFG_AMI_CK_DIV_OVERRIDE_EN, 1374 crtc_state->port_clock > 500000 ? 1375 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1376 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1377 } 1378 1379 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1380 for (ln = 0; ln < 2; ln++) { 1381 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1382 0, CRI_CALCINIT); 1383 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1384 0, CRI_CALCINIT); 1385 } 1386 } 1387 1388 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1389 const struct intel_crtc_state *crtc_state) 1390 { 1391 struct intel_display *display = to_intel_display(encoder); 1392 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1393 const struct intel_ddi_buf_trans *trans; 1394 int n_entries, ln; 1395 1396 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1397 return; 1398 1399 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1400 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1401 return; 1402 1403 for (ln = 0; ln < 2; ln++) { 1404 int level; 1405 1406 /* Wa_16011342517:adl-p */ 1407 if (intel_display_wa(display, INTEL_DISPLAY_WA_16011342517)) { 1408 if ((intel_encoder_is_hdmi(encoder) && 1409 crtc_state->port_clock == 594000) || 1410 (intel_encoder_is_dp(encoder) && 1411 crtc_state->port_clock == 162000)) { 1412 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1413 LOADGEN_SHARING_PMD_DISABLE, 1); 1414 } else { 1415 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1416 LOADGEN_SHARING_PMD_DISABLE, 0); 1417 } 1418 } 1419 1420 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1421 1422 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1423 1424 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1425 DKL_TX_PRESHOOT_COEFF_MASK | 1426 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1427 DKL_TX_VSWING_CONTROL_MASK, 1428 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1429 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1430 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1431 1432 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1433 1434 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1435 DKL_TX_PRESHOOT_COEFF_MASK | 1436 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1437 DKL_TX_VSWING_CONTROL_MASK, 1438 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1439 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1440 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1441 1442 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1443 DKL_TX_DP20BITMODE, 0); 1444 1445 if (display->platform.alderlake_p) { 1446 u32 val; 1447 1448 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1449 if (ln == 0) { 1450 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1451 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1452 } else { 1453 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1454 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1455 } 1456 } else { 1457 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1458 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1459 } 1460 1461 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1462 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1463 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1464 val); 1465 } 1466 } 1467 } 1468 1469 static int translate_signal_level(struct intel_dp *intel_dp, 1470 u8 signal_levels) 1471 { 1472 struct intel_display *display = to_intel_display(intel_dp); 1473 const u8 *signal_array; 1474 size_t array_size; 1475 int i; 1476 1477 signal_array = index_to_dp_signal_levels; 1478 array_size = ARRAY_SIZE(index_to_dp_signal_levels); 1479 1480 for (i = 0; i < array_size; i++) { 1481 if (signal_array[i] == signal_levels) 1482 return i; 1483 } 1484 1485 drm_WARN(display->drm, 1, 1486 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1487 signal_levels); 1488 1489 return 0; 1490 } 1491 1492 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1493 const struct intel_crtc_state *crtc_state, 1494 int lane) 1495 { 1496 u8 train_set = intel_dp->train_set[lane]; 1497 1498 if (intel_dp_is_uhbr(crtc_state)) { 1499 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1500 } else { 1501 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1502 DP_TRAIN_PRE_EMPHASIS_MASK); 1503 1504 return translate_signal_level(intel_dp, signal_levels); 1505 } 1506 } 1507 1508 int intel_ddi_level(struct intel_encoder *encoder, 1509 const struct intel_crtc_state *crtc_state, 1510 int lane) 1511 { 1512 struct intel_display *display = to_intel_display(encoder); 1513 const struct intel_ddi_buf_trans *trans; 1514 int level, n_entries; 1515 1516 trans = intel_ddi_buf_trans_get(encoder, crtc_state, &n_entries); 1517 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1518 return 0; 1519 1520 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1521 level = intel_ddi_hdmi_level(encoder, trans); 1522 else 1523 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1524 lane); 1525 1526 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1527 level = n_entries - 1; 1528 1529 return level; 1530 } 1531 1532 int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock) 1533 { 1534 if (intel_encoder_is_dp(encoder)) 1535 return intel_dp_link_symbol_clock(clock); 1536 1537 if (intel_hdmi_is_frl(clock)) 1538 return DIV_ROUND_CLOSEST(clock * 10, 18); 1539 1540 return clock; 1541 } 1542 1543 static void 1544 hsw_set_signal_levels(struct intel_encoder *encoder, 1545 const struct intel_crtc_state *crtc_state) 1546 { 1547 struct intel_display *display = to_intel_display(encoder); 1548 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1549 int level = intel_ddi_level(encoder, crtc_state, 0); 1550 enum port port = encoder->port; 1551 u32 signal_levels; 1552 1553 if (has_iboost(display)) 1554 skl_ddi_set_iboost(encoder, crtc_state, level); 1555 1556 /* HDMI ignores the rest */ 1557 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1558 return; 1559 1560 signal_levels = DDI_BUF_TRANS_SELECT(level); 1561 1562 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1563 signal_levels); 1564 1565 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1566 intel_dp->DP |= signal_levels; 1567 1568 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1569 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1570 } 1571 1572 static void _icl_ddi_enable_clock(struct intel_display *display, intel_reg_t reg, 1573 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1574 { 1575 mutex_lock(&display->dpll.lock); 1576 1577 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1578 1579 /* 1580 * "This step and the step before must be 1581 * done with separate register writes." 1582 */ 1583 intel_de_rmw(display, reg, clk_off, 0); 1584 1585 mutex_unlock(&display->dpll.lock); 1586 } 1587 1588 static void _icl_ddi_disable_clock(struct intel_display *display, intel_reg_t reg, 1589 u32 clk_off) 1590 { 1591 mutex_lock(&display->dpll.lock); 1592 1593 intel_de_rmw(display, reg, 0, clk_off); 1594 1595 mutex_unlock(&display->dpll.lock); 1596 } 1597 1598 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, intel_reg_t reg, 1599 u32 clk_off) 1600 { 1601 return !(intel_de_read(display, reg) & clk_off); 1602 } 1603 1604 static struct intel_dpll * 1605 _icl_ddi_get_pll(struct intel_display *display, intel_reg_t reg, 1606 u32 clk_sel_mask, u32 clk_sel_shift) 1607 { 1608 enum intel_dpll_id id; 1609 1610 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1611 1612 return intel_get_dpll_by_id(display, id); 1613 } 1614 1615 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1616 const struct intel_crtc_state *crtc_state) 1617 { 1618 struct intel_display *display = to_intel_display(encoder); 1619 const struct intel_dpll *pll = crtc_state->intel_dpll; 1620 enum phy phy = intel_encoder_to_phy(encoder); 1621 1622 if (drm_WARN_ON(display->drm, !pll)) 1623 return; 1624 1625 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1626 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1627 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1628 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1629 } 1630 1631 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1632 { 1633 struct intel_display *display = to_intel_display(encoder); 1634 enum phy phy = intel_encoder_to_phy(encoder); 1635 1636 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1637 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1638 } 1639 1640 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1641 { 1642 struct intel_display *display = to_intel_display(encoder); 1643 enum phy phy = intel_encoder_to_phy(encoder); 1644 1645 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1646 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1647 } 1648 1649 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1650 { 1651 struct intel_display *display = to_intel_display(encoder); 1652 enum phy phy = intel_encoder_to_phy(encoder); 1653 1654 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1655 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1656 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1657 } 1658 1659 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1660 const struct intel_crtc_state *crtc_state) 1661 { 1662 struct intel_display *display = to_intel_display(encoder); 1663 const struct intel_dpll *pll = crtc_state->intel_dpll; 1664 enum phy phy = intel_encoder_to_phy(encoder); 1665 1666 if (drm_WARN_ON(display->drm, !pll)) 1667 return; 1668 1669 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1670 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1671 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1672 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1673 } 1674 1675 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1676 { 1677 struct intel_display *display = to_intel_display(encoder); 1678 enum phy phy = intel_encoder_to_phy(encoder); 1679 1680 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1681 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1682 } 1683 1684 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1685 { 1686 struct intel_display *display = to_intel_display(encoder); 1687 enum phy phy = intel_encoder_to_phy(encoder); 1688 1689 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1690 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1691 } 1692 1693 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1694 { 1695 struct intel_display *display = to_intel_display(encoder); 1696 enum phy phy = intel_encoder_to_phy(encoder); 1697 1698 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1699 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1700 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1701 } 1702 1703 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1704 const struct intel_crtc_state *crtc_state) 1705 { 1706 struct intel_display *display = to_intel_display(encoder); 1707 const struct intel_dpll *pll = crtc_state->intel_dpll; 1708 enum phy phy = intel_encoder_to_phy(encoder); 1709 1710 if (drm_WARN_ON(display->drm, !pll)) 1711 return; 1712 1713 /* 1714 * If we fail this, something went very wrong: first 2 PLLs should be 1715 * used by first 2 phys and last 2 PLLs by last phys 1716 */ 1717 if (drm_WARN_ON(display->drm, 1718 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1719 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1720 return; 1721 1722 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1723 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1724 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1725 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1726 } 1727 1728 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1729 { 1730 struct intel_display *display = to_intel_display(encoder); 1731 enum phy phy = intel_encoder_to_phy(encoder); 1732 1733 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1734 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1735 } 1736 1737 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1738 { 1739 struct intel_display *display = to_intel_display(encoder); 1740 enum phy phy = intel_encoder_to_phy(encoder); 1741 1742 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1743 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1744 } 1745 1746 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1747 { 1748 struct intel_display *display = to_intel_display(encoder); 1749 enum phy phy = intel_encoder_to_phy(encoder); 1750 enum intel_dpll_id id; 1751 u32 val; 1752 1753 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1754 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1755 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1756 id = val; 1757 1758 /* 1759 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1760 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1761 * bit for phy C and D. 1762 */ 1763 if (phy >= PHY_C) 1764 id += DPLL_ID_DG1_DPLL2; 1765 1766 return intel_get_dpll_by_id(display, id); 1767 } 1768 1769 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1770 const struct intel_crtc_state *crtc_state) 1771 { 1772 struct intel_display *display = to_intel_display(encoder); 1773 const struct intel_dpll *pll = crtc_state->intel_dpll; 1774 enum phy phy = intel_encoder_to_phy(encoder); 1775 1776 if (drm_WARN_ON(display->drm, !pll)) 1777 return; 1778 1779 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1780 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1781 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1782 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1783 } 1784 1785 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1786 { 1787 struct intel_display *display = to_intel_display(encoder); 1788 enum phy phy = intel_encoder_to_phy(encoder); 1789 1790 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1791 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1792 } 1793 1794 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1795 { 1796 struct intel_display *display = to_intel_display(encoder); 1797 enum phy phy = intel_encoder_to_phy(encoder); 1798 1799 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1800 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1801 } 1802 1803 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1804 { 1805 struct intel_display *display = to_intel_display(encoder); 1806 enum phy phy = intel_encoder_to_phy(encoder); 1807 1808 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1809 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1810 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1811 } 1812 1813 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1814 const struct intel_crtc_state *crtc_state) 1815 { 1816 struct intel_display *display = to_intel_display(encoder); 1817 const struct intel_dpll *pll = crtc_state->intel_dpll; 1818 enum port port = encoder->port; 1819 1820 if (drm_WARN_ON(display->drm, !pll)) 1821 return; 1822 1823 /* 1824 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1825 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1826 */ 1827 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1828 1829 icl_ddi_combo_enable_clock(encoder, crtc_state); 1830 } 1831 1832 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1833 { 1834 struct intel_display *display = to_intel_display(encoder); 1835 enum port port = encoder->port; 1836 1837 icl_ddi_combo_disable_clock(encoder); 1838 1839 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1840 } 1841 1842 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1843 { 1844 struct intel_display *display = to_intel_display(encoder); 1845 enum port port = encoder->port; 1846 u32 tmp; 1847 1848 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1849 1850 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1851 return false; 1852 1853 return icl_ddi_combo_is_clock_enabled(encoder); 1854 } 1855 1856 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1857 const struct intel_crtc_state *crtc_state) 1858 { 1859 struct intel_display *display = to_intel_display(encoder); 1860 const struct intel_dpll *pll = crtc_state->intel_dpll; 1861 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1862 enum port port = encoder->port; 1863 1864 if (drm_WARN_ON(display->drm, !pll)) 1865 return; 1866 1867 intel_de_write(display, DDI_CLK_SEL(port), 1868 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1869 1870 mutex_lock(&display->dpll.lock); 1871 1872 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1873 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1874 1875 mutex_unlock(&display->dpll.lock); 1876 } 1877 1878 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1879 { 1880 struct intel_display *display = to_intel_display(encoder); 1881 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1882 enum port port = encoder->port; 1883 1884 mutex_lock(&display->dpll.lock); 1885 1886 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1887 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1888 1889 mutex_unlock(&display->dpll.lock); 1890 1891 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1892 } 1893 1894 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1895 { 1896 struct intel_display *display = to_intel_display(encoder); 1897 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1898 enum port port = encoder->port; 1899 u32 tmp; 1900 1901 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1902 1903 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1904 return false; 1905 1906 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1907 1908 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1909 } 1910 1911 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1912 { 1913 struct intel_display *display = to_intel_display(encoder); 1914 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1915 enum port port = encoder->port; 1916 enum intel_dpll_id id; 1917 u32 tmp; 1918 1919 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1920 1921 switch (tmp & DDI_CLK_SEL_MASK) { 1922 case DDI_CLK_SEL_TBT_162: 1923 case DDI_CLK_SEL_TBT_270: 1924 case DDI_CLK_SEL_TBT_540: 1925 case DDI_CLK_SEL_TBT_810: 1926 id = DPLL_ID_ICL_TBTPLL; 1927 break; 1928 case DDI_CLK_SEL_MG: 1929 id = icl_tc_port_to_pll_id(tc_port); 1930 break; 1931 default: 1932 MISSING_CASE(tmp); 1933 fallthrough; 1934 case DDI_CLK_SEL_NONE: 1935 return NULL; 1936 } 1937 1938 return intel_get_dpll_by_id(display, id); 1939 } 1940 1941 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1942 { 1943 struct intel_display *display = to_intel_display(encoder->base.dev); 1944 enum intel_dpll_id id; 1945 1946 switch (encoder->port) { 1947 case PORT_A: 1948 id = DPLL_ID_SKL_DPLL0; 1949 break; 1950 case PORT_B: 1951 id = DPLL_ID_SKL_DPLL1; 1952 break; 1953 case PORT_C: 1954 id = DPLL_ID_SKL_DPLL2; 1955 break; 1956 default: 1957 MISSING_CASE(encoder->port); 1958 return NULL; 1959 } 1960 1961 return intel_get_dpll_by_id(display, id); 1962 } 1963 1964 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1965 const struct intel_crtc_state *crtc_state) 1966 { 1967 struct intel_display *display = to_intel_display(encoder); 1968 const struct intel_dpll *pll = crtc_state->intel_dpll; 1969 enum port port = encoder->port; 1970 1971 if (drm_WARN_ON(display->drm, !pll)) 1972 return; 1973 1974 mutex_lock(&display->dpll.lock); 1975 1976 intel_de_rmw(display, DPLL_CTRL2, 1977 DPLL_CTRL2_DDI_CLK_OFF(port) | 1978 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1979 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1980 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1981 1982 mutex_unlock(&display->dpll.lock); 1983 } 1984 1985 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1986 { 1987 struct intel_display *display = to_intel_display(encoder); 1988 enum port port = encoder->port; 1989 1990 mutex_lock(&display->dpll.lock); 1991 1992 intel_de_rmw(display, DPLL_CTRL2, 1993 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1994 1995 mutex_unlock(&display->dpll.lock); 1996 } 1997 1998 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1999 { 2000 struct intel_display *display = to_intel_display(encoder); 2001 enum port port = encoder->port; 2002 2003 /* 2004 * FIXME Not sure if the override affects both 2005 * the PLL selection and the CLK_OFF bit. 2006 */ 2007 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 2008 } 2009 2010 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 2011 { 2012 struct intel_display *display = to_intel_display(encoder); 2013 enum port port = encoder->port; 2014 enum intel_dpll_id id; 2015 u32 tmp; 2016 2017 tmp = intel_de_read(display, DPLL_CTRL2); 2018 2019 /* 2020 * FIXME Not sure if the override affects both 2021 * the PLL selection and the CLK_OFF bit. 2022 */ 2023 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2024 return NULL; 2025 2026 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2027 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2028 2029 return intel_get_dpll_by_id(display, id); 2030 } 2031 2032 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2033 const struct intel_crtc_state *crtc_state) 2034 { 2035 struct intel_display *display = to_intel_display(encoder); 2036 const struct intel_dpll *pll = crtc_state->intel_dpll; 2037 enum port port = encoder->port; 2038 2039 if (drm_WARN_ON(display->drm, !pll)) 2040 return; 2041 2042 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2043 } 2044 2045 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2046 { 2047 struct intel_display *display = to_intel_display(encoder); 2048 enum port port = encoder->port; 2049 2050 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2051 } 2052 2053 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2054 { 2055 struct intel_display *display = to_intel_display(encoder); 2056 enum port port = encoder->port; 2057 2058 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2059 } 2060 2061 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2062 { 2063 struct intel_display *display = to_intel_display(encoder); 2064 enum port port = encoder->port; 2065 enum intel_dpll_id id; 2066 u32 tmp; 2067 2068 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2069 2070 switch (tmp & PORT_CLK_SEL_MASK) { 2071 case PORT_CLK_SEL_WRPLL1: 2072 id = DPLL_ID_WRPLL1; 2073 break; 2074 case PORT_CLK_SEL_WRPLL2: 2075 id = DPLL_ID_WRPLL2; 2076 break; 2077 case PORT_CLK_SEL_SPLL: 2078 id = DPLL_ID_SPLL; 2079 break; 2080 case PORT_CLK_SEL_LCPLL_810: 2081 id = DPLL_ID_LCPLL_810; 2082 break; 2083 case PORT_CLK_SEL_LCPLL_1350: 2084 id = DPLL_ID_LCPLL_1350; 2085 break; 2086 case PORT_CLK_SEL_LCPLL_2700: 2087 id = DPLL_ID_LCPLL_2700; 2088 break; 2089 default: 2090 MISSING_CASE(tmp); 2091 fallthrough; 2092 case PORT_CLK_SEL_NONE: 2093 return NULL; 2094 } 2095 2096 return intel_get_dpll_by_id(display, id); 2097 } 2098 2099 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2100 const struct intel_crtc_state *crtc_state) 2101 { 2102 if (encoder->enable_clock) 2103 encoder->enable_clock(encoder, crtc_state); 2104 } 2105 2106 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2107 { 2108 if (encoder->disable_clock) 2109 encoder->disable_clock(encoder); 2110 } 2111 2112 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2113 { 2114 struct intel_display *display = to_intel_display(encoder); 2115 u32 port_mask; 2116 bool ddi_clk_needed; 2117 2118 /* 2119 * In case of DP MST, we sanitize the primary encoder only, not the 2120 * virtual ones. 2121 */ 2122 if (encoder->type == INTEL_OUTPUT_DP_MST) 2123 return; 2124 2125 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2126 u8 pipe_mask; 2127 bool is_mst; 2128 2129 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2130 /* 2131 * In the unlikely case that BIOS enables DP in MST mode, just 2132 * warn since our MST HW readout is incomplete. 2133 */ 2134 if (drm_WARN_ON(display->drm, is_mst)) 2135 return; 2136 } 2137 2138 port_mask = BIT(encoder->port); 2139 ddi_clk_needed = encoder->base.crtc; 2140 2141 if (encoder->type == INTEL_OUTPUT_DSI) { 2142 struct intel_encoder *other_encoder; 2143 2144 port_mask = intel_dsi_encoder_ports(encoder); 2145 /* 2146 * Sanity check that we haven't incorrectly registered another 2147 * encoder using any of the ports of this DSI encoder. 2148 */ 2149 for_each_intel_encoder(display->drm, other_encoder) { 2150 if (other_encoder == encoder) 2151 continue; 2152 2153 if (drm_WARN_ON(display->drm, 2154 port_mask & BIT(other_encoder->port))) 2155 return; 2156 } 2157 /* 2158 * For DSI we keep the ddi clocks gated 2159 * except during enable/disable sequence. 2160 */ 2161 ddi_clk_needed = false; 2162 } 2163 2164 if (ddi_clk_needed || !encoder->is_clock_enabled || 2165 !encoder->is_clock_enabled(encoder)) 2166 return; 2167 2168 drm_dbg_kms(display->drm, 2169 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2170 encoder->base.base.id, encoder->base.name); 2171 2172 encoder->disable_clock(encoder); 2173 } 2174 2175 static void 2176 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2177 enum tc_port tc_port, u32 ln0, u32 ln1) 2178 { 2179 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2180 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2181 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2182 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2183 } 2184 2185 static void 2186 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2187 const struct intel_crtc_state *crtc_state) 2188 { 2189 struct intel_display *display = to_intel_display(crtc_state); 2190 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2191 enum intel_tc_pin_assignment pin_assignment; 2192 u32 ln0, ln1; 2193 u8 width; 2194 2195 if (DISPLAY_VER(display) >= 14) 2196 return; 2197 2198 if (!intel_encoder_is_tc(&dig_port->base) || 2199 intel_tc_port_in_tbt_alt_mode(dig_port)) 2200 return; 2201 2202 if (DISPLAY_VER(display) >= 12) { 2203 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2204 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2205 } else { 2206 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2207 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2208 } 2209 2210 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2211 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2212 2213 /* DPPATC */ 2214 pin_assignment = intel_tc_port_get_pin_assignment(dig_port); 2215 width = crtc_state->lane_count; 2216 2217 switch (pin_assignment) { 2218 case INTEL_TC_PIN_ASSIGNMENT_NONE: 2219 drm_WARN_ON(display->drm, 2220 !intel_tc_port_in_legacy_mode(dig_port)); 2221 if (width == 1) { 2222 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2223 } else { 2224 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2225 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2226 } 2227 break; 2228 case INTEL_TC_PIN_ASSIGNMENT_A: 2229 if (width == 4) { 2230 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2231 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2232 } 2233 break; 2234 case INTEL_TC_PIN_ASSIGNMENT_B: 2235 if (width == 2) { 2236 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2237 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2238 } 2239 break; 2240 case INTEL_TC_PIN_ASSIGNMENT_C: 2241 case INTEL_TC_PIN_ASSIGNMENT_E: 2242 if (width == 1) { 2243 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2244 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2245 } else { 2246 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2247 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2248 } 2249 break; 2250 case INTEL_TC_PIN_ASSIGNMENT_D: 2251 case INTEL_TC_PIN_ASSIGNMENT_F: 2252 if (width == 1) { 2253 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2254 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2255 } else { 2256 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2257 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2258 } 2259 break; 2260 default: 2261 MISSING_CASE(pin_assignment); 2262 } 2263 2264 if (DISPLAY_VER(display) >= 12) { 2265 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2266 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2267 /* WA_14018221282 */ 2268 if (IS_DISPLAY_VER(display, 12, 13)) 2269 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2270 2271 } else { 2272 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2273 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2274 } 2275 } 2276 2277 static enum transcoder 2278 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2279 { 2280 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2281 return crtc_state->mst_master_transcoder; 2282 else 2283 return crtc_state->cpu_transcoder; 2284 } 2285 2286 intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2287 const struct intel_crtc_state *crtc_state) 2288 { 2289 struct intel_display *display = to_intel_display(encoder); 2290 2291 if (DISPLAY_VER(display) >= 12) 2292 return TGL_DP_TP_CTL(display, 2293 tgl_dp_tp_transcoder(crtc_state)); 2294 else 2295 return DP_TP_CTL(encoder->port); 2296 } 2297 2298 static intel_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2299 const struct intel_crtc_state *crtc_state) 2300 { 2301 struct intel_display *display = to_intel_display(encoder); 2302 2303 if (DISPLAY_VER(display) >= 12) 2304 return TGL_DP_TP_STATUS(display, 2305 tgl_dp_tp_transcoder(crtc_state)); 2306 else 2307 return DP_TP_STATUS(encoder->port); 2308 } 2309 2310 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2311 const struct intel_crtc_state *crtc_state) 2312 { 2313 struct intel_display *display = to_intel_display(encoder); 2314 2315 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2316 DP_TP_STATUS_ACT_SENT); 2317 } 2318 2319 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2320 const struct intel_crtc_state *crtc_state) 2321 { 2322 struct intel_display *display = to_intel_display(encoder); 2323 2324 if (intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state), 2325 DP_TP_STATUS_ACT_SENT, 1)) 2326 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2327 } 2328 2329 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2330 const struct intel_crtc_state *crtc_state, 2331 bool enable) 2332 { 2333 struct intel_display *display = to_intel_display(intel_dp); 2334 2335 if (!crtc_state->vrr.enable) 2336 return; 2337 2338 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2339 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2340 drm_dbg_kms(display->drm, 2341 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2342 str_enable_disable(enable)); 2343 } 2344 2345 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2346 const struct intel_crtc_state *crtc_state, 2347 bool enable) 2348 { 2349 struct intel_display *display = to_intel_display(intel_dp); 2350 2351 if (!crtc_state->fec_enable) 2352 return; 2353 2354 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2355 enable ? DP_FEC_READY : 0) <= 0) 2356 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2357 str_enabled_disabled(enable)); 2358 2359 if (enable && 2360 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2361 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2362 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2363 } 2364 2365 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2366 { 2367 struct intel_display *display = to_intel_display(aux->drm_dev); 2368 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2369 u8 status = 0; 2370 int ret, err; 2371 2372 ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status), 2373 err || (status & mask), 2374 10 * 1000, 200 * 1000, false); 2375 2376 /* Either can be non-zero, but not both */ 2377 ret = ret ?: err; 2378 if (ret) { 2379 drm_dbg_kms(display->drm, 2380 "Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n", 2381 str_enabled_disabled(enabled), ret, status); 2382 return ret; 2383 } 2384 2385 return 0; 2386 } 2387 2388 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2389 const struct intel_crtc_state *crtc_state, 2390 bool enabled) 2391 { 2392 struct intel_display *display = to_intel_display(encoder); 2393 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2394 int ret; 2395 2396 if (!crtc_state->fec_enable) 2397 return 0; 2398 2399 if (enabled) 2400 ret = intel_de_wait_for_set_ms(display, dp_tp_status_reg(encoder, crtc_state), 2401 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2402 else 2403 ret = intel_de_wait_for_clear_ms(display, dp_tp_status_reg(encoder, crtc_state), 2404 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2405 2406 if (ret) { 2407 drm_err(display->drm, 2408 "Timeout waiting for FEC live state to get %s\n", 2409 str_enabled_disabled(enabled)); 2410 return ret; 2411 } 2412 /* 2413 * At least the Synoptics MST hub doesn't set the detected flag for 2414 * FEC decoding disabling so skip waiting for that. 2415 */ 2416 if (enabled) { 2417 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2418 if (ret) 2419 return ret; 2420 } 2421 2422 return 0; 2423 } 2424 2425 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2426 const struct intel_crtc_state *crtc_state) 2427 { 2428 struct intel_display *display = to_intel_display(encoder); 2429 int i; 2430 int ret; 2431 2432 if (!crtc_state->fec_enable) 2433 return; 2434 2435 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2436 0, DP_TP_CTL_FEC_ENABLE); 2437 2438 if (DISPLAY_VER(display) < 30) 2439 return; 2440 2441 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2442 if (!ret) 2443 return; 2444 2445 for (i = 0; i < 3; i++) { 2446 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2447 2448 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2449 DP_TP_CTL_FEC_ENABLE, 0); 2450 2451 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2452 if (ret) 2453 continue; 2454 2455 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2456 0, DP_TP_CTL_FEC_ENABLE); 2457 2458 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2459 if (!ret) 2460 return; 2461 } 2462 2463 drm_dbg_kms(display->drm, "Failed to enable FEC after retries\n"); 2464 } 2465 2466 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2467 const struct intel_crtc_state *crtc_state) 2468 { 2469 struct intel_display *display = to_intel_display(encoder); 2470 2471 if (!crtc_state->fec_enable) 2472 return; 2473 2474 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2475 DP_TP_CTL_FEC_ENABLE, 0); 2476 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2477 } 2478 2479 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2480 const struct intel_crtc_state *crtc_state) 2481 { 2482 struct intel_display *display = to_intel_display(encoder); 2483 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2484 2485 if (intel_encoder_is_combo(encoder)) { 2486 enum phy phy = intel_encoder_to_phy(encoder); 2487 2488 intel_combo_phy_power_up_lanes(display, phy, false, 2489 crtc_state->lane_count, 2490 dig_port->lane_reversal); 2491 } 2492 } 2493 2494 /* 2495 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2496 * platforms. 2497 */ 2498 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2499 { 2500 if (DISPLAY_VER(display) > 20) 2501 return ~0; 2502 else if (display->platform.alderlake_p) 2503 return BIT(PIPE_A) | BIT(PIPE_B); 2504 else 2505 return BIT(PIPE_A); 2506 } 2507 2508 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2509 struct intel_crtc_state *pipe_config) 2510 { 2511 struct intel_display *display = to_intel_display(pipe_config); 2512 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2513 enum pipe pipe = crtc->pipe; 2514 u32 dss1; 2515 2516 if (!HAS_MSO(display)) 2517 return; 2518 2519 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2520 2521 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2522 if (!pipe_config->splitter.enable) 2523 return; 2524 2525 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2526 pipe_config->splitter.enable = false; 2527 return; 2528 } 2529 2530 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2531 default: 2532 drm_WARN(display->drm, true, 2533 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2534 fallthrough; 2535 case SPLITTER_CONFIGURATION_2_SEGMENT: 2536 pipe_config->splitter.link_count = 2; 2537 break; 2538 case SPLITTER_CONFIGURATION_4_SEGMENT: 2539 pipe_config->splitter.link_count = 4; 2540 break; 2541 } 2542 2543 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2544 } 2545 2546 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2547 { 2548 struct intel_display *display = to_intel_display(crtc_state); 2549 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2550 enum pipe pipe = crtc->pipe; 2551 u32 dss1 = 0; 2552 2553 if (!HAS_MSO(display)) 2554 return; 2555 2556 if (crtc_state->splitter.enable) { 2557 dss1 |= SPLITTER_ENABLE; 2558 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2559 if (crtc_state->splitter.link_count == 2) 2560 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2561 else 2562 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2563 } 2564 2565 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2566 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2567 OVERLAP_PIXELS_MASK, dss1); 2568 } 2569 2570 static void 2571 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2572 { 2573 struct intel_display *display = to_intel_display(encoder); 2574 enum port port = encoder->port; 2575 intel_reg_t reg; 2576 u32 set_bits, wait_bits; 2577 int ret; 2578 2579 if (DISPLAY_VER(display) < 14) 2580 return; 2581 2582 if (DISPLAY_VER(display) >= 20) { 2583 reg = DDI_BUF_CTL(port); 2584 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2585 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2586 } else { 2587 reg = XELPDP_PORT_BUF_CTL1(display, port); 2588 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2589 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2590 } 2591 2592 intel_de_rmw(display, reg, 0, set_bits); 2593 2594 ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100); 2595 if (ret) { 2596 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2597 port_name(port)); 2598 } 2599 } 2600 2601 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2602 const struct intel_crtc_state *crtc_state) 2603 { 2604 struct intel_display *display = to_intel_display(encoder); 2605 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2606 enum port port = encoder->port; 2607 u32 val = 0; 2608 2609 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2610 2611 if (intel_dp_is_uhbr(crtc_state)) 2612 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2613 else 2614 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2615 2616 if (dig_port->lane_reversal) 2617 val |= XELPDP_PORT_REVERSAL; 2618 2619 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2620 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2621 val); 2622 } 2623 2624 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2625 { 2626 struct intel_display *display = to_intel_display(encoder); 2627 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2628 u32 val; 2629 2630 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2631 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2632 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2633 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2634 } 2635 2636 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2637 struct intel_encoder *encoder, 2638 const struct intel_crtc_state *crtc_state, 2639 const struct drm_connector_state *conn_state) 2640 { 2641 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2642 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2643 bool transparent_mode; 2644 int ret; 2645 2646 intel_dp_set_link_params(intel_dp, 2647 crtc_state->port_clock, 2648 crtc_state->lane_count); 2649 2650 /* 2651 * We only configure what the register value will be here. Actual 2652 * enabling happens during link training farther down. 2653 */ 2654 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2655 2656 /* 2657 * 1. Enable Power Wells 2658 * 2659 * This was handled at the beginning of intel_atomic_commit_tail(), 2660 * before we called down into this function. 2661 */ 2662 2663 /* 2. PMdemand was already set */ 2664 2665 /* 3. Select Thunderbolt */ 2666 mtl_port_buf_ctl_io_selection(encoder); 2667 2668 /* 5. Enable the port PLL */ 2669 intel_ddi_enable_clock(encoder, crtc_state); 2670 2671 /* 2672 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2673 * Transcoder. 2674 */ 2675 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2676 2677 /* 2678 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2679 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2680 * Transport Select 2681 */ 2682 intel_ddi_config_transcoder_func(encoder, crtc_state); 2683 2684 /* 2685 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2686 */ 2687 intel_ddi_mso_configure(crtc_state); 2688 2689 if (!is_mst) 2690 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2691 2692 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2693 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2694 2695 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2696 if (!is_mst) 2697 intel_dp_sink_enable_decompression(state, 2698 to_intel_connector(conn_state->connector), 2699 crtc_state); 2700 2701 /* 2702 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2703 * in the FEC_CONFIGURATION register to 1 before initiating link 2704 * training 2705 */ 2706 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2707 2708 intel_dp_check_frl_training(intel_dp); 2709 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2710 2711 /* 2712 * 6. The rest of the below are substeps under the bspec's "Enable and 2713 * Train Display Port" step. Note that steps that are specific to 2714 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2715 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2716 * us when active_mst_links==0, so any steps designated for "single 2717 * stream or multi-stream master transcoder" can just be performed 2718 * unconditionally here. 2719 * 2720 * mtl_ddi_prepare_link_retrain() that is called by 2721 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2722 * 6.i and 6.j 2723 * 2724 * 6.k Follow DisplayPort specification training sequence (see notes for 2725 * failure handling) 2726 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2727 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2728 * (timeout after 800 us) 2729 */ 2730 intel_dp_start_link_train(state, intel_dp, crtc_state); 2731 2732 /* 6.n Set DP_TP_CTL link training to Normal */ 2733 if (!is_trans_port_sync_mode(crtc_state)) 2734 intel_dp_stop_link_train(intel_dp, crtc_state); 2735 2736 /* 6.o Configure and enable FEC if needed */ 2737 intel_ddi_enable_fec(encoder, crtc_state); 2738 2739 /* 7.a 128b/132b SST. */ 2740 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2741 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2742 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2743 if (ret < 0) 2744 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2745 } 2746 2747 if (!is_mst) 2748 intel_dsc_dp_pps_write(encoder, crtc_state); 2749 } 2750 2751 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2752 struct intel_encoder *encoder, 2753 const struct intel_crtc_state *crtc_state, 2754 const struct drm_connector_state *conn_state) 2755 { 2756 struct intel_display *display = to_intel_display(encoder); 2757 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2758 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2759 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2760 int ret; 2761 2762 intel_dp_set_link_params(intel_dp, 2763 crtc_state->port_clock, 2764 crtc_state->lane_count); 2765 2766 /* 2767 * We only configure what the register value will be here. Actual 2768 * enabling happens during link training farther down. 2769 */ 2770 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2771 2772 /* 2773 * 1. Enable Power Wells 2774 * 2775 * This was handled at the beginning of intel_atomic_commit_tail(), 2776 * before we called down into this function. 2777 */ 2778 2779 /* 2. Enable Panel Power if PPS is required */ 2780 intel_pps_on(intel_dp); 2781 2782 /* 2783 * 3. For non-TBT Type-C ports, set FIA lane count 2784 * (DFLEXDPSP.DPX4TXLATC) 2785 * 2786 * This was done before tgl_ddi_pre_enable_dp by 2787 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2788 */ 2789 2790 /* 2791 * 4. Enable the port PLL. 2792 * 2793 * The PLL enabling itself was already done before this function by 2794 * hsw_crtc_enable()->intel_enable_dpll(). We need only 2795 * configure the PLL to port mapping here. 2796 */ 2797 intel_ddi_enable_clock(encoder, crtc_state); 2798 2799 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2800 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2801 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2802 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2803 dig_port->ddi_io_power_domain); 2804 } 2805 2806 /* 6. Program DP_MODE */ 2807 icl_program_mg_dp_mode(dig_port, crtc_state); 2808 2809 /* 2810 * 7. The rest of the below are substeps under the bspec's "Enable and 2811 * Train Display Port" step. Note that steps that are specific to 2812 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2813 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2814 * us when active_mst_links==0, so any steps designated for "single 2815 * stream or multi-stream master transcoder" can just be performed 2816 * unconditionally here. 2817 */ 2818 2819 /* 2820 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2821 * Transcoder. 2822 */ 2823 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2824 2825 /* 2826 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2827 * Transport Select 2828 */ 2829 intel_ddi_config_transcoder_func(encoder, crtc_state); 2830 2831 /* 2832 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2833 * selected 2834 * 2835 * This will be handled by the intel_dp_start_link_train() farther 2836 * down this function. 2837 */ 2838 2839 /* 7.e Configure voltage swing and related IO settings */ 2840 encoder->set_signal_levels(encoder, crtc_state); 2841 2842 /* 2843 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2844 * the used lanes of the DDI. 2845 */ 2846 intel_ddi_power_up_lanes(encoder, crtc_state); 2847 2848 /* 2849 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2850 */ 2851 intel_ddi_mso_configure(crtc_state); 2852 2853 if (!is_mst) 2854 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2855 2856 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2857 if (!is_mst) 2858 intel_dp_sink_enable_decompression(state, 2859 to_intel_connector(conn_state->connector), 2860 crtc_state); 2861 /* 2862 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2863 * in the FEC_CONFIGURATION register to 1 before initiating link 2864 * training 2865 */ 2866 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2867 2868 intel_dp_check_frl_training(intel_dp); 2869 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2870 2871 /* 2872 * 7.i Follow DisplayPort specification training sequence (see notes for 2873 * failure handling) 2874 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2875 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2876 * (timeout after 800 us) 2877 */ 2878 intel_dp_start_link_train(state, intel_dp, crtc_state); 2879 2880 /* 7.k Set DP_TP_CTL link training to Normal */ 2881 if (!is_trans_port_sync_mode(crtc_state)) 2882 intel_dp_stop_link_train(intel_dp, crtc_state); 2883 2884 /* 7.l Configure and enable FEC if needed */ 2885 intel_ddi_enable_fec(encoder, crtc_state); 2886 2887 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2888 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2889 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2890 if (ret < 0) 2891 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2892 } 2893 2894 if (!is_mst) 2895 intel_dsc_dp_pps_write(encoder, crtc_state); 2896 } 2897 2898 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2899 struct intel_encoder *encoder, 2900 const struct intel_crtc_state *crtc_state, 2901 const struct drm_connector_state *conn_state) 2902 { 2903 struct intel_display *display = to_intel_display(encoder); 2904 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2905 enum port port = encoder->port; 2906 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2907 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2908 2909 if (DISPLAY_VER(display) < 11) 2910 drm_WARN_ON(display->drm, 2911 is_mst && (port == PORT_A || port == PORT_E)); 2912 else 2913 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2914 2915 intel_dp_set_link_params(intel_dp, 2916 crtc_state->port_clock, 2917 crtc_state->lane_count); 2918 2919 /* 2920 * We only configure what the register value will be here. Actual 2921 * enabling happens during link training farther down. 2922 */ 2923 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2924 2925 intel_pps_on(intel_dp); 2926 2927 intel_ddi_enable_clock(encoder, crtc_state); 2928 2929 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2930 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2931 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2932 dig_port->ddi_io_power_domain); 2933 } 2934 2935 icl_program_mg_dp_mode(dig_port, crtc_state); 2936 2937 if (has_buf_trans_select(display)) 2938 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2939 2940 encoder->set_signal_levels(encoder, crtc_state); 2941 2942 intel_ddi_power_up_lanes(encoder, crtc_state); 2943 2944 if (!is_mst) 2945 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2946 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2947 if (!is_mst) 2948 intel_dp_sink_enable_decompression(state, 2949 to_intel_connector(conn_state->connector), 2950 crtc_state); 2951 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2952 intel_dp_start_link_train(state, intel_dp, crtc_state); 2953 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2954 !is_trans_port_sync_mode(crtc_state)) 2955 intel_dp_stop_link_train(intel_dp, crtc_state); 2956 2957 intel_ddi_enable_fec(encoder, crtc_state); 2958 2959 if (!is_mst) { 2960 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2961 intel_dsc_dp_pps_write(encoder, crtc_state); 2962 } 2963 } 2964 2965 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2966 struct intel_encoder *encoder, 2967 const struct intel_crtc_state *crtc_state, 2968 const struct drm_connector_state *conn_state) 2969 { 2970 struct intel_display *display = to_intel_display(encoder); 2971 2972 if (HAS_DP20(display)) 2973 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2974 crtc_state); 2975 2976 /* Panel replay has to be enabled in sink dpcd before link training. */ 2977 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2978 2979 if (DISPLAY_VER(display) >= 14) 2980 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2981 else if (DISPLAY_VER(display) >= 12) 2982 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2983 else 2984 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2985 2986 /* MST will call a setting of MSA after an allocating of Virtual Channel 2987 * from MST encoder pre_enable callback. 2988 */ 2989 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2990 intel_ddi_set_dp_msa(crtc_state, conn_state); 2991 } 2992 2993 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2994 struct intel_encoder *encoder, 2995 const struct intel_crtc_state *crtc_state, 2996 const struct drm_connector_state *conn_state) 2997 { 2998 struct intel_display *display = to_intel_display(encoder); 2999 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3000 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3001 3002 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 3003 intel_ddi_enable_clock(encoder, crtc_state); 3004 3005 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 3006 dig_port->ddi_io_wakeref = intel_display_power_get(display, 3007 dig_port->ddi_io_power_domain); 3008 3009 icl_program_mg_dp_mode(dig_port, crtc_state); 3010 3011 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 3012 3013 dig_port->set_infoframes(encoder, 3014 crtc_state->has_infoframe, 3015 crtc_state, conn_state); 3016 } 3017 3018 /* 3019 * Note: Also called from the ->pre_enable of the first active MST stream 3020 * encoder on its primary encoder. 3021 * 3022 * When called from DP MST code: 3023 * 3024 * - conn_state will be NULL 3025 * 3026 * - encoder will be the primary encoder (i.e. mst->primary) 3027 * 3028 * - the main connector associated with this port won't be active or linked to a 3029 * crtc 3030 * 3031 * - crtc_state will be the state of the first stream to be activated on this 3032 * port, and it may not be the same stream that will be deactivated last, but 3033 * each stream should have a state that is identical when it comes to the DP 3034 * link parameters. 3035 */ 3036 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3037 struct intel_encoder *encoder, 3038 const struct intel_crtc_state *crtc_state, 3039 const struct drm_connector_state *conn_state) 3040 { 3041 struct intel_display *display = to_intel_display(state); 3042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3043 enum pipe pipe = crtc->pipe; 3044 3045 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3046 3047 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3048 3049 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3050 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3051 conn_state); 3052 } else { 3053 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3054 3055 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3056 conn_state); 3057 3058 /* FIXME precompute everything properly */ 3059 /* FIXME how do we turn infoframes off again? */ 3060 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3061 dig_port->set_infoframes(encoder, 3062 crtc_state->has_infoframe, 3063 crtc_state, conn_state); 3064 } 3065 } 3066 3067 static void 3068 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3069 { 3070 struct intel_display *display = to_intel_display(encoder); 3071 enum port port = encoder->port; 3072 intel_reg_t reg; 3073 u32 clr_bits, wait_bits; 3074 int ret; 3075 3076 if (DISPLAY_VER(display) < 14) 3077 return; 3078 3079 if (DISPLAY_VER(display) >= 20) { 3080 reg = DDI_BUF_CTL(port); 3081 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3082 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3083 } else { 3084 reg = XELPDP_PORT_BUF_CTL1(display, port); 3085 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3086 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3087 } 3088 3089 intel_de_rmw(display, reg, clr_bits, 0); 3090 3091 ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100); 3092 if (ret) 3093 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3094 port_name(port)); 3095 } 3096 3097 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3098 { 3099 struct intel_display *display = to_intel_display(encoder); 3100 enum port port = encoder->port; 3101 3102 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3103 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3104 3105 intel_wait_ddi_buf_active(encoder); 3106 } 3107 3108 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3109 const struct intel_crtc_state *crtc_state) 3110 { 3111 struct intel_display *display = to_intel_display(encoder); 3112 enum port port = encoder->port; 3113 3114 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3115 3116 if (DISPLAY_VER(display) >= 14) 3117 intel_wait_ddi_buf_idle(display, port); 3118 3119 mtl_ddi_disable_d2d(encoder); 3120 3121 if (intel_crtc_has_dp_encoder(crtc_state)) { 3122 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3123 DP_TP_CTL_ENABLE, 0); 3124 } 3125 3126 intel_ddi_disable_fec(encoder, crtc_state); 3127 3128 if (DISPLAY_VER(display) < 14) 3129 intel_wait_ddi_buf_idle(display, port); 3130 3131 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3132 } 3133 3134 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3135 struct intel_encoder *encoder, 3136 const struct intel_crtc_state *old_crtc_state, 3137 const struct drm_connector_state *old_conn_state) 3138 { 3139 struct intel_display *display = to_intel_display(encoder); 3140 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3141 struct intel_dp *intel_dp = &dig_port->dp; 3142 struct ref_tracker *wakeref; 3143 bool is_mst = intel_crtc_has_type(old_crtc_state, 3144 INTEL_OUTPUT_DP_MST); 3145 3146 if (!is_mst) 3147 intel_dp_set_infoframes(encoder, false, 3148 old_crtc_state, old_conn_state); 3149 3150 /* 3151 * Power down sink before disabling the port, otherwise we end 3152 * up getting interrupts from the sink on detecting link loss. 3153 */ 3154 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3155 3156 if (DISPLAY_VER(display) >= 12) { 3157 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3158 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3159 3160 intel_de_rmw(display, 3161 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3162 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3163 0); 3164 } 3165 } else { 3166 if (!is_mst) 3167 intel_ddi_disable_transcoder_clock(old_crtc_state); 3168 } 3169 3170 intel_ddi_buf_disable(encoder, old_crtc_state); 3171 3172 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3173 3174 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3175 3176 /* 3177 * From TGL spec: "If single stream or multi-stream master transcoder: 3178 * Configure Transcoder Clock select to direct no clock to the 3179 * transcoder" 3180 */ 3181 if (DISPLAY_VER(display) >= 12) 3182 intel_ddi_disable_transcoder_clock(old_crtc_state); 3183 3184 intel_pps_vdd_on(intel_dp); 3185 intel_pps_off(intel_dp); 3186 3187 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3188 3189 if (wakeref) 3190 intel_display_power_put(display, 3191 dig_port->ddi_io_power_domain, 3192 wakeref); 3193 3194 intel_ddi_disable_clock(encoder); 3195 3196 /* De-select Thunderbolt */ 3197 if (DISPLAY_VER(display) >= 14) 3198 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3199 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3200 } 3201 3202 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3203 struct intel_encoder *encoder, 3204 const struct intel_crtc_state *old_crtc_state, 3205 const struct drm_connector_state *old_conn_state) 3206 { 3207 struct intel_display *display = to_intel_display(encoder); 3208 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3209 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3210 struct ref_tracker *wakeref; 3211 3212 dig_port->set_infoframes(encoder, false, 3213 old_crtc_state, old_conn_state); 3214 3215 if (DISPLAY_VER(display) < 12) 3216 intel_ddi_disable_transcoder_clock(old_crtc_state); 3217 3218 intel_ddi_buf_disable(encoder, old_crtc_state); 3219 3220 if (DISPLAY_VER(display) >= 12) 3221 intel_ddi_disable_transcoder_clock(old_crtc_state); 3222 3223 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3224 if (wakeref) 3225 intel_display_power_put(display, 3226 dig_port->ddi_io_power_domain, 3227 wakeref); 3228 3229 intel_ddi_disable_clock(encoder); 3230 3231 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3232 } 3233 3234 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3235 struct intel_encoder *encoder, 3236 const struct intel_crtc_state *old_crtc_state, 3237 const struct drm_connector_state *old_conn_state) 3238 { 3239 struct intel_display *display = to_intel_display(encoder); 3240 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3241 struct intel_crtc *pipe_crtc; 3242 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3243 3244 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) { 3245 const struct intel_crtc_state *old_pipe_crtc_state = 3246 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3247 3248 intel_crtc_vblank_off(old_pipe_crtc_state); 3249 } 3250 3251 intel_disable_transcoder(old_crtc_state); 3252 3253 /* 128b/132b SST */ 3254 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3255 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3256 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3257 3258 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3259 3260 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3261 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3262 3263 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3264 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3265 } 3266 3267 intel_vrr_transcoder_disable(old_crtc_state); 3268 3269 intel_ddi_disable_transcoder_func(old_crtc_state); 3270 3271 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state) { 3272 const struct intel_crtc_state *old_pipe_crtc_state = 3273 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3274 3275 intel_dsc_disable(old_pipe_crtc_state); 3276 3277 if (DISPLAY_VER(display) >= 9) 3278 skl_scaler_disable(old_pipe_crtc_state); 3279 else 3280 ilk_pfit_disable(old_pipe_crtc_state); 3281 } 3282 } 3283 3284 /* 3285 * Note: Also called from the ->post_disable of the last active MST stream 3286 * encoder on its primary encoder. See also the comment for 3287 * intel_ddi_pre_enable(). 3288 */ 3289 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3290 struct intel_encoder *encoder, 3291 const struct intel_crtc_state *old_crtc_state, 3292 const struct drm_connector_state *old_conn_state) 3293 { 3294 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3295 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3296 old_conn_state); 3297 3298 /* 3299 * When called from DP MST code: 3300 * - old_conn_state will be NULL 3301 * - encoder will be the main encoder (ie. mst->primary) 3302 * - the main connector associated with this port 3303 * won't be active or linked to a crtc 3304 * - old_crtc_state will be the state of the last stream to 3305 * be deactivated on this port, and it may not be the same 3306 * stream that was activated last, but each stream 3307 * should have a state that is identical when it comes to 3308 * the DP link parameters 3309 */ 3310 3311 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3312 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3313 old_conn_state); 3314 else 3315 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3316 old_conn_state); 3317 } 3318 3319 /* 3320 * Note: Also called from the ->post_pll_disable of the last active MST stream 3321 * encoder on its primary encoder. See also the comment for 3322 * intel_ddi_pre_enable(). 3323 */ 3324 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3325 struct intel_encoder *encoder, 3326 const struct intel_crtc_state *old_crtc_state, 3327 const struct drm_connector_state *old_conn_state) 3328 { 3329 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3330 3331 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3332 3333 if (intel_encoder_is_tc(encoder)) 3334 intel_tc_port_put_link(dig_port); 3335 } 3336 3337 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3338 struct intel_encoder *encoder, 3339 const struct intel_crtc_state *crtc_state) 3340 { 3341 const struct drm_connector_state *conn_state; 3342 struct drm_connector *conn; 3343 int i; 3344 3345 if (!crtc_state->sync_mode_slaves_mask) 3346 return; 3347 3348 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3349 struct intel_encoder *slave_encoder = 3350 to_intel_encoder(conn_state->best_encoder); 3351 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3352 const struct intel_crtc_state *slave_crtc_state; 3353 3354 if (!slave_crtc) 3355 continue; 3356 3357 slave_crtc_state = 3358 intel_atomic_get_new_crtc_state(state, slave_crtc); 3359 3360 if (slave_crtc_state->master_transcoder != 3361 crtc_state->cpu_transcoder) 3362 continue; 3363 3364 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3365 slave_crtc_state); 3366 } 3367 3368 usleep_range(200, 400); 3369 3370 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3371 crtc_state); 3372 } 3373 3374 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3375 struct intel_encoder *encoder, 3376 const struct intel_crtc_state *crtc_state, 3377 const struct drm_connector_state *conn_state) 3378 { 3379 struct intel_display *display = to_intel_display(encoder); 3380 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3381 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3382 enum port port = encoder->port; 3383 3384 if (port == PORT_A && DISPLAY_VER(display) < 9) 3385 intel_dp_stop_link_train(intel_dp, crtc_state); 3386 3387 drm_connector_update_privacy_screen(conn_state); 3388 intel_edp_backlight_on(crtc_state, conn_state); 3389 3390 intel_panel_prepare(crtc_state, conn_state); 3391 3392 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3393 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3394 3395 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3396 } 3397 3398 static intel_reg_t 3399 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3400 { 3401 static const enum transcoder trans[] = { 3402 [PORT_A] = TRANSCODER_EDP, 3403 [PORT_B] = TRANSCODER_A, 3404 [PORT_C] = TRANSCODER_B, 3405 [PORT_D] = TRANSCODER_C, 3406 [PORT_E] = TRANSCODER_A, 3407 }; 3408 3409 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3410 3411 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3412 port = PORT_A; 3413 3414 return CHICKEN_TRANS(display, trans[port]); 3415 } 3416 3417 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3418 struct intel_encoder *encoder, 3419 const struct intel_crtc_state *crtc_state, 3420 const struct drm_connector_state *conn_state) 3421 { 3422 struct intel_display *display = to_intel_display(encoder); 3423 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3424 struct drm_connector *connector = conn_state->connector; 3425 enum port port = encoder->port; 3426 u32 buf_ctl = 0; 3427 3428 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3429 crtc_state->hdmi_high_tmds_clock_ratio, 3430 crtc_state->hdmi_scrambling)) 3431 drm_dbg_kms(display->drm, 3432 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3433 connector->base.id, connector->name); 3434 3435 if (has_buf_trans_select(display)) 3436 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3437 3438 /* e. Enable D2D Link for C10/C20 Phy */ 3439 mtl_ddi_enable_d2d(encoder); 3440 3441 encoder->set_signal_levels(encoder, crtc_state); 3442 3443 /* Display WA #1143: skl,kbl,cfl */ 3444 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3445 /* 3446 * For some reason these chicken bits have been 3447 * stuffed into a transcoder register, event though 3448 * the bits affect a specific DDI port rather than 3449 * a specific transcoder. 3450 */ 3451 intel_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3452 u32 val; 3453 3454 val = intel_de_read(display, reg); 3455 3456 if (port == PORT_E) 3457 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3458 DDIE_TRAINING_OVERRIDE_VALUE; 3459 else 3460 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3461 DDI_TRAINING_OVERRIDE_VALUE; 3462 3463 intel_de_write(display, reg, val); 3464 intel_de_posting_read(display, reg); 3465 3466 udelay(1); 3467 3468 if (port == PORT_E) 3469 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3470 DDIE_TRAINING_OVERRIDE_VALUE); 3471 else 3472 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3473 DDI_TRAINING_OVERRIDE_VALUE); 3474 3475 intel_de_write(display, reg, val); 3476 } 3477 3478 intel_ddi_power_up_lanes(encoder, crtc_state); 3479 3480 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3481 * are ignored so nothing special needs to be done besides 3482 * enabling the port. 3483 * 3484 * On ADL_P the PHY link rate and lane count must be programmed but 3485 * these are both 0 for HDMI. 3486 * 3487 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3488 * is filled with lane count, already set in the crtc_state. 3489 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3490 */ 3491 if (dig_port->lane_reversal) 3492 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3493 if (dig_port->ddi_a_4_lanes) 3494 buf_ctl |= DDI_A_4_LANES; 3495 3496 if (DISPLAY_VER(display) >= 14) { 3497 u32 port_buf = 0; 3498 3499 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3500 3501 if (dig_port->lane_reversal) 3502 port_buf |= XELPDP_PORT_REVERSAL; 3503 3504 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3505 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3506 3507 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3508 3509 if (DISPLAY_VER(display) >= 20) 3510 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3511 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3512 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3513 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3514 } 3515 3516 intel_ddi_buf_enable(encoder, buf_ctl); 3517 3518 intel_hdmi_poll_for_scrambling_enable(crtc_state, connector); 3519 } 3520 3521 static void intel_ddi_enable(struct intel_atomic_state *state, 3522 struct intel_encoder *encoder, 3523 const struct intel_crtc_state *crtc_state, 3524 const struct drm_connector_state *conn_state) 3525 { 3526 struct intel_display *display = to_intel_display(encoder); 3527 struct intel_crtc *pipe_crtc; 3528 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3529 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3530 3531 /* 128b/132b SST */ 3532 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3533 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3534 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3535 3536 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3537 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3538 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3539 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3540 } 3541 3542 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3543 3544 intel_vrr_transcoder_enable(crtc_state); 3545 3546 /* 128b/132b SST */ 3547 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3548 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3549 3550 intel_ddi_clear_act_sent(encoder, crtc_state); 3551 3552 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3553 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3554 3555 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3556 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3557 } 3558 3559 intel_enable_transcoder(crtc_state); 3560 3561 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3562 3563 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) { 3564 const struct intel_crtc_state *pipe_crtc_state = 3565 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3566 3567 intel_crtc_vblank_on(pipe_crtc_state); 3568 } 3569 3570 if (is_hdmi) 3571 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3572 else 3573 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3574 3575 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3576 3577 } 3578 3579 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3580 struct intel_encoder *encoder, 3581 const struct intel_crtc_state *old_crtc_state, 3582 const struct drm_connector_state *old_conn_state) 3583 { 3584 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3585 struct intel_connector *connector = 3586 to_intel_connector(old_conn_state->connector); 3587 3588 intel_dp->link.active = false; 3589 3590 intel_panel_unprepare(old_conn_state); 3591 intel_psr_disable(intel_dp, old_crtc_state); 3592 intel_alpm_disable(intel_dp); 3593 intel_edp_backlight_off(old_conn_state); 3594 /* Disable the decompression in DP Sink */ 3595 intel_dp_sink_disable_decompression(state, 3596 connector, old_crtc_state); 3597 /* Disable Ignore_MSA bit in DP Sink */ 3598 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3599 false); 3600 } 3601 3602 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3603 struct intel_encoder *encoder, 3604 const struct intel_crtc_state *old_crtc_state, 3605 const struct drm_connector_state *old_conn_state) 3606 { 3607 struct intel_display *display = to_intel_display(encoder); 3608 struct drm_connector *connector = old_conn_state->connector; 3609 3610 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3611 false, false)) 3612 drm_dbg_kms(display->drm, 3613 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3614 connector->base.id, connector->name); 3615 } 3616 3617 static void intel_ddi_disable(struct intel_atomic_state *state, 3618 struct intel_encoder *encoder, 3619 const struct intel_crtc_state *old_crtc_state, 3620 const struct drm_connector_state *old_conn_state) 3621 { 3622 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3623 3624 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3625 3626 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3627 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3628 old_conn_state); 3629 else 3630 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3631 old_conn_state); 3632 } 3633 3634 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3635 struct intel_encoder *encoder, 3636 const struct intel_crtc_state *crtc_state, 3637 const struct drm_connector_state *conn_state) 3638 { 3639 intel_ddi_set_dp_msa(crtc_state, conn_state); 3640 3641 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3642 3643 intel_backlight_update(state, encoder, crtc_state, conn_state); 3644 drm_connector_update_privacy_screen(conn_state); 3645 } 3646 3647 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3648 const struct intel_crtc_state *crtc_state, 3649 const struct drm_connector_state *conn_state) 3650 { 3651 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3652 } 3653 3654 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3655 struct intel_encoder *encoder, 3656 const struct intel_crtc_state *crtc_state, 3657 const struct drm_connector_state *conn_state) 3658 { 3659 3660 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3661 !intel_encoder_is_mst(encoder)) 3662 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3663 conn_state); 3664 3665 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3666 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3667 conn_state); 3668 3669 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3670 } 3671 3672 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3673 struct intel_encoder *encoder, 3674 struct intel_crtc *crtc) 3675 { 3676 struct intel_display *display = to_intel_display(encoder); 3677 const struct intel_crtc_state *crtc_state = 3678 intel_atomic_get_new_crtc_state(state, crtc); 3679 struct intel_crtc *pipe_crtc; 3680 3681 /* FIXME: Add NVL+ and DG2 pll_mgr */ 3682 if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr) 3683 return; 3684 3685 for_each_intel_crtc_in_pipe_mask(display, pipe_crtc, 3686 intel_crtc_joined_pipe_mask(crtc_state)) 3687 intel_dpll_update_active(state, pipe_crtc, encoder); 3688 } 3689 3690 /* 3691 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3692 * encoder on its primary encoder. See also the comment for 3693 * intel_ddi_pre_enable(). 3694 */ 3695 static void 3696 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3697 struct intel_encoder *encoder, 3698 const struct intel_crtc_state *crtc_state, 3699 const struct drm_connector_state *conn_state) 3700 { 3701 struct intel_display *display = to_intel_display(encoder); 3702 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3703 bool is_tc_port = intel_encoder_is_tc(encoder); 3704 3705 if (is_tc_port) { 3706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3707 3708 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3709 intel_ddi_update_active_dpll(state, encoder, crtc); 3710 } 3711 3712 main_link_aux_power_domain_get(dig_port, crtc_state); 3713 3714 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3715 /* 3716 * Program the lane count for static/dynamic connections on 3717 * Type-C ports. Skip this step for TBT. 3718 */ 3719 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3720 else if (display->platform.geminilake || display->platform.broxton) 3721 bxt_dpio_phy_set_lane_optim_mask(encoder, 3722 crtc_state->lane_lat_optim_mask); 3723 3724 /* 3725 * There is no direct connection between the PLL and PPS, however 3726 * enabling PPS before PLL is required to avoid PLL/DDI BUF timeouts 3727 * during system resume. Do that matching the Bspec order as well. 3728 */ 3729 if (DISPLAY_VER(display) >= 14) 3730 intel_pps_on(&dig_port->dp); 3731 } 3732 3733 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3734 { 3735 struct intel_display *display = to_intel_display(encoder); 3736 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3737 int ln; 3738 3739 for (ln = 0; ln < 2; ln++) 3740 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3741 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3742 } 3743 3744 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3745 const struct intel_crtc_state *crtc_state) 3746 { 3747 struct intel_display *display = to_intel_display(crtc_state); 3748 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3749 struct intel_encoder *encoder = &dig_port->base; 3750 u32 dp_tp_ctl; 3751 3752 /* 3753 * TODO: To train with only a different voltage swing entry is not 3754 * necessary disable and enable port 3755 */ 3756 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3757 3758 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3759 3760 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3761 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3762 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3763 intel_dp_is_uhbr(crtc_state)) { 3764 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3765 } else { 3766 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3767 if (crtc_state->enhanced_framing) 3768 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3769 } 3770 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3771 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3772 3773 /* 6.f Enable D2D Link */ 3774 mtl_ddi_enable_d2d(encoder); 3775 3776 /* 6.g Configure voltage swing and related IO settings */ 3777 encoder->set_signal_levels(encoder, crtc_state); 3778 3779 /* 6.h Configure PORT_BUF_CTL1 */ 3780 mtl_port_buf_ctl_program(encoder, crtc_state); 3781 3782 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3783 if (DISPLAY_VER(display) >= 20) 3784 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3785 3786 intel_ddi_buf_enable(encoder, intel_dp->DP); 3787 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3788 3789 /* 3790 * 6.k If AUX-Less ALPM is going to be enabled: 3791 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here 3792 */ 3793 intel_alpm_port_configure(intel_dp, crtc_state); 3794 3795 /* 3796 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE 3797 * register 3798 */ 3799 intel_lnl_mac_transmit_lfps(encoder, crtc_state); 3800 } 3801 3802 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3803 const struct intel_crtc_state *crtc_state) 3804 { 3805 struct intel_display *display = to_intel_display(intel_dp); 3806 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3807 struct intel_encoder *encoder = &dig_port->base; 3808 u32 dp_tp_ctl; 3809 3810 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3811 3812 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3813 3814 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3815 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3816 intel_dp_is_uhbr(crtc_state)) { 3817 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3818 } else { 3819 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3820 if (crtc_state->enhanced_framing) 3821 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3822 } 3823 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3824 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3825 3826 if (display->platform.alderlake_p && 3827 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3828 adlp_tbt_to_dp_alt_switch_wa(encoder); 3829 3830 intel_ddi_buf_enable(encoder, intel_dp->DP); 3831 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3832 } 3833 3834 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3835 const struct intel_crtc_state *crtc_state, 3836 u8 dp_train_pat) 3837 { 3838 struct intel_display *display = to_intel_display(intel_dp); 3839 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3840 u32 temp; 3841 3842 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3843 3844 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3845 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3846 case DP_TRAINING_PATTERN_DISABLE: 3847 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3848 break; 3849 case DP_TRAINING_PATTERN_1: 3850 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3851 break; 3852 case DP_TRAINING_PATTERN_2: 3853 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3854 break; 3855 case DP_TRAINING_PATTERN_3: 3856 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3857 break; 3858 case DP_TRAINING_PATTERN_4: 3859 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3860 break; 3861 } 3862 3863 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3864 } 3865 3866 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3867 const struct intel_crtc_state *crtc_state) 3868 { 3869 struct intel_display *display = to_intel_display(intel_dp); 3870 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3871 enum port port = encoder->port; 3872 3873 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3874 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3875 3876 /* 3877 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3878 * reason we need to set idle transmission mode is to work around a HW 3879 * issue where we enable the pipe while not in idle link-training mode. 3880 * In this case there is requirement to wait for a minimum number of 3881 * idle patterns to be sent. 3882 */ 3883 if (port == PORT_A && DISPLAY_VER(display) < 12) 3884 return; 3885 3886 if (intel_de_wait_for_set_ms(display, 3887 dp_tp_status_reg(encoder, crtc_state), 3888 DP_TP_STATUS_IDLE_DONE, 2)) 3889 drm_err(display->drm, 3890 "Timed out waiting for DP idle patterns\n"); 3891 } 3892 3893 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3894 enum transcoder cpu_transcoder) 3895 { 3896 if (cpu_transcoder == TRANSCODER_EDP) 3897 return false; 3898 3899 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3900 return false; 3901 3902 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3903 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3904 } 3905 3906 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3907 { 3908 if (crtc_state->port_clock > 594000) 3909 return 2; 3910 else 3911 return 0; 3912 } 3913 3914 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3915 { 3916 if (crtc_state->port_clock > 594000) 3917 return 3; 3918 else 3919 return 0; 3920 } 3921 3922 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3923 { 3924 if (crtc_state->port_clock > 594000) 3925 return 1; 3926 else 3927 return 0; 3928 } 3929 3930 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3931 { 3932 struct intel_display *display = to_intel_display(crtc_state); 3933 3934 if (DISPLAY_VER(display) >= 14) 3935 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3936 else if (DISPLAY_VER(display) >= 12) 3937 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3938 else if (display->platform.jasperlake || display->platform.elkhartlake) 3939 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3940 else if (DISPLAY_VER(display) >= 11) 3941 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3942 } 3943 3944 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3945 enum transcoder cpu_transcoder) 3946 { 3947 u32 master_select; 3948 3949 if (DISPLAY_VER(display) >= 11) { 3950 u32 ctl2 = intel_de_read(display, 3951 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3952 3953 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3954 return INVALID_TRANSCODER; 3955 3956 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3957 } else { 3958 u32 ctl = intel_de_read(display, 3959 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3960 3961 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3962 return INVALID_TRANSCODER; 3963 3964 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3965 } 3966 3967 if (master_select == 0) 3968 return TRANSCODER_EDP; 3969 else 3970 return master_select - 1; 3971 } 3972 3973 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3974 { 3975 struct intel_display *display = to_intel_display(crtc_state); 3976 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3977 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3978 enum transcoder cpu_transcoder; 3979 3980 crtc_state->master_transcoder = 3981 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3982 3983 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3984 enum intel_display_power_domain power_domain; 3985 struct ref_tracker *trans_wakeref; 3986 3987 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3988 trans_wakeref = intel_display_power_get_if_enabled(display, 3989 power_domain); 3990 3991 if (!trans_wakeref) 3992 continue; 3993 3994 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3995 crtc_state->cpu_transcoder) 3996 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3997 3998 intel_display_power_put(display, power_domain, trans_wakeref); 3999 } 4000 4001 drm_WARN_ON(display->drm, 4002 crtc_state->master_transcoder != INVALID_TRANSCODER && 4003 crtc_state->sync_mode_slaves_mask); 4004 } 4005 4006 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 4007 struct intel_crtc_state *crtc_state, 4008 u32 ddi_func_ctl) 4009 { 4010 struct intel_display *display = to_intel_display(encoder); 4011 4012 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 4013 if (DISPLAY_VER(display) >= 14) 4014 crtc_state->lane_count = 4015 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4016 else 4017 crtc_state->lane_count = 4; 4018 } 4019 4020 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 4021 struct intel_crtc_state *crtc_state, 4022 u32 ddi_func_ctl) 4023 { 4024 crtc_state->has_hdmi_sink = true; 4025 4026 crtc_state->infoframes.enable |= 4027 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4028 4029 if (crtc_state->infoframes.enable) 4030 crtc_state->has_infoframe = true; 4031 4032 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4033 crtc_state->hdmi_scrambling = true; 4034 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4035 crtc_state->hdmi_high_tmds_clock_ratio = true; 4036 4037 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4038 } 4039 4040 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4041 struct intel_crtc_state *crtc_state, 4042 u32 ddi_func_ctl) 4043 { 4044 struct intel_display *display = to_intel_display(encoder); 4045 4046 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4047 crtc_state->enhanced_framing = 4048 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4049 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4050 } 4051 4052 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4053 struct intel_crtc_state *crtc_state, 4054 u32 ddi_func_ctl) 4055 { 4056 struct intel_display *display = to_intel_display(encoder); 4057 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4058 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4059 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4060 4061 if (encoder->type == INTEL_OUTPUT_EDP) 4062 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4063 else 4064 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4065 crtc_state->lane_count = 4066 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4067 4068 if (DISPLAY_VER(display) >= 12 && 4069 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4070 crtc_state->mst_master_transcoder = 4071 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4072 4073 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4074 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4075 4076 crtc_state->enhanced_framing = 4077 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4078 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4079 4080 if (DISPLAY_VER(display) >= 11) 4081 crtc_state->fec_enable = 4082 intel_de_read(display, 4083 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4084 4085 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4086 crtc_state->infoframes.enable |= 4087 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4088 else 4089 crtc_state->infoframes.enable |= 4090 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4091 } 4092 4093 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4094 struct intel_crtc_state *crtc_state, 4095 u32 ddi_func_ctl) 4096 { 4097 struct intel_display *display = to_intel_display(encoder); 4098 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4099 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4100 4101 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4102 crtc_state->lane_count = 4103 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4104 4105 if (DISPLAY_VER(display) >= 12) 4106 crtc_state->mst_master_transcoder = 4107 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4108 4109 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4110 4111 if (DISPLAY_VER(display) >= 11) 4112 crtc_state->fec_enable = 4113 intel_de_read(display, 4114 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4115 4116 crtc_state->infoframes.enable |= 4117 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4118 } 4119 4120 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4121 struct intel_crtc_state *pipe_config) 4122 { 4123 struct intel_display *display = to_intel_display(encoder); 4124 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4125 u32 ddi_func_ctl, ddi_mode, flags = 0; 4126 4127 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4128 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4129 flags |= DRM_MODE_FLAG_PHSYNC; 4130 else 4131 flags |= DRM_MODE_FLAG_NHSYNC; 4132 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4133 flags |= DRM_MODE_FLAG_PVSYNC; 4134 else 4135 flags |= DRM_MODE_FLAG_NVSYNC; 4136 4137 pipe_config->hw.adjusted_mode.flags |= flags; 4138 4139 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4140 case TRANS_DDI_BPC_6: 4141 pipe_config->pipe_bpp = 18; 4142 break; 4143 case TRANS_DDI_BPC_8: 4144 pipe_config->pipe_bpp = 24; 4145 break; 4146 case TRANS_DDI_BPC_10: 4147 pipe_config->pipe_bpp = 30; 4148 break; 4149 case TRANS_DDI_BPC_12: 4150 pipe_config->pipe_bpp = 36; 4151 break; 4152 default: 4153 break; 4154 } 4155 4156 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4157 4158 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4159 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4160 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4161 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4162 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4163 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4164 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4165 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4166 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4167 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4168 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4169 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4170 4171 /* 4172 * If this is true, we know we're being called from mst stream 4173 * encoder's ->get_config(). 4174 */ 4175 if (intel_dp_mst_active_streams(intel_dp)) 4176 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4177 else 4178 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4179 } 4180 } 4181 4182 /* 4183 * Note: Also called from the ->get_config of the MST stream encoders on their 4184 * primary encoder, via the platform specific hooks here. See also the comment 4185 * for intel_ddi_pre_enable(). 4186 */ 4187 static void intel_ddi_get_config(struct intel_encoder *encoder, 4188 struct intel_crtc_state *pipe_config) 4189 { 4190 struct intel_display *display = to_intel_display(encoder); 4191 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4192 4193 /* XXX: DSI transcoder paranoia */ 4194 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4195 return; 4196 4197 intel_ddi_read_func_ctl(encoder, pipe_config); 4198 4199 intel_ddi_mso_get_config(encoder, pipe_config); 4200 4201 pipe_config->has_audio = 4202 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4203 4204 if (encoder->type == INTEL_OUTPUT_EDP) 4205 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4206 4207 ddi_dotclock_get(pipe_config); 4208 4209 if (display->platform.geminilake || display->platform.broxton) 4210 pipe_config->lane_lat_optim_mask = 4211 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4212 4213 intel_ddi_compute_min_voltage_level(pipe_config); 4214 4215 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4216 4217 intel_read_infoframe(encoder, pipe_config, 4218 HDMI_INFOFRAME_TYPE_AVI, 4219 &pipe_config->infoframes.avi); 4220 intel_read_infoframe(encoder, pipe_config, 4221 HDMI_INFOFRAME_TYPE_SPD, 4222 &pipe_config->infoframes.spd); 4223 intel_read_infoframe(encoder, pipe_config, 4224 HDMI_INFOFRAME_TYPE_VENDOR, 4225 &pipe_config->infoframes.hdmi); 4226 intel_read_infoframe(encoder, pipe_config, 4227 HDMI_INFOFRAME_TYPE_DRM, 4228 &pipe_config->infoframes.drm); 4229 4230 if (DISPLAY_VER(display) >= 8) 4231 bdw_get_trans_port_sync_config(pipe_config); 4232 4233 intel_psr_get_config(encoder, pipe_config); 4234 4235 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4236 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4237 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4238 4239 intel_audio_codec_get_config(encoder, pipe_config); 4240 } 4241 4242 void intel_ddi_get_clock(struct intel_encoder *encoder, 4243 struct intel_crtc_state *crtc_state, 4244 struct intel_dpll *pll) 4245 { 4246 struct intel_display *display = to_intel_display(encoder); 4247 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4248 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4249 bool pll_active; 4250 4251 if (drm_WARN_ON(display->drm, !pll)) 4252 return; 4253 4254 port_dpll->pll = pll; 4255 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4256 drm_WARN_ON(display->drm, !pll_active); 4257 4258 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4259 4260 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4261 &crtc_state->dpll_hw_state); 4262 } 4263 4264 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4265 { 4266 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4267 } 4268 4269 static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder, 4270 struct intel_crtc_state *crtc_state, 4271 enum icl_port_dpll_id port_dpll_id, 4272 enum intel_dpll_id pll_id) 4273 { 4274 struct intel_display *display = to_intel_display(encoder); 4275 struct icl_port_dpll *port_dpll; 4276 struct intel_dpll *pll; 4277 bool pll_active; 4278 4279 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4280 pll = intel_get_dpll_by_id(display, pll_id); 4281 4282 if (drm_WARN_ON(display->drm, !pll)) 4283 return; 4284 4285 port_dpll->pll = pll; 4286 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4287 drm_WARN_ON(display->drm, !pll_active); 4288 4289 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4290 4291 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4292 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4293 else 4294 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4295 &crtc_state->dpll_hw_state); 4296 4297 intel_ddi_get_config(encoder, crtc_state); 4298 } 4299 4300 /* 4301 * Get the configuration for either a port using a C10 PHY PLL, or a port using a 4302 * C20 PHY PLL in the cases of: 4303 * - BMG port A/B 4304 * - PTL port B eDP over TypeC PHY 4305 */ 4306 static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder, 4307 struct intel_crtc_state *crtc_state) 4308 { 4309 struct intel_display *display = to_intel_display(encoder); 4310 4311 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4312 mtl_port_to_pll_id(display, encoder->port)); 4313 } 4314 4315 static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder, 4316 struct intel_crtc_state *crtc_state) 4317 { 4318 struct intel_display *display = to_intel_display(encoder); 4319 4320 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 4321 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4322 DPLL_ID_ICL_TBTPLL); 4323 else 4324 mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY, 4325 mtl_port_to_pll_id(display, encoder->port)); 4326 } 4327 4328 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4329 struct intel_crtc_state *crtc_state) 4330 { 4331 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4332 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4333 4334 intel_ddi_get_config(encoder, crtc_state); 4335 } 4336 4337 static void adls_ddi_get_config(struct intel_encoder *encoder, 4338 struct intel_crtc_state *crtc_state) 4339 { 4340 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4341 intel_ddi_get_config(encoder, crtc_state); 4342 } 4343 4344 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4345 struct intel_crtc_state *crtc_state) 4346 { 4347 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4348 intel_ddi_get_config(encoder, crtc_state); 4349 } 4350 4351 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4352 struct intel_crtc_state *crtc_state) 4353 { 4354 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4355 intel_ddi_get_config(encoder, crtc_state); 4356 } 4357 4358 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4359 struct intel_crtc_state *crtc_state) 4360 { 4361 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4362 intel_ddi_get_config(encoder, crtc_state); 4363 } 4364 4365 static enum icl_port_dpll_id 4366 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4367 const struct intel_crtc_state *crtc_state) 4368 { 4369 struct intel_display *display = to_intel_display(encoder); 4370 const struct intel_dpll *pll = crtc_state->intel_dpll; 4371 4372 if (drm_WARN_ON(display->drm, !pll)) 4373 return ICL_PORT_DPLL_DEFAULT; 4374 4375 if (icl_ddi_tc_pll_is_tbt(pll)) 4376 return ICL_PORT_DPLL_DEFAULT; 4377 else 4378 return ICL_PORT_DPLL_MG_PHY; 4379 } 4380 4381 enum icl_port_dpll_id 4382 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4383 const struct intel_crtc_state *crtc_state) 4384 { 4385 if (!encoder->port_pll_type) 4386 return ICL_PORT_DPLL_DEFAULT; 4387 4388 return encoder->port_pll_type(encoder, crtc_state); 4389 } 4390 4391 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4392 struct intel_crtc_state *crtc_state, 4393 struct intel_dpll *pll) 4394 { 4395 struct intel_display *display = to_intel_display(encoder); 4396 enum icl_port_dpll_id port_dpll_id; 4397 struct icl_port_dpll *port_dpll; 4398 bool pll_active; 4399 4400 if (drm_WARN_ON(display->drm, !pll)) 4401 return; 4402 4403 if (icl_ddi_tc_pll_is_tbt(pll)) 4404 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4405 else 4406 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4407 4408 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4409 4410 port_dpll->pll = pll; 4411 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4412 drm_WARN_ON(display->drm, !pll_active); 4413 4414 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4415 4416 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4417 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4418 else 4419 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4420 &crtc_state->dpll_hw_state); 4421 } 4422 4423 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4424 struct intel_crtc_state *crtc_state) 4425 { 4426 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4427 intel_ddi_get_config(encoder, crtc_state); 4428 } 4429 4430 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4431 struct intel_crtc_state *crtc_state) 4432 { 4433 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4434 intel_ddi_get_config(encoder, crtc_state); 4435 } 4436 4437 static void skl_ddi_get_config(struct intel_encoder *encoder, 4438 struct intel_crtc_state *crtc_state) 4439 { 4440 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4441 intel_ddi_get_config(encoder, crtc_state); 4442 } 4443 4444 void hsw_ddi_get_config(struct intel_encoder *encoder, 4445 struct intel_crtc_state *crtc_state) 4446 { 4447 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4448 intel_ddi_get_config(encoder, crtc_state); 4449 } 4450 4451 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4452 const struct intel_crtc_state *crtc_state) 4453 { 4454 if (intel_encoder_is_tc(encoder)) 4455 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4456 crtc_state); 4457 4458 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4459 (!crtc_state && intel_encoder_is_dp(encoder))) 4460 intel_dp_sync_state(encoder, crtc_state); 4461 } 4462 4463 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4464 struct intel_crtc_state *crtc_state) 4465 { 4466 struct intel_display *display = to_intel_display(encoder); 4467 bool fastset = true; 4468 4469 if (intel_encoder_is_tc(encoder)) { 4470 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4471 encoder->base.base.id, encoder->base.name); 4472 crtc_state->uapi.mode_changed = true; 4473 fastset = false; 4474 } 4475 4476 if (intel_crtc_has_dp_encoder(crtc_state) && 4477 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4478 fastset = false; 4479 4480 return fastset; 4481 } 4482 4483 static enum intel_output_type 4484 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4485 struct intel_crtc_state *crtc_state, 4486 struct drm_connector_state *conn_state) 4487 { 4488 switch (conn_state->connector->connector_type) { 4489 case DRM_MODE_CONNECTOR_HDMIA: 4490 return INTEL_OUTPUT_HDMI; 4491 case DRM_MODE_CONNECTOR_eDP: 4492 return INTEL_OUTPUT_EDP; 4493 case DRM_MODE_CONNECTOR_DisplayPort: 4494 return INTEL_OUTPUT_DP; 4495 default: 4496 MISSING_CASE(conn_state->connector->connector_type); 4497 return INTEL_OUTPUT_UNUSED; 4498 } 4499 } 4500 4501 static int intel_ddi_compute_config(struct intel_atomic_state *state, 4502 struct intel_encoder *encoder, 4503 struct intel_crtc_state *pipe_config, 4504 struct drm_connector_state *conn_state) 4505 { 4506 struct intel_display *display = to_intel_display(encoder); 4507 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4508 enum port port = encoder->port; 4509 int ret; 4510 4511 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4512 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4513 4514 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4515 pipe_config->has_hdmi_sink = 4516 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4517 4518 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4519 } else { 4520 ret = intel_dp_compute_config(state, encoder, pipe_config, conn_state); 4521 } 4522 4523 if (ret) 4524 return ret; 4525 4526 if (display->platform.haswell && crtc->pipe == PIPE_A && 4527 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4528 pipe_config->pch_pfit.force_thru = 4529 pipe_config->pch_pfit.enabled || 4530 pipe_config->crc_enabled; 4531 4532 if (display->platform.geminilake || display->platform.broxton) 4533 pipe_config->lane_lat_optim_mask = 4534 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4535 4536 intel_ddi_compute_min_voltage_level(pipe_config); 4537 4538 return 0; 4539 } 4540 4541 static bool mode_equal(const struct drm_display_mode *mode1, 4542 const struct drm_display_mode *mode2) 4543 { 4544 return drm_mode_match(mode1, mode2, 4545 DRM_MODE_MATCH_TIMINGS | 4546 DRM_MODE_MATCH_FLAGS | 4547 DRM_MODE_MATCH_3D_FLAGS) && 4548 mode1->clock == mode2->clock; /* we want an exact match */ 4549 } 4550 4551 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4552 const struct intel_link_m_n *m_n_2) 4553 { 4554 return m_n_1->tu == m_n_2->tu && 4555 m_n_1->data_m == m_n_2->data_m && 4556 m_n_1->data_n == m_n_2->data_n && 4557 m_n_1->link_m == m_n_2->link_m && 4558 m_n_1->link_n == m_n_2->link_n; 4559 } 4560 4561 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4562 const struct intel_crtc_state *crtc_state2) 4563 { 4564 /* 4565 * FIXME the modeset sequence is currently wrong and 4566 * can't deal with joiner + port sync at the same time. 4567 */ 4568 return crtc_state1->hw.active && crtc_state2->hw.active && 4569 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4570 crtc_state1->output_types == crtc_state2->output_types && 4571 crtc_state1->output_format == crtc_state2->output_format && 4572 crtc_state1->lane_count == crtc_state2->lane_count && 4573 crtc_state1->port_clock == crtc_state2->port_clock && 4574 mode_equal(&crtc_state1->hw.adjusted_mode, 4575 &crtc_state2->hw.adjusted_mode) && 4576 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4577 } 4578 4579 static u16 4580 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4581 int tile_group_id) 4582 { 4583 struct intel_display *display = to_intel_display(ref_crtc_state); 4584 struct drm_connector *connector; 4585 const struct drm_connector_state *conn_state; 4586 struct intel_atomic_state *state = 4587 to_intel_atomic_state(ref_crtc_state->uapi.state); 4588 u16 transcoders = 0; 4589 int i; 4590 4591 /* 4592 * We don't enable port sync on BDW due to missing w/as and 4593 * due to not having adjusted the modeset sequence appropriately. 4594 * From, xe3lpd onwards we have defeatured this with reference to 4595 * Wa_16024710867 4596 */ 4597 if (!IS_DISPLAY_VER(display, 9, 20)) 4598 return 0; 4599 4600 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4601 return 0; 4602 4603 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4604 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4605 const struct intel_crtc_state *crtc_state; 4606 4607 if (!crtc) 4608 continue; 4609 4610 if (!connector->has_tile || 4611 connector->tile_group->id != 4612 tile_group_id) 4613 continue; 4614 crtc_state = intel_atomic_get_new_crtc_state(state, 4615 crtc); 4616 if (!crtcs_port_sync_compatible(ref_crtc_state, 4617 crtc_state)) 4618 continue; 4619 transcoders |= BIT(crtc_state->cpu_transcoder); 4620 } 4621 4622 return transcoders; 4623 } 4624 4625 static int intel_ddi_compute_config_late(struct intel_atomic_state *state, 4626 struct intel_encoder *encoder, 4627 struct intel_crtc_state *crtc_state, 4628 struct drm_connector_state *conn_state) 4629 { 4630 struct intel_display *display = to_intel_display(encoder); 4631 struct drm_connector *connector = conn_state->connector; 4632 u16 port_sync_transcoders = 0; 4633 int ret = 0; 4634 4635 if (intel_crtc_has_dp_encoder(crtc_state)) 4636 ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state); 4637 4638 if (ret) 4639 return ret; 4640 4641 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4642 encoder->base.base.id, encoder->base.name, 4643 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4644 4645 if (connector->has_tile) 4646 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4647 connector->tile_group->id); 4648 4649 /* 4650 * EDP Transcoders cannot be ensalved 4651 * make them a master always when present 4652 */ 4653 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4654 crtc_state->master_transcoder = TRANSCODER_EDP; 4655 else 4656 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4657 4658 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4659 crtc_state->master_transcoder = INVALID_TRANSCODER; 4660 crtc_state->sync_mode_slaves_mask = 4661 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4662 } 4663 4664 return 0; 4665 } 4666 4667 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4668 { 4669 struct intel_display *display = to_intel_display(encoder->dev); 4670 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4671 4672 intel_dp_encoder_flush_work(encoder); 4673 if (intel_encoder_is_tc(&dig_port->base)) 4674 intel_tc_port_cleanup(dig_port); 4675 intel_display_power_flush_work(display); 4676 4677 drm_encoder_cleanup(encoder); 4678 kfree(dig_port->hdcp.port_data.streams); 4679 intel_dp_link_cleanup(&dig_port->dp); 4680 kfree(dig_port); 4681 } 4682 4683 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4684 { 4685 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4686 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4687 4688 intel_dp->reset_link_params = true; 4689 intel_dp_invalidate_source_oui(intel_dp); 4690 4691 intel_pps_encoder_reset(intel_dp); 4692 4693 if (intel_encoder_is_tc(&dig_port->base)) 4694 intel_tc_port_init_mode(dig_port); 4695 } 4696 4697 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4698 { 4699 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4700 4701 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4702 4703 return 0; 4704 } 4705 4706 static const struct drm_encoder_funcs intel_ddi_funcs = { 4707 .reset = intel_ddi_encoder_reset, 4708 .destroy = intel_ddi_encoder_destroy, 4709 .late_register = intel_ddi_encoder_late_register, 4710 }; 4711 4712 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4713 { 4714 struct intel_display *display = to_intel_display(dig_port); 4715 struct intel_connector *connector; 4716 enum port port = dig_port->base.port; 4717 int err; 4718 4719 connector = intel_connector_alloc(); 4720 if (!connector) 4721 return -ENOMEM; 4722 4723 err = intel_dp_link_init(&dig_port->dp); 4724 if (err) 4725 goto err_dp_init; 4726 4727 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4728 if (DISPLAY_VER(display) >= 14) 4729 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4730 else 4731 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4732 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4733 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4734 4735 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4736 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4737 4738 if (!intel_dp_init_connector(dig_port, connector)) { 4739 err = -EINVAL; 4740 4741 goto err_init_connector; 4742 } 4743 4744 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4745 struct drm_privacy_screen *privacy_screen; 4746 4747 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4748 if (!IS_ERR(privacy_screen)) { 4749 drm_connector_attach_privacy_screen_provider(&connector->base, 4750 privacy_screen); 4751 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4752 drm_warn(display->drm, "Error getting privacy-screen\n"); 4753 } 4754 } 4755 4756 return 0; 4757 4758 err_init_connector: 4759 intel_dp_link_cleanup(&dig_port->dp); 4760 err_dp_init: 4761 kfree(connector); 4762 4763 return err; 4764 } 4765 4766 static void intel_ddi_cleanup_dp_connector(struct intel_digital_port *dig_port) 4767 { 4768 struct intel_dp *intel_dp = &dig_port->dp; 4769 struct intel_connector *connector = intel_dp->attached_connector; 4770 4771 intel_dp_cleanup_connector(dig_port, connector); 4772 intel_dp_link_cleanup(intel_dp); 4773 kfree(connector); 4774 } 4775 4776 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4777 struct drm_modeset_acquire_ctx *ctx) 4778 { 4779 struct intel_display *display = to_intel_display(encoder); 4780 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4781 struct intel_connector *connector = hdmi->attached_connector; 4782 struct i2c_adapter *ddc = connector->base.ddc; 4783 struct drm_connector_state *conn_state; 4784 struct intel_crtc_state *crtc_state; 4785 struct intel_crtc *crtc; 4786 u8 config; 4787 int ret; 4788 4789 if (connector->base.status != connector_status_connected) 4790 return 0; 4791 4792 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4793 ctx); 4794 if (ret) 4795 return ret; 4796 4797 conn_state = connector->base.state; 4798 4799 crtc = to_intel_crtc(conn_state->crtc); 4800 if (!crtc) 4801 return 0; 4802 4803 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4804 if (ret) 4805 return ret; 4806 4807 crtc_state = to_intel_crtc_state(crtc->base.state); 4808 4809 drm_WARN_ON(display->drm, 4810 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4811 4812 if (!crtc_state->hw.active) 4813 return 0; 4814 4815 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4816 !crtc_state->hdmi_scrambling) 4817 return 0; 4818 4819 if (conn_state->commit && 4820 !try_wait_for_completion(&conn_state->commit->hw_done)) 4821 return 0; 4822 4823 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4824 if (ret < 0) { 4825 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4826 connector->base.base.id, connector->base.name, ret); 4827 return 0; 4828 } 4829 4830 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4831 crtc_state->hdmi_high_tmds_clock_ratio && 4832 !!(config & SCDC_SCRAMBLING_ENABLE) == 4833 crtc_state->hdmi_scrambling) 4834 return 0; 4835 4836 /* 4837 * HDMI 2.0 says that one should not send scrambled data 4838 * prior to configuring the sink scrambling, and that 4839 * TMDS clock/data transmission should be suspended when 4840 * changing the TMDS clock rate in the sink. So let's 4841 * just do a full modeset here, even though some sinks 4842 * would be perfectly happy if were to just reconfigure 4843 * the SCDC settings on the fly. 4844 */ 4845 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4846 } 4847 4848 static void intel_ddi_link_check(struct intel_encoder *encoder) 4849 { 4850 struct intel_display *display = to_intel_display(encoder); 4851 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4852 4853 /* TODO: Move checking the HDMI link state here as well. */ 4854 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4855 4856 intel_dp_link_check(encoder); 4857 } 4858 4859 static enum intel_hotplug_state 4860 intel_ddi_hotplug(struct intel_encoder *encoder, 4861 struct intel_connector *connector) 4862 { 4863 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4864 struct intel_dp *intel_dp = &dig_port->dp; 4865 bool is_tc = intel_encoder_is_tc(encoder); 4866 struct drm_modeset_acquire_ctx ctx; 4867 enum intel_hotplug_state state; 4868 int ret; 4869 4870 if (intel_dp_test_phy(intel_dp)) 4871 return INTEL_HOTPLUG_UNCHANGED; 4872 4873 state = intel_encoder_hotplug(encoder, connector); 4874 4875 if (!intel_tc_port_link_reset(dig_port)) { 4876 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4877 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4878 ret = intel_hdmi_reset_link(encoder, &ctx); 4879 drm_WARN_ON(encoder->base.dev, ret); 4880 } else { 4881 intel_dp_check_link_state(intel_dp); 4882 } 4883 } 4884 4885 /* 4886 * Unpowered type-c dongles can take some time to boot and be 4887 * responsible, so here giving some time to those dongles to power up 4888 * and then retrying the probe. 4889 * 4890 * On many platforms the HDMI live state signal is known to be 4891 * unreliable, so we can't use it to detect if a sink is connected or 4892 * not. Instead we detect if it's connected based on whether we can 4893 * read the EDID or not. That in turn has a problem during disconnect, 4894 * since the HPD interrupt may be raised before the DDC lines get 4895 * disconnected (due to how the required length of DDC vs. HPD 4896 * connector pins are specified) and so we'll still be able to get a 4897 * valid EDID. To solve this schedule another detection cycle if this 4898 * time around we didn't detect any change in the sink's connection 4899 * status. 4900 * 4901 * Type-c connectors which get their HPD signal deasserted then 4902 * reasserted, without unplugging/replugging the sink from the 4903 * connector, introduce a delay until the AUX channel communication 4904 * becomes functional. Retry the detection for 5 seconds on type-c 4905 * connectors to account for this delay. 4906 */ 4907 if (state == INTEL_HOTPLUG_UNCHANGED && 4908 connector->hotplug_retries < (is_tc ? 5 : 1) && 4909 !dig_port->dp.is_mst) 4910 state = INTEL_HOTPLUG_RETRY; 4911 4912 return state; 4913 } 4914 4915 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4916 { 4917 struct intel_display *display = to_intel_display(encoder); 4918 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4919 4920 return intel_de_read(display, SDEISR) & bit; 4921 } 4922 4923 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4924 { 4925 struct intel_display *display = to_intel_display(encoder); 4926 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4927 4928 return intel_de_read(display, DEISR) & bit; 4929 } 4930 4931 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4932 { 4933 struct intel_display *display = to_intel_display(encoder); 4934 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4935 4936 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4937 } 4938 4939 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4940 { 4941 struct intel_connector *connector; 4942 enum port port = dig_port->base.port; 4943 4944 connector = intel_connector_alloc(); 4945 if (!connector) 4946 return -ENOMEM; 4947 4948 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4949 4950 if (!intel_hdmi_init_connector(dig_port, connector)) { 4951 /* 4952 * HDMI connector init failures may just mean conflicting DDC 4953 * pins or not having enough lanes. Handle them gracefully, but 4954 * don't fail the entire DDI init. 4955 */ 4956 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4957 kfree(connector); 4958 } 4959 4960 return 0; 4961 } 4962 4963 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4964 { 4965 struct intel_display *display = to_intel_display(dig_port); 4966 4967 if (dig_port->base.port != PORT_A) 4968 return false; 4969 4970 if (dig_port->ddi_a_4_lanes) 4971 return false; 4972 4973 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4974 * supported configuration 4975 */ 4976 if (display->platform.geminilake || display->platform.broxton) 4977 return true; 4978 4979 return false; 4980 } 4981 4982 static int 4983 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4984 { 4985 struct intel_display *display = to_intel_display(dig_port); 4986 enum port port = dig_port->base.port; 4987 int max_lanes = 4; 4988 4989 if (DISPLAY_VER(display) >= 11) 4990 return max_lanes; 4991 4992 if (port == PORT_A || port == PORT_E) { 4993 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4994 max_lanes = port == PORT_A ? 4 : 0; 4995 else 4996 /* Both A and E share 2 lanes */ 4997 max_lanes = 2; 4998 } 4999 5000 /* 5001 * Some BIOS might fail to set this bit on port A if eDP 5002 * wasn't lit up at boot. Force this bit set when needed 5003 * so we use the proper lane count for our calculations. 5004 */ 5005 if (intel_ddi_a_force_4_lanes(dig_port)) { 5006 drm_dbg_kms(display->drm, 5007 "Forcing DDI_A_4_LANES for port A\n"); 5008 dig_port->ddi_a_4_lanes = true; 5009 max_lanes = 4; 5010 } 5011 5012 return max_lanes; 5013 } 5014 5015 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 5016 { 5017 if (port >= PORT_D_XELPD) 5018 return HPD_PORT_D + port - PORT_D_XELPD; 5019 else if (port >= PORT_TC1) 5020 return HPD_PORT_TC1 + port - PORT_TC1; 5021 else 5022 return HPD_PORT_A + port - PORT_A; 5023 } 5024 5025 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 5026 { 5027 if (port >= PORT_TC1) 5028 return HPD_PORT_C + port - PORT_TC1; 5029 else 5030 return HPD_PORT_A + port - PORT_A; 5031 } 5032 5033 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 5034 { 5035 if (port >= PORT_TC1) 5036 return HPD_PORT_TC1 + port - PORT_TC1; 5037 else 5038 return HPD_PORT_A + port - PORT_A; 5039 } 5040 5041 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 5042 { 5043 if (HAS_PCH_TGP(display)) 5044 return tgl_hpd_pin(display, port); 5045 5046 if (port >= PORT_TC1) 5047 return HPD_PORT_C + port - PORT_TC1; 5048 else 5049 return HPD_PORT_A + port - PORT_A; 5050 } 5051 5052 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 5053 { 5054 if (port >= PORT_C) 5055 return HPD_PORT_TC1 + port - PORT_C; 5056 else 5057 return HPD_PORT_A + port - PORT_A; 5058 } 5059 5060 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 5061 { 5062 if (port == PORT_D) 5063 return HPD_PORT_A; 5064 5065 if (HAS_PCH_TGP(display)) 5066 return icl_hpd_pin(display, port); 5067 5068 return HPD_PORT_A + port - PORT_A; 5069 } 5070 5071 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 5072 { 5073 if (HAS_PCH_TGP(display)) 5074 return icl_hpd_pin(display, port); 5075 5076 return HPD_PORT_A + port - PORT_A; 5077 } 5078 5079 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 5080 { 5081 if (DISPLAY_VER(display) >= 12) 5082 return port >= PORT_TC1; 5083 else if (DISPLAY_VER(display) >= 11) 5084 return port >= PORT_C; 5085 else 5086 return false; 5087 } 5088 5089 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 5090 { 5091 intel_dp_encoder_suspend(encoder); 5092 } 5093 5094 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 5095 { 5096 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5097 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5098 5099 /* 5100 * TODO: Move this to intel_dp_encoder_suspend(), 5101 * once modeset locking around that is removed. 5102 */ 5103 intel_encoder_link_check_flush_work(encoder); 5104 intel_tc_port_suspend(dig_port); 5105 } 5106 5107 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5108 { 5109 if (intel_encoder_is_dp(encoder)) 5110 intel_dp_encoder_shutdown(encoder); 5111 if (intel_encoder_is_hdmi(encoder)) 5112 intel_hdmi_encoder_shutdown(encoder); 5113 } 5114 5115 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5116 { 5117 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5118 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5119 5120 intel_tc_port_cleanup(dig_port); 5121 } 5122 5123 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5124 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5125 5126 static bool port_strap_detected(struct intel_display *display, enum port port) 5127 { 5128 /* straps not used on skl+ */ 5129 if (DISPLAY_VER(display) >= 9) 5130 return true; 5131 5132 switch (port) { 5133 case PORT_A: 5134 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5135 case PORT_B: 5136 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5137 case PORT_C: 5138 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5139 case PORT_D: 5140 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5141 case PORT_E: 5142 return true; /* no strap for DDI-E */ 5143 default: 5144 MISSING_CASE(port); 5145 return false; 5146 } 5147 } 5148 5149 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5150 { 5151 return init_dp || intel_encoder_is_tc(encoder); 5152 } 5153 5154 static bool assert_has_icl_dsi(struct intel_display *display) 5155 { 5156 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5157 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5158 "Platform does not support DSI\n"); 5159 } 5160 5161 static bool port_in_use(struct intel_display *display, enum port port) 5162 { 5163 struct intel_encoder *encoder; 5164 5165 for_each_intel_encoder(display->drm, encoder) { 5166 /* FIXME what about second port for dual link DSI? */ 5167 if (encoder->port == port) 5168 return true; 5169 } 5170 5171 return false; 5172 } 5173 5174 static const char *intel_ddi_encoder_name(struct intel_display *display, 5175 enum port port, enum phy phy, 5176 struct seq_buf *s) 5177 { 5178 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5179 seq_buf_printf(s, "DDI %c/PHY %c", 5180 port_name(port - PORT_D_XELPD + PORT_D), 5181 phy_name(phy)); 5182 } else if (DISPLAY_VER(display) >= 12) { 5183 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5184 5185 seq_buf_printf(s, "DDI %s%c/PHY %s%c", 5186 port >= PORT_TC1 ? "TC" : "", 5187 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5188 tc_port != TC_PORT_NONE ? "TC" : "", 5189 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5190 } else if (DISPLAY_VER(display) >= 11) { 5191 enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5192 5193 seq_buf_printf(s, "DDI %c%s/PHY %s%c", 5194 port_name(port), 5195 port >= PORT_C ? " (TC)" : "", 5196 tc_port != TC_PORT_NONE ? "TC" : "", 5197 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5198 } else { 5199 seq_buf_printf(s, "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5200 } 5201 5202 drm_WARN_ON(display->drm, seq_buf_has_overflowed(s)); 5203 5204 return seq_buf_str(s); 5205 } 5206 5207 void intel_ddi_init(struct intel_display *display, 5208 const struct intel_bios_encoder_data *devdata) 5209 { 5210 struct intel_digital_port *dig_port; 5211 struct intel_encoder *encoder; 5212 DECLARE_SEQ_BUF(encoder_name, 20); 5213 bool init_hdmi, init_dp; 5214 enum port port; 5215 enum phy phy; 5216 u32 ddi_buf_ctl; 5217 5218 port = intel_bios_encoder_port(devdata); 5219 if (port == PORT_NONE) 5220 return; 5221 5222 if (!port_strap_detected(display, port)) { 5223 drm_dbg_kms(display->drm, 5224 "Port %c strap not detected\n", port_name(port)); 5225 return; 5226 } 5227 5228 if (!assert_port_valid(display, port)) 5229 return; 5230 5231 if (port_in_use(display, port)) { 5232 drm_dbg_kms(display->drm, 5233 "Port %c already claimed\n", port_name(port)); 5234 return; 5235 } 5236 5237 if (intel_bios_encoder_supports_dsi(devdata)) { 5238 /* BXT/GLK handled elsewhere, for now at least */ 5239 if (!assert_has_icl_dsi(display)) 5240 return; 5241 5242 icl_dsi_init(display, devdata); 5243 return; 5244 } 5245 5246 phy = intel_port_to_phy(display, port); 5247 5248 /* 5249 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5250 * have taken over some of the PHYs and made them unavailable to the 5251 * driver. In that case we should skip initializing the corresponding 5252 * outputs. 5253 */ 5254 if (intel_hti_uses_phy(display, phy)) { 5255 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5256 port_name(port), phy_name(phy)); 5257 return; 5258 } 5259 5260 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5261 intel_bios_encoder_supports_hdmi(devdata); 5262 init_dp = intel_bios_encoder_supports_dp(devdata); 5263 5264 if (intel_bios_encoder_is_lspcon(devdata)) { 5265 /* 5266 * Lspcon device needs to be driven with DP connector 5267 * with special detection sequence. So make sure DP 5268 * is initialized before lspcon. 5269 */ 5270 init_dp = true; 5271 init_hdmi = false; 5272 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5273 port_name(port)); 5274 } 5275 5276 if (!init_dp && !init_hdmi) { 5277 drm_dbg_kms(display->drm, 5278 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5279 port_name(port)); 5280 return; 5281 } 5282 5283 if (intel_phy_is_snps(display, phy) && 5284 display->snps.phy_failed_calibration & BIT(phy)) { 5285 drm_dbg_kms(display->drm, 5286 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5287 phy_name(phy)); 5288 } 5289 5290 dig_port = intel_dig_port_alloc(); 5291 if (!dig_port) 5292 return; 5293 5294 encoder = &dig_port->base; 5295 encoder->devdata = devdata; 5296 5297 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5298 DRM_MODE_ENCODER_TMDS, "%s", 5299 intel_ddi_encoder_name(display, port, phy, &encoder_name)); 5300 5301 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5302 5303 encoder->hotplug = intel_ddi_hotplug; 5304 encoder->compute_output_type = intel_ddi_compute_output_type; 5305 encoder->compute_config = intel_ddi_compute_config; 5306 encoder->compute_config_late = intel_ddi_compute_config_late; 5307 encoder->enable = intel_ddi_enable; 5308 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5309 encoder->pre_enable = intel_ddi_pre_enable; 5310 encoder->disable = intel_ddi_disable; 5311 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5312 encoder->post_disable = intel_ddi_post_disable; 5313 encoder->update_pipe = intel_ddi_update_pipe; 5314 encoder->audio_enable = intel_audio_codec_enable; 5315 encoder->audio_disable = intel_audio_codec_disable; 5316 encoder->get_hw_state = intel_ddi_get_hw_state; 5317 encoder->sync_state = intel_ddi_sync_state; 5318 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5319 encoder->suspend = intel_ddi_encoder_suspend; 5320 encoder->shutdown = intel_ddi_encoder_shutdown; 5321 encoder->get_power_domains = intel_ddi_get_power_domains; 5322 5323 encoder->type = INTEL_OUTPUT_DDI; 5324 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5325 encoder->port = port; 5326 encoder->cloneable = 0; 5327 encoder->pipe_mask = ~0; 5328 5329 if (HAS_LT_PHY(display)) { 5330 encoder->enable_clock = intel_mtl_pll_enable_clock; 5331 encoder->disable_clock = intel_mtl_pll_disable_clock; 5332 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5333 if (intel_encoder_is_tc(encoder)) 5334 encoder->get_config = mtl_ddi_tc_phy_get_config; 5335 else 5336 encoder->get_config = mtl_ddi_non_tc_phy_get_config; 5337 } else if (DISPLAY_VER(display) >= 14) { 5338 encoder->enable_clock = intel_mtl_pll_enable_clock; 5339 encoder->disable_clock = intel_mtl_pll_disable_clock; 5340 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5341 if (intel_encoder_is_tc(encoder)) 5342 encoder->get_config = mtl_ddi_tc_phy_get_config; 5343 else 5344 encoder->get_config = mtl_ddi_non_tc_phy_get_config; 5345 } else if (display->platform.dg2) { 5346 encoder->enable_clock = intel_mpllb_enable; 5347 encoder->disable_clock = intel_mpllb_disable; 5348 encoder->get_config = dg2_ddi_get_config; 5349 } else if (display->platform.alderlake_s) { 5350 encoder->enable_clock = adls_ddi_enable_clock; 5351 encoder->disable_clock = adls_ddi_disable_clock; 5352 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5353 encoder->get_config = adls_ddi_get_config; 5354 } else if (display->platform.rocketlake) { 5355 encoder->enable_clock = rkl_ddi_enable_clock; 5356 encoder->disable_clock = rkl_ddi_disable_clock; 5357 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5358 encoder->get_config = rkl_ddi_get_config; 5359 } else if (display->platform.dg1) { 5360 encoder->enable_clock = dg1_ddi_enable_clock; 5361 encoder->disable_clock = dg1_ddi_disable_clock; 5362 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5363 encoder->get_config = dg1_ddi_get_config; 5364 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5365 if (intel_ddi_is_tc(display, port)) { 5366 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5367 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5368 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5369 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5370 encoder->get_config = icl_ddi_combo_get_config; 5371 } else { 5372 encoder->enable_clock = icl_ddi_combo_enable_clock; 5373 encoder->disable_clock = icl_ddi_combo_disable_clock; 5374 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5375 encoder->get_config = icl_ddi_combo_get_config; 5376 } 5377 } else if (DISPLAY_VER(display) >= 11) { 5378 if (intel_ddi_is_tc(display, port)) { 5379 encoder->enable_clock = icl_ddi_tc_enable_clock; 5380 encoder->disable_clock = icl_ddi_tc_disable_clock; 5381 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5382 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5383 encoder->get_config = icl_ddi_tc_get_config; 5384 } else { 5385 encoder->enable_clock = icl_ddi_combo_enable_clock; 5386 encoder->disable_clock = icl_ddi_combo_disable_clock; 5387 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5388 encoder->get_config = icl_ddi_combo_get_config; 5389 } 5390 } else if (display->platform.geminilake || display->platform.broxton) { 5391 /* BXT/GLK have fixed PLL->port mapping */ 5392 encoder->get_config = bxt_ddi_get_config; 5393 } else if (DISPLAY_VER(display) == 9) { 5394 encoder->enable_clock = skl_ddi_enable_clock; 5395 encoder->disable_clock = skl_ddi_disable_clock; 5396 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5397 encoder->get_config = skl_ddi_get_config; 5398 } else if (display->platform.broadwell || display->platform.haswell) { 5399 encoder->enable_clock = hsw_ddi_enable_clock; 5400 encoder->disable_clock = hsw_ddi_disable_clock; 5401 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5402 encoder->get_config = hsw_ddi_get_config; 5403 } 5404 5405 if (HAS_LT_PHY(display)) { 5406 encoder->set_signal_levels = intel_lt_phy_set_signal_levels; 5407 } else if (DISPLAY_VER(display) >= 14) { 5408 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5409 } else if (display->platform.dg2) { 5410 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5411 } else if (DISPLAY_VER(display) >= 12) { 5412 if (intel_encoder_is_combo(encoder)) 5413 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5414 else 5415 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5416 } else if (DISPLAY_VER(display) >= 11) { 5417 if (intel_encoder_is_combo(encoder)) 5418 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5419 else 5420 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5421 } else if (display->platform.geminilake || display->platform.broxton) { 5422 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5423 } else { 5424 encoder->set_signal_levels = hsw_set_signal_levels; 5425 } 5426 5427 intel_ddi_buf_trans_init(encoder); 5428 5429 if (DISPLAY_VER(display) >= 13) 5430 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5431 else if (display->platform.dg1) 5432 encoder->hpd_pin = dg1_hpd_pin(display, port); 5433 else if (display->platform.rocketlake) 5434 encoder->hpd_pin = rkl_hpd_pin(display, port); 5435 else if (DISPLAY_VER(display) >= 12) 5436 encoder->hpd_pin = tgl_hpd_pin(display, port); 5437 else if (display->platform.jasperlake || display->platform.elkhartlake) 5438 encoder->hpd_pin = ehl_hpd_pin(display, port); 5439 else if (DISPLAY_VER(display) == 11) 5440 encoder->hpd_pin = icl_hpd_pin(display, port); 5441 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5442 encoder->hpd_pin = skl_hpd_pin(display, port); 5443 else 5444 encoder->hpd_pin = intel_hpd_pin_default(port); 5445 5446 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5447 5448 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5449 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5450 5451 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5452 5453 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5454 5455 if (need_aux_ch(encoder, init_dp)) { 5456 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5457 if (dig_port->aux_ch == AUX_CH_NONE) 5458 goto err_aux_ch_init; 5459 } 5460 5461 /* 5462 * FIXME: We currently need to store dedicated_external because devdata 5463 * does not live long enough for when intel_encoder_is_tc() is called on 5464 * the unbind path. This needs to be fixed by making sure that the VBT 5465 * data is kept long enough, so that 5466 * intel_bios_encoder_is_dedicated_external() can be called directly 5467 * from intel_encoder_is_tc(). 5468 */ 5469 if (intel_bios_encoder_is_dedicated_external(devdata)) 5470 dig_port->dedicated_external = true; 5471 5472 if (intel_encoder_is_tc(encoder)) { 5473 bool is_legacy = 5474 !intel_bios_encoder_supports_typec_usb(devdata) && 5475 !intel_bios_encoder_supports_tbt(devdata); 5476 5477 if (!is_legacy && init_hdmi) { 5478 is_legacy = !init_dp; 5479 5480 drm_dbg_kms(display->drm, 5481 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5482 port_name(port), 5483 str_yes_no(init_dp), 5484 is_legacy ? "legacy" : "non-legacy"); 5485 } 5486 5487 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5488 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5489 5490 dig_port->lock = intel_tc_port_lock; 5491 dig_port->unlock = intel_tc_port_unlock; 5492 5493 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5494 goto err_aux_ch_init; 5495 } 5496 5497 drm_WARN_ON(display->drm, port > PORT_I); 5498 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5499 5500 if (DISPLAY_VER(display) >= 11) { 5501 if (intel_encoder_is_tc(encoder)) 5502 dig_port->connected = intel_tc_port_connected; 5503 else 5504 dig_port->connected = lpt_digital_port_connected; 5505 } else if (display->platform.geminilake || display->platform.broxton) { 5506 dig_port->connected = bdw_digital_port_connected; 5507 } else if (DISPLAY_VER(display) == 9) { 5508 dig_port->connected = lpt_digital_port_connected; 5509 } else if (display->platform.broadwell) { 5510 if (port == PORT_A) 5511 dig_port->connected = bdw_digital_port_connected; 5512 else 5513 dig_port->connected = lpt_digital_port_connected; 5514 } else if (display->platform.haswell) { 5515 if (port == PORT_A) 5516 dig_port->connected = hsw_digital_port_connected; 5517 else 5518 dig_port->connected = lpt_digital_port_connected; 5519 } 5520 5521 intel_infoframe_init(dig_port); 5522 5523 if (init_dp) { 5524 if (intel_ddi_init_dp_connector(dig_port)) 5525 goto err_dp_connector_init; 5526 5527 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5528 5529 if (dig_port->dp.mso_link_count) 5530 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5531 } 5532 5533 /* 5534 * In theory we don't need the encoder->type check, 5535 * but leave it just in case we have some really bad VBTs... 5536 */ 5537 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5538 if (intel_ddi_init_hdmi_connector(dig_port)) 5539 goto err_hdmi_connector_init; 5540 } 5541 5542 return; 5543 5544 err_hdmi_connector_init: 5545 if (init_dp) 5546 intel_ddi_cleanup_dp_connector(dig_port); 5547 err_dp_connector_init: 5548 if (intel_encoder_is_tc(encoder)) 5549 intel_tc_port_cleanup(dig_port); 5550 err_aux_ch_init: 5551 drm_encoder_cleanup(&encoder->base); 5552 kfree(dig_port); 5553 } 5554