1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/seq_buf.h> 30 #include <linux/string_helpers.h> 31 32 #include <drm/display/drm_dp_helper.h> 33 #include <drm/display/drm_scdc_helper.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_privacy_screen_consumer.h> 36 37 #include "i915_reg.h" 38 #include "i915_utils.h" 39 #include "icl_dsi.h" 40 #include "intel_alpm.h" 41 #include "intel_audio.h" 42 #include "intel_audio_regs.h" 43 #include "intel_backlight.h" 44 #include "intel_combo_phy.h" 45 #include "intel_combo_phy_regs.h" 46 #include "intel_connector.h" 47 #include "intel_crtc.h" 48 #include "intel_cx0_phy.h" 49 #include "intel_cx0_phy_regs.h" 50 #include "intel_ddi.h" 51 #include "intel_ddi_buf_trans.h" 52 #include "intel_de.h" 53 #include "intel_display_power.h" 54 #include "intel_display_regs.h" 55 #include "intel_display_types.h" 56 #include "intel_dkl_phy.h" 57 #include "intel_dkl_phy_regs.h" 58 #include "intel_dp.h" 59 #include "intel_dp_aux.h" 60 #include "intel_dp_link_training.h" 61 #include "intel_dp_mst.h" 62 #include "intel_dp_test.h" 63 #include "intel_dp_tunnel.h" 64 #include "intel_dpio_phy.h" 65 #include "intel_dsi.h" 66 #include "intel_encoder.h" 67 #include "intel_fdi.h" 68 #include "intel_fifo_underrun.h" 69 #include "intel_gmbus.h" 70 #include "intel_hdcp.h" 71 #include "intel_hdmi.h" 72 #include "intel_hotplug.h" 73 #include "intel_hti.h" 74 #include "intel_lspcon.h" 75 #include "intel_mg_phy_regs.h" 76 #include "intel_modeset_lock.h" 77 #include "intel_panel.h" 78 #include "intel_pfit.h" 79 #include "intel_pps.h" 80 #include "intel_psr.h" 81 #include "intel_quirks.h" 82 #include "intel_snps_phy.h" 83 #include "intel_step.h" 84 #include "intel_tc.h" 85 #include "intel_vdsc.h" 86 #include "intel_vdsc_regs.h" 87 #include "intel_vrr.h" 88 #include "skl_scaler.h" 89 #include "skl_universal_plane.h" 90 91 static const u8 index_to_dp_signal_levels[] = { 92 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 93 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 94 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 95 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 96 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 97 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 98 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 99 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 100 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 101 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 102 }; 103 104 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 105 const struct intel_ddi_buf_trans *trans) 106 { 107 int level; 108 109 level = intel_bios_hdmi_level_shift(encoder->devdata); 110 if (level < 0) 111 level = trans->hdmi_default_entry; 112 113 return level; 114 } 115 116 static bool has_buf_trans_select(struct intel_display *display) 117 { 118 return DISPLAY_VER(display) < 10 && !display->platform.broxton; 119 } 120 121 static bool has_iboost(struct intel_display *display) 122 { 123 return DISPLAY_VER(display) == 9 && !display->platform.broxton; 124 } 125 126 /* 127 * Starting with Haswell, DDI port buffers must be programmed with correct 128 * values in advance. This function programs the correct values for 129 * DP/eDP/FDI use cases. 130 */ 131 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 132 const struct intel_crtc_state *crtc_state) 133 { 134 struct intel_display *display = to_intel_display(encoder); 135 u32 iboost_bit = 0; 136 int i, n_entries; 137 enum port port = encoder->port; 138 const struct intel_ddi_buf_trans *trans; 139 140 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 141 if (drm_WARN_ON_ONCE(display->drm, !trans)) 142 return; 143 144 /* If we're boosting the current, set bit 31 of trans1 */ 145 if (has_iboost(display) && 146 intel_bios_dp_boost_level(encoder->devdata)) 147 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 148 149 for (i = 0; i < n_entries; i++) { 150 intel_de_write(display, DDI_BUF_TRANS_LO(port, i), 151 trans->entries[i].hsw.trans1 | iboost_bit); 152 intel_de_write(display, DDI_BUF_TRANS_HI(port, i), 153 trans->entries[i].hsw.trans2); 154 } 155 } 156 157 /* 158 * Starting with Haswell, DDI port buffers must be programmed with correct 159 * values in advance. This function programs the correct values for 160 * HDMI/DVI use cases. 161 */ 162 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 163 const struct intel_crtc_state *crtc_state) 164 { 165 struct intel_display *display = to_intel_display(encoder); 166 int level = intel_ddi_level(encoder, crtc_state, 0); 167 u32 iboost_bit = 0; 168 int n_entries; 169 enum port port = encoder->port; 170 const struct intel_ddi_buf_trans *trans; 171 172 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 173 if (drm_WARN_ON_ONCE(display->drm, !trans)) 174 return; 175 176 /* If we're boosting the current, set bit 31 of trans1 */ 177 if (has_iboost(display) && 178 intel_bios_hdmi_boost_level(encoder->devdata)) 179 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 180 181 /* Entry 9 is for HDMI: */ 182 intel_de_write(display, DDI_BUF_TRANS_LO(port, 9), 183 trans->entries[level].hsw.trans1 | iboost_bit); 184 intel_de_write(display, DDI_BUF_TRANS_HI(port, 9), 185 trans->entries[level].hsw.trans2); 186 } 187 188 static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) 189 { 190 if (DISPLAY_VER(display) >= 14) 191 return XELPDP_PORT_BUF_CTL1(display, port); 192 else 193 return DDI_BUF_CTL(port); 194 } 195 196 void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) 197 { 198 /* 199 * Bspec's platform specific timeouts: 200 * MTL+ : 100 us 201 * BXT : fixed 16 us 202 * HSW-ADL: 8 us 203 * 204 * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short 205 */ 206 if (display->platform.broxton) { 207 udelay(16); 208 return; 209 } 210 211 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 212 if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), 213 DDI_BUF_IS_IDLE, 10)) 214 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", 215 port_name(port)); 216 } 217 218 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 219 { 220 struct intel_display *display = to_intel_display(encoder); 221 enum port port = encoder->port; 222 223 /* 224 * Bspec's platform specific timeouts: 225 * MTL+ : 10000 us 226 * DG2 : 1200 us 227 * TGL-ADL combo PHY: 1000 us 228 * TGL-ADL TypeC PHY: 3000 us 229 * HSW-ICL : fixed 518 us 230 */ 231 if (DISPLAY_VER(display) < 10) { 232 usleep_range(518, 1000); 233 return; 234 } 235 236 static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); 237 if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), 238 DDI_BUF_IS_IDLE, 10)) 239 drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", 240 port_name(port)); 241 } 242 243 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll) 244 { 245 switch (pll->info->id) { 246 case DPLL_ID_WRPLL1: 247 return PORT_CLK_SEL_WRPLL1; 248 case DPLL_ID_WRPLL2: 249 return PORT_CLK_SEL_WRPLL2; 250 case DPLL_ID_SPLL: 251 return PORT_CLK_SEL_SPLL; 252 case DPLL_ID_LCPLL_810: 253 return PORT_CLK_SEL_LCPLL_810; 254 case DPLL_ID_LCPLL_1350: 255 return PORT_CLK_SEL_LCPLL_1350; 256 case DPLL_ID_LCPLL_2700: 257 return PORT_CLK_SEL_LCPLL_2700; 258 default: 259 MISSING_CASE(pll->info->id); 260 return PORT_CLK_SEL_NONE; 261 } 262 } 263 264 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 265 const struct intel_crtc_state *crtc_state) 266 { 267 const struct intel_dpll *pll = crtc_state->intel_dpll; 268 int clock = crtc_state->port_clock; 269 const enum intel_dpll_id id = pll->info->id; 270 271 switch (id) { 272 default: 273 /* 274 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 275 * here, so do warn if this get passed in 276 */ 277 MISSING_CASE(id); 278 return DDI_CLK_SEL_NONE; 279 case DPLL_ID_ICL_TBTPLL: 280 switch (clock) { 281 case 162000: 282 return DDI_CLK_SEL_TBT_162; 283 case 270000: 284 return DDI_CLK_SEL_TBT_270; 285 case 540000: 286 return DDI_CLK_SEL_TBT_540; 287 case 810000: 288 return DDI_CLK_SEL_TBT_810; 289 default: 290 MISSING_CASE(clock); 291 return DDI_CLK_SEL_NONE; 292 } 293 case DPLL_ID_ICL_MGPLL1: 294 case DPLL_ID_ICL_MGPLL2: 295 case DPLL_ID_ICL_MGPLL3: 296 case DPLL_ID_ICL_MGPLL4: 297 case DPLL_ID_TGL_MGPLL5: 298 case DPLL_ID_TGL_MGPLL6: 299 return DDI_CLK_SEL_MG; 300 } 301 } 302 303 static u32 ddi_buf_phy_link_rate(int port_clock) 304 { 305 switch (port_clock) { 306 case 162000: 307 return DDI_BUF_PHY_LINK_RATE(0); 308 case 216000: 309 return DDI_BUF_PHY_LINK_RATE(4); 310 case 243000: 311 return DDI_BUF_PHY_LINK_RATE(5); 312 case 270000: 313 return DDI_BUF_PHY_LINK_RATE(1); 314 case 324000: 315 return DDI_BUF_PHY_LINK_RATE(6); 316 case 432000: 317 return DDI_BUF_PHY_LINK_RATE(7); 318 case 540000: 319 return DDI_BUF_PHY_LINK_RATE(2); 320 case 810000: 321 return DDI_BUF_PHY_LINK_RATE(3); 322 default: 323 MISSING_CASE(port_clock); 324 return DDI_BUF_PHY_LINK_RATE(0); 325 } 326 } 327 328 static int dp_phy_lane_stagger_delay(int port_clock) 329 { 330 /* 331 * Return the number of symbol clocks delay used to stagger the 332 * assertion/desassertion of the port lane enables. The target delay 333 * time is 100 ns or greater, return the number of symbols specific to 334 * the provided port_clock (aka link clock) corresponding to this delay 335 * time, i.e. so that 336 * 337 * number_of_symbols * duration_of_one_symbol >= 100 ns 338 * 339 * The delay must be applied only on TypeC DP outputs, for everything else 340 * the delay must be set to 0. 341 * 342 * Return the number of link symbols per 100 ns: 343 * port_clock (10 kHz) -> bits / 100 us 344 * / symbol_size -> symbols / 100 us 345 * / 1000 -> symbols / 100 ns 346 */ 347 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); 348 } 349 350 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 351 const struct intel_crtc_state *crtc_state) 352 { 353 struct intel_display *display = to_intel_display(encoder); 354 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 355 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 356 357 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 358 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 359 DDI_BUF_TRANS_SELECT(0); 360 361 if (dig_port->lane_reversal) 362 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 363 if (dig_port->ddi_a_4_lanes) 364 intel_dp->DP |= DDI_A_4_LANES; 365 366 if (DISPLAY_VER(display) >= 14) { 367 if (intel_dp_is_uhbr(crtc_state)) 368 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 369 else 370 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 371 } 372 373 if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 374 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 375 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 376 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 377 } 378 379 if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { 380 int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); 381 382 intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); 383 } 384 } 385 386 static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) 387 { 388 u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 389 390 switch (val) { 391 case DDI_CLK_SEL_NONE: 392 return 0; 393 case DDI_CLK_SEL_TBT_162: 394 return 162000; 395 case DDI_CLK_SEL_TBT_270: 396 return 270000; 397 case DDI_CLK_SEL_TBT_540: 398 return 540000; 399 case DDI_CLK_SEL_TBT_810: 400 return 810000; 401 default: 402 MISSING_CASE(val); 403 return 0; 404 } 405 } 406 407 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 408 { 409 /* CRT dotclock is determined via other means */ 410 if (pipe_config->has_pch_encoder) 411 return; 412 413 pipe_config->hw.adjusted_mode.crtc_clock = 414 intel_crtc_dotclock(pipe_config); 415 } 416 417 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 418 const struct drm_connector_state *conn_state) 419 { 420 struct intel_display *display = to_intel_display(crtc_state); 421 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 422 u32 temp; 423 424 if (!intel_crtc_has_dp_encoder(crtc_state)) 425 return; 426 427 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 428 429 temp = DP_MSA_MISC_SYNC_CLOCK; 430 431 switch (crtc_state->pipe_bpp) { 432 case 18: 433 temp |= DP_MSA_MISC_6_BPC; 434 break; 435 case 24: 436 temp |= DP_MSA_MISC_8_BPC; 437 break; 438 case 30: 439 temp |= DP_MSA_MISC_10_BPC; 440 break; 441 case 36: 442 temp |= DP_MSA_MISC_12_BPC; 443 break; 444 default: 445 MISSING_CASE(crtc_state->pipe_bpp); 446 break; 447 } 448 449 /* nonsense combination */ 450 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 451 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 452 453 if (crtc_state->limited_color_range) 454 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 455 456 /* 457 * As per DP 1.2 spec section 2.3.4.3 while sending 458 * YCBCR 444 signals we should program MSA MISC1/0 fields with 459 * colorspace information. 460 */ 461 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 462 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 463 464 /* 465 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 466 * of Color Encoding Format and Content Color Gamut] while sending 467 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 468 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 469 */ 470 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 471 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 472 473 intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder), 474 temp); 475 } 476 477 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 478 { 479 if (master_transcoder == TRANSCODER_EDP) 480 return 0; 481 else 482 return master_transcoder + 1; 483 } 484 485 static void 486 intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 487 bool enable) 488 { 489 struct intel_display *display = to_intel_display(crtc_state); 490 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 491 u32 val = 0; 492 493 if (!HAS_DP20(display)) 494 return; 495 496 if (enable && intel_dp_is_uhbr(crtc_state)) 497 val = TRANS_DP2_128B132B_CHANNEL_CODING; 498 499 intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 500 } 501 502 /* 503 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 504 * 505 * Only intended to be used by intel_ddi_enable_transcoder_func() and 506 * intel_ddi_config_transcoder_func(). 507 */ 508 static u32 509 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 510 const struct intel_crtc_state *crtc_state) 511 { 512 struct intel_display *display = to_intel_display(crtc_state); 513 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 514 enum pipe pipe = crtc->pipe; 515 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 516 enum port port = encoder->port; 517 u32 temp; 518 519 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 520 temp = TRANS_DDI_FUNC_ENABLE; 521 if (DISPLAY_VER(display) >= 12) 522 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 523 else 524 temp |= TRANS_DDI_SELECT_PORT(port); 525 526 switch (crtc_state->pipe_bpp) { 527 default: 528 MISSING_CASE(crtc_state->pipe_bpp); 529 fallthrough; 530 case 18: 531 temp |= TRANS_DDI_BPC_6; 532 break; 533 case 24: 534 temp |= TRANS_DDI_BPC_8; 535 break; 536 case 30: 537 temp |= TRANS_DDI_BPC_10; 538 break; 539 case 36: 540 temp |= TRANS_DDI_BPC_12; 541 break; 542 } 543 544 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 545 temp |= TRANS_DDI_PVSYNC; 546 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 547 temp |= TRANS_DDI_PHSYNC; 548 549 if (cpu_transcoder == TRANSCODER_EDP) { 550 switch (pipe) { 551 default: 552 MISSING_CASE(pipe); 553 fallthrough; 554 case PIPE_A: 555 /* On Haswell, can only use the always-on power well for 556 * eDP when not using the panel fitter, and when not 557 * using motion blur mitigation (which we don't 558 * support). */ 559 if (crtc_state->pch_pfit.force_thru) 560 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 561 else 562 temp |= TRANS_DDI_EDP_INPUT_A_ON; 563 break; 564 case PIPE_B: 565 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 566 break; 567 case PIPE_C: 568 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 569 break; 570 } 571 } 572 573 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 574 if (crtc_state->has_hdmi_sink) 575 temp |= TRANS_DDI_MODE_SELECT_HDMI; 576 else 577 temp |= TRANS_DDI_MODE_SELECT_DVI; 578 579 if (crtc_state->hdmi_scrambling) 580 temp |= TRANS_DDI_HDMI_SCRAMBLING; 581 if (crtc_state->hdmi_high_tmds_clock_ratio) 582 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 583 if (DISPLAY_VER(display) >= 14) 584 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 585 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 586 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 587 temp |= (crtc_state->fdi_lanes - 1) << 1; 588 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 589 intel_dp_is_uhbr(crtc_state)) { 590 if (intel_dp_is_uhbr(crtc_state)) 591 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 592 else 593 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 594 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 595 596 if (DISPLAY_VER(display) >= 12) { 597 enum transcoder master; 598 599 master = crtc_state->mst_master_transcoder; 600 drm_WARN_ON(display->drm, 601 master == INVALID_TRANSCODER); 602 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 603 } 604 } else { 605 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 606 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 607 } 608 609 if (IS_DISPLAY_VER(display, 8, 10) && 610 crtc_state->master_transcoder != INVALID_TRANSCODER) { 611 u8 master_select = 612 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 613 614 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 615 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 616 } 617 618 return temp; 619 } 620 621 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 622 const struct intel_crtc_state *crtc_state) 623 { 624 struct intel_display *display = to_intel_display(crtc_state); 625 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 626 627 if (DISPLAY_VER(display) >= 11) { 628 enum transcoder master_transcoder = crtc_state->master_transcoder; 629 u32 ctl2 = 0; 630 631 if (master_transcoder != INVALID_TRANSCODER) { 632 u8 master_select = 633 bdw_trans_port_sync_master_select(master_transcoder); 634 635 ctl2 |= PORT_SYNC_MODE_ENABLE | 636 PORT_SYNC_MODE_MASTER_SELECT(master_select); 637 } 638 639 intel_de_write(display, 640 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 641 ctl2); 642 } 643 644 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 645 intel_ddi_transcoder_func_reg_val_get(encoder, 646 crtc_state)); 647 } 648 649 /* 650 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 651 * bit for the DDI function and enables the DP2 configuration. Called for all 652 * transcoder types. 653 */ 654 void 655 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 656 const struct intel_crtc_state *crtc_state) 657 { 658 struct intel_display *display = to_intel_display(crtc_state); 659 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 660 u32 ctl; 661 662 intel_ddi_config_transcoder_dp2(crtc_state, true); 663 664 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 665 ctl &= ~TRANS_DDI_FUNC_ENABLE; 666 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 667 ctl); 668 } 669 670 /* 671 * Disable the DDI function and port syncing. 672 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 673 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 674 * transcoders these are done later in intel_ddi_post_disable_dp(). 675 */ 676 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 677 { 678 struct intel_display *display = to_intel_display(crtc_state); 679 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 680 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 681 u32 ctl; 682 683 if (DISPLAY_VER(display) >= 11) 684 intel_de_write(display, 685 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 686 0); 687 688 ctl = intel_de_read(display, 689 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 690 691 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 692 693 ctl &= ~TRANS_DDI_FUNC_ENABLE; 694 695 if (IS_DISPLAY_VER(display, 8, 10)) 696 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 697 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 698 699 if (DISPLAY_VER(display) >= 12) { 700 if (!intel_dp_mst_is_master_trans(crtc_state)) { 701 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 702 TRANS_DDI_MODE_SELECT_MASK); 703 } 704 } else { 705 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 706 } 707 708 intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 709 ctl); 710 711 if (intel_dp_mst_is_slave_trans(crtc_state)) 712 intel_ddi_config_transcoder_dp2(crtc_state, false); 713 714 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 715 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 716 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 717 /* Quirk time at 100ms for reliable operation */ 718 msleep(100); 719 } 720 } 721 722 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 723 enum transcoder cpu_transcoder, 724 bool enable, u32 hdcp_mask) 725 { 726 struct intel_display *display = to_intel_display(intel_encoder); 727 intel_wakeref_t wakeref; 728 int ret = 0; 729 730 wakeref = intel_display_power_get_if_enabled(display, 731 intel_encoder->power_domain); 732 if (drm_WARN_ON(display->drm, !wakeref)) 733 return -ENXIO; 734 735 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 736 hdcp_mask, enable ? hdcp_mask : 0); 737 intel_display_power_put(display, intel_encoder->power_domain, wakeref); 738 return ret; 739 } 740 741 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 742 { 743 struct intel_display *display = to_intel_display(intel_connector); 744 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 745 int type = intel_connector->base.connector_type; 746 enum port port = encoder->port; 747 enum transcoder cpu_transcoder; 748 intel_wakeref_t wakeref; 749 enum pipe pipe = 0; 750 u32 ddi_mode; 751 bool ret; 752 753 wakeref = intel_display_power_get_if_enabled(display, 754 encoder->power_domain); 755 if (!wakeref) 756 return false; 757 758 /* Note: This returns false for DP MST primary encoders. */ 759 if (!encoder->get_hw_state(encoder, &pipe)) { 760 ret = false; 761 goto out; 762 } 763 764 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 765 cpu_transcoder = TRANSCODER_EDP; 766 else 767 cpu_transcoder = (enum transcoder) pipe; 768 769 ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 770 TRANS_DDI_MODE_SELECT_MASK; 771 772 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 773 ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 774 ret = type == DRM_MODE_CONNECTOR_HDMIA; 775 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 776 ret = type == DRM_MODE_CONNECTOR_VGA; 777 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 778 ret = type == DRM_MODE_CONNECTOR_eDP || 779 type == DRM_MODE_CONNECTOR_DisplayPort; 780 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 781 /* 782 * encoder->get_hw_state() should have bailed out on MST. This 783 * must be SST and non-eDP. 784 */ 785 ret = type == DRM_MODE_CONNECTOR_DisplayPort; 786 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 787 /* encoder->get_hw_state() should have bailed out on MST. */ 788 ret = false; 789 } else { 790 ret = false; 791 } 792 793 out: 794 intel_display_power_put(display, encoder->power_domain, wakeref); 795 796 return ret; 797 } 798 799 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 800 u8 *pipe_mask, bool *is_dp_mst) 801 { 802 struct intel_display *display = to_intel_display(encoder); 803 enum port port = encoder->port; 804 intel_wakeref_t wakeref; 805 enum pipe p; 806 u32 tmp; 807 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; 808 809 *pipe_mask = 0; 810 *is_dp_mst = false; 811 812 wakeref = intel_display_power_get_if_enabled(display, 813 encoder->power_domain); 814 if (!wakeref) 815 return; 816 817 tmp = intel_de_read(display, DDI_BUF_CTL(port)); 818 if (!(tmp & DDI_BUF_CTL_ENABLE)) 819 goto out; 820 821 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) { 822 tmp = intel_de_read(display, 823 TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP)); 824 825 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 826 default: 827 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 828 fallthrough; 829 case TRANS_DDI_EDP_INPUT_A_ON: 830 case TRANS_DDI_EDP_INPUT_A_ONOFF: 831 *pipe_mask = BIT(PIPE_A); 832 break; 833 case TRANS_DDI_EDP_INPUT_B_ONOFF: 834 *pipe_mask = BIT(PIPE_B); 835 break; 836 case TRANS_DDI_EDP_INPUT_C_ONOFF: 837 *pipe_mask = BIT(PIPE_C); 838 break; 839 } 840 841 goto out; 842 } 843 844 for_each_pipe(display, p) { 845 enum transcoder cpu_transcoder = (enum transcoder)p; 846 u32 port_mask, ddi_select, ddi_mode; 847 intel_wakeref_t trans_wakeref; 848 849 trans_wakeref = intel_display_power_get_if_enabled(display, 850 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 851 if (!trans_wakeref) 852 continue; 853 854 if (DISPLAY_VER(display) >= 12) { 855 port_mask = TGL_TRANS_DDI_PORT_MASK; 856 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 857 } else { 858 port_mask = TRANS_DDI_PORT_MASK; 859 ddi_select = TRANS_DDI_SELECT_PORT(port); 860 } 861 862 tmp = intel_de_read(display, 863 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 864 intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 865 trans_wakeref); 866 867 if ((tmp & port_mask) != ddi_select) 868 continue; 869 870 ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 871 872 if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) 873 mst_pipe_mask |= BIT(p); 874 else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) 875 dp128b132b_pipe_mask |= BIT(p); 876 877 *pipe_mask |= BIT(p); 878 } 879 880 if (!*pipe_mask) 881 drm_dbg_kms(display->drm, 882 "No pipe for [ENCODER:%d:%s] found\n", 883 encoder->base.base.id, encoder->base.name); 884 885 if (!mst_pipe_mask && dp128b132b_pipe_mask) { 886 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 887 888 /* 889 * If we don't have 8b/10b MST, but have more than one 890 * transcoder in 128b/132b mode, we know it must be 128b/132b 891 * MST. 892 * 893 * Otherwise, we fall back to checking the current MST 894 * state. It's not accurate for hardware takeover at probe, but 895 * we don't expect MST to have been enabled at that point, and 896 * can assume it's SST. 897 */ 898 if (hweight8(dp128b132b_pipe_mask) > 1 || 899 intel_dp_mst_active_streams(intel_dp)) 900 mst_pipe_mask = dp128b132b_pipe_mask; 901 } 902 903 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 904 drm_dbg_kms(display->drm, 905 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 906 encoder->base.base.id, encoder->base.name, 907 *pipe_mask); 908 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 909 } 910 911 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 912 drm_dbg_kms(display->drm, 913 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n", 914 encoder->base.base.id, encoder->base.name, 915 *pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask); 916 else 917 *is_dp_mst = mst_pipe_mask; 918 919 out: 920 if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) { 921 tmp = intel_de_read(display, BXT_PHY_CTL(port)); 922 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 923 BXT_PHY_LANE_POWERDOWN_ACK | 924 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 925 drm_err(display->drm, 926 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 927 encoder->base.base.id, encoder->base.name, tmp); 928 } 929 930 intel_display_power_put(display, encoder->power_domain, wakeref); 931 } 932 933 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 934 enum pipe *pipe) 935 { 936 u8 pipe_mask; 937 bool is_mst; 938 939 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 940 941 if (is_mst || !pipe_mask) 942 return false; 943 944 *pipe = ffs(pipe_mask) - 1; 945 946 return true; 947 } 948 949 static enum intel_display_power_domain 950 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 951 const struct intel_crtc_state *crtc_state) 952 { 953 struct intel_display *display = to_intel_display(dig_port); 954 955 /* 956 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 957 * DC states enabled at the same time, while for driver initiated AUX 958 * transfers we need the same AUX IOs to be powered but with DC states 959 * disabled. Accordingly use the AUX_IO_<port> power domain here which 960 * leaves DC states enabled. 961 * 962 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 963 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 964 * well, so we can acquire a wider AUX_<port> power domain reference 965 * instead of a specific AUX_IO_<port> reference without powering up any 966 * extra wells. 967 */ 968 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) 969 return intel_display_power_aux_io_domain(display, dig_port->aux_ch); 970 else if (DISPLAY_VER(display) < 14 && 971 (intel_crtc_has_dp_encoder(crtc_state) || 972 intel_encoder_is_tc(&dig_port->base))) 973 return intel_aux_power_domain(dig_port); 974 else 975 return POWER_DOMAIN_INVALID; 976 } 977 978 static void 979 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 980 const struct intel_crtc_state *crtc_state) 981 { 982 struct intel_display *display = to_intel_display(dig_port); 983 enum intel_display_power_domain domain = 984 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 985 986 drm_WARN_ON(display->drm, dig_port->aux_wakeref); 987 988 if (domain == POWER_DOMAIN_INVALID) 989 return; 990 991 dig_port->aux_wakeref = intel_display_power_get(display, domain); 992 } 993 994 static void 995 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 996 const struct intel_crtc_state *crtc_state) 997 { 998 struct intel_display *display = to_intel_display(dig_port); 999 enum intel_display_power_domain domain = 1000 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1001 intel_wakeref_t wf; 1002 1003 wf = fetch_and_zero(&dig_port->aux_wakeref); 1004 if (!wf) 1005 return; 1006 1007 intel_display_power_put(display, domain, wf); 1008 } 1009 1010 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 1011 struct intel_crtc_state *crtc_state) 1012 { 1013 struct intel_display *display = to_intel_display(encoder); 1014 struct intel_digital_port *dig_port; 1015 1016 /* 1017 * TODO: Add support for MST encoders. Atm, the following should never 1018 * happen since fake-MST encoders don't set their get_power_domains() 1019 * hook. 1020 */ 1021 if (drm_WARN_ON(display->drm, 1022 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 1023 return; 1024 1025 dig_port = enc_to_dig_port(encoder); 1026 1027 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 1028 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 1029 dig_port->ddi_io_wakeref = intel_display_power_get(display, 1030 dig_port->ddi_io_power_domain); 1031 } 1032 1033 main_link_aux_power_domain_get(dig_port, crtc_state); 1034 } 1035 1036 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 1037 const struct intel_crtc_state *crtc_state) 1038 { 1039 struct intel_display *display = to_intel_display(crtc_state); 1040 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1041 enum phy phy = intel_encoder_to_phy(encoder); 1042 u32 val; 1043 1044 if (cpu_transcoder == TRANSCODER_EDP) 1045 return; 1046 1047 if (DISPLAY_VER(display) >= 13) 1048 val = TGL_TRANS_CLK_SEL_PORT(phy); 1049 else if (DISPLAY_VER(display) >= 12) 1050 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 1051 else 1052 val = TRANS_CLK_SEL_PORT(encoder->port); 1053 1054 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1055 } 1056 1057 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1058 { 1059 struct intel_display *display = to_intel_display(crtc_state); 1060 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1061 u32 val; 1062 1063 if (cpu_transcoder == TRANSCODER_EDP) 1064 return; 1065 1066 if (DISPLAY_VER(display) >= 12) 1067 val = TGL_TRANS_CLK_SEL_DISABLED; 1068 else 1069 val = TRANS_CLK_SEL_DISABLED; 1070 1071 intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val); 1072 } 1073 1074 static void _skl_ddi_set_iboost(struct intel_display *display, 1075 enum port port, u8 iboost) 1076 { 1077 u32 tmp; 1078 1079 tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0); 1080 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1081 if (iboost) 1082 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1083 else 1084 tmp |= BALANCE_LEG_DISABLE(port); 1085 intel_de_write(display, DISPIO_CR_TX_BMU_CR0, tmp); 1086 } 1087 1088 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1089 const struct intel_crtc_state *crtc_state, 1090 int level) 1091 { 1092 struct intel_display *display = to_intel_display(encoder); 1093 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1094 u8 iboost; 1095 1096 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1097 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1098 else 1099 iboost = intel_bios_dp_boost_level(encoder->devdata); 1100 1101 if (iboost == 0) { 1102 const struct intel_ddi_buf_trans *trans; 1103 int n_entries; 1104 1105 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1106 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1107 return; 1108 1109 iboost = trans->entries[level].hsw.i_boost; 1110 } 1111 1112 /* Make sure that the requested I_boost is valid */ 1113 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1114 drm_err(display->drm, "Invalid I_boost value %u\n", iboost); 1115 return; 1116 } 1117 1118 _skl_ddi_set_iboost(display, encoder->port, iboost); 1119 1120 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1121 _skl_ddi_set_iboost(display, PORT_E, iboost); 1122 } 1123 1124 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1125 const struct intel_crtc_state *crtc_state) 1126 { 1127 struct intel_display *display = to_intel_display(intel_dp); 1128 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1129 int n_entries; 1130 1131 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1132 1133 if (drm_WARN_ON(display->drm, n_entries < 1)) 1134 n_entries = 1; 1135 if (drm_WARN_ON(display->drm, 1136 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1137 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1138 1139 return index_to_dp_signal_levels[n_entries - 1] & 1140 DP_TRAIN_VOLTAGE_SWING_MASK; 1141 } 1142 1143 /* 1144 * We assume that the full set of pre-emphasis values can be 1145 * used on all DDI platforms. Should that change we need to 1146 * rethink this code. 1147 */ 1148 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1149 { 1150 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1151 } 1152 1153 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1154 int lane) 1155 { 1156 if (crtc_state->port_clock > 600000) 1157 return 0; 1158 1159 if (crtc_state->lane_count == 4) 1160 return lane >= 1 ? LOADGEN_SELECT : 0; 1161 else 1162 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1163 } 1164 1165 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1166 const struct intel_crtc_state *crtc_state) 1167 { 1168 struct intel_display *display = to_intel_display(encoder); 1169 const struct intel_ddi_buf_trans *trans; 1170 enum phy phy = intel_encoder_to_phy(encoder); 1171 int n_entries, ln; 1172 u32 val; 1173 1174 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1175 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1176 return; 1177 1178 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1179 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1180 1181 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1182 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1183 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), val, 1184 intel_dp->hobl_active ? val : 0); 1185 } 1186 1187 /* Set PORT_TX_DW5 */ 1188 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1189 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1190 COEFF_POLARITY | CURSOR_PROGRAM | 1191 TAP2_DISABLE | TAP3_DISABLE); 1192 val |= SCALING_MODE_SEL(0x2); 1193 val |= RTERM_SELECT(0x6); 1194 val |= TAP3_DISABLE; 1195 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1196 1197 /* Program PORT_TX_DW2 */ 1198 for (ln = 0; ln < 4; ln++) { 1199 int level = intel_ddi_level(encoder, crtc_state, ln); 1200 1201 intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy), 1202 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1203 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1204 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1205 RCOMP_SCALAR(0x98)); 1206 } 1207 1208 /* Program PORT_TX_DW4 */ 1209 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1210 for (ln = 0; ln < 4; ln++) { 1211 int level = intel_ddi_level(encoder, crtc_state, ln); 1212 1213 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1214 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1215 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1216 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1217 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1218 } 1219 1220 /* Program PORT_TX_DW7 */ 1221 for (ln = 0; ln < 4; ln++) { 1222 int level = intel_ddi_level(encoder, crtc_state, ln); 1223 1224 intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy), 1225 N_SCALAR_MASK, 1226 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1227 } 1228 } 1229 1230 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1231 const struct intel_crtc_state *crtc_state) 1232 { 1233 struct intel_display *display = to_intel_display(encoder); 1234 enum phy phy = intel_encoder_to_phy(encoder); 1235 u32 val; 1236 int ln; 1237 1238 /* 1239 * 1. If port type is eDP or DP, 1240 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1241 * else clear to 0b. 1242 */ 1243 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 1244 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1245 val &= ~COMMON_KEEPER_EN; 1246 else 1247 val |= COMMON_KEEPER_EN; 1248 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); 1249 1250 /* 2. Program loadgen select */ 1251 /* 1252 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1253 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1254 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1255 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1256 */ 1257 for (ln = 0; ln < 4; ln++) { 1258 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy), 1259 LOADGEN_SELECT, 1260 icl_combo_phy_loadgen_select(crtc_state, ln)); 1261 } 1262 1263 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1264 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 1265 0, SUS_CLOCK_CONFIG); 1266 1267 /* 4. Clear training enable to change swing values */ 1268 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1269 val &= ~TX_TRAINING_EN; 1270 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1271 1272 /* 5. Program swing and de-emphasis */ 1273 icl_ddi_combo_vswing_program(encoder, crtc_state); 1274 1275 /* 6. Set training enable to trigger update */ 1276 val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 1277 val |= TX_TRAINING_EN; 1278 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val); 1279 } 1280 1281 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1282 const struct intel_crtc_state *crtc_state) 1283 { 1284 struct intel_display *display = to_intel_display(encoder); 1285 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1286 const struct intel_ddi_buf_trans *trans; 1287 int n_entries, ln; 1288 1289 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1290 return; 1291 1292 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1293 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1294 return; 1295 1296 for (ln = 0; ln < 2; ln++) { 1297 intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port), 1298 CRI_USE_FS32, 0); 1299 intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port), 1300 CRI_USE_FS32, 0); 1301 } 1302 1303 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1304 for (ln = 0; ln < 2; ln++) { 1305 int level; 1306 1307 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1308 1309 intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port), 1310 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1311 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1312 1313 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1314 1315 intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port), 1316 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1317 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1318 } 1319 1320 /* Program MG_TX_DRVCTRL with values from vswing table */ 1321 for (ln = 0; ln < 2; ln++) { 1322 int level; 1323 1324 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1325 1326 intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port), 1327 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1328 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1329 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1330 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1331 CRI_TXDEEMPH_OVERRIDE_EN); 1332 1333 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1334 1335 intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port), 1336 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1337 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1338 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1339 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1340 CRI_TXDEEMPH_OVERRIDE_EN); 1341 1342 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1343 } 1344 1345 /* 1346 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1347 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1348 * values from table for which TX1 and TX2 enabled. 1349 */ 1350 for (ln = 0; ln < 2; ln++) { 1351 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), 1352 CFG_LOW_RATE_LKREN_EN, 1353 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1354 } 1355 1356 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1357 for (ln = 0; ln < 2; ln++) { 1358 intel_de_rmw(display, MG_TX1_DCC(ln, tc_port), 1359 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1360 CFG_AMI_CK_DIV_OVERRIDE_EN, 1361 crtc_state->port_clock > 500000 ? 1362 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1363 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1364 1365 intel_de_rmw(display, MG_TX2_DCC(ln, tc_port), 1366 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1367 CFG_AMI_CK_DIV_OVERRIDE_EN, 1368 crtc_state->port_clock > 500000 ? 1369 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1370 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1371 } 1372 1373 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1374 for (ln = 0; ln < 2; ln++) { 1375 intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port), 1376 0, CRI_CALCINIT); 1377 intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port), 1378 0, CRI_CALCINIT); 1379 } 1380 } 1381 1382 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1383 const struct intel_crtc_state *crtc_state) 1384 { 1385 struct intel_display *display = to_intel_display(encoder); 1386 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1387 const struct intel_ddi_buf_trans *trans; 1388 int n_entries, ln; 1389 1390 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1391 return; 1392 1393 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1394 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1395 return; 1396 1397 for (ln = 0; ln < 2; ln++) { 1398 int level; 1399 1400 /* Wa_16011342517:adl-p */ 1401 if (display->platform.alderlake_p && 1402 IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) { 1403 if ((intel_encoder_is_hdmi(encoder) && 1404 crtc_state->port_clock == 594000) || 1405 (intel_encoder_is_dp(encoder) && 1406 crtc_state->port_clock == 162000)) { 1407 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1408 LOADGEN_SHARING_PMD_DISABLE, 1); 1409 } else { 1410 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1411 LOADGEN_SHARING_PMD_DISABLE, 0); 1412 } 1413 } 1414 1415 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1416 1417 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1418 1419 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), 1420 DKL_TX_PRESHOOT_COEFF_MASK | 1421 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1422 DKL_TX_VSWING_CONTROL_MASK, 1423 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1424 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1425 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1426 1427 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1428 1429 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), 1430 DKL_TX_PRESHOOT_COEFF_MASK | 1431 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1432 DKL_TX_VSWING_CONTROL_MASK, 1433 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1434 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1435 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1436 1437 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1438 DKL_TX_DP20BITMODE, 0); 1439 1440 if (display->platform.alderlake_p) { 1441 u32 val; 1442 1443 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1444 if (ln == 0) { 1445 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1446 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1447 } else { 1448 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1449 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1450 } 1451 } else { 1452 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1453 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1454 } 1455 1456 intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), 1457 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1458 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1459 val); 1460 } 1461 } 1462 } 1463 1464 static int translate_signal_level(struct intel_dp *intel_dp, 1465 u8 signal_levels) 1466 { 1467 struct intel_display *display = to_intel_display(intel_dp); 1468 int i; 1469 1470 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1471 if (index_to_dp_signal_levels[i] == signal_levels) 1472 return i; 1473 } 1474 1475 drm_WARN(display->drm, 1, 1476 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1477 signal_levels); 1478 1479 return 0; 1480 } 1481 1482 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1483 const struct intel_crtc_state *crtc_state, 1484 int lane) 1485 { 1486 u8 train_set = intel_dp->train_set[lane]; 1487 1488 if (intel_dp_is_uhbr(crtc_state)) { 1489 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1490 } else { 1491 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1492 DP_TRAIN_PRE_EMPHASIS_MASK); 1493 1494 return translate_signal_level(intel_dp, signal_levels); 1495 } 1496 } 1497 1498 int intel_ddi_level(struct intel_encoder *encoder, 1499 const struct intel_crtc_state *crtc_state, 1500 int lane) 1501 { 1502 struct intel_display *display = to_intel_display(encoder); 1503 const struct intel_ddi_buf_trans *trans; 1504 int level, n_entries; 1505 1506 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1507 if (drm_WARN_ON_ONCE(display->drm, !trans)) 1508 return 0; 1509 1510 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1511 level = intel_ddi_hdmi_level(encoder, trans); 1512 else 1513 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1514 lane); 1515 1516 if (drm_WARN_ON_ONCE(display->drm, level >= n_entries)) 1517 level = n_entries - 1; 1518 1519 return level; 1520 } 1521 1522 static void 1523 hsw_set_signal_levels(struct intel_encoder *encoder, 1524 const struct intel_crtc_state *crtc_state) 1525 { 1526 struct intel_display *display = to_intel_display(encoder); 1527 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1528 int level = intel_ddi_level(encoder, crtc_state, 0); 1529 enum port port = encoder->port; 1530 u32 signal_levels; 1531 1532 if (has_iboost(display)) 1533 skl_ddi_set_iboost(encoder, crtc_state, level); 1534 1535 /* HDMI ignores the rest */ 1536 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1537 return; 1538 1539 signal_levels = DDI_BUF_TRANS_SELECT(level); 1540 1541 drm_dbg_kms(display->drm, "Using signal levels %08x\n", 1542 signal_levels); 1543 1544 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1545 intel_dp->DP |= signal_levels; 1546 1547 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); 1548 intel_de_posting_read(display, DDI_BUF_CTL(port)); 1549 } 1550 1551 static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, 1552 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1553 { 1554 mutex_lock(&display->dpll.lock); 1555 1556 intel_de_rmw(display, reg, clk_sel_mask, clk_sel); 1557 1558 /* 1559 * "This step and the step before must be 1560 * done with separate register writes." 1561 */ 1562 intel_de_rmw(display, reg, clk_off, 0); 1563 1564 mutex_unlock(&display->dpll.lock); 1565 } 1566 1567 static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, 1568 u32 clk_off) 1569 { 1570 mutex_lock(&display->dpll.lock); 1571 1572 intel_de_rmw(display, reg, 0, clk_off); 1573 1574 mutex_unlock(&display->dpll.lock); 1575 } 1576 1577 static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, 1578 u32 clk_off) 1579 { 1580 return !(intel_de_read(display, reg) & clk_off); 1581 } 1582 1583 static struct intel_dpll * 1584 _icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, 1585 u32 clk_sel_mask, u32 clk_sel_shift) 1586 { 1587 enum intel_dpll_id id; 1588 1589 id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; 1590 1591 return intel_get_dpll_by_id(display, id); 1592 } 1593 1594 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1595 const struct intel_crtc_state *crtc_state) 1596 { 1597 struct intel_display *display = to_intel_display(encoder); 1598 const struct intel_dpll *pll = crtc_state->intel_dpll; 1599 enum phy phy = intel_encoder_to_phy(encoder); 1600 1601 if (drm_WARN_ON(display->drm, !pll)) 1602 return; 1603 1604 _icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1605 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1606 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1607 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1608 } 1609 1610 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1611 { 1612 struct intel_display *display = to_intel_display(encoder); 1613 enum phy phy = intel_encoder_to_phy(encoder); 1614 1615 _icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy), 1616 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1617 } 1618 1619 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1620 { 1621 struct intel_display *display = to_intel_display(encoder); 1622 enum phy phy = intel_encoder_to_phy(encoder); 1623 1624 return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy), 1625 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1626 } 1627 1628 static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1629 { 1630 struct intel_display *display = to_intel_display(encoder); 1631 enum phy phy = intel_encoder_to_phy(encoder); 1632 1633 return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), 1634 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1635 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1636 } 1637 1638 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1639 const struct intel_crtc_state *crtc_state) 1640 { 1641 struct intel_display *display = to_intel_display(encoder); 1642 const struct intel_dpll *pll = crtc_state->intel_dpll; 1643 enum phy phy = intel_encoder_to_phy(encoder); 1644 1645 if (drm_WARN_ON(display->drm, !pll)) 1646 return; 1647 1648 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1649 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1650 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1651 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1652 } 1653 1654 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1655 { 1656 struct intel_display *display = to_intel_display(encoder); 1657 enum phy phy = intel_encoder_to_phy(encoder); 1658 1659 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1660 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1661 } 1662 1663 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1664 { 1665 struct intel_display *display = to_intel_display(encoder); 1666 enum phy phy = intel_encoder_to_phy(encoder); 1667 1668 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1669 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1670 } 1671 1672 static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1673 { 1674 struct intel_display *display = to_intel_display(encoder); 1675 enum phy phy = intel_encoder_to_phy(encoder); 1676 1677 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1678 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1679 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1680 } 1681 1682 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1683 const struct intel_crtc_state *crtc_state) 1684 { 1685 struct intel_display *display = to_intel_display(encoder); 1686 const struct intel_dpll *pll = crtc_state->intel_dpll; 1687 enum phy phy = intel_encoder_to_phy(encoder); 1688 1689 if (drm_WARN_ON(display->drm, !pll)) 1690 return; 1691 1692 /* 1693 * If we fail this, something went very wrong: first 2 PLLs should be 1694 * used by first 2 phys and last 2 PLLs by last phys 1695 */ 1696 if (drm_WARN_ON(display->drm, 1697 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1698 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1699 return; 1700 1701 _icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1702 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1703 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1704 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1705 } 1706 1707 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1708 { 1709 struct intel_display *display = to_intel_display(encoder); 1710 enum phy phy = intel_encoder_to_phy(encoder); 1711 1712 _icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy), 1713 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1714 } 1715 1716 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1717 { 1718 struct intel_display *display = to_intel_display(encoder); 1719 enum phy phy = intel_encoder_to_phy(encoder); 1720 1721 return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy), 1722 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1723 } 1724 1725 static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1726 { 1727 struct intel_display *display = to_intel_display(encoder); 1728 enum phy phy = intel_encoder_to_phy(encoder); 1729 enum intel_dpll_id id; 1730 u32 val; 1731 1732 val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); 1733 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1734 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1735 id = val; 1736 1737 /* 1738 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1739 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1740 * bit for phy C and D. 1741 */ 1742 if (phy >= PHY_C) 1743 id += DPLL_ID_DG1_DPLL2; 1744 1745 return intel_get_dpll_by_id(display, id); 1746 } 1747 1748 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1749 const struct intel_crtc_state *crtc_state) 1750 { 1751 struct intel_display *display = to_intel_display(encoder); 1752 const struct intel_dpll *pll = crtc_state->intel_dpll; 1753 enum phy phy = intel_encoder_to_phy(encoder); 1754 1755 if (drm_WARN_ON(display->drm, !pll)) 1756 return; 1757 1758 _icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0, 1759 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1760 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1761 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1762 } 1763 1764 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1765 { 1766 struct intel_display *display = to_intel_display(encoder); 1767 enum phy phy = intel_encoder_to_phy(encoder); 1768 1769 _icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0, 1770 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1771 } 1772 1773 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1774 { 1775 struct intel_display *display = to_intel_display(encoder); 1776 enum phy phy = intel_encoder_to_phy(encoder); 1777 1778 return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0, 1779 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1780 } 1781 1782 struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1783 { 1784 struct intel_display *display = to_intel_display(encoder); 1785 enum phy phy = intel_encoder_to_phy(encoder); 1786 1787 return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, 1788 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1789 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1790 } 1791 1792 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1793 const struct intel_crtc_state *crtc_state) 1794 { 1795 struct intel_display *display = to_intel_display(encoder); 1796 const struct intel_dpll *pll = crtc_state->intel_dpll; 1797 enum port port = encoder->port; 1798 1799 if (drm_WARN_ON(display->drm, !pll)) 1800 return; 1801 1802 /* 1803 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1804 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1805 */ 1806 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1807 1808 icl_ddi_combo_enable_clock(encoder, crtc_state); 1809 } 1810 1811 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1812 { 1813 struct intel_display *display = to_intel_display(encoder); 1814 enum port port = encoder->port; 1815 1816 icl_ddi_combo_disable_clock(encoder); 1817 1818 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1819 } 1820 1821 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1822 { 1823 struct intel_display *display = to_intel_display(encoder); 1824 enum port port = encoder->port; 1825 u32 tmp; 1826 1827 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1828 1829 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1830 return false; 1831 1832 return icl_ddi_combo_is_clock_enabled(encoder); 1833 } 1834 1835 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1836 const struct intel_crtc_state *crtc_state) 1837 { 1838 struct intel_display *display = to_intel_display(encoder); 1839 const struct intel_dpll *pll = crtc_state->intel_dpll; 1840 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1841 enum port port = encoder->port; 1842 1843 if (drm_WARN_ON(display->drm, !pll)) 1844 return; 1845 1846 intel_de_write(display, DDI_CLK_SEL(port), 1847 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1848 1849 mutex_lock(&display->dpll.lock); 1850 1851 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1852 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1853 1854 mutex_unlock(&display->dpll.lock); 1855 } 1856 1857 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1858 { 1859 struct intel_display *display = to_intel_display(encoder); 1860 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1861 enum port port = encoder->port; 1862 1863 mutex_lock(&display->dpll.lock); 1864 1865 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, 1866 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1867 1868 mutex_unlock(&display->dpll.lock); 1869 1870 intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1871 } 1872 1873 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1874 { 1875 struct intel_display *display = to_intel_display(encoder); 1876 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1877 enum port port = encoder->port; 1878 u32 tmp; 1879 1880 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1881 1882 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1883 return false; 1884 1885 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 1886 1887 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1888 } 1889 1890 static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1891 { 1892 struct intel_display *display = to_intel_display(encoder); 1893 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1894 enum port port = encoder->port; 1895 enum intel_dpll_id id; 1896 u32 tmp; 1897 1898 tmp = intel_de_read(display, DDI_CLK_SEL(port)); 1899 1900 switch (tmp & DDI_CLK_SEL_MASK) { 1901 case DDI_CLK_SEL_TBT_162: 1902 case DDI_CLK_SEL_TBT_270: 1903 case DDI_CLK_SEL_TBT_540: 1904 case DDI_CLK_SEL_TBT_810: 1905 id = DPLL_ID_ICL_TBTPLL; 1906 break; 1907 case DDI_CLK_SEL_MG: 1908 id = icl_tc_port_to_pll_id(tc_port); 1909 break; 1910 default: 1911 MISSING_CASE(tmp); 1912 fallthrough; 1913 case DDI_CLK_SEL_NONE: 1914 return NULL; 1915 } 1916 1917 return intel_get_dpll_by_id(display, id); 1918 } 1919 1920 static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1921 { 1922 struct intel_display *display = to_intel_display(encoder->base.dev); 1923 enum intel_dpll_id id; 1924 1925 switch (encoder->port) { 1926 case PORT_A: 1927 id = DPLL_ID_SKL_DPLL0; 1928 break; 1929 case PORT_B: 1930 id = DPLL_ID_SKL_DPLL1; 1931 break; 1932 case PORT_C: 1933 id = DPLL_ID_SKL_DPLL2; 1934 break; 1935 default: 1936 MISSING_CASE(encoder->port); 1937 return NULL; 1938 } 1939 1940 return intel_get_dpll_by_id(display, id); 1941 } 1942 1943 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1944 const struct intel_crtc_state *crtc_state) 1945 { 1946 struct intel_display *display = to_intel_display(encoder); 1947 const struct intel_dpll *pll = crtc_state->intel_dpll; 1948 enum port port = encoder->port; 1949 1950 if (drm_WARN_ON(display->drm, !pll)) 1951 return; 1952 1953 mutex_lock(&display->dpll.lock); 1954 1955 intel_de_rmw(display, DPLL_CTRL2, 1956 DPLL_CTRL2_DDI_CLK_OFF(port) | 1957 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1958 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1959 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1960 1961 mutex_unlock(&display->dpll.lock); 1962 } 1963 1964 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1965 { 1966 struct intel_display *display = to_intel_display(encoder); 1967 enum port port = encoder->port; 1968 1969 mutex_lock(&display->dpll.lock); 1970 1971 intel_de_rmw(display, DPLL_CTRL2, 1972 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1973 1974 mutex_unlock(&display->dpll.lock); 1975 } 1976 1977 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1978 { 1979 struct intel_display *display = to_intel_display(encoder); 1980 enum port port = encoder->port; 1981 1982 /* 1983 * FIXME Not sure if the override affects both 1984 * the PLL selection and the CLK_OFF bit. 1985 */ 1986 return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1987 } 1988 1989 static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1990 { 1991 struct intel_display *display = to_intel_display(encoder); 1992 enum port port = encoder->port; 1993 enum intel_dpll_id id; 1994 u32 tmp; 1995 1996 tmp = intel_de_read(display, DPLL_CTRL2); 1997 1998 /* 1999 * FIXME Not sure if the override affects both 2000 * the PLL selection and the CLK_OFF bit. 2001 */ 2002 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2003 return NULL; 2004 2005 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2006 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2007 2008 return intel_get_dpll_by_id(display, id); 2009 } 2010 2011 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2012 const struct intel_crtc_state *crtc_state) 2013 { 2014 struct intel_display *display = to_intel_display(encoder); 2015 const struct intel_dpll *pll = crtc_state->intel_dpll; 2016 enum port port = encoder->port; 2017 2018 if (drm_WARN_ON(display->drm, !pll)) 2019 return; 2020 2021 intel_de_write(display, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2022 } 2023 2024 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2025 { 2026 struct intel_display *display = to_intel_display(encoder); 2027 enum port port = encoder->port; 2028 2029 intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2030 } 2031 2032 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2033 { 2034 struct intel_display *display = to_intel_display(encoder); 2035 enum port port = encoder->port; 2036 2037 return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2038 } 2039 2040 static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2041 { 2042 struct intel_display *display = to_intel_display(encoder); 2043 enum port port = encoder->port; 2044 enum intel_dpll_id id; 2045 u32 tmp; 2046 2047 tmp = intel_de_read(display, PORT_CLK_SEL(port)); 2048 2049 switch (tmp & PORT_CLK_SEL_MASK) { 2050 case PORT_CLK_SEL_WRPLL1: 2051 id = DPLL_ID_WRPLL1; 2052 break; 2053 case PORT_CLK_SEL_WRPLL2: 2054 id = DPLL_ID_WRPLL2; 2055 break; 2056 case PORT_CLK_SEL_SPLL: 2057 id = DPLL_ID_SPLL; 2058 break; 2059 case PORT_CLK_SEL_LCPLL_810: 2060 id = DPLL_ID_LCPLL_810; 2061 break; 2062 case PORT_CLK_SEL_LCPLL_1350: 2063 id = DPLL_ID_LCPLL_1350; 2064 break; 2065 case PORT_CLK_SEL_LCPLL_2700: 2066 id = DPLL_ID_LCPLL_2700; 2067 break; 2068 default: 2069 MISSING_CASE(tmp); 2070 fallthrough; 2071 case PORT_CLK_SEL_NONE: 2072 return NULL; 2073 } 2074 2075 return intel_get_dpll_by_id(display, id); 2076 } 2077 2078 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2079 const struct intel_crtc_state *crtc_state) 2080 { 2081 if (encoder->enable_clock) 2082 encoder->enable_clock(encoder, crtc_state); 2083 } 2084 2085 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2086 { 2087 if (encoder->disable_clock) 2088 encoder->disable_clock(encoder); 2089 } 2090 2091 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2092 { 2093 struct intel_display *display = to_intel_display(encoder); 2094 u32 port_mask; 2095 bool ddi_clk_needed; 2096 2097 /* 2098 * In case of DP MST, we sanitize the primary encoder only, not the 2099 * virtual ones. 2100 */ 2101 if (encoder->type == INTEL_OUTPUT_DP_MST) 2102 return; 2103 2104 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2105 u8 pipe_mask; 2106 bool is_mst; 2107 2108 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2109 /* 2110 * In the unlikely case that BIOS enables DP in MST mode, just 2111 * warn since our MST HW readout is incomplete. 2112 */ 2113 if (drm_WARN_ON(display->drm, is_mst)) 2114 return; 2115 } 2116 2117 port_mask = BIT(encoder->port); 2118 ddi_clk_needed = encoder->base.crtc; 2119 2120 if (encoder->type == INTEL_OUTPUT_DSI) { 2121 struct intel_encoder *other_encoder; 2122 2123 port_mask = intel_dsi_encoder_ports(encoder); 2124 /* 2125 * Sanity check that we haven't incorrectly registered another 2126 * encoder using any of the ports of this DSI encoder. 2127 */ 2128 for_each_intel_encoder(display->drm, other_encoder) { 2129 if (other_encoder == encoder) 2130 continue; 2131 2132 if (drm_WARN_ON(display->drm, 2133 port_mask & BIT(other_encoder->port))) 2134 return; 2135 } 2136 /* 2137 * For DSI we keep the ddi clocks gated 2138 * except during enable/disable sequence. 2139 */ 2140 ddi_clk_needed = false; 2141 } 2142 2143 if (ddi_clk_needed || !encoder->is_clock_enabled || 2144 !encoder->is_clock_enabled(encoder)) 2145 return; 2146 2147 drm_dbg_kms(display->drm, 2148 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2149 encoder->base.base.id, encoder->base.name); 2150 2151 encoder->disable_clock(encoder); 2152 } 2153 2154 static void 2155 tgl_dkl_phy_check_and_rewrite(struct intel_display *display, 2156 enum tc_port tc_port, u32 ln0, u32 ln1) 2157 { 2158 if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) 2159 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2160 if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) 2161 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2162 } 2163 2164 static void 2165 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2166 const struct intel_crtc_state *crtc_state) 2167 { 2168 struct intel_display *display = to_intel_display(crtc_state); 2169 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2170 enum intel_tc_pin_assignment pin_assignment; 2171 u32 ln0, ln1; 2172 u8 width; 2173 2174 if (DISPLAY_VER(display) >= 14) 2175 return; 2176 2177 if (!intel_encoder_is_tc(&dig_port->base) || 2178 intel_tc_port_in_tbt_alt_mode(dig_port)) 2179 return; 2180 2181 if (DISPLAY_VER(display) >= 12) { 2182 ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); 2183 ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); 2184 } else { 2185 ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); 2186 ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); 2187 } 2188 2189 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2190 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2191 2192 /* DPPATC */ 2193 pin_assignment = intel_tc_port_get_pin_assignment(dig_port); 2194 width = crtc_state->lane_count; 2195 2196 switch (pin_assignment) { 2197 case INTEL_TC_PIN_ASSIGNMENT_NONE: 2198 drm_WARN_ON(display->drm, 2199 !intel_tc_port_in_legacy_mode(dig_port)); 2200 if (width == 1) { 2201 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2202 } else { 2203 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2204 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2205 } 2206 break; 2207 case INTEL_TC_PIN_ASSIGNMENT_A: 2208 if (width == 4) { 2209 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2210 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2211 } 2212 break; 2213 case INTEL_TC_PIN_ASSIGNMENT_B: 2214 if (width == 2) { 2215 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2216 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2217 } 2218 break; 2219 case INTEL_TC_PIN_ASSIGNMENT_C: 2220 case INTEL_TC_PIN_ASSIGNMENT_E: 2221 if (width == 1) { 2222 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2223 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2224 } else { 2225 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2226 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2227 } 2228 break; 2229 case INTEL_TC_PIN_ASSIGNMENT_D: 2230 case INTEL_TC_PIN_ASSIGNMENT_F: 2231 if (width == 1) { 2232 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2233 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2234 } else { 2235 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2236 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2237 } 2238 break; 2239 default: 2240 MISSING_CASE(pin_assignment); 2241 } 2242 2243 if (DISPLAY_VER(display) >= 12) { 2244 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); 2245 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); 2246 /* WA_14018221282 */ 2247 if (IS_DISPLAY_VER(display, 12, 13)) 2248 tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); 2249 2250 } else { 2251 intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); 2252 intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); 2253 } 2254 } 2255 2256 static enum transcoder 2257 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2258 { 2259 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2260 return crtc_state->mst_master_transcoder; 2261 else 2262 return crtc_state->cpu_transcoder; 2263 } 2264 2265 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2266 const struct intel_crtc_state *crtc_state) 2267 { 2268 struct intel_display *display = to_intel_display(encoder); 2269 2270 if (DISPLAY_VER(display) >= 12) 2271 return TGL_DP_TP_CTL(display, 2272 tgl_dp_tp_transcoder(crtc_state)); 2273 else 2274 return DP_TP_CTL(encoder->port); 2275 } 2276 2277 static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2278 const struct intel_crtc_state *crtc_state) 2279 { 2280 struct intel_display *display = to_intel_display(encoder); 2281 2282 if (DISPLAY_VER(display) >= 12) 2283 return TGL_DP_TP_STATUS(display, 2284 tgl_dp_tp_transcoder(crtc_state)); 2285 else 2286 return DP_TP_STATUS(encoder->port); 2287 } 2288 2289 void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2290 const struct intel_crtc_state *crtc_state) 2291 { 2292 struct intel_display *display = to_intel_display(encoder); 2293 2294 intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2295 DP_TP_STATUS_ACT_SENT); 2296 } 2297 2298 void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2299 const struct intel_crtc_state *crtc_state) 2300 { 2301 struct intel_display *display = to_intel_display(encoder); 2302 2303 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2304 DP_TP_STATUS_ACT_SENT, 1)) 2305 drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2306 } 2307 2308 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2309 const struct intel_crtc_state *crtc_state, 2310 bool enable) 2311 { 2312 struct intel_display *display = to_intel_display(intel_dp); 2313 2314 if (!crtc_state->vrr.enable) 2315 return; 2316 2317 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2318 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2319 drm_dbg_kms(display->drm, 2320 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2321 str_enable_disable(enable)); 2322 } 2323 2324 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2325 const struct intel_crtc_state *crtc_state, 2326 bool enable) 2327 { 2328 struct intel_display *display = to_intel_display(intel_dp); 2329 2330 if (!crtc_state->fec_enable) 2331 return; 2332 2333 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2334 enable ? DP_FEC_READY : 0) <= 0) 2335 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", 2336 str_enabled_disabled(enable)); 2337 2338 if (enable && 2339 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2340 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2341 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); 2342 } 2343 2344 static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2345 { 2346 struct intel_display *display = to_intel_display(aux->drm_dev); 2347 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2348 u8 status = 0; 2349 int ret, err; 2350 2351 ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status), 2352 err || (status & mask), 2353 10 * 1000, 200 * 1000, false); 2354 2355 /* Either can be non-zero, but not both */ 2356 ret = ret ?: err; 2357 if (ret) { 2358 drm_dbg_kms(display->drm, 2359 "Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n", 2360 str_enabled_disabled(enabled), ret, status); 2361 return ret; 2362 } 2363 2364 return 0; 2365 } 2366 2367 int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2368 const struct intel_crtc_state *crtc_state, 2369 bool enabled) 2370 { 2371 struct intel_display *display = to_intel_display(encoder); 2372 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2373 int ret; 2374 2375 if (!crtc_state->fec_enable) 2376 return 0; 2377 2378 if (enabled) 2379 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2380 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2381 else 2382 ret = intel_de_wait_for_clear(display, dp_tp_status_reg(encoder, crtc_state), 2383 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2384 2385 if (ret) { 2386 drm_err(display->drm, 2387 "Timeout waiting for FEC live state to get %s\n", 2388 str_enabled_disabled(enabled)); 2389 return ret; 2390 } 2391 /* 2392 * At least the Synoptics MST hub doesn't set the detected flag for 2393 * FEC decoding disabling so skip waiting for that. 2394 */ 2395 if (enabled) { 2396 ret = wait_for_fec_detected(&intel_dp->aux, enabled); 2397 if (ret) 2398 return ret; 2399 } 2400 2401 return 0; 2402 } 2403 2404 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2405 const struct intel_crtc_state *crtc_state) 2406 { 2407 struct intel_display *display = to_intel_display(encoder); 2408 int i; 2409 int ret; 2410 2411 if (!crtc_state->fec_enable) 2412 return; 2413 2414 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2415 0, DP_TP_CTL_FEC_ENABLE); 2416 2417 if (DISPLAY_VER(display) < 30) 2418 return; 2419 2420 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2421 if (!ret) 2422 return; 2423 2424 for (i = 0; i < 3; i++) { 2425 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); 2426 2427 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2428 DP_TP_CTL_FEC_ENABLE, 0); 2429 2430 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 2431 if (ret) 2432 continue; 2433 2434 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2435 0, DP_TP_CTL_FEC_ENABLE); 2436 2437 ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 2438 if (!ret) 2439 return; 2440 } 2441 2442 drm_err(display->drm, "Failed to enable FEC after retries\n"); 2443 } 2444 2445 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2446 const struct intel_crtc_state *crtc_state) 2447 { 2448 struct intel_display *display = to_intel_display(encoder); 2449 2450 if (!crtc_state->fec_enable) 2451 return; 2452 2453 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 2454 DP_TP_CTL_FEC_ENABLE, 0); 2455 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 2456 } 2457 2458 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2459 const struct intel_crtc_state *crtc_state) 2460 { 2461 struct intel_display *display = to_intel_display(encoder); 2462 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2463 2464 if (intel_encoder_is_combo(encoder)) { 2465 enum phy phy = intel_encoder_to_phy(encoder); 2466 2467 intel_combo_phy_power_up_lanes(display, phy, false, 2468 crtc_state->lane_count, 2469 dig_port->lane_reversal); 2470 } 2471 } 2472 2473 /* 2474 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2475 * platforms. 2476 */ 2477 static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display) 2478 { 2479 if (DISPLAY_VER(display) > 20) 2480 return ~0; 2481 else if (display->platform.alderlake_p) 2482 return BIT(PIPE_A) | BIT(PIPE_B); 2483 else 2484 return BIT(PIPE_A); 2485 } 2486 2487 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2488 struct intel_crtc_state *pipe_config) 2489 { 2490 struct intel_display *display = to_intel_display(pipe_config); 2491 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2492 enum pipe pipe = crtc->pipe; 2493 u32 dss1; 2494 2495 if (!HAS_MSO(display)) 2496 return; 2497 2498 dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 2499 2500 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2501 if (!pipe_config->splitter.enable) 2502 return; 2503 2504 if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) { 2505 pipe_config->splitter.enable = false; 2506 return; 2507 } 2508 2509 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2510 default: 2511 drm_WARN(display->drm, true, 2512 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2513 fallthrough; 2514 case SPLITTER_CONFIGURATION_2_SEGMENT: 2515 pipe_config->splitter.link_count = 2; 2516 break; 2517 case SPLITTER_CONFIGURATION_4_SEGMENT: 2518 pipe_config->splitter.link_count = 4; 2519 break; 2520 } 2521 2522 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2523 } 2524 2525 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2526 { 2527 struct intel_display *display = to_intel_display(crtc_state); 2528 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2529 enum pipe pipe = crtc->pipe; 2530 u32 dss1 = 0; 2531 2532 if (!HAS_MSO(display)) 2533 return; 2534 2535 if (crtc_state->splitter.enable) { 2536 dss1 |= SPLITTER_ENABLE; 2537 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2538 if (crtc_state->splitter.link_count == 2) 2539 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2540 else 2541 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2542 } 2543 2544 intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe), 2545 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2546 OVERLAP_PIXELS_MASK, dss1); 2547 } 2548 2549 static void 2550 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2551 { 2552 struct intel_display *display = to_intel_display(encoder); 2553 enum port port = encoder->port; 2554 i915_reg_t reg; 2555 u32 set_bits, wait_bits; 2556 int ret; 2557 2558 if (DISPLAY_VER(display) < 14) 2559 return; 2560 2561 if (DISPLAY_VER(display) >= 20) { 2562 reg = DDI_BUF_CTL(port); 2563 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2564 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2565 } else { 2566 reg = XELPDP_PORT_BUF_CTL1(display, port); 2567 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2568 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2569 } 2570 2571 intel_de_rmw(display, reg, 0, set_bits); 2572 2573 ret = intel_de_wait_custom(display, reg, 2574 wait_bits, wait_bits, 2575 100, 0, NULL); 2576 if (ret) { 2577 drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2578 port_name(port)); 2579 } 2580 } 2581 2582 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2583 const struct intel_crtc_state *crtc_state) 2584 { 2585 struct intel_display *display = to_intel_display(encoder); 2586 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2587 enum port port = encoder->port; 2588 u32 val = 0; 2589 2590 val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 2591 2592 if (intel_dp_is_uhbr(crtc_state)) 2593 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2594 else 2595 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2596 2597 if (dig_port->lane_reversal) 2598 val |= XELPDP_PORT_REVERSAL; 2599 2600 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 2601 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2602 val); 2603 } 2604 2605 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2606 { 2607 struct intel_display *display = to_intel_display(encoder); 2608 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2609 u32 val; 2610 2611 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2612 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2613 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 2614 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2615 } 2616 2617 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2618 struct intel_encoder *encoder, 2619 const struct intel_crtc_state *crtc_state, 2620 const struct drm_connector_state *conn_state) 2621 { 2622 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2623 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2624 bool transparent_mode; 2625 int ret; 2626 2627 intel_dp_set_link_params(intel_dp, 2628 crtc_state->port_clock, 2629 crtc_state->lane_count); 2630 2631 /* 2632 * We only configure what the register value will be here. Actual 2633 * enabling happens during link training farther down. 2634 */ 2635 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2636 2637 /* 2638 * 1. Enable Power Wells 2639 * 2640 * This was handled at the beginning of intel_atomic_commit_tail(), 2641 * before we called down into this function. 2642 */ 2643 2644 /* 2. PMdemand was already set */ 2645 2646 /* 3. Select Thunderbolt */ 2647 mtl_port_buf_ctl_io_selection(encoder); 2648 2649 /* 4. Enable Panel Power if PPS is required */ 2650 intel_pps_on(intel_dp); 2651 2652 /* 5. Enable the port PLL */ 2653 intel_ddi_enable_clock(encoder, crtc_state); 2654 2655 /* 2656 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2657 * Transcoder. 2658 */ 2659 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2660 2661 /* 2662 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2663 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2664 * Transport Select 2665 */ 2666 intel_ddi_config_transcoder_func(encoder, crtc_state); 2667 2668 /* 2669 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2670 */ 2671 intel_ddi_mso_configure(crtc_state); 2672 2673 if (!is_mst) 2674 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2675 2676 transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); 2677 drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); 2678 2679 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2680 if (!is_mst) 2681 intel_dp_sink_enable_decompression(state, 2682 to_intel_connector(conn_state->connector), 2683 crtc_state); 2684 2685 /* 2686 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2687 * in the FEC_CONFIGURATION register to 1 before initiating link 2688 * training 2689 */ 2690 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2691 2692 intel_dp_check_frl_training(intel_dp); 2693 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2694 2695 /* 2696 * 6. The rest of the below are substeps under the bspec's "Enable and 2697 * Train Display Port" step. Note that steps that are specific to 2698 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2699 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2700 * us when active_mst_links==0, so any steps designated for "single 2701 * stream or multi-stream master transcoder" can just be performed 2702 * unconditionally here. 2703 * 2704 * mtl_ddi_prepare_link_retrain() that is called by 2705 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2706 * 6.i and 6.j 2707 * 2708 * 6.k Follow DisplayPort specification training sequence (see notes for 2709 * failure handling) 2710 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2711 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2712 * (timeout after 800 us) 2713 */ 2714 intel_dp_start_link_train(state, intel_dp, crtc_state); 2715 2716 /* 6.n Set DP_TP_CTL link training to Normal */ 2717 if (!is_trans_port_sync_mode(crtc_state)) 2718 intel_dp_stop_link_train(intel_dp, crtc_state); 2719 2720 /* 6.o Configure and enable FEC if needed */ 2721 intel_ddi_enable_fec(encoder, crtc_state); 2722 2723 /* 7.a 128b/132b SST. */ 2724 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2725 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2726 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2727 if (ret < 0) 2728 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2729 } 2730 2731 if (!is_mst) 2732 intel_dsc_dp_pps_write(encoder, crtc_state); 2733 } 2734 2735 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2736 struct intel_encoder *encoder, 2737 const struct intel_crtc_state *crtc_state, 2738 const struct drm_connector_state *conn_state) 2739 { 2740 struct intel_display *display = to_intel_display(encoder); 2741 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2742 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2743 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2744 int ret; 2745 2746 intel_dp_set_link_params(intel_dp, 2747 crtc_state->port_clock, 2748 crtc_state->lane_count); 2749 2750 /* 2751 * We only configure what the register value will be here. Actual 2752 * enabling happens during link training farther down. 2753 */ 2754 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2755 2756 /* 2757 * 1. Enable Power Wells 2758 * 2759 * This was handled at the beginning of intel_atomic_commit_tail(), 2760 * before we called down into this function. 2761 */ 2762 2763 /* 2. Enable Panel Power if PPS is required */ 2764 intel_pps_on(intel_dp); 2765 2766 /* 2767 * 3. For non-TBT Type-C ports, set FIA lane count 2768 * (DFLEXDPSP.DPX4TXLATC) 2769 * 2770 * This was done before tgl_ddi_pre_enable_dp by 2771 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2772 */ 2773 2774 /* 2775 * 4. Enable the port PLL. 2776 * 2777 * The PLL enabling itself was already done before this function by 2778 * hsw_crtc_enable()->intel_enable_dpll(). We need only 2779 * configure the PLL to port mapping here. 2780 */ 2781 intel_ddi_enable_clock(encoder, crtc_state); 2782 2783 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2784 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2785 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2786 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2787 dig_port->ddi_io_power_domain); 2788 } 2789 2790 /* 6. Program DP_MODE */ 2791 icl_program_mg_dp_mode(dig_port, crtc_state); 2792 2793 /* 2794 * 7. The rest of the below are substeps under the bspec's "Enable and 2795 * Train Display Port" step. Note that steps that are specific to 2796 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2797 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2798 * us when active_mst_links==0, so any steps designated for "single 2799 * stream or multi-stream master transcoder" can just be performed 2800 * unconditionally here. 2801 */ 2802 2803 /* 2804 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2805 * Transcoder. 2806 */ 2807 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2808 2809 /* 2810 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2811 * Transport Select 2812 */ 2813 intel_ddi_config_transcoder_func(encoder, crtc_state); 2814 2815 /* 2816 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2817 * selected 2818 * 2819 * This will be handled by the intel_dp_start_link_train() farther 2820 * down this function. 2821 */ 2822 2823 /* 7.e Configure voltage swing and related IO settings */ 2824 encoder->set_signal_levels(encoder, crtc_state); 2825 2826 /* 2827 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2828 * the used lanes of the DDI. 2829 */ 2830 intel_ddi_power_up_lanes(encoder, crtc_state); 2831 2832 /* 2833 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2834 */ 2835 intel_ddi_mso_configure(crtc_state); 2836 2837 if (!is_mst) 2838 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2839 2840 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2841 if (!is_mst) 2842 intel_dp_sink_enable_decompression(state, 2843 to_intel_connector(conn_state->connector), 2844 crtc_state); 2845 /* 2846 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2847 * in the FEC_CONFIGURATION register to 1 before initiating link 2848 * training 2849 */ 2850 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2851 2852 intel_dp_check_frl_training(intel_dp); 2853 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2854 2855 /* 2856 * 7.i Follow DisplayPort specification training sequence (see notes for 2857 * failure handling) 2858 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2859 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2860 * (timeout after 800 us) 2861 */ 2862 intel_dp_start_link_train(state, intel_dp, crtc_state); 2863 2864 /* 7.k Set DP_TP_CTL link training to Normal */ 2865 if (!is_trans_port_sync_mode(crtc_state)) 2866 intel_dp_stop_link_train(intel_dp, crtc_state); 2867 2868 /* 7.l Configure and enable FEC if needed */ 2869 intel_ddi_enable_fec(encoder, crtc_state); 2870 2871 if (!is_mst && intel_dp_is_uhbr(crtc_state)) { 2872 /* VCPID 1, start slot 0 for 128b/132b, tu slots */ 2873 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); 2874 if (ret < 0) 2875 intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); 2876 } 2877 2878 if (!is_mst) 2879 intel_dsc_dp_pps_write(encoder, crtc_state); 2880 } 2881 2882 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2883 struct intel_encoder *encoder, 2884 const struct intel_crtc_state *crtc_state, 2885 const struct drm_connector_state *conn_state) 2886 { 2887 struct intel_display *display = to_intel_display(encoder); 2888 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2889 enum port port = encoder->port; 2890 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2891 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2892 2893 if (DISPLAY_VER(display) < 11) 2894 drm_WARN_ON(display->drm, 2895 is_mst && (port == PORT_A || port == PORT_E)); 2896 else 2897 drm_WARN_ON(display->drm, is_mst && port == PORT_A); 2898 2899 intel_dp_set_link_params(intel_dp, 2900 crtc_state->port_clock, 2901 crtc_state->lane_count); 2902 2903 /* 2904 * We only configure what the register value will be here. Actual 2905 * enabling happens during link training farther down. 2906 */ 2907 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2908 2909 intel_pps_on(intel_dp); 2910 2911 intel_ddi_enable_clock(encoder, crtc_state); 2912 2913 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2914 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2915 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2916 dig_port->ddi_io_power_domain); 2917 } 2918 2919 icl_program_mg_dp_mode(dig_port, crtc_state); 2920 2921 if (has_buf_trans_select(display)) 2922 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2923 2924 encoder->set_signal_levels(encoder, crtc_state); 2925 2926 intel_ddi_power_up_lanes(encoder, crtc_state); 2927 2928 if (!is_mst) 2929 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2930 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2931 if (!is_mst) 2932 intel_dp_sink_enable_decompression(state, 2933 to_intel_connector(conn_state->connector), 2934 crtc_state); 2935 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2936 intel_dp_start_link_train(state, intel_dp, crtc_state); 2937 if ((port != PORT_A || DISPLAY_VER(display) >= 9) && 2938 !is_trans_port_sync_mode(crtc_state)) 2939 intel_dp_stop_link_train(intel_dp, crtc_state); 2940 2941 intel_ddi_enable_fec(encoder, crtc_state); 2942 2943 if (!is_mst) { 2944 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2945 intel_dsc_dp_pps_write(encoder, crtc_state); 2946 } 2947 } 2948 2949 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2950 struct intel_encoder *encoder, 2951 const struct intel_crtc_state *crtc_state, 2952 const struct drm_connector_state *conn_state) 2953 { 2954 struct intel_display *display = to_intel_display(encoder); 2955 2956 if (HAS_DP20(display)) 2957 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2958 crtc_state); 2959 2960 /* Panel replay has to be enabled in sink dpcd before link training. */ 2961 intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); 2962 2963 if (DISPLAY_VER(display) >= 14) 2964 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2965 else if (DISPLAY_VER(display) >= 12) 2966 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2967 else 2968 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2969 2970 /* MST will call a setting of MSA after an allocating of Virtual Channel 2971 * from MST encoder pre_enable callback. 2972 */ 2973 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2974 intel_ddi_set_dp_msa(crtc_state, conn_state); 2975 } 2976 2977 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2978 struct intel_encoder *encoder, 2979 const struct intel_crtc_state *crtc_state, 2980 const struct drm_connector_state *conn_state) 2981 { 2982 struct intel_display *display = to_intel_display(encoder); 2983 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2984 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2985 2986 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2987 intel_ddi_enable_clock(encoder, crtc_state); 2988 2989 drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); 2990 dig_port->ddi_io_wakeref = intel_display_power_get(display, 2991 dig_port->ddi_io_power_domain); 2992 2993 icl_program_mg_dp_mode(dig_port, crtc_state); 2994 2995 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2996 2997 dig_port->set_infoframes(encoder, 2998 crtc_state->has_infoframe, 2999 crtc_state, conn_state); 3000 } 3001 3002 /* 3003 * Note: Also called from the ->pre_enable of the first active MST stream 3004 * encoder on its primary encoder. 3005 * 3006 * When called from DP MST code: 3007 * 3008 * - conn_state will be NULL 3009 * 3010 * - encoder will be the primary encoder (i.e. mst->primary) 3011 * 3012 * - the main connector associated with this port won't be active or linked to a 3013 * crtc 3014 * 3015 * - crtc_state will be the state of the first stream to be activated on this 3016 * port, and it may not be the same stream that will be deactivated last, but 3017 * each stream should have a state that is identical when it comes to the DP 3018 * link parameters. 3019 */ 3020 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 3021 struct intel_encoder *encoder, 3022 const struct intel_crtc_state *crtc_state, 3023 const struct drm_connector_state *conn_state) 3024 { 3025 struct intel_display *display = to_intel_display(state); 3026 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3027 enum pipe pipe = crtc->pipe; 3028 3029 drm_WARN_ON(display->drm, crtc_state->has_pch_encoder); 3030 3031 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 3032 3033 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 3034 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 3035 conn_state); 3036 } else { 3037 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3038 3039 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 3040 conn_state); 3041 3042 /* FIXME precompute everything properly */ 3043 /* FIXME how do we turn infoframes off again? */ 3044 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 3045 dig_port->set_infoframes(encoder, 3046 crtc_state->has_infoframe, 3047 crtc_state, conn_state); 3048 } 3049 } 3050 3051 static void 3052 mtl_ddi_disable_d2d(struct intel_encoder *encoder) 3053 { 3054 struct intel_display *display = to_intel_display(encoder); 3055 enum port port = encoder->port; 3056 i915_reg_t reg; 3057 u32 clr_bits, wait_bits; 3058 int ret; 3059 3060 if (DISPLAY_VER(display) < 14) 3061 return; 3062 3063 if (DISPLAY_VER(display) >= 20) { 3064 reg = DDI_BUF_CTL(port); 3065 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3066 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 3067 } else { 3068 reg = XELPDP_PORT_BUF_CTL1(display, port); 3069 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 3070 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 3071 } 3072 3073 intel_de_rmw(display, reg, clr_bits, 0); 3074 3075 ret = intel_de_wait_custom(display, reg, 3076 wait_bits, 0, 3077 100, 0, NULL); 3078 if (ret) 3079 drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 3080 port_name(port)); 3081 } 3082 3083 static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) 3084 { 3085 struct intel_display *display = to_intel_display(encoder); 3086 enum port port = encoder->port; 3087 3088 intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); 3089 intel_de_posting_read(display, DDI_BUF_CTL(port)); 3090 3091 intel_wait_ddi_buf_active(encoder); 3092 } 3093 3094 static void intel_ddi_buf_disable(struct intel_encoder *encoder, 3095 const struct intel_crtc_state *crtc_state) 3096 { 3097 struct intel_display *display = to_intel_display(encoder); 3098 enum port port = encoder->port; 3099 3100 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 3101 3102 if (DISPLAY_VER(display) >= 14) 3103 intel_wait_ddi_buf_idle(display, port); 3104 3105 mtl_ddi_disable_d2d(encoder); 3106 3107 if (intel_crtc_has_dp_encoder(crtc_state)) { 3108 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3109 DP_TP_CTL_ENABLE, 0); 3110 } 3111 3112 intel_ddi_disable_fec(encoder, crtc_state); 3113 3114 if (DISPLAY_VER(display) < 14) 3115 intel_wait_ddi_buf_idle(display, port); 3116 3117 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3118 } 3119 3120 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3121 struct intel_encoder *encoder, 3122 const struct intel_crtc_state *old_crtc_state, 3123 const struct drm_connector_state *old_conn_state) 3124 { 3125 struct intel_display *display = to_intel_display(encoder); 3126 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3127 struct intel_dp *intel_dp = &dig_port->dp; 3128 intel_wakeref_t wakeref; 3129 bool is_mst = intel_crtc_has_type(old_crtc_state, 3130 INTEL_OUTPUT_DP_MST); 3131 3132 if (!is_mst) 3133 intel_dp_set_infoframes(encoder, false, 3134 old_crtc_state, old_conn_state); 3135 3136 /* 3137 * Power down sink before disabling the port, otherwise we end 3138 * up getting interrupts from the sink on detecting link loss. 3139 */ 3140 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3141 3142 if (DISPLAY_VER(display) >= 12) { 3143 if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { 3144 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3145 3146 intel_de_rmw(display, 3147 TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 3148 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3149 0); 3150 } 3151 } else { 3152 if (!is_mst) 3153 intel_ddi_disable_transcoder_clock(old_crtc_state); 3154 } 3155 3156 intel_ddi_buf_disable(encoder, old_crtc_state); 3157 3158 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3159 3160 intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3161 3162 /* 3163 * From TGL spec: "If single stream or multi-stream master transcoder: 3164 * Configure Transcoder Clock select to direct no clock to the 3165 * transcoder" 3166 */ 3167 if (DISPLAY_VER(display) >= 12) 3168 intel_ddi_disable_transcoder_clock(old_crtc_state); 3169 3170 intel_pps_vdd_on(intel_dp); 3171 intel_pps_off(intel_dp); 3172 3173 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3174 3175 if (wakeref) 3176 intel_display_power_put(display, 3177 dig_port->ddi_io_power_domain, 3178 wakeref); 3179 3180 intel_ddi_disable_clock(encoder); 3181 3182 /* De-select Thunderbolt */ 3183 if (DISPLAY_VER(display) >= 14) 3184 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 3185 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3186 } 3187 3188 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3189 struct intel_encoder *encoder, 3190 const struct intel_crtc_state *old_crtc_state, 3191 const struct drm_connector_state *old_conn_state) 3192 { 3193 struct intel_display *display = to_intel_display(encoder); 3194 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3195 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3196 intel_wakeref_t wakeref; 3197 3198 dig_port->set_infoframes(encoder, false, 3199 old_crtc_state, old_conn_state); 3200 3201 if (DISPLAY_VER(display) < 12) 3202 intel_ddi_disable_transcoder_clock(old_crtc_state); 3203 3204 intel_ddi_buf_disable(encoder, old_crtc_state); 3205 3206 if (DISPLAY_VER(display) >= 12) 3207 intel_ddi_disable_transcoder_clock(old_crtc_state); 3208 3209 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3210 if (wakeref) 3211 intel_display_power_put(display, 3212 dig_port->ddi_io_power_domain, 3213 wakeref); 3214 3215 intel_ddi_disable_clock(encoder); 3216 3217 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3218 } 3219 3220 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3221 struct intel_encoder *encoder, 3222 const struct intel_crtc_state *old_crtc_state, 3223 const struct drm_connector_state *old_conn_state) 3224 { 3225 struct intel_display *display = to_intel_display(encoder); 3226 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3227 struct intel_crtc *pipe_crtc; 3228 bool is_hdmi = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI); 3229 int i; 3230 3231 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3232 const struct intel_crtc_state *old_pipe_crtc_state = 3233 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3234 3235 intel_crtc_vblank_off(old_pipe_crtc_state); 3236 } 3237 3238 intel_disable_transcoder(old_crtc_state); 3239 3240 /* 128b/132b SST */ 3241 if (!is_hdmi && intel_dp_is_uhbr(old_crtc_state)) { 3242 /* VCPID 1, start slot 0 for 128b/132b, clear */ 3243 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); 3244 3245 intel_ddi_clear_act_sent(encoder, old_crtc_state); 3246 3247 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 3248 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 3249 3250 intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 3251 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3252 } 3253 3254 intel_vrr_transcoder_disable(old_crtc_state); 3255 3256 intel_ddi_disable_transcoder_func(old_crtc_state); 3257 3258 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 3259 const struct intel_crtc_state *old_pipe_crtc_state = 3260 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3261 3262 intel_dsc_disable(old_pipe_crtc_state); 3263 3264 if (DISPLAY_VER(display) >= 9) 3265 skl_scaler_disable(old_pipe_crtc_state); 3266 else 3267 ilk_pfit_disable(old_pipe_crtc_state); 3268 } 3269 } 3270 3271 /* 3272 * Note: Also called from the ->post_disable of the last active MST stream 3273 * encoder on its primary encoder. See also the comment for 3274 * intel_ddi_pre_enable(). 3275 */ 3276 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3277 struct intel_encoder *encoder, 3278 const struct intel_crtc_state *old_crtc_state, 3279 const struct drm_connector_state *old_conn_state) 3280 { 3281 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3282 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3283 old_conn_state); 3284 3285 /* 3286 * When called from DP MST code: 3287 * - old_conn_state will be NULL 3288 * - encoder will be the main encoder (ie. mst->primary) 3289 * - the main connector associated with this port 3290 * won't be active or linked to a crtc 3291 * - old_crtc_state will be the state of the last stream to 3292 * be deactivated on this port, and it may not be the same 3293 * stream that was activated last, but each stream 3294 * should have a state that is identical when it comes to 3295 * the DP link parameters 3296 */ 3297 3298 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3299 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3300 old_conn_state); 3301 else 3302 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3303 old_conn_state); 3304 } 3305 3306 /* 3307 * Note: Also called from the ->post_pll_disable of the last active MST stream 3308 * encoder on its primary encoder. See also the comment for 3309 * intel_ddi_pre_enable(). 3310 */ 3311 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3312 struct intel_encoder *encoder, 3313 const struct intel_crtc_state *old_crtc_state, 3314 const struct drm_connector_state *old_conn_state) 3315 { 3316 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3317 3318 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3319 3320 if (intel_encoder_is_tc(encoder)) 3321 intel_tc_port_put_link(dig_port); 3322 } 3323 3324 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3325 struct intel_encoder *encoder, 3326 const struct intel_crtc_state *crtc_state) 3327 { 3328 const struct drm_connector_state *conn_state; 3329 struct drm_connector *conn; 3330 int i; 3331 3332 if (!crtc_state->sync_mode_slaves_mask) 3333 return; 3334 3335 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3336 struct intel_encoder *slave_encoder = 3337 to_intel_encoder(conn_state->best_encoder); 3338 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3339 const struct intel_crtc_state *slave_crtc_state; 3340 3341 if (!slave_crtc) 3342 continue; 3343 3344 slave_crtc_state = 3345 intel_atomic_get_new_crtc_state(state, slave_crtc); 3346 3347 if (slave_crtc_state->master_transcoder != 3348 crtc_state->cpu_transcoder) 3349 continue; 3350 3351 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3352 slave_crtc_state); 3353 } 3354 3355 usleep_range(200, 400); 3356 3357 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3358 crtc_state); 3359 } 3360 3361 static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3362 struct intel_encoder *encoder, 3363 const struct intel_crtc_state *crtc_state, 3364 const struct drm_connector_state *conn_state) 3365 { 3366 struct intel_display *display = to_intel_display(encoder); 3367 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3368 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3369 enum port port = encoder->port; 3370 3371 if (port == PORT_A && DISPLAY_VER(display) < 9) 3372 intel_dp_stop_link_train(intel_dp, crtc_state); 3373 3374 drm_connector_update_privacy_screen(conn_state); 3375 intel_edp_backlight_on(crtc_state, conn_state); 3376 3377 intel_panel_prepare(crtc_state, conn_state); 3378 3379 if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) 3380 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3381 3382 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3383 } 3384 3385 static i915_reg_t 3386 gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3387 { 3388 static const enum transcoder trans[] = { 3389 [PORT_A] = TRANSCODER_EDP, 3390 [PORT_B] = TRANSCODER_A, 3391 [PORT_C] = TRANSCODER_B, 3392 [PORT_D] = TRANSCODER_C, 3393 [PORT_E] = TRANSCODER_A, 3394 }; 3395 3396 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3397 3398 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3399 port = PORT_A; 3400 3401 return CHICKEN_TRANS(display, trans[port]); 3402 } 3403 3404 static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3405 struct intel_encoder *encoder, 3406 const struct intel_crtc_state *crtc_state, 3407 const struct drm_connector_state *conn_state) 3408 { 3409 struct intel_display *display = to_intel_display(encoder); 3410 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3411 struct drm_connector *connector = conn_state->connector; 3412 enum port port = encoder->port; 3413 u32 buf_ctl = 0; 3414 3415 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3416 crtc_state->hdmi_high_tmds_clock_ratio, 3417 crtc_state->hdmi_scrambling)) 3418 drm_dbg_kms(display->drm, 3419 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3420 connector->base.id, connector->name); 3421 3422 if (has_buf_trans_select(display)) 3423 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3424 3425 /* e. Enable D2D Link for C10/C20 Phy */ 3426 mtl_ddi_enable_d2d(encoder); 3427 3428 encoder->set_signal_levels(encoder, crtc_state); 3429 3430 /* Display WA #1143: skl,kbl,cfl */ 3431 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 3432 /* 3433 * For some reason these chicken bits have been 3434 * stuffed into a transcoder register, event though 3435 * the bits affect a specific DDI port rather than 3436 * a specific transcoder. 3437 */ 3438 i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3439 u32 val; 3440 3441 val = intel_de_read(display, reg); 3442 3443 if (port == PORT_E) 3444 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3445 DDIE_TRAINING_OVERRIDE_VALUE; 3446 else 3447 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3448 DDI_TRAINING_OVERRIDE_VALUE; 3449 3450 intel_de_write(display, reg, val); 3451 intel_de_posting_read(display, reg); 3452 3453 udelay(1); 3454 3455 if (port == PORT_E) 3456 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3457 DDIE_TRAINING_OVERRIDE_VALUE); 3458 else 3459 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3460 DDI_TRAINING_OVERRIDE_VALUE); 3461 3462 intel_de_write(display, reg, val); 3463 } 3464 3465 intel_ddi_power_up_lanes(encoder, crtc_state); 3466 3467 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3468 * are ignored so nothing special needs to be done besides 3469 * enabling the port. 3470 * 3471 * On ADL_P the PHY link rate and lane count must be programmed but 3472 * these are both 0 for HDMI. 3473 * 3474 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3475 * is filled with lane count, already set in the crtc_state. 3476 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3477 */ 3478 if (dig_port->lane_reversal) 3479 buf_ctl |= DDI_BUF_PORT_REVERSAL; 3480 if (dig_port->ddi_a_4_lanes) 3481 buf_ctl |= DDI_A_4_LANES; 3482 3483 if (DISPLAY_VER(display) >= 14) { 3484 u32 port_buf = 0; 3485 3486 port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); 3487 3488 if (dig_port->lane_reversal) 3489 port_buf |= XELPDP_PORT_REVERSAL; 3490 3491 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 3492 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3493 3494 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); 3495 3496 if (DISPLAY_VER(display) >= 20) 3497 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3498 } else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) { 3499 drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3500 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3501 } 3502 3503 intel_ddi_buf_enable(encoder, buf_ctl); 3504 } 3505 3506 static void intel_ddi_enable(struct intel_atomic_state *state, 3507 struct intel_encoder *encoder, 3508 const struct intel_crtc_state *crtc_state, 3509 const struct drm_connector_state *conn_state) 3510 { 3511 struct intel_display *display = to_intel_display(encoder); 3512 struct intel_crtc *pipe_crtc; 3513 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3514 bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); 3515 int i; 3516 3517 /* 128b/132b SST */ 3518 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3519 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 3520 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 3521 3522 intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder), 3523 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 3524 intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder), 3525 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 3526 } 3527 3528 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3529 3530 intel_vrr_transcoder_enable(crtc_state); 3531 3532 /* 128b/132b SST */ 3533 if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) { 3534 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3535 3536 intel_ddi_clear_act_sent(encoder, crtc_state); 3537 3538 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0, 3539 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 3540 3541 intel_ddi_wait_for_act_sent(encoder, crtc_state); 3542 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); 3543 } 3544 3545 intel_enable_transcoder(crtc_state); 3546 3547 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3548 3549 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) { 3550 const struct intel_crtc_state *pipe_crtc_state = 3551 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3552 3553 intel_crtc_vblank_on(pipe_crtc_state); 3554 } 3555 3556 if (is_hdmi) 3557 intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3558 else 3559 intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3560 3561 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3562 3563 } 3564 3565 static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3566 struct intel_encoder *encoder, 3567 const struct intel_crtc_state *old_crtc_state, 3568 const struct drm_connector_state *old_conn_state) 3569 { 3570 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3571 struct intel_connector *connector = 3572 to_intel_connector(old_conn_state->connector); 3573 3574 intel_dp->link.active = false; 3575 3576 intel_panel_unprepare(old_conn_state); 3577 intel_psr_disable(intel_dp, old_crtc_state); 3578 intel_alpm_disable(intel_dp); 3579 intel_edp_backlight_off(old_conn_state); 3580 /* Disable the decompression in DP Sink */ 3581 intel_dp_sink_disable_decompression(state, 3582 connector, old_crtc_state); 3583 /* Disable Ignore_MSA bit in DP Sink */ 3584 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3585 false); 3586 } 3587 3588 static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3589 struct intel_encoder *encoder, 3590 const struct intel_crtc_state *old_crtc_state, 3591 const struct drm_connector_state *old_conn_state) 3592 { 3593 struct intel_display *display = to_intel_display(encoder); 3594 struct drm_connector *connector = old_conn_state->connector; 3595 3596 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3597 false, false)) 3598 drm_dbg_kms(display->drm, 3599 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3600 connector->base.id, connector->name); 3601 } 3602 3603 static void intel_ddi_disable(struct intel_atomic_state *state, 3604 struct intel_encoder *encoder, 3605 const struct intel_crtc_state *old_crtc_state, 3606 const struct drm_connector_state *old_conn_state) 3607 { 3608 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3609 3610 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3611 3612 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3613 intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3614 old_conn_state); 3615 else 3616 intel_ddi_disable_dp(state, encoder, old_crtc_state, 3617 old_conn_state); 3618 } 3619 3620 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3621 struct intel_encoder *encoder, 3622 const struct intel_crtc_state *crtc_state, 3623 const struct drm_connector_state *conn_state) 3624 { 3625 intel_ddi_set_dp_msa(crtc_state, conn_state); 3626 3627 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3628 3629 intel_backlight_update(state, encoder, crtc_state, conn_state); 3630 drm_connector_update_privacy_screen(conn_state); 3631 } 3632 3633 static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder, 3634 const struct intel_crtc_state *crtc_state, 3635 const struct drm_connector_state *conn_state) 3636 { 3637 intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state); 3638 } 3639 3640 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3641 struct intel_encoder *encoder, 3642 const struct intel_crtc_state *crtc_state, 3643 const struct drm_connector_state *conn_state) 3644 { 3645 3646 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3647 !intel_encoder_is_mst(encoder)) 3648 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3649 conn_state); 3650 3651 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3652 intel_ddi_update_pipe_hdmi(encoder, crtc_state, 3653 conn_state); 3654 3655 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3656 } 3657 3658 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3659 struct intel_encoder *encoder, 3660 struct intel_crtc *crtc) 3661 { 3662 struct intel_display *display = to_intel_display(encoder); 3663 const struct intel_crtc_state *crtc_state = 3664 intel_atomic_get_new_crtc_state(state, crtc); 3665 struct intel_crtc *pipe_crtc; 3666 3667 /* FIXME: Add MTL pll_mgr */ 3668 if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) 3669 return; 3670 3671 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 3672 intel_crtc_joined_pipe_mask(crtc_state)) 3673 intel_dpll_update_active(state, pipe_crtc, encoder); 3674 } 3675 3676 /* 3677 * Note: Also called from the ->pre_pll_enable of the first active MST stream 3678 * encoder on its primary encoder. See also the comment for 3679 * intel_ddi_pre_enable(). 3680 */ 3681 static void 3682 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3683 struct intel_encoder *encoder, 3684 const struct intel_crtc_state *crtc_state, 3685 const struct drm_connector_state *conn_state) 3686 { 3687 struct intel_display *display = to_intel_display(encoder); 3688 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3689 bool is_tc_port = intel_encoder_is_tc(encoder); 3690 3691 if (is_tc_port) { 3692 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3693 3694 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3695 intel_ddi_update_active_dpll(state, encoder, crtc); 3696 } 3697 3698 main_link_aux_power_domain_get(dig_port, crtc_state); 3699 3700 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3701 /* 3702 * Program the lane count for static/dynamic connections on 3703 * Type-C ports. Skip this step for TBT. 3704 */ 3705 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3706 else if (display->platform.geminilake || display->platform.broxton) 3707 bxt_dpio_phy_set_lane_optim_mask(encoder, 3708 crtc_state->lane_lat_optim_mask); 3709 } 3710 3711 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3712 { 3713 struct intel_display *display = to_intel_display(encoder); 3714 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3715 int ln; 3716 3717 for (ln = 0; ln < 2; ln++) 3718 intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), 3719 DKL_PCS_DW5_CORE_SOFTRESET, 0); 3720 } 3721 3722 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3723 const struct intel_crtc_state *crtc_state) 3724 { 3725 struct intel_display *display = to_intel_display(crtc_state); 3726 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3727 struct intel_encoder *encoder = &dig_port->base; 3728 u32 dp_tp_ctl; 3729 3730 /* 3731 * TODO: To train with only a different voltage swing entry is not 3732 * necessary disable and enable port 3733 */ 3734 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3735 3736 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3737 3738 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3739 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3740 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3741 intel_dp_is_uhbr(crtc_state)) { 3742 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3743 } else { 3744 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3745 if (crtc_state->enhanced_framing) 3746 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3747 } 3748 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3749 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3750 3751 /* 6.f Enable D2D Link */ 3752 mtl_ddi_enable_d2d(encoder); 3753 3754 /* 6.g Configure voltage swing and related IO settings */ 3755 encoder->set_signal_levels(encoder, crtc_state); 3756 3757 /* 6.h Configure PORT_BUF_CTL1 */ 3758 mtl_port_buf_ctl_program(encoder, crtc_state); 3759 3760 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3761 if (DISPLAY_VER(display) >= 20) 3762 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3763 3764 intel_ddi_buf_enable(encoder, intel_dp->DP); 3765 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3766 3767 /* 3768 * 6.k If AUX-Less ALPM is going to be enabled: 3769 * i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here 3770 */ 3771 intel_alpm_port_configure(intel_dp, crtc_state); 3772 3773 /* 3774 * ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE 3775 * register 3776 */ 3777 intel_lnl_mac_transmit_lfps(encoder, crtc_state); 3778 } 3779 3780 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3781 const struct intel_crtc_state *crtc_state) 3782 { 3783 struct intel_display *display = to_intel_display(intel_dp); 3784 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3785 struct intel_encoder *encoder = &dig_port->base; 3786 u32 dp_tp_ctl; 3787 3788 dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3789 3790 drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); 3791 3792 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3793 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 3794 intel_dp_is_uhbr(crtc_state)) { 3795 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3796 } else { 3797 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3798 if (crtc_state->enhanced_framing) 3799 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3800 } 3801 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3802 intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3803 3804 if (display->platform.alderlake_p && 3805 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3806 adlp_tbt_to_dp_alt_switch_wa(encoder); 3807 3808 intel_ddi_buf_enable(encoder, intel_dp->DP); 3809 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3810 } 3811 3812 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3813 const struct intel_crtc_state *crtc_state, 3814 u8 dp_train_pat) 3815 { 3816 struct intel_display *display = to_intel_display(intel_dp); 3817 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3818 u32 temp; 3819 3820 temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); 3821 3822 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3823 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3824 case DP_TRAINING_PATTERN_DISABLE: 3825 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3826 break; 3827 case DP_TRAINING_PATTERN_1: 3828 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3829 break; 3830 case DP_TRAINING_PATTERN_2: 3831 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3832 break; 3833 case DP_TRAINING_PATTERN_3: 3834 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3835 break; 3836 case DP_TRAINING_PATTERN_4: 3837 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3838 break; 3839 } 3840 3841 intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp); 3842 } 3843 3844 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3845 const struct intel_crtc_state *crtc_state) 3846 { 3847 struct intel_display *display = to_intel_display(intel_dp); 3848 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3849 enum port port = encoder->port; 3850 3851 intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state), 3852 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3853 3854 /* 3855 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3856 * reason we need to set idle transmission mode is to work around a HW 3857 * issue where we enable the pipe while not in idle link-training mode. 3858 * In this case there is requirement to wait for a minimum number of 3859 * idle patterns to be sent. 3860 */ 3861 if (port == PORT_A && DISPLAY_VER(display) < 12) 3862 return; 3863 3864 if (intel_de_wait_for_set(display, 3865 dp_tp_status_reg(encoder, crtc_state), 3866 DP_TP_STATUS_IDLE_DONE, 2)) 3867 drm_err(display->drm, 3868 "Timed out waiting for DP idle patterns\n"); 3869 } 3870 3871 static bool intel_ddi_is_audio_enabled(struct intel_display *display, 3872 enum transcoder cpu_transcoder) 3873 { 3874 if (cpu_transcoder == TRANSCODER_EDP) 3875 return false; 3876 3877 if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) 3878 return false; 3879 3880 return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) & 3881 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3882 } 3883 3884 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3885 { 3886 if (crtc_state->port_clock > 594000) 3887 return 2; 3888 else 3889 return 0; 3890 } 3891 3892 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3893 { 3894 if (crtc_state->port_clock > 594000) 3895 return 3; 3896 else 3897 return 0; 3898 } 3899 3900 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3901 { 3902 if (crtc_state->port_clock > 594000) 3903 return 1; 3904 else 3905 return 0; 3906 } 3907 3908 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3909 { 3910 struct intel_display *display = to_intel_display(crtc_state); 3911 3912 if (DISPLAY_VER(display) >= 14) 3913 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3914 else if (DISPLAY_VER(display) >= 12) 3915 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3916 else if (display->platform.jasperlake || display->platform.elkhartlake) 3917 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3918 else if (DISPLAY_VER(display) >= 11) 3919 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3920 } 3921 3922 static enum transcoder bdw_transcoder_master_readout(struct intel_display *display, 3923 enum transcoder cpu_transcoder) 3924 { 3925 u32 master_select; 3926 3927 if (DISPLAY_VER(display) >= 11) { 3928 u32 ctl2 = intel_de_read(display, 3929 TRANS_DDI_FUNC_CTL2(display, cpu_transcoder)); 3930 3931 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3932 return INVALID_TRANSCODER; 3933 3934 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3935 } else { 3936 u32 ctl = intel_de_read(display, 3937 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3938 3939 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3940 return INVALID_TRANSCODER; 3941 3942 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3943 } 3944 3945 if (master_select == 0) 3946 return TRANSCODER_EDP; 3947 else 3948 return master_select - 1; 3949 } 3950 3951 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3952 { 3953 struct intel_display *display = to_intel_display(crtc_state); 3954 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3955 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3956 enum transcoder cpu_transcoder; 3957 3958 crtc_state->master_transcoder = 3959 bdw_transcoder_master_readout(display, crtc_state->cpu_transcoder); 3960 3961 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3962 enum intel_display_power_domain power_domain; 3963 intel_wakeref_t trans_wakeref; 3964 3965 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3966 trans_wakeref = intel_display_power_get_if_enabled(display, 3967 power_domain); 3968 3969 if (!trans_wakeref) 3970 continue; 3971 3972 if (bdw_transcoder_master_readout(display, cpu_transcoder) == 3973 crtc_state->cpu_transcoder) 3974 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3975 3976 intel_display_power_put(display, power_domain, trans_wakeref); 3977 } 3978 3979 drm_WARN_ON(display->drm, 3980 crtc_state->master_transcoder != INVALID_TRANSCODER && 3981 crtc_state->sync_mode_slaves_mask); 3982 } 3983 3984 static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3985 struct intel_crtc_state *crtc_state, 3986 u32 ddi_func_ctl) 3987 { 3988 struct intel_display *display = to_intel_display(encoder); 3989 3990 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3991 if (DISPLAY_VER(display) >= 14) 3992 crtc_state->lane_count = 3993 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3994 else 3995 crtc_state->lane_count = 4; 3996 } 3997 3998 static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 3999 struct intel_crtc_state *crtc_state, 4000 u32 ddi_func_ctl) 4001 { 4002 crtc_state->has_hdmi_sink = true; 4003 4004 crtc_state->infoframes.enable |= 4005 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4006 4007 if (crtc_state->infoframes.enable) 4008 crtc_state->has_infoframe = true; 4009 4010 if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 4011 crtc_state->hdmi_scrambling = true; 4012 if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4013 crtc_state->hdmi_high_tmds_clock_ratio = true; 4014 4015 intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 4016 } 4017 4018 static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 4019 struct intel_crtc_state *crtc_state, 4020 u32 ddi_func_ctl) 4021 { 4022 struct intel_display *display = to_intel_display(encoder); 4023 4024 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4025 crtc_state->enhanced_framing = 4026 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4027 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4028 } 4029 4030 static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 4031 struct intel_crtc_state *crtc_state, 4032 u32 ddi_func_ctl) 4033 { 4034 struct intel_display *display = to_intel_display(encoder); 4035 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4036 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4037 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4038 4039 if (encoder->type == INTEL_OUTPUT_EDP) 4040 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 4041 else 4042 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 4043 crtc_state->lane_count = 4044 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4045 4046 if (DISPLAY_VER(display) >= 12 && 4047 (ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B) 4048 crtc_state->mst_master_transcoder = 4049 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4050 4051 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4052 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 4053 4054 crtc_state->enhanced_framing = 4055 intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 4056 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4057 4058 if (DISPLAY_VER(display) >= 11) 4059 crtc_state->fec_enable = 4060 intel_de_read(display, 4061 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4062 4063 if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) 4064 crtc_state->infoframes.enable |= 4065 intel_lspcon_infoframes_enabled(encoder, crtc_state); 4066 else 4067 crtc_state->infoframes.enable |= 4068 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4069 } 4070 4071 static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 4072 struct intel_crtc_state *crtc_state, 4073 u32 ddi_func_ctl) 4074 { 4075 struct intel_display *display = to_intel_display(encoder); 4076 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4077 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 4078 4079 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4080 crtc_state->lane_count = 4081 ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4082 4083 if (DISPLAY_VER(display) >= 12) 4084 crtc_state->mst_master_transcoder = 4085 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 4086 4087 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 4088 4089 if (DISPLAY_VER(display) >= 11) 4090 crtc_state->fec_enable = 4091 intel_de_read(display, 4092 dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 4093 4094 crtc_state->infoframes.enable |= 4095 intel_hdmi_infoframes_enabled(encoder, crtc_state); 4096 } 4097 4098 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 4099 struct intel_crtc_state *pipe_config) 4100 { 4101 struct intel_display *display = to_intel_display(encoder); 4102 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4103 u32 ddi_func_ctl, ddi_mode, flags = 0; 4104 4105 ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 4106 if (ddi_func_ctl & TRANS_DDI_PHSYNC) 4107 flags |= DRM_MODE_FLAG_PHSYNC; 4108 else 4109 flags |= DRM_MODE_FLAG_NHSYNC; 4110 if (ddi_func_ctl & TRANS_DDI_PVSYNC) 4111 flags |= DRM_MODE_FLAG_PVSYNC; 4112 else 4113 flags |= DRM_MODE_FLAG_NVSYNC; 4114 4115 pipe_config->hw.adjusted_mode.flags |= flags; 4116 4117 switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 4118 case TRANS_DDI_BPC_6: 4119 pipe_config->pipe_bpp = 18; 4120 break; 4121 case TRANS_DDI_BPC_8: 4122 pipe_config->pipe_bpp = 24; 4123 break; 4124 case TRANS_DDI_BPC_10: 4125 pipe_config->pipe_bpp = 30; 4126 break; 4127 case TRANS_DDI_BPC_12: 4128 pipe_config->pipe_bpp = 36; 4129 break; 4130 default: 4131 break; 4132 } 4133 4134 ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4135 4136 if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 4137 intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 4138 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 4139 intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 4140 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 4141 intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 4142 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 4143 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4144 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { 4145 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4146 } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 4147 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4148 4149 /* 4150 * If this is true, we know we're being called from mst stream 4151 * encoder's ->get_config(). 4152 */ 4153 if (intel_dp_mst_active_streams(intel_dp)) 4154 intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4155 else 4156 intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 4157 } 4158 } 4159 4160 /* 4161 * Note: Also called from the ->get_config of the MST stream encoders on their 4162 * primary encoder, via the platform specific hooks here. See also the comment 4163 * for intel_ddi_pre_enable(). 4164 */ 4165 static void intel_ddi_get_config(struct intel_encoder *encoder, 4166 struct intel_crtc_state *pipe_config) 4167 { 4168 struct intel_display *display = to_intel_display(encoder); 4169 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 4170 4171 /* XXX: DSI transcoder paranoia */ 4172 if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder))) 4173 return; 4174 4175 intel_ddi_read_func_ctl(encoder, pipe_config); 4176 4177 intel_ddi_mso_get_config(encoder, pipe_config); 4178 4179 pipe_config->has_audio = 4180 intel_ddi_is_audio_enabled(display, cpu_transcoder); 4181 4182 if (encoder->type == INTEL_OUTPUT_EDP) 4183 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 4184 4185 ddi_dotclock_get(pipe_config); 4186 4187 if (display->platform.geminilake || display->platform.broxton) 4188 pipe_config->lane_lat_optim_mask = 4189 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 4190 4191 intel_ddi_compute_min_voltage_level(pipe_config); 4192 4193 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 4194 4195 intel_read_infoframe(encoder, pipe_config, 4196 HDMI_INFOFRAME_TYPE_AVI, 4197 &pipe_config->infoframes.avi); 4198 intel_read_infoframe(encoder, pipe_config, 4199 HDMI_INFOFRAME_TYPE_SPD, 4200 &pipe_config->infoframes.spd); 4201 intel_read_infoframe(encoder, pipe_config, 4202 HDMI_INFOFRAME_TYPE_VENDOR, 4203 &pipe_config->infoframes.hdmi); 4204 intel_read_infoframe(encoder, pipe_config, 4205 HDMI_INFOFRAME_TYPE_DRM, 4206 &pipe_config->infoframes.drm); 4207 4208 if (DISPLAY_VER(display) >= 8) 4209 bdw_get_trans_port_sync_config(pipe_config); 4210 4211 intel_psr_get_config(encoder, pipe_config); 4212 4213 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 4214 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 4215 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 4216 4217 intel_audio_codec_get_config(encoder, pipe_config); 4218 } 4219 4220 void intel_ddi_get_clock(struct intel_encoder *encoder, 4221 struct intel_crtc_state *crtc_state, 4222 struct intel_dpll *pll) 4223 { 4224 struct intel_display *display = to_intel_display(encoder); 4225 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4226 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4227 bool pll_active; 4228 4229 if (drm_WARN_ON(display->drm, !pll)) 4230 return; 4231 4232 port_dpll->pll = pll; 4233 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4234 drm_WARN_ON(display->drm, !pll_active); 4235 4236 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4237 4238 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4239 &crtc_state->dpll_hw_state); 4240 } 4241 4242 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4243 struct intel_crtc_state *crtc_state) 4244 { 4245 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4246 4247 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4248 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4249 else 4250 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4251 4252 intel_ddi_get_config(encoder, crtc_state); 4253 } 4254 4255 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4256 struct intel_crtc_state *crtc_state) 4257 { 4258 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4259 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4260 4261 intel_ddi_get_config(encoder, crtc_state); 4262 } 4263 4264 static void adls_ddi_get_config(struct intel_encoder *encoder, 4265 struct intel_crtc_state *crtc_state) 4266 { 4267 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4268 intel_ddi_get_config(encoder, crtc_state); 4269 } 4270 4271 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4272 struct intel_crtc_state *crtc_state) 4273 { 4274 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4275 intel_ddi_get_config(encoder, crtc_state); 4276 } 4277 4278 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4279 struct intel_crtc_state *crtc_state) 4280 { 4281 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4282 intel_ddi_get_config(encoder, crtc_state); 4283 } 4284 4285 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4286 struct intel_crtc_state *crtc_state) 4287 { 4288 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4289 intel_ddi_get_config(encoder, crtc_state); 4290 } 4291 4292 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4293 { 4294 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4295 } 4296 4297 static enum icl_port_dpll_id 4298 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4299 const struct intel_crtc_state *crtc_state) 4300 { 4301 struct intel_display *display = to_intel_display(encoder); 4302 const struct intel_dpll *pll = crtc_state->intel_dpll; 4303 4304 if (drm_WARN_ON(display->drm, !pll)) 4305 return ICL_PORT_DPLL_DEFAULT; 4306 4307 if (icl_ddi_tc_pll_is_tbt(pll)) 4308 return ICL_PORT_DPLL_DEFAULT; 4309 else 4310 return ICL_PORT_DPLL_MG_PHY; 4311 } 4312 4313 enum icl_port_dpll_id 4314 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4315 const struct intel_crtc_state *crtc_state) 4316 { 4317 if (!encoder->port_pll_type) 4318 return ICL_PORT_DPLL_DEFAULT; 4319 4320 return encoder->port_pll_type(encoder, crtc_state); 4321 } 4322 4323 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4324 struct intel_crtc_state *crtc_state, 4325 struct intel_dpll *pll) 4326 { 4327 struct intel_display *display = to_intel_display(encoder); 4328 enum icl_port_dpll_id port_dpll_id; 4329 struct icl_port_dpll *port_dpll; 4330 bool pll_active; 4331 4332 if (drm_WARN_ON(display->drm, !pll)) 4333 return; 4334 4335 if (icl_ddi_tc_pll_is_tbt(pll)) 4336 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4337 else 4338 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4339 4340 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4341 4342 port_dpll->pll = pll; 4343 pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4344 drm_WARN_ON(display->drm, !pll_active); 4345 4346 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4347 4348 if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4349 crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); 4350 else 4351 crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4352 &crtc_state->dpll_hw_state); 4353 } 4354 4355 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4356 struct intel_crtc_state *crtc_state) 4357 { 4358 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4359 intel_ddi_get_config(encoder, crtc_state); 4360 } 4361 4362 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4363 struct intel_crtc_state *crtc_state) 4364 { 4365 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4366 intel_ddi_get_config(encoder, crtc_state); 4367 } 4368 4369 static void skl_ddi_get_config(struct intel_encoder *encoder, 4370 struct intel_crtc_state *crtc_state) 4371 { 4372 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4373 intel_ddi_get_config(encoder, crtc_state); 4374 } 4375 4376 void hsw_ddi_get_config(struct intel_encoder *encoder, 4377 struct intel_crtc_state *crtc_state) 4378 { 4379 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4380 intel_ddi_get_config(encoder, crtc_state); 4381 } 4382 4383 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4384 const struct intel_crtc_state *crtc_state) 4385 { 4386 if (intel_encoder_is_tc(encoder)) 4387 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4388 crtc_state); 4389 4390 if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) || 4391 (!crtc_state && intel_encoder_is_dp(encoder))) 4392 intel_dp_sync_state(encoder, crtc_state); 4393 } 4394 4395 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4396 struct intel_crtc_state *crtc_state) 4397 { 4398 struct intel_display *display = to_intel_display(encoder); 4399 bool fastset = true; 4400 4401 if (intel_encoder_is_tc(encoder)) { 4402 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4403 encoder->base.base.id, encoder->base.name); 4404 crtc_state->uapi.mode_changed = true; 4405 fastset = false; 4406 } 4407 4408 if (intel_crtc_has_dp_encoder(crtc_state) && 4409 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4410 fastset = false; 4411 4412 return fastset; 4413 } 4414 4415 static enum intel_output_type 4416 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4417 struct intel_crtc_state *crtc_state, 4418 struct drm_connector_state *conn_state) 4419 { 4420 switch (conn_state->connector->connector_type) { 4421 case DRM_MODE_CONNECTOR_HDMIA: 4422 return INTEL_OUTPUT_HDMI; 4423 case DRM_MODE_CONNECTOR_eDP: 4424 return INTEL_OUTPUT_EDP; 4425 case DRM_MODE_CONNECTOR_DisplayPort: 4426 return INTEL_OUTPUT_DP; 4427 default: 4428 MISSING_CASE(conn_state->connector->connector_type); 4429 return INTEL_OUTPUT_UNUSED; 4430 } 4431 } 4432 4433 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4434 struct intel_crtc_state *pipe_config, 4435 struct drm_connector_state *conn_state) 4436 { 4437 struct intel_display *display = to_intel_display(encoder); 4438 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4439 enum port port = encoder->port; 4440 int ret; 4441 4442 if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) 4443 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4444 4445 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4446 pipe_config->has_hdmi_sink = 4447 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4448 4449 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4450 } else { 4451 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4452 } 4453 4454 if (ret) 4455 return ret; 4456 4457 if (display->platform.haswell && crtc->pipe == PIPE_A && 4458 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4459 pipe_config->pch_pfit.force_thru = 4460 pipe_config->pch_pfit.enabled || 4461 pipe_config->crc_enabled; 4462 4463 if (display->platform.geminilake || display->platform.broxton) 4464 pipe_config->lane_lat_optim_mask = 4465 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4466 4467 intel_ddi_compute_min_voltage_level(pipe_config); 4468 4469 return 0; 4470 } 4471 4472 static bool mode_equal(const struct drm_display_mode *mode1, 4473 const struct drm_display_mode *mode2) 4474 { 4475 return drm_mode_match(mode1, mode2, 4476 DRM_MODE_MATCH_TIMINGS | 4477 DRM_MODE_MATCH_FLAGS | 4478 DRM_MODE_MATCH_3D_FLAGS) && 4479 mode1->clock == mode2->clock; /* we want an exact match */ 4480 } 4481 4482 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4483 const struct intel_link_m_n *m_n_2) 4484 { 4485 return m_n_1->tu == m_n_2->tu && 4486 m_n_1->data_m == m_n_2->data_m && 4487 m_n_1->data_n == m_n_2->data_n && 4488 m_n_1->link_m == m_n_2->link_m && 4489 m_n_1->link_n == m_n_2->link_n; 4490 } 4491 4492 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4493 const struct intel_crtc_state *crtc_state2) 4494 { 4495 /* 4496 * FIXME the modeset sequence is currently wrong and 4497 * can't deal with joiner + port sync at the same time. 4498 */ 4499 return crtc_state1->hw.active && crtc_state2->hw.active && 4500 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && 4501 crtc_state1->output_types == crtc_state2->output_types && 4502 crtc_state1->output_format == crtc_state2->output_format && 4503 crtc_state1->lane_count == crtc_state2->lane_count && 4504 crtc_state1->port_clock == crtc_state2->port_clock && 4505 mode_equal(&crtc_state1->hw.adjusted_mode, 4506 &crtc_state2->hw.adjusted_mode) && 4507 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4508 } 4509 4510 static u8 4511 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4512 int tile_group_id) 4513 { 4514 struct intel_display *display = to_intel_display(ref_crtc_state); 4515 struct drm_connector *connector; 4516 const struct drm_connector_state *conn_state; 4517 struct intel_atomic_state *state = 4518 to_intel_atomic_state(ref_crtc_state->uapi.state); 4519 u8 transcoders = 0; 4520 int i; 4521 4522 /* 4523 * We don't enable port sync on BDW due to missing w/as and 4524 * due to not having adjusted the modeset sequence appropriately. 4525 */ 4526 if (DISPLAY_VER(display) < 9) 4527 return 0; 4528 4529 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4530 return 0; 4531 4532 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4533 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4534 const struct intel_crtc_state *crtc_state; 4535 4536 if (!crtc) 4537 continue; 4538 4539 if (!connector->has_tile || 4540 connector->tile_group->id != 4541 tile_group_id) 4542 continue; 4543 crtc_state = intel_atomic_get_new_crtc_state(state, 4544 crtc); 4545 if (!crtcs_port_sync_compatible(ref_crtc_state, 4546 crtc_state)) 4547 continue; 4548 transcoders |= BIT(crtc_state->cpu_transcoder); 4549 } 4550 4551 return transcoders; 4552 } 4553 4554 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4555 struct intel_crtc_state *crtc_state, 4556 struct drm_connector_state *conn_state) 4557 { 4558 struct intel_display *display = to_intel_display(encoder); 4559 struct drm_connector *connector = conn_state->connector; 4560 u8 port_sync_transcoders = 0; 4561 4562 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4563 encoder->base.base.id, encoder->base.name, 4564 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4565 4566 if (connector->has_tile) 4567 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4568 connector->tile_group->id); 4569 4570 /* 4571 * EDP Transcoders cannot be ensalved 4572 * make them a master always when present 4573 */ 4574 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4575 crtc_state->master_transcoder = TRANSCODER_EDP; 4576 else 4577 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4578 4579 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4580 crtc_state->master_transcoder = INVALID_TRANSCODER; 4581 crtc_state->sync_mode_slaves_mask = 4582 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4583 } 4584 4585 return 0; 4586 } 4587 4588 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4589 { 4590 struct intel_display *display = to_intel_display(encoder->dev); 4591 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4592 4593 intel_dp_encoder_flush_work(encoder); 4594 if (intel_encoder_is_tc(&dig_port->base)) 4595 intel_tc_port_cleanup(dig_port); 4596 intel_display_power_flush_work(display); 4597 4598 drm_encoder_cleanup(encoder); 4599 kfree(dig_port->hdcp.port_data.streams); 4600 kfree(dig_port); 4601 } 4602 4603 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4604 { 4605 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4606 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4607 4608 intel_dp->reset_link_params = true; 4609 intel_dp_invalidate_source_oui(intel_dp); 4610 4611 intel_pps_encoder_reset(intel_dp); 4612 4613 if (intel_encoder_is_tc(&dig_port->base)) 4614 intel_tc_port_init_mode(dig_port); 4615 } 4616 4617 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4618 { 4619 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4620 4621 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4622 4623 return 0; 4624 } 4625 4626 static const struct drm_encoder_funcs intel_ddi_funcs = { 4627 .reset = intel_ddi_encoder_reset, 4628 .destroy = intel_ddi_encoder_destroy, 4629 .late_register = intel_ddi_encoder_late_register, 4630 }; 4631 4632 static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4633 { 4634 struct intel_display *display = to_intel_display(dig_port); 4635 struct intel_connector *connector; 4636 enum port port = dig_port->base.port; 4637 4638 connector = intel_connector_alloc(); 4639 if (!connector) 4640 return -ENOMEM; 4641 4642 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4643 if (DISPLAY_VER(display) >= 14) 4644 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4645 else 4646 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4647 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4648 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4649 4650 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4651 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4652 4653 if (!intel_dp_init_connector(dig_port, connector)) { 4654 kfree(connector); 4655 return -EINVAL; 4656 } 4657 4658 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4659 struct drm_privacy_screen *privacy_screen; 4660 4661 privacy_screen = drm_privacy_screen_get(display->drm->dev, NULL); 4662 if (!IS_ERR(privacy_screen)) { 4663 drm_connector_attach_privacy_screen_provider(&connector->base, 4664 privacy_screen); 4665 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4666 drm_warn(display->drm, "Error getting privacy-screen\n"); 4667 } 4668 } 4669 4670 return 0; 4671 } 4672 4673 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4674 struct drm_modeset_acquire_ctx *ctx) 4675 { 4676 struct intel_display *display = to_intel_display(encoder); 4677 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4678 struct intel_connector *connector = hdmi->attached_connector; 4679 struct i2c_adapter *ddc = connector->base.ddc; 4680 struct drm_connector_state *conn_state; 4681 struct intel_crtc_state *crtc_state; 4682 struct intel_crtc *crtc; 4683 u8 config; 4684 int ret; 4685 4686 if (connector->base.status != connector_status_connected) 4687 return 0; 4688 4689 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, 4690 ctx); 4691 if (ret) 4692 return ret; 4693 4694 conn_state = connector->base.state; 4695 4696 crtc = to_intel_crtc(conn_state->crtc); 4697 if (!crtc) 4698 return 0; 4699 4700 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4701 if (ret) 4702 return ret; 4703 4704 crtc_state = to_intel_crtc_state(crtc->base.state); 4705 4706 drm_WARN_ON(display->drm, 4707 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4708 4709 if (!crtc_state->hw.active) 4710 return 0; 4711 4712 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4713 !crtc_state->hdmi_scrambling) 4714 return 0; 4715 4716 if (conn_state->commit && 4717 !try_wait_for_completion(&conn_state->commit->hw_done)) 4718 return 0; 4719 4720 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4721 if (ret < 0) { 4722 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4723 connector->base.base.id, connector->base.name, ret); 4724 return 0; 4725 } 4726 4727 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4728 crtc_state->hdmi_high_tmds_clock_ratio && 4729 !!(config & SCDC_SCRAMBLING_ENABLE) == 4730 crtc_state->hdmi_scrambling) 4731 return 0; 4732 4733 /* 4734 * HDMI 2.0 says that one should not send scrambled data 4735 * prior to configuring the sink scrambling, and that 4736 * TMDS clock/data transmission should be suspended when 4737 * changing the TMDS clock rate in the sink. So let's 4738 * just do a full modeset here, even though some sinks 4739 * would be perfectly happy if were to just reconfigure 4740 * the SCDC settings on the fly. 4741 */ 4742 return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); 4743 } 4744 4745 static void intel_ddi_link_check(struct intel_encoder *encoder) 4746 { 4747 struct intel_display *display = to_intel_display(encoder); 4748 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4749 4750 /* TODO: Move checking the HDMI link state here as well. */ 4751 drm_WARN_ON(display->drm, !dig_port->dp.attached_connector); 4752 4753 intel_dp_link_check(encoder); 4754 } 4755 4756 static enum intel_hotplug_state 4757 intel_ddi_hotplug(struct intel_encoder *encoder, 4758 struct intel_connector *connector) 4759 { 4760 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4761 struct intel_dp *intel_dp = &dig_port->dp; 4762 bool is_tc = intel_encoder_is_tc(encoder); 4763 struct drm_modeset_acquire_ctx ctx; 4764 enum intel_hotplug_state state; 4765 int ret; 4766 4767 if (intel_dp_test_phy(intel_dp)) 4768 return INTEL_HOTPLUG_UNCHANGED; 4769 4770 state = intel_encoder_hotplug(encoder, connector); 4771 4772 if (!intel_tc_port_link_reset(dig_port)) { 4773 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 4774 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) 4775 ret = intel_hdmi_reset_link(encoder, &ctx); 4776 drm_WARN_ON(encoder->base.dev, ret); 4777 } else { 4778 intel_dp_check_link_state(intel_dp); 4779 } 4780 } 4781 4782 /* 4783 * Unpowered type-c dongles can take some time to boot and be 4784 * responsible, so here giving some time to those dongles to power up 4785 * and then retrying the probe. 4786 * 4787 * On many platforms the HDMI live state signal is known to be 4788 * unreliable, so we can't use it to detect if a sink is connected or 4789 * not. Instead we detect if it's connected based on whether we can 4790 * read the EDID or not. That in turn has a problem during disconnect, 4791 * since the HPD interrupt may be raised before the DDC lines get 4792 * disconnected (due to how the required length of DDC vs. HPD 4793 * connector pins are specified) and so we'll still be able to get a 4794 * valid EDID. To solve this schedule another detection cycle if this 4795 * time around we didn't detect any change in the sink's connection 4796 * status. 4797 * 4798 * Type-c connectors which get their HPD signal deasserted then 4799 * reasserted, without unplugging/replugging the sink from the 4800 * connector, introduce a delay until the AUX channel communication 4801 * becomes functional. Retry the detection for 5 seconds on type-c 4802 * connectors to account for this delay. 4803 */ 4804 if (state == INTEL_HOTPLUG_UNCHANGED && 4805 connector->hotplug_retries < (is_tc ? 5 : 1) && 4806 !dig_port->dp.is_mst) 4807 state = INTEL_HOTPLUG_RETRY; 4808 4809 return state; 4810 } 4811 4812 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4813 { 4814 struct intel_display *display = to_intel_display(encoder); 4815 u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin]; 4816 4817 return intel_de_read(display, SDEISR) & bit; 4818 } 4819 4820 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4821 { 4822 struct intel_display *display = to_intel_display(encoder); 4823 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4824 4825 return intel_de_read(display, DEISR) & bit; 4826 } 4827 4828 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4829 { 4830 struct intel_display *display = to_intel_display(encoder); 4831 u32 bit = display->hotplug.hpd[encoder->hpd_pin]; 4832 4833 return intel_de_read(display, GEN8_DE_PORT_ISR) & bit; 4834 } 4835 4836 static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4837 { 4838 struct intel_connector *connector; 4839 enum port port = dig_port->base.port; 4840 4841 connector = intel_connector_alloc(); 4842 if (!connector) 4843 return -ENOMEM; 4844 4845 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4846 4847 if (!intel_hdmi_init_connector(dig_port, connector)) { 4848 /* 4849 * HDMI connector init failures may just mean conflicting DDC 4850 * pins or not having enough lanes. Handle them gracefully, but 4851 * don't fail the entire DDI init. 4852 */ 4853 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; 4854 kfree(connector); 4855 } 4856 4857 return 0; 4858 } 4859 4860 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4861 { 4862 struct intel_display *display = to_intel_display(dig_port); 4863 4864 if (dig_port->base.port != PORT_A) 4865 return false; 4866 4867 if (dig_port->ddi_a_4_lanes) 4868 return false; 4869 4870 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4871 * supported configuration 4872 */ 4873 if (display->platform.geminilake || display->platform.broxton) 4874 return true; 4875 4876 return false; 4877 } 4878 4879 static int 4880 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4881 { 4882 struct intel_display *display = to_intel_display(dig_port); 4883 enum port port = dig_port->base.port; 4884 int max_lanes = 4; 4885 4886 if (DISPLAY_VER(display) >= 11) 4887 return max_lanes; 4888 4889 if (port == PORT_A || port == PORT_E) { 4890 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4891 max_lanes = port == PORT_A ? 4 : 0; 4892 else 4893 /* Both A and E share 2 lanes */ 4894 max_lanes = 2; 4895 } 4896 4897 /* 4898 * Some BIOS might fail to set this bit on port A if eDP 4899 * wasn't lit up at boot. Force this bit set when needed 4900 * so we use the proper lane count for our calculations. 4901 */ 4902 if (intel_ddi_a_force_4_lanes(dig_port)) { 4903 drm_dbg_kms(display->drm, 4904 "Forcing DDI_A_4_LANES for port A\n"); 4905 dig_port->ddi_a_4_lanes = true; 4906 max_lanes = 4; 4907 } 4908 4909 return max_lanes; 4910 } 4911 4912 static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port) 4913 { 4914 if (port >= PORT_D_XELPD) 4915 return HPD_PORT_D + port - PORT_D_XELPD; 4916 else if (port >= PORT_TC1) 4917 return HPD_PORT_TC1 + port - PORT_TC1; 4918 else 4919 return HPD_PORT_A + port - PORT_A; 4920 } 4921 4922 static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port) 4923 { 4924 if (port >= PORT_TC1) 4925 return HPD_PORT_C + port - PORT_TC1; 4926 else 4927 return HPD_PORT_A + port - PORT_A; 4928 } 4929 4930 static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port) 4931 { 4932 if (port >= PORT_TC1) 4933 return HPD_PORT_TC1 + port - PORT_TC1; 4934 else 4935 return HPD_PORT_A + port - PORT_A; 4936 } 4937 4938 static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port) 4939 { 4940 if (HAS_PCH_TGP(display)) 4941 return tgl_hpd_pin(display, port); 4942 4943 if (port >= PORT_TC1) 4944 return HPD_PORT_C + port - PORT_TC1; 4945 else 4946 return HPD_PORT_A + port - PORT_A; 4947 } 4948 4949 static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port) 4950 { 4951 if (port >= PORT_C) 4952 return HPD_PORT_TC1 + port - PORT_C; 4953 else 4954 return HPD_PORT_A + port - PORT_A; 4955 } 4956 4957 static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port) 4958 { 4959 if (port == PORT_D) 4960 return HPD_PORT_A; 4961 4962 if (HAS_PCH_TGP(display)) 4963 return icl_hpd_pin(display, port); 4964 4965 return HPD_PORT_A + port - PORT_A; 4966 } 4967 4968 static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port) 4969 { 4970 if (HAS_PCH_TGP(display)) 4971 return icl_hpd_pin(display, port); 4972 4973 return HPD_PORT_A + port - PORT_A; 4974 } 4975 4976 static bool intel_ddi_is_tc(struct intel_display *display, enum port port) 4977 { 4978 if (DISPLAY_VER(display) >= 12) 4979 return port >= PORT_TC1; 4980 else if (DISPLAY_VER(display) >= 11) 4981 return port >= PORT_C; 4982 else 4983 return false; 4984 } 4985 4986 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4987 { 4988 intel_dp_encoder_suspend(encoder); 4989 } 4990 4991 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4992 { 4993 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4994 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4995 4996 /* 4997 * TODO: Move this to intel_dp_encoder_suspend(), 4998 * once modeset locking around that is removed. 4999 */ 5000 intel_encoder_link_check_flush_work(encoder); 5001 intel_tc_port_suspend(dig_port); 5002 } 5003 5004 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 5005 { 5006 if (intel_encoder_is_dp(encoder)) 5007 intel_dp_encoder_shutdown(encoder); 5008 if (intel_encoder_is_hdmi(encoder)) 5009 intel_hdmi_encoder_shutdown(encoder); 5010 } 5011 5012 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 5013 { 5014 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 5015 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5016 5017 intel_tc_port_cleanup(dig_port); 5018 } 5019 5020 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 5021 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 5022 5023 static bool port_strap_detected(struct intel_display *display, enum port port) 5024 { 5025 /* straps not used on skl+ */ 5026 if (DISPLAY_VER(display) >= 9) 5027 return true; 5028 5029 switch (port) { 5030 case PORT_A: 5031 return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 5032 case PORT_B: 5033 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 5034 case PORT_C: 5035 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 5036 case PORT_D: 5037 return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 5038 case PORT_E: 5039 return true; /* no strap for DDI-E */ 5040 default: 5041 MISSING_CASE(port); 5042 return false; 5043 } 5044 } 5045 5046 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 5047 { 5048 return init_dp || intel_encoder_is_tc(encoder); 5049 } 5050 5051 static bool assert_has_icl_dsi(struct intel_display *display) 5052 { 5053 return !drm_WARN(display->drm, !display->platform.alderlake_p && 5054 !display->platform.tigerlake && DISPLAY_VER(display) != 11, 5055 "Platform does not support DSI\n"); 5056 } 5057 5058 static bool port_in_use(struct intel_display *display, enum port port) 5059 { 5060 struct intel_encoder *encoder; 5061 5062 for_each_intel_encoder(display->drm, encoder) { 5063 /* FIXME what about second port for dual link DSI? */ 5064 if (encoder->port == port) 5065 return true; 5066 } 5067 5068 return false; 5069 } 5070 5071 static const char *intel_ddi_encoder_name(struct intel_display *display, 5072 enum port port, enum phy phy, 5073 struct seq_buf *s) 5074 { 5075 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) { 5076 seq_buf_printf(s, "DDI %c/PHY %c", 5077 port_name(port - PORT_D_XELPD + PORT_D), 5078 phy_name(phy)); 5079 } else if (DISPLAY_VER(display) >= 12) { 5080 enum tc_port tc_port = intel_port_to_tc(display, port); 5081 5082 seq_buf_printf(s, "DDI %s%c/PHY %s%c", 5083 port >= PORT_TC1 ? "TC" : "", 5084 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 5085 tc_port != TC_PORT_NONE ? "TC" : "", 5086 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5087 } else if (DISPLAY_VER(display) >= 11) { 5088 enum tc_port tc_port = intel_port_to_tc(display, port); 5089 5090 seq_buf_printf(s, "DDI %c%s/PHY %s%c", 5091 port_name(port), 5092 port >= PORT_C ? " (TC)" : "", 5093 tc_port != TC_PORT_NONE ? "TC" : "", 5094 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5095 } else { 5096 seq_buf_printf(s, "DDI %c/PHY %c", port_name(port), phy_name(phy)); 5097 } 5098 5099 drm_WARN_ON(display->drm, seq_buf_has_overflowed(s)); 5100 5101 return seq_buf_str(s); 5102 } 5103 5104 void intel_ddi_init(struct intel_display *display, 5105 const struct intel_bios_encoder_data *devdata) 5106 { 5107 struct intel_digital_port *dig_port; 5108 struct intel_encoder *encoder; 5109 DECLARE_SEQ_BUF(encoder_name, 20); 5110 bool init_hdmi, init_dp; 5111 enum port port; 5112 enum phy phy; 5113 u32 ddi_buf_ctl; 5114 5115 port = intel_bios_encoder_port(devdata); 5116 if (port == PORT_NONE) 5117 return; 5118 5119 if (!port_strap_detected(display, port)) { 5120 drm_dbg_kms(display->drm, 5121 "Port %c strap not detected\n", port_name(port)); 5122 return; 5123 } 5124 5125 if (!assert_port_valid(display, port)) 5126 return; 5127 5128 if (port_in_use(display, port)) { 5129 drm_dbg_kms(display->drm, 5130 "Port %c already claimed\n", port_name(port)); 5131 return; 5132 } 5133 5134 if (intel_bios_encoder_supports_dsi(devdata)) { 5135 /* BXT/GLK handled elsewhere, for now at least */ 5136 if (!assert_has_icl_dsi(display)) 5137 return; 5138 5139 icl_dsi_init(display, devdata); 5140 return; 5141 } 5142 5143 phy = intel_port_to_phy(display, port); 5144 5145 /* 5146 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 5147 * have taken over some of the PHYs and made them unavailable to the 5148 * driver. In that case we should skip initializing the corresponding 5149 * outputs. 5150 */ 5151 if (intel_hti_uses_phy(display, phy)) { 5152 drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n", 5153 port_name(port), phy_name(phy)); 5154 return; 5155 } 5156 5157 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 5158 intel_bios_encoder_supports_hdmi(devdata); 5159 init_dp = intel_bios_encoder_supports_dp(devdata); 5160 5161 if (intel_bios_encoder_is_lspcon(devdata)) { 5162 /* 5163 * Lspcon device needs to be driven with DP connector 5164 * with special detection sequence. So make sure DP 5165 * is initialized before lspcon. 5166 */ 5167 init_dp = true; 5168 init_hdmi = false; 5169 drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n", 5170 port_name(port)); 5171 } 5172 5173 if (!init_dp && !init_hdmi) { 5174 drm_dbg_kms(display->drm, 5175 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 5176 port_name(port)); 5177 return; 5178 } 5179 5180 if (intel_phy_is_snps(display, phy) && 5181 display->snps.phy_failed_calibration & BIT(phy)) { 5182 drm_dbg_kms(display->drm, 5183 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 5184 phy_name(phy)); 5185 } 5186 5187 dig_port = intel_dig_port_alloc(); 5188 if (!dig_port) 5189 return; 5190 5191 encoder = &dig_port->base; 5192 encoder->devdata = devdata; 5193 5194 drm_encoder_init(display->drm, &encoder->base, &intel_ddi_funcs, 5195 DRM_MODE_ENCODER_TMDS, "%s", 5196 intel_ddi_encoder_name(display, port, phy, &encoder_name)); 5197 5198 intel_encoder_link_check_init(encoder, intel_ddi_link_check); 5199 5200 encoder->hotplug = intel_ddi_hotplug; 5201 encoder->compute_output_type = intel_ddi_compute_output_type; 5202 encoder->compute_config = intel_ddi_compute_config; 5203 encoder->compute_config_late = intel_ddi_compute_config_late; 5204 encoder->enable = intel_ddi_enable; 5205 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5206 encoder->pre_enable = intel_ddi_pre_enable; 5207 encoder->disable = intel_ddi_disable; 5208 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5209 encoder->post_disable = intel_ddi_post_disable; 5210 encoder->update_pipe = intel_ddi_update_pipe; 5211 encoder->audio_enable = intel_audio_codec_enable; 5212 encoder->audio_disable = intel_audio_codec_disable; 5213 encoder->get_hw_state = intel_ddi_get_hw_state; 5214 encoder->sync_state = intel_ddi_sync_state; 5215 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 5216 encoder->suspend = intel_ddi_encoder_suspend; 5217 encoder->shutdown = intel_ddi_encoder_shutdown; 5218 encoder->get_power_domains = intel_ddi_get_power_domains; 5219 5220 encoder->type = INTEL_OUTPUT_DDI; 5221 encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 5222 encoder->port = port; 5223 encoder->cloneable = 0; 5224 encoder->pipe_mask = ~0; 5225 5226 if (DISPLAY_VER(display) >= 14) { 5227 encoder->enable_clock = intel_mtl_pll_enable; 5228 encoder->disable_clock = intel_mtl_pll_disable; 5229 encoder->port_pll_type = intel_mtl_port_pll_type; 5230 encoder->get_config = mtl_ddi_get_config; 5231 } else if (display->platform.dg2) { 5232 encoder->enable_clock = intel_mpllb_enable; 5233 encoder->disable_clock = intel_mpllb_disable; 5234 encoder->get_config = dg2_ddi_get_config; 5235 } else if (display->platform.alderlake_s) { 5236 encoder->enable_clock = adls_ddi_enable_clock; 5237 encoder->disable_clock = adls_ddi_disable_clock; 5238 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5239 encoder->get_config = adls_ddi_get_config; 5240 } else if (display->platform.rocketlake) { 5241 encoder->enable_clock = rkl_ddi_enable_clock; 5242 encoder->disable_clock = rkl_ddi_disable_clock; 5243 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5244 encoder->get_config = rkl_ddi_get_config; 5245 } else if (display->platform.dg1) { 5246 encoder->enable_clock = dg1_ddi_enable_clock; 5247 encoder->disable_clock = dg1_ddi_disable_clock; 5248 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5249 encoder->get_config = dg1_ddi_get_config; 5250 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 5251 if (intel_ddi_is_tc(display, port)) { 5252 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5253 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5254 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5255 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5256 encoder->get_config = icl_ddi_combo_get_config; 5257 } else { 5258 encoder->enable_clock = icl_ddi_combo_enable_clock; 5259 encoder->disable_clock = icl_ddi_combo_disable_clock; 5260 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5261 encoder->get_config = icl_ddi_combo_get_config; 5262 } 5263 } else if (DISPLAY_VER(display) >= 11) { 5264 if (intel_ddi_is_tc(display, port)) { 5265 encoder->enable_clock = icl_ddi_tc_enable_clock; 5266 encoder->disable_clock = icl_ddi_tc_disable_clock; 5267 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5268 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5269 encoder->get_config = icl_ddi_tc_get_config; 5270 } else { 5271 encoder->enable_clock = icl_ddi_combo_enable_clock; 5272 encoder->disable_clock = icl_ddi_combo_disable_clock; 5273 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5274 encoder->get_config = icl_ddi_combo_get_config; 5275 } 5276 } else if (display->platform.geminilake || display->platform.broxton) { 5277 /* BXT/GLK have fixed PLL->port mapping */ 5278 encoder->get_config = bxt_ddi_get_config; 5279 } else if (DISPLAY_VER(display) == 9) { 5280 encoder->enable_clock = skl_ddi_enable_clock; 5281 encoder->disable_clock = skl_ddi_disable_clock; 5282 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5283 encoder->get_config = skl_ddi_get_config; 5284 } else if (display->platform.broadwell || display->platform.haswell) { 5285 encoder->enable_clock = hsw_ddi_enable_clock; 5286 encoder->disable_clock = hsw_ddi_disable_clock; 5287 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5288 encoder->get_config = hsw_ddi_get_config; 5289 } 5290 5291 if (DISPLAY_VER(display) >= 14) { 5292 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5293 } else if (display->platform.dg2) { 5294 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5295 } else if (DISPLAY_VER(display) >= 12) { 5296 if (intel_encoder_is_combo(encoder)) 5297 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5298 else 5299 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5300 } else if (DISPLAY_VER(display) >= 11) { 5301 if (intel_encoder_is_combo(encoder)) 5302 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5303 else 5304 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5305 } else if (display->platform.geminilake || display->platform.broxton) { 5306 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5307 } else { 5308 encoder->set_signal_levels = hsw_set_signal_levels; 5309 } 5310 5311 intel_ddi_buf_trans_init(encoder); 5312 5313 if (DISPLAY_VER(display) >= 13) 5314 encoder->hpd_pin = xelpd_hpd_pin(display, port); 5315 else if (display->platform.dg1) 5316 encoder->hpd_pin = dg1_hpd_pin(display, port); 5317 else if (display->platform.rocketlake) 5318 encoder->hpd_pin = rkl_hpd_pin(display, port); 5319 else if (DISPLAY_VER(display) >= 12) 5320 encoder->hpd_pin = tgl_hpd_pin(display, port); 5321 else if (display->platform.jasperlake || display->platform.elkhartlake) 5322 encoder->hpd_pin = ehl_hpd_pin(display, port); 5323 else if (DISPLAY_VER(display) == 11) 5324 encoder->hpd_pin = icl_hpd_pin(display, port); 5325 else if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 5326 encoder->hpd_pin = skl_hpd_pin(display, port); 5327 else 5328 encoder->hpd_pin = intel_hpd_pin_default(port); 5329 5330 ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port)); 5331 5332 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5333 ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5334 5335 dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5336 5337 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5338 5339 if (need_aux_ch(encoder, init_dp)) { 5340 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5341 if (dig_port->aux_ch == AUX_CH_NONE) 5342 goto err; 5343 } 5344 5345 if (intel_encoder_is_tc(encoder)) { 5346 bool is_legacy = 5347 !intel_bios_encoder_supports_typec_usb(devdata) && 5348 !intel_bios_encoder_supports_tbt(devdata); 5349 5350 if (!is_legacy && init_hdmi) { 5351 is_legacy = !init_dp; 5352 5353 drm_dbg_kms(display->drm, 5354 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5355 port_name(port), 5356 str_yes_no(init_dp), 5357 is_legacy ? "legacy" : "non-legacy"); 5358 } 5359 5360 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5361 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5362 5363 dig_port->lock = intel_tc_port_lock; 5364 dig_port->unlock = intel_tc_port_unlock; 5365 5366 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5367 goto err; 5368 } 5369 5370 drm_WARN_ON(display->drm, port > PORT_I); 5371 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); 5372 5373 if (DISPLAY_VER(display) >= 11) { 5374 if (intel_encoder_is_tc(encoder)) 5375 dig_port->connected = intel_tc_port_connected; 5376 else 5377 dig_port->connected = lpt_digital_port_connected; 5378 } else if (display->platform.geminilake || display->platform.broxton) { 5379 dig_port->connected = bdw_digital_port_connected; 5380 } else if (DISPLAY_VER(display) == 9) { 5381 dig_port->connected = lpt_digital_port_connected; 5382 } else if (display->platform.broadwell) { 5383 if (port == PORT_A) 5384 dig_port->connected = bdw_digital_port_connected; 5385 else 5386 dig_port->connected = lpt_digital_port_connected; 5387 } else if (display->platform.haswell) { 5388 if (port == PORT_A) 5389 dig_port->connected = hsw_digital_port_connected; 5390 else 5391 dig_port->connected = lpt_digital_port_connected; 5392 } 5393 5394 intel_infoframe_init(dig_port); 5395 5396 if (init_dp) { 5397 if (intel_ddi_init_dp_connector(dig_port)) 5398 goto err; 5399 5400 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5401 5402 if (dig_port->dp.mso_link_count) 5403 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display); 5404 } 5405 5406 /* 5407 * In theory we don't need the encoder->type check, 5408 * but leave it just in case we have some really bad VBTs... 5409 */ 5410 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5411 if (intel_ddi_init_hdmi_connector(dig_port)) 5412 goto err; 5413 } 5414 5415 return; 5416 5417 err: 5418 drm_encoder_cleanup(&encoder->base); 5419 kfree(dig_port); 5420 } 5421