1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drm_scdc_helper.h> 29 30 #include "i915_drv.h" 31 #include "intel_audio.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_crtc.h" 35 #include "intel_ddi.h" 36 #include "intel_ddi_buf_trans.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_dp.h" 40 #include "intel_dp_link_training.h" 41 #include "intel_dp_mst.h" 42 #include "intel_dpio_phy.h" 43 #include "intel_dsi.h" 44 #include "intel_fdi.h" 45 #include "intel_fifo_underrun.h" 46 #include "intel_gmbus.h" 47 #include "intel_hdcp.h" 48 #include "intel_hdmi.h" 49 #include "intel_hotplug.h" 50 #include "intel_lspcon.h" 51 #include "intel_panel.h" 52 #include "intel_pps.h" 53 #include "intel_psr.h" 54 #include "intel_sprite.h" 55 #include "intel_tc.h" 56 #include "intel_vdsc.h" 57 #include "intel_vrr.h" 58 #include "skl_scaler.h" 59 #include "skl_universal_plane.h" 60 61 static const u8 index_to_dp_signal_levels[] = { 62 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 63 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 64 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 65 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 66 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 67 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 68 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 69 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 70 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 71 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 72 }; 73 74 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 75 const struct intel_crtc_state *crtc_state) 76 { 77 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 78 int n_entries, level, default_entry; 79 80 n_entries = intel_ddi_hdmi_num_entries(encoder, crtc_state, &default_entry); 81 if (n_entries == 0) 82 return 0; 83 level = intel_bios_hdmi_level_shift(encoder); 84 if (level < 0) 85 level = default_entry; 86 87 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 88 level = n_entries - 1; 89 90 return level; 91 } 92 93 /* 94 * Starting with Haswell, DDI port buffers must be programmed with correct 95 * values in advance. This function programs the correct values for 96 * DP/eDP/FDI use cases. 97 */ 98 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 99 const struct intel_crtc_state *crtc_state) 100 { 101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 102 u32 iboost_bit = 0; 103 int i, n_entries; 104 enum port port = encoder->port; 105 const struct intel_ddi_buf_trans *ddi_translations; 106 107 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 108 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 109 return; 110 111 /* If we're boosting the current, set bit 31 of trans1 */ 112 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 113 intel_bios_encoder_dp_boost_level(encoder->devdata)) 114 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 115 116 for (i = 0; i < n_entries; i++) { 117 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 118 ddi_translations->entries[i].hsw.trans1 | iboost_bit); 119 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 120 ddi_translations->entries[i].hsw.trans2); 121 } 122 } 123 124 /* 125 * Starting with Haswell, DDI port buffers must be programmed with correct 126 * values in advance. This function programs the correct values for 127 * HDMI/DVI use cases. 128 */ 129 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 130 const struct intel_crtc_state *crtc_state, 131 int level) 132 { 133 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 134 u32 iboost_bit = 0; 135 int n_entries; 136 enum port port = encoder->port; 137 const struct intel_ddi_buf_trans *ddi_translations; 138 139 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 140 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 141 return; 142 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 143 level = n_entries - 1; 144 145 /* If we're boosting the current, set bit 31 of trans1 */ 146 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 147 intel_bios_encoder_hdmi_boost_level(encoder->devdata)) 148 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 149 150 /* Entry 9 is for HDMI: */ 151 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 152 ddi_translations->entries[level].hsw.trans1 | iboost_bit); 153 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 154 ddi_translations->entries[level].hsw.trans2); 155 } 156 157 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 158 enum port port) 159 { 160 if (IS_BROXTON(dev_priv)) { 161 udelay(16); 162 return; 163 } 164 165 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 166 DDI_BUF_IS_IDLE), 8)) 167 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 168 port_name(port)); 169 } 170 171 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv, 172 enum port port) 173 { 174 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 175 if (DISPLAY_VER(dev_priv) < 10) { 176 usleep_range(518, 1000); 177 return; 178 } 179 180 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 181 DDI_BUF_IS_IDLE), 500)) 182 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 183 port_name(port)); 184 } 185 186 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 187 { 188 switch (pll->info->id) { 189 case DPLL_ID_WRPLL1: 190 return PORT_CLK_SEL_WRPLL1; 191 case DPLL_ID_WRPLL2: 192 return PORT_CLK_SEL_WRPLL2; 193 case DPLL_ID_SPLL: 194 return PORT_CLK_SEL_SPLL; 195 case DPLL_ID_LCPLL_810: 196 return PORT_CLK_SEL_LCPLL_810; 197 case DPLL_ID_LCPLL_1350: 198 return PORT_CLK_SEL_LCPLL_1350; 199 case DPLL_ID_LCPLL_2700: 200 return PORT_CLK_SEL_LCPLL_2700; 201 default: 202 MISSING_CASE(pll->info->id); 203 return PORT_CLK_SEL_NONE; 204 } 205 } 206 207 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 208 const struct intel_crtc_state *crtc_state) 209 { 210 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 211 int clock = crtc_state->port_clock; 212 const enum intel_dpll_id id = pll->info->id; 213 214 switch (id) { 215 default: 216 /* 217 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 218 * here, so do warn if this get passed in 219 */ 220 MISSING_CASE(id); 221 return DDI_CLK_SEL_NONE; 222 case DPLL_ID_ICL_TBTPLL: 223 switch (clock) { 224 case 162000: 225 return DDI_CLK_SEL_TBT_162; 226 case 270000: 227 return DDI_CLK_SEL_TBT_270; 228 case 540000: 229 return DDI_CLK_SEL_TBT_540; 230 case 810000: 231 return DDI_CLK_SEL_TBT_810; 232 default: 233 MISSING_CASE(clock); 234 return DDI_CLK_SEL_NONE; 235 } 236 case DPLL_ID_ICL_MGPLL1: 237 case DPLL_ID_ICL_MGPLL2: 238 case DPLL_ID_ICL_MGPLL3: 239 case DPLL_ID_ICL_MGPLL4: 240 case DPLL_ID_TGL_MGPLL5: 241 case DPLL_ID_TGL_MGPLL6: 242 return DDI_CLK_SEL_MG; 243 } 244 } 245 246 static u32 ddi_buf_phy_link_rate(int port_clock) 247 { 248 switch (port_clock) { 249 case 162000: 250 return DDI_BUF_PHY_LINK_RATE(0); 251 case 216000: 252 return DDI_BUF_PHY_LINK_RATE(4); 253 case 243000: 254 return DDI_BUF_PHY_LINK_RATE(5); 255 case 270000: 256 return DDI_BUF_PHY_LINK_RATE(1); 257 case 324000: 258 return DDI_BUF_PHY_LINK_RATE(6); 259 case 432000: 260 return DDI_BUF_PHY_LINK_RATE(7); 261 case 540000: 262 return DDI_BUF_PHY_LINK_RATE(2); 263 case 810000: 264 return DDI_BUF_PHY_LINK_RATE(3); 265 default: 266 MISSING_CASE(port_clock); 267 return DDI_BUF_PHY_LINK_RATE(0); 268 } 269 } 270 271 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 272 const struct intel_crtc_state *crtc_state) 273 { 274 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 275 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 276 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 277 enum phy phy = intel_port_to_phy(i915, encoder->port); 278 279 intel_dp->DP = dig_port->saved_port_bits | 280 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 281 intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count); 282 283 if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) { 284 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 285 if (dig_port->tc_mode != TC_PORT_TBT_ALT) 286 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 287 } 288 } 289 290 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 291 enum port port) 292 { 293 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 294 295 switch (val) { 296 case DDI_CLK_SEL_NONE: 297 return 0; 298 case DDI_CLK_SEL_TBT_162: 299 return 162000; 300 case DDI_CLK_SEL_TBT_270: 301 return 270000; 302 case DDI_CLK_SEL_TBT_540: 303 return 540000; 304 case DDI_CLK_SEL_TBT_810: 305 return 810000; 306 default: 307 MISSING_CASE(val); 308 return 0; 309 } 310 } 311 312 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 313 { 314 int dotclock; 315 316 if (pipe_config->has_pch_encoder) 317 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 318 &pipe_config->fdi_m_n); 319 else if (intel_crtc_has_dp_encoder(pipe_config)) 320 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 321 &pipe_config->dp_m_n); 322 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 323 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; 324 else 325 dotclock = pipe_config->port_clock; 326 327 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 328 !intel_crtc_has_dp_encoder(pipe_config)) 329 dotclock *= 2; 330 331 if (pipe_config->pixel_multiplier) 332 dotclock /= pipe_config->pixel_multiplier; 333 334 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 335 } 336 337 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 338 const struct drm_connector_state *conn_state) 339 { 340 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 341 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 342 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 343 u32 temp; 344 345 if (!intel_crtc_has_dp_encoder(crtc_state)) 346 return; 347 348 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 349 350 temp = DP_MSA_MISC_SYNC_CLOCK; 351 352 switch (crtc_state->pipe_bpp) { 353 case 18: 354 temp |= DP_MSA_MISC_6_BPC; 355 break; 356 case 24: 357 temp |= DP_MSA_MISC_8_BPC; 358 break; 359 case 30: 360 temp |= DP_MSA_MISC_10_BPC; 361 break; 362 case 36: 363 temp |= DP_MSA_MISC_12_BPC; 364 break; 365 default: 366 MISSING_CASE(crtc_state->pipe_bpp); 367 break; 368 } 369 370 /* nonsense combination */ 371 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 372 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 373 374 if (crtc_state->limited_color_range) 375 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 376 377 /* 378 * As per DP 1.2 spec section 2.3.4.3 while sending 379 * YCBCR 444 signals we should program MSA MISC1/0 fields with 380 * colorspace information. 381 */ 382 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 383 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 384 385 /* 386 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 387 * of Color Encoding Format and Content Color Gamut] while sending 388 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 389 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 390 */ 391 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 392 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 393 394 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 395 } 396 397 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 398 { 399 if (master_transcoder == TRANSCODER_EDP) 400 return 0; 401 else 402 return master_transcoder + 1; 403 } 404 405 /* 406 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 407 * 408 * Only intended to be used by intel_ddi_enable_transcoder_func() and 409 * intel_ddi_config_transcoder_func(). 410 */ 411 static u32 412 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 413 const struct intel_crtc_state *crtc_state) 414 { 415 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 416 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 417 enum pipe pipe = crtc->pipe; 418 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 419 enum port port = encoder->port; 420 u32 temp; 421 422 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 423 temp = TRANS_DDI_FUNC_ENABLE; 424 if (DISPLAY_VER(dev_priv) >= 12) 425 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 426 else 427 temp |= TRANS_DDI_SELECT_PORT(port); 428 429 switch (crtc_state->pipe_bpp) { 430 case 18: 431 temp |= TRANS_DDI_BPC_6; 432 break; 433 case 24: 434 temp |= TRANS_DDI_BPC_8; 435 break; 436 case 30: 437 temp |= TRANS_DDI_BPC_10; 438 break; 439 case 36: 440 temp |= TRANS_DDI_BPC_12; 441 break; 442 default: 443 BUG(); 444 } 445 446 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 447 temp |= TRANS_DDI_PVSYNC; 448 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 449 temp |= TRANS_DDI_PHSYNC; 450 451 if (cpu_transcoder == TRANSCODER_EDP) { 452 switch (pipe) { 453 case PIPE_A: 454 /* On Haswell, can only use the always-on power well for 455 * eDP when not using the panel fitter, and when not 456 * using motion blur mitigation (which we don't 457 * support). */ 458 if (crtc_state->pch_pfit.force_thru) 459 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 460 else 461 temp |= TRANS_DDI_EDP_INPUT_A_ON; 462 break; 463 case PIPE_B: 464 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 465 break; 466 case PIPE_C: 467 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 468 break; 469 default: 470 BUG(); 471 break; 472 } 473 } 474 475 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 476 if (crtc_state->has_hdmi_sink) 477 temp |= TRANS_DDI_MODE_SELECT_HDMI; 478 else 479 temp |= TRANS_DDI_MODE_SELECT_DVI; 480 481 if (crtc_state->hdmi_scrambling) 482 temp |= TRANS_DDI_HDMI_SCRAMBLING; 483 if (crtc_state->hdmi_high_tmds_clock_ratio) 484 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 485 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 486 temp |= TRANS_DDI_MODE_SELECT_FDI; 487 temp |= (crtc_state->fdi_lanes - 1) << 1; 488 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 489 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 490 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 491 492 if (DISPLAY_VER(dev_priv) >= 12) { 493 enum transcoder master; 494 495 master = crtc_state->mst_master_transcoder; 496 drm_WARN_ON(&dev_priv->drm, 497 master == INVALID_TRANSCODER); 498 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 499 } 500 } else { 501 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 502 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 503 } 504 505 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 506 crtc_state->master_transcoder != INVALID_TRANSCODER) { 507 u8 master_select = 508 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 509 510 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 511 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 512 } 513 514 return temp; 515 } 516 517 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 518 const struct intel_crtc_state *crtc_state) 519 { 520 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 521 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 522 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 523 524 if (DISPLAY_VER(dev_priv) >= 11) { 525 enum transcoder master_transcoder = crtc_state->master_transcoder; 526 u32 ctl2 = 0; 527 528 if (master_transcoder != INVALID_TRANSCODER) { 529 u8 master_select = 530 bdw_trans_port_sync_master_select(master_transcoder); 531 532 ctl2 |= PORT_SYNC_MODE_ENABLE | 533 PORT_SYNC_MODE_MASTER_SELECT(master_select); 534 } 535 536 intel_de_write(dev_priv, 537 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 538 } 539 540 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 541 intel_ddi_transcoder_func_reg_val_get(encoder, 542 crtc_state)); 543 } 544 545 /* 546 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 547 * bit. 548 */ 549 static void 550 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 551 const struct intel_crtc_state *crtc_state) 552 { 553 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 554 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 555 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 556 u32 ctl; 557 558 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 559 ctl &= ~TRANS_DDI_FUNC_ENABLE; 560 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 561 } 562 563 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 564 { 565 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 566 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 567 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 568 u32 ctl; 569 570 if (DISPLAY_VER(dev_priv) >= 11) 571 intel_de_write(dev_priv, 572 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 573 574 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 575 576 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 577 578 ctl &= ~TRANS_DDI_FUNC_ENABLE; 579 580 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 581 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 582 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 583 584 if (DISPLAY_VER(dev_priv) >= 12) { 585 if (!intel_dp_mst_is_master_trans(crtc_state)) { 586 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 587 TRANS_DDI_MODE_SELECT_MASK); 588 } 589 } else { 590 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 591 } 592 593 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 594 595 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && 596 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 597 drm_dbg_kms(&dev_priv->drm, 598 "Quirk Increase DDI disabled time\n"); 599 /* Quirk time at 100ms for reliable operation */ 600 msleep(100); 601 } 602 } 603 604 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 605 enum transcoder cpu_transcoder, 606 bool enable, u32 hdcp_mask) 607 { 608 struct drm_device *dev = intel_encoder->base.dev; 609 struct drm_i915_private *dev_priv = to_i915(dev); 610 intel_wakeref_t wakeref; 611 int ret = 0; 612 u32 tmp; 613 614 wakeref = intel_display_power_get_if_enabled(dev_priv, 615 intel_encoder->power_domain); 616 if (drm_WARN_ON(dev, !wakeref)) 617 return -ENXIO; 618 619 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 620 if (enable) 621 tmp |= hdcp_mask; 622 else 623 tmp &= ~hdcp_mask; 624 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp); 625 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 626 return ret; 627 } 628 629 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 630 { 631 struct drm_device *dev = intel_connector->base.dev; 632 struct drm_i915_private *dev_priv = to_i915(dev); 633 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 634 int type = intel_connector->base.connector_type; 635 enum port port = encoder->port; 636 enum transcoder cpu_transcoder; 637 intel_wakeref_t wakeref; 638 enum pipe pipe = 0; 639 u32 tmp; 640 bool ret; 641 642 wakeref = intel_display_power_get_if_enabled(dev_priv, 643 encoder->power_domain); 644 if (!wakeref) 645 return false; 646 647 if (!encoder->get_hw_state(encoder, &pipe)) { 648 ret = false; 649 goto out; 650 } 651 652 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 653 cpu_transcoder = TRANSCODER_EDP; 654 else 655 cpu_transcoder = (enum transcoder) pipe; 656 657 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 658 659 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 660 case TRANS_DDI_MODE_SELECT_HDMI: 661 case TRANS_DDI_MODE_SELECT_DVI: 662 ret = type == DRM_MODE_CONNECTOR_HDMIA; 663 break; 664 665 case TRANS_DDI_MODE_SELECT_DP_SST: 666 ret = type == DRM_MODE_CONNECTOR_eDP || 667 type == DRM_MODE_CONNECTOR_DisplayPort; 668 break; 669 670 case TRANS_DDI_MODE_SELECT_DP_MST: 671 /* if the transcoder is in MST state then 672 * connector isn't connected */ 673 ret = false; 674 break; 675 676 case TRANS_DDI_MODE_SELECT_FDI: 677 ret = type == DRM_MODE_CONNECTOR_VGA; 678 break; 679 680 default: 681 ret = false; 682 break; 683 } 684 685 out: 686 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 687 688 return ret; 689 } 690 691 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 692 u8 *pipe_mask, bool *is_dp_mst) 693 { 694 struct drm_device *dev = encoder->base.dev; 695 struct drm_i915_private *dev_priv = to_i915(dev); 696 enum port port = encoder->port; 697 intel_wakeref_t wakeref; 698 enum pipe p; 699 u32 tmp; 700 u8 mst_pipe_mask; 701 702 *pipe_mask = 0; 703 *is_dp_mst = false; 704 705 wakeref = intel_display_power_get_if_enabled(dev_priv, 706 encoder->power_domain); 707 if (!wakeref) 708 return; 709 710 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 711 if (!(tmp & DDI_BUF_CTL_ENABLE)) 712 goto out; 713 714 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 715 tmp = intel_de_read(dev_priv, 716 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 717 718 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 719 default: 720 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 721 fallthrough; 722 case TRANS_DDI_EDP_INPUT_A_ON: 723 case TRANS_DDI_EDP_INPUT_A_ONOFF: 724 *pipe_mask = BIT(PIPE_A); 725 break; 726 case TRANS_DDI_EDP_INPUT_B_ONOFF: 727 *pipe_mask = BIT(PIPE_B); 728 break; 729 case TRANS_DDI_EDP_INPUT_C_ONOFF: 730 *pipe_mask = BIT(PIPE_C); 731 break; 732 } 733 734 goto out; 735 } 736 737 mst_pipe_mask = 0; 738 for_each_pipe(dev_priv, p) { 739 enum transcoder cpu_transcoder = (enum transcoder)p; 740 unsigned int port_mask, ddi_select; 741 intel_wakeref_t trans_wakeref; 742 743 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 744 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 745 if (!trans_wakeref) 746 continue; 747 748 if (DISPLAY_VER(dev_priv) >= 12) { 749 port_mask = TGL_TRANS_DDI_PORT_MASK; 750 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 751 } else { 752 port_mask = TRANS_DDI_PORT_MASK; 753 ddi_select = TRANS_DDI_SELECT_PORT(port); 754 } 755 756 tmp = intel_de_read(dev_priv, 757 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 758 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 759 trans_wakeref); 760 761 if ((tmp & port_mask) != ddi_select) 762 continue; 763 764 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == 765 TRANS_DDI_MODE_SELECT_DP_MST) 766 mst_pipe_mask |= BIT(p); 767 768 *pipe_mask |= BIT(p); 769 } 770 771 if (!*pipe_mask) 772 drm_dbg_kms(&dev_priv->drm, 773 "No pipe for [ENCODER:%d:%s] found\n", 774 encoder->base.base.id, encoder->base.name); 775 776 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 777 drm_dbg_kms(&dev_priv->drm, 778 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 779 encoder->base.base.id, encoder->base.name, 780 *pipe_mask); 781 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 782 } 783 784 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 785 drm_dbg_kms(&dev_priv->drm, 786 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 787 encoder->base.base.id, encoder->base.name, 788 *pipe_mask, mst_pipe_mask); 789 else 790 *is_dp_mst = mst_pipe_mask; 791 792 out: 793 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 794 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 795 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 796 BXT_PHY_LANE_POWERDOWN_ACK | 797 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 798 drm_err(&dev_priv->drm, 799 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 800 encoder->base.base.id, encoder->base.name, tmp); 801 } 802 803 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 804 } 805 806 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 807 enum pipe *pipe) 808 { 809 u8 pipe_mask; 810 bool is_mst; 811 812 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 813 814 if (is_mst || !pipe_mask) 815 return false; 816 817 *pipe = ffs(pipe_mask) - 1; 818 819 return true; 820 } 821 822 static enum intel_display_power_domain 823 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 824 { 825 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with 826 * DC states enabled at the same time, while for driver initiated AUX 827 * transfers we need the same AUX IOs to be powered but with DC states 828 * disabled. Accordingly use the AUX power domain here which leaves DC 829 * states enabled. 830 * However, for non-A AUX ports the corresponding non-EDP transcoders 831 * would have already enabled power well 2 and DC_OFF. This means we can 832 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a 833 * specific AUX_IO reference without powering up any extra wells. 834 * Note that PSR is enabled only on Port A even though this function 835 * returns the correct domain for other ports too. 836 */ 837 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : 838 intel_aux_power_domain(dig_port); 839 } 840 841 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 842 struct intel_crtc_state *crtc_state) 843 { 844 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 845 struct intel_digital_port *dig_port; 846 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 847 848 /* 849 * TODO: Add support for MST encoders. Atm, the following should never 850 * happen since fake-MST encoders don't set their get_power_domains() 851 * hook. 852 */ 853 if (drm_WARN_ON(&dev_priv->drm, 854 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 855 return; 856 857 dig_port = enc_to_dig_port(encoder); 858 859 if (!intel_phy_is_tc(dev_priv, phy) || 860 dig_port->tc_mode != TC_PORT_TBT_ALT) { 861 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 862 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 863 dig_port->ddi_io_power_domain); 864 } 865 866 /* 867 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC 868 * ports. 869 */ 870 if (intel_crtc_has_dp_encoder(crtc_state) || 871 intel_phy_is_tc(dev_priv, phy)) { 872 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 873 dig_port->aux_wakeref = 874 intel_display_power_get(dev_priv, 875 intel_ddi_main_link_aux_domain(dig_port)); 876 } 877 } 878 879 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 880 const struct intel_crtc_state *crtc_state) 881 { 882 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 883 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 884 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 885 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 886 u32 val; 887 888 if (cpu_transcoder != TRANSCODER_EDP) { 889 if (DISPLAY_VER(dev_priv) >= 13) 890 val = TGL_TRANS_CLK_SEL_PORT(phy); 891 else if (DISPLAY_VER(dev_priv) >= 12) 892 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 893 else 894 val = TRANS_CLK_SEL_PORT(encoder->port); 895 896 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 897 } 898 } 899 900 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) 901 { 902 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 903 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 904 905 if (cpu_transcoder != TRANSCODER_EDP) { 906 if (DISPLAY_VER(dev_priv) >= 12) 907 intel_de_write(dev_priv, 908 TRANS_CLK_SEL(cpu_transcoder), 909 TGL_TRANS_CLK_SEL_DISABLED); 910 else 911 intel_de_write(dev_priv, 912 TRANS_CLK_SEL(cpu_transcoder), 913 TRANS_CLK_SEL_DISABLED); 914 } 915 } 916 917 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 918 enum port port, u8 iboost) 919 { 920 u32 tmp; 921 922 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 923 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 924 if (iboost) 925 tmp |= iboost << BALANCE_LEG_SHIFT(port); 926 else 927 tmp |= BALANCE_LEG_DISABLE(port); 928 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 929 } 930 931 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 932 const struct intel_crtc_state *crtc_state, 933 int level) 934 { 935 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 936 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 937 u8 iboost; 938 939 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 940 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); 941 else 942 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); 943 944 if (iboost == 0) { 945 const struct intel_ddi_buf_trans *ddi_translations; 946 int n_entries; 947 948 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 949 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 950 return; 951 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 952 level = n_entries - 1; 953 954 iboost = ddi_translations->entries[level].hsw.i_boost; 955 } 956 957 /* Make sure that the requested I_boost is valid */ 958 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 959 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 960 return; 961 } 962 963 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 964 965 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 966 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 967 } 968 969 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, 970 const struct intel_crtc_state *crtc_state, 971 int level) 972 { 973 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 974 const struct intel_ddi_buf_trans *ddi_translations; 975 enum port port = encoder->port; 976 int n_entries; 977 978 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 979 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 980 return; 981 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 982 level = n_entries - 1; 983 984 bxt_ddi_phy_set_signal_level(dev_priv, port, 985 ddi_translations->entries[level].bxt.margin, 986 ddi_translations->entries[level].bxt.scale, 987 ddi_translations->entries[level].bxt.enable, 988 ddi_translations->entries[level].bxt.deemphasis); 989 } 990 991 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 992 const struct intel_crtc_state *crtc_state) 993 { 994 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 996 int n_entries; 997 998 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 999 1000 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1001 n_entries = 1; 1002 if (drm_WARN_ON(&dev_priv->drm, 1003 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1004 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1005 1006 return index_to_dp_signal_levels[n_entries - 1] & 1007 DP_TRAIN_VOLTAGE_SWING_MASK; 1008 } 1009 1010 /* 1011 * We assume that the full set of pre-emphasis values can be 1012 * used on all DDI platforms. Should that change we need to 1013 * rethink this code. 1014 */ 1015 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1016 { 1017 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1018 } 1019 1020 static void cnl_ddi_vswing_program(struct intel_encoder *encoder, 1021 const struct intel_crtc_state *crtc_state, 1022 int level) 1023 { 1024 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1025 const struct intel_ddi_buf_trans *ddi_translations; 1026 enum port port = encoder->port; 1027 int n_entries, ln; 1028 u32 val; 1029 1030 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1031 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1032 return; 1033 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1034 level = n_entries - 1; 1035 1036 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ 1037 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1038 val &= ~SCALING_MODE_SEL_MASK; 1039 val |= SCALING_MODE_SEL(2); 1040 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1041 1042 /* Program PORT_TX_DW2 */ 1043 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); 1044 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 1045 RCOMP_SCALAR_MASK); 1046 val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel); 1047 val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel); 1048 /* Rcomp scalar is fixed as 0x98 for every table entry */ 1049 val |= RCOMP_SCALAR(0x98); 1050 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); 1051 1052 /* Program PORT_TX_DW4 */ 1053 /* We cannot write to GRP. It would overrite individual loadgen */ 1054 for (ln = 0; ln < 4; ln++) { 1055 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 1056 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 1057 CURSOR_COEFF_MASK); 1058 val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1); 1059 val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2); 1060 val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff); 1061 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 1062 } 1063 1064 /* Program PORT_TX_DW5 */ 1065 /* All DW5 values are fixed for every table entry */ 1066 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1067 val &= ~RTERM_SELECT_MASK; 1068 val |= RTERM_SELECT(6); 1069 val |= TAP3_DISABLE; 1070 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1071 1072 /* Program PORT_TX_DW7 */ 1073 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); 1074 val &= ~N_SCALAR_MASK; 1075 val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar); 1076 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); 1077 } 1078 1079 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, 1080 const struct intel_crtc_state *crtc_state, 1081 int level) 1082 { 1083 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1084 enum port port = encoder->port; 1085 int width, rate, ln; 1086 u32 val; 1087 1088 width = crtc_state->lane_count; 1089 rate = crtc_state->port_clock; 1090 1091 /* 1092 * 1. If port type is eDP or DP, 1093 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1094 * else clear to 0b. 1095 */ 1096 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); 1097 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1098 val &= ~COMMON_KEEPER_EN; 1099 else 1100 val |= COMMON_KEEPER_EN; 1101 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); 1102 1103 /* 2. Program loadgen select */ 1104 /* 1105 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 1106 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1107 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1108 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1109 */ 1110 for (ln = 0; ln <= 3; ln++) { 1111 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); 1112 val &= ~LOADGEN_SELECT; 1113 1114 if ((rate <= 600000 && width == 4 && ln >= 1) || 1115 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 1116 val |= LOADGEN_SELECT; 1117 } 1118 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); 1119 } 1120 1121 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1122 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 1123 val |= SUS_CLOCK_CONFIG; 1124 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 1125 1126 /* 4. Clear training enable to change swing values */ 1127 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1128 val &= ~TX_TRAINING_EN; 1129 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1130 1131 /* 5. Program swing and de-emphasis */ 1132 cnl_ddi_vswing_program(encoder, crtc_state, level); 1133 1134 /* 6. Set training enable to trigger update */ 1135 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); 1136 val |= TX_TRAINING_EN; 1137 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); 1138 } 1139 1140 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1141 const struct intel_crtc_state *crtc_state, 1142 int level) 1143 { 1144 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1145 const struct intel_ddi_buf_trans *ddi_translations; 1146 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1147 int n_entries, ln; 1148 u32 val; 1149 1150 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1151 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1152 return; 1153 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1154 level = n_entries - 1; 1155 1156 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1157 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1158 1159 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1160 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations); 1161 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1162 intel_dp->hobl_active ? val : 0); 1163 } 1164 1165 /* Set PORT_TX_DW5 */ 1166 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1167 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1168 TAP2_DISABLE | TAP3_DISABLE); 1169 val |= SCALING_MODE_SEL(0x2); 1170 val |= RTERM_SELECT(0x6); 1171 val |= TAP3_DISABLE; 1172 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1173 1174 /* Program PORT_TX_DW2 */ 1175 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 1176 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 1177 RCOMP_SCALAR_MASK); 1178 val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel); 1179 val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel); 1180 /* Program Rcomp scalar for every table entry */ 1181 val |= RCOMP_SCALAR(0x98); 1182 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); 1183 1184 /* Program PORT_TX_DW4 */ 1185 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1186 for (ln = 0; ln <= 3; ln++) { 1187 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 1188 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 1189 CURSOR_COEFF_MASK); 1190 val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1); 1191 val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2); 1192 val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff); 1193 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 1194 } 1195 1196 /* Program PORT_TX_DW7 */ 1197 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); 1198 val &= ~N_SCALAR_MASK; 1199 val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar); 1200 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); 1201 } 1202 1203 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1204 const struct intel_crtc_state *crtc_state, 1205 int level) 1206 { 1207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1208 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1209 int width, rate, ln; 1210 u32 val; 1211 1212 width = crtc_state->lane_count; 1213 rate = crtc_state->port_clock; 1214 1215 /* 1216 * 1. If port type is eDP or DP, 1217 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1218 * else clear to 0b. 1219 */ 1220 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 1221 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1222 val &= ~COMMON_KEEPER_EN; 1223 else 1224 val |= COMMON_KEEPER_EN; 1225 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1226 1227 /* 2. Program loadgen select */ 1228 /* 1229 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes 1230 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1231 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1232 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1233 */ 1234 for (ln = 0; ln <= 3; ln++) { 1235 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); 1236 val &= ~LOADGEN_SELECT; 1237 1238 if ((rate <= 600000 && width == 4 && ln >= 1) || 1239 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { 1240 val |= LOADGEN_SELECT; 1241 } 1242 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); 1243 } 1244 1245 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1246 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 1247 val |= SUS_CLOCK_CONFIG; 1248 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 1249 1250 /* 4. Clear training enable to change swing values */ 1251 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1252 val &= ~TX_TRAINING_EN; 1253 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1254 1255 /* 5. Program swing and de-emphasis */ 1256 icl_ddi_combo_vswing_program(encoder, crtc_state, level); 1257 1258 /* 6. Set training enable to trigger update */ 1259 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 1260 val |= TX_TRAINING_EN; 1261 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1262 } 1263 1264 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1265 const struct intel_crtc_state *crtc_state, 1266 int level) 1267 { 1268 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1269 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1270 const struct intel_ddi_buf_trans *ddi_translations; 1271 int n_entries, ln; 1272 u32 val; 1273 1274 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 1275 return; 1276 1277 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1278 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1279 return; 1280 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1281 level = n_entries - 1; 1282 1283 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ 1284 for (ln = 0; ln < 2; ln++) { 1285 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); 1286 val &= ~CRI_USE_FS32; 1287 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); 1288 1289 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); 1290 val &= ~CRI_USE_FS32; 1291 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); 1292 } 1293 1294 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1295 for (ln = 0; ln < 2; ln++) { 1296 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); 1297 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 1298 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 1299 ddi_translations->entries[level].mg.cri_txdeemph_override_17_12); 1300 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); 1301 1302 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); 1303 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; 1304 val |= CRI_TXDEEMPH_OVERRIDE_17_12( 1305 ddi_translations->entries[level].mg.cri_txdeemph_override_17_12); 1306 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); 1307 } 1308 1309 /* Program MG_TX_DRVCTRL with values from vswing table */ 1310 for (ln = 0; ln < 2; ln++) { 1311 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); 1312 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1313 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 1314 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 1315 ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) | 1316 CRI_TXDEEMPH_OVERRIDE_11_6( 1317 ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) | 1318 CRI_TXDEEMPH_OVERRIDE_EN; 1319 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); 1320 1321 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); 1322 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1323 CRI_TXDEEMPH_OVERRIDE_5_0_MASK); 1324 val |= CRI_TXDEEMPH_OVERRIDE_5_0( 1325 ddi_translations->entries[level].mg.cri_txdeemph_override_5_0) | 1326 CRI_TXDEEMPH_OVERRIDE_11_6( 1327 ddi_translations->entries[level].mg.cri_txdeemph_override_11_6) | 1328 CRI_TXDEEMPH_OVERRIDE_EN; 1329 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); 1330 1331 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1332 } 1333 1334 /* 1335 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1336 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1337 * values from table for which TX1 and TX2 enabled. 1338 */ 1339 for (ln = 0; ln < 2; ln++) { 1340 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); 1341 if (crtc_state->port_clock < 300000) 1342 val |= CFG_LOW_RATE_LKREN_EN; 1343 else 1344 val &= ~CFG_LOW_RATE_LKREN_EN; 1345 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); 1346 } 1347 1348 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1349 for (ln = 0; ln < 2; ln++) { 1350 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); 1351 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 1352 if (crtc_state->port_clock <= 500000) { 1353 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 1354 } else { 1355 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 1356 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 1357 } 1358 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); 1359 1360 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); 1361 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; 1362 if (crtc_state->port_clock <= 500000) { 1363 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; 1364 } else { 1365 val |= CFG_AMI_CK_DIV_OVERRIDE_EN | 1366 CFG_AMI_CK_DIV_OVERRIDE_VAL(1); 1367 } 1368 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); 1369 } 1370 1371 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1372 for (ln = 0; ln < 2; ln++) { 1373 val = intel_de_read(dev_priv, 1374 MG_TX1_PISO_READLOAD(ln, tc_port)); 1375 val |= CRI_CALCINIT; 1376 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1377 val); 1378 1379 val = intel_de_read(dev_priv, 1380 MG_TX2_PISO_READLOAD(ln, tc_port)); 1381 val |= CRI_CALCINIT; 1382 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1383 val); 1384 } 1385 } 1386 1387 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, 1388 const struct intel_crtc_state *crtc_state, 1389 int level) 1390 { 1391 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1392 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1393 1394 if (intel_phy_is_combo(dev_priv, phy)) 1395 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1396 else 1397 icl_mg_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1398 } 1399 1400 static void 1401 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, 1402 const struct intel_crtc_state *crtc_state, 1403 int level) 1404 { 1405 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1406 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); 1407 const struct intel_ddi_buf_trans *ddi_translations; 1408 u32 val, dpcnt_mask, dpcnt_val; 1409 int n_entries, ln; 1410 1411 if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT) 1412 return; 1413 1414 ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1415 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) 1416 return; 1417 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) 1418 level = n_entries - 1; 1419 1420 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK | 1421 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1422 DKL_TX_VSWING_CONTROL_MASK); 1423 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations->entries[level].dkl.dkl_vswing_control); 1424 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations->entries[level].dkl.dkl_de_emphasis_control); 1425 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations->entries[level].dkl.dkl_preshoot_control); 1426 1427 for (ln = 0; ln < 2; ln++) { 1428 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 1429 HIP_INDEX_VAL(tc_port, ln)); 1430 1431 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); 1432 1433 /* All the registers are RMW */ 1434 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); 1435 val &= ~dpcnt_mask; 1436 val |= dpcnt_val; 1437 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); 1438 1439 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); 1440 val &= ~dpcnt_mask; 1441 val |= dpcnt_val; 1442 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); 1443 1444 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); 1445 val &= ~DKL_TX_DP20BITMODE; 1446 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); 1447 1448 if ((intel_crtc_has_dp_encoder(crtc_state) && 1449 crtc_state->port_clock == 162000) || 1450 (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 1451 crtc_state->port_clock == 594000)) 1452 val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE; 1453 else 1454 val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE; 1455 } 1456 } 1457 1458 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder, 1459 const struct intel_crtc_state *crtc_state, 1460 int level) 1461 { 1462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1463 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 1464 1465 if (intel_phy_is_combo(dev_priv, phy)) 1466 icl_combo_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1467 else 1468 tgl_dkl_phy_ddi_vswing_sequence(encoder, crtc_state, level); 1469 } 1470 1471 static int translate_signal_level(struct intel_dp *intel_dp, 1472 u8 signal_levels) 1473 { 1474 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1475 int i; 1476 1477 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1478 if (index_to_dp_signal_levels[i] == signal_levels) 1479 return i; 1480 } 1481 1482 drm_WARN(&i915->drm, 1, 1483 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1484 signal_levels); 1485 1486 return 0; 1487 } 1488 1489 static int intel_ddi_dp_level(struct intel_dp *intel_dp) 1490 { 1491 u8 train_set = intel_dp->train_set[0]; 1492 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1493 DP_TRAIN_PRE_EMPHASIS_MASK); 1494 1495 return translate_signal_level(intel_dp, signal_levels); 1496 } 1497 1498 static void 1499 tgl_set_signal_levels(struct intel_dp *intel_dp, 1500 const struct intel_crtc_state *crtc_state) 1501 { 1502 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1503 int level = intel_ddi_dp_level(intel_dp); 1504 1505 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 1506 } 1507 1508 static void 1509 icl_set_signal_levels(struct intel_dp *intel_dp, 1510 const struct intel_crtc_state *crtc_state) 1511 { 1512 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1513 int level = intel_ddi_dp_level(intel_dp); 1514 1515 icl_ddi_vswing_sequence(encoder, crtc_state, level); 1516 } 1517 1518 static void 1519 cnl_set_signal_levels(struct intel_dp *intel_dp, 1520 const struct intel_crtc_state *crtc_state) 1521 { 1522 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1523 int level = intel_ddi_dp_level(intel_dp); 1524 1525 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 1526 } 1527 1528 static void 1529 bxt_set_signal_levels(struct intel_dp *intel_dp, 1530 const struct intel_crtc_state *crtc_state) 1531 { 1532 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1533 int level = intel_ddi_dp_level(intel_dp); 1534 1535 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 1536 } 1537 1538 static void 1539 hsw_set_signal_levels(struct intel_dp *intel_dp, 1540 const struct intel_crtc_state *crtc_state) 1541 { 1542 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1543 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1544 int level = intel_ddi_dp_level(intel_dp); 1545 enum port port = encoder->port; 1546 u32 signal_levels; 1547 1548 signal_levels = DDI_BUF_TRANS_SELECT(level); 1549 1550 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1551 signal_levels); 1552 1553 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1554 intel_dp->DP |= signal_levels; 1555 1556 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 1557 skl_ddi_set_iboost(encoder, crtc_state, level); 1558 1559 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1560 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1561 } 1562 1563 static void _cnl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1564 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1565 { 1566 mutex_lock(&i915->dpll.lock); 1567 1568 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1569 1570 /* 1571 * "This step and the step before must be 1572 * done with separate register writes." 1573 */ 1574 intel_de_rmw(i915, reg, clk_off, 0); 1575 1576 mutex_unlock(&i915->dpll.lock); 1577 } 1578 1579 static void _cnl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1580 u32 clk_off) 1581 { 1582 mutex_lock(&i915->dpll.lock); 1583 1584 intel_de_rmw(i915, reg, 0, clk_off); 1585 1586 mutex_unlock(&i915->dpll.lock); 1587 } 1588 1589 static bool _cnl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1590 u32 clk_off) 1591 { 1592 return !(intel_de_read(i915, reg) & clk_off); 1593 } 1594 1595 static struct intel_shared_dpll * 1596 _cnl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1597 u32 clk_sel_mask, u32 clk_sel_shift) 1598 { 1599 enum intel_dpll_id id; 1600 1601 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1602 1603 return intel_get_shared_dpll_by_id(i915, id); 1604 } 1605 1606 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1607 const struct intel_crtc_state *crtc_state) 1608 { 1609 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1610 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1611 enum phy phy = intel_port_to_phy(i915, encoder->port); 1612 1613 if (drm_WARN_ON(&i915->drm, !pll)) 1614 return; 1615 1616 _cnl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1617 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1618 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1619 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1620 } 1621 1622 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1623 { 1624 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1625 enum phy phy = intel_port_to_phy(i915, encoder->port); 1626 1627 _cnl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1628 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1629 } 1630 1631 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1632 { 1633 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1634 enum phy phy = intel_port_to_phy(i915, encoder->port); 1635 1636 return _cnl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1637 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1638 } 1639 1640 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1641 { 1642 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1643 enum phy phy = intel_port_to_phy(i915, encoder->port); 1644 1645 return _cnl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1646 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1647 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1648 } 1649 1650 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1651 const struct intel_crtc_state *crtc_state) 1652 { 1653 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1654 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1655 enum phy phy = intel_port_to_phy(i915, encoder->port); 1656 1657 if (drm_WARN_ON(&i915->drm, !pll)) 1658 return; 1659 1660 _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1661 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1662 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1663 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1664 } 1665 1666 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1667 { 1668 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1669 enum phy phy = intel_port_to_phy(i915, encoder->port); 1670 1671 _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1672 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1673 } 1674 1675 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1676 { 1677 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1678 enum phy phy = intel_port_to_phy(i915, encoder->port); 1679 1680 return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1681 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1682 } 1683 1684 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1685 { 1686 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1687 enum phy phy = intel_port_to_phy(i915, encoder->port); 1688 1689 return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1690 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1691 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1692 } 1693 1694 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1695 const struct intel_crtc_state *crtc_state) 1696 { 1697 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1698 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1699 enum phy phy = intel_port_to_phy(i915, encoder->port); 1700 1701 if (drm_WARN_ON(&i915->drm, !pll)) 1702 return; 1703 1704 /* 1705 * If we fail this, something went very wrong: first 2 PLLs should be 1706 * used by first 2 phys and last 2 PLLs by last phys 1707 */ 1708 if (drm_WARN_ON(&i915->drm, 1709 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1710 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1711 return; 1712 1713 _cnl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1714 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1715 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1716 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1717 } 1718 1719 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1720 { 1721 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1722 enum phy phy = intel_port_to_phy(i915, encoder->port); 1723 1724 _cnl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1725 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1726 } 1727 1728 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1729 { 1730 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1731 enum phy phy = intel_port_to_phy(i915, encoder->port); 1732 1733 return _cnl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1734 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1735 } 1736 1737 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1738 { 1739 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1740 enum phy phy = intel_port_to_phy(i915, encoder->port); 1741 enum intel_dpll_id id; 1742 u32 val; 1743 1744 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1745 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1746 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1747 id = val; 1748 1749 /* 1750 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1751 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1752 * bit for phy C and D. 1753 */ 1754 if (phy >= PHY_C) 1755 id += DPLL_ID_DG1_DPLL2; 1756 1757 return intel_get_shared_dpll_by_id(i915, id); 1758 } 1759 1760 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1761 const struct intel_crtc_state *crtc_state) 1762 { 1763 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1764 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1765 enum phy phy = intel_port_to_phy(i915, encoder->port); 1766 1767 if (drm_WARN_ON(&i915->drm, !pll)) 1768 return; 1769 1770 _cnl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1771 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1772 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1773 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1774 } 1775 1776 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1777 { 1778 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1779 enum phy phy = intel_port_to_phy(i915, encoder->port); 1780 1781 _cnl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1782 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1783 } 1784 1785 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1786 { 1787 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1788 enum phy phy = intel_port_to_phy(i915, encoder->port); 1789 1790 return _cnl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1791 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1792 } 1793 1794 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1795 { 1796 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1797 enum phy phy = intel_port_to_phy(i915, encoder->port); 1798 1799 return _cnl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1800 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1801 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1802 } 1803 1804 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1805 const struct intel_crtc_state *crtc_state) 1806 { 1807 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1808 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1809 enum port port = encoder->port; 1810 1811 if (drm_WARN_ON(&i915->drm, !pll)) 1812 return; 1813 1814 /* 1815 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1816 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1817 */ 1818 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1819 1820 icl_ddi_combo_enable_clock(encoder, crtc_state); 1821 } 1822 1823 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1824 { 1825 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1826 enum port port = encoder->port; 1827 1828 icl_ddi_combo_disable_clock(encoder); 1829 1830 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1831 } 1832 1833 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1834 { 1835 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1836 enum port port = encoder->port; 1837 u32 tmp; 1838 1839 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1840 1841 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1842 return false; 1843 1844 return icl_ddi_combo_is_clock_enabled(encoder); 1845 } 1846 1847 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1848 const struct intel_crtc_state *crtc_state) 1849 { 1850 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1851 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1852 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1853 enum port port = encoder->port; 1854 1855 if (drm_WARN_ON(&i915->drm, !pll)) 1856 return; 1857 1858 intel_de_write(i915, DDI_CLK_SEL(port), 1859 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1860 1861 mutex_lock(&i915->dpll.lock); 1862 1863 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1864 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1865 1866 mutex_unlock(&i915->dpll.lock); 1867 } 1868 1869 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1870 { 1871 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1872 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1873 enum port port = encoder->port; 1874 1875 mutex_lock(&i915->dpll.lock); 1876 1877 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1878 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1879 1880 mutex_unlock(&i915->dpll.lock); 1881 1882 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1883 } 1884 1885 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1886 { 1887 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1888 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1889 enum port port = encoder->port; 1890 u32 tmp; 1891 1892 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1893 1894 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1895 return false; 1896 1897 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1898 1899 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1900 } 1901 1902 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1903 { 1904 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1905 enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); 1906 enum port port = encoder->port; 1907 enum intel_dpll_id id; 1908 u32 tmp; 1909 1910 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1911 1912 switch (tmp & DDI_CLK_SEL_MASK) { 1913 case DDI_CLK_SEL_TBT_162: 1914 case DDI_CLK_SEL_TBT_270: 1915 case DDI_CLK_SEL_TBT_540: 1916 case DDI_CLK_SEL_TBT_810: 1917 id = DPLL_ID_ICL_TBTPLL; 1918 break; 1919 case DDI_CLK_SEL_MG: 1920 id = icl_tc_port_to_pll_id(tc_port); 1921 break; 1922 default: 1923 MISSING_CASE(tmp); 1924 fallthrough; 1925 case DDI_CLK_SEL_NONE: 1926 return NULL; 1927 } 1928 1929 return intel_get_shared_dpll_by_id(i915, id); 1930 } 1931 1932 static void cnl_ddi_enable_clock(struct intel_encoder *encoder, 1933 const struct intel_crtc_state *crtc_state) 1934 { 1935 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1936 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1937 enum port port = encoder->port; 1938 1939 if (drm_WARN_ON(&i915->drm, !pll)) 1940 return; 1941 1942 _cnl_ddi_enable_clock(i915, DPCLKA_CFGCR0, 1943 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), 1944 DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port), 1945 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 1946 } 1947 1948 static void cnl_ddi_disable_clock(struct intel_encoder *encoder) 1949 { 1950 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1951 enum port port = encoder->port; 1952 1953 _cnl_ddi_disable_clock(i915, DPCLKA_CFGCR0, 1954 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 1955 } 1956 1957 static bool cnl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1958 { 1959 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1960 enum port port = encoder->port; 1961 1962 return _cnl_ddi_is_clock_enabled(i915, DPCLKA_CFGCR0, 1963 DPCLKA_CFGCR0_DDI_CLK_OFF(port)); 1964 } 1965 1966 static struct intel_shared_dpll *cnl_ddi_get_pll(struct intel_encoder *encoder) 1967 { 1968 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1969 enum port port = encoder->port; 1970 1971 return _cnl_ddi_get_pll(i915, DPCLKA_CFGCR0, 1972 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port), 1973 DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)); 1974 } 1975 1976 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1977 { 1978 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1979 enum intel_dpll_id id; 1980 1981 switch (encoder->port) { 1982 case PORT_A: 1983 id = DPLL_ID_SKL_DPLL0; 1984 break; 1985 case PORT_B: 1986 id = DPLL_ID_SKL_DPLL1; 1987 break; 1988 case PORT_C: 1989 id = DPLL_ID_SKL_DPLL2; 1990 break; 1991 default: 1992 MISSING_CASE(encoder->port); 1993 return NULL; 1994 } 1995 1996 return intel_get_shared_dpll_by_id(i915, id); 1997 } 1998 1999 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 2000 const struct intel_crtc_state *crtc_state) 2001 { 2002 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2003 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2004 enum port port = encoder->port; 2005 2006 if (drm_WARN_ON(&i915->drm, !pll)) 2007 return; 2008 2009 mutex_lock(&i915->dpll.lock); 2010 2011 intel_de_rmw(i915, DPLL_CTRL2, 2012 DPLL_CTRL2_DDI_CLK_OFF(port) | 2013 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 2014 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 2015 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2016 2017 mutex_unlock(&i915->dpll.lock); 2018 } 2019 2020 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 2021 { 2022 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2023 enum port port = encoder->port; 2024 2025 mutex_lock(&i915->dpll.lock); 2026 2027 intel_de_rmw(i915, DPLL_CTRL2, 2028 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 2029 2030 mutex_unlock(&i915->dpll.lock); 2031 } 2032 2033 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 2034 { 2035 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2036 enum port port = encoder->port; 2037 2038 /* 2039 * FIXME Not sure if the override affects both 2040 * the PLL selection and the CLK_OFF bit. 2041 */ 2042 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 2043 } 2044 2045 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 2046 { 2047 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2048 enum port port = encoder->port; 2049 enum intel_dpll_id id; 2050 u32 tmp; 2051 2052 tmp = intel_de_read(i915, DPLL_CTRL2); 2053 2054 /* 2055 * FIXME Not sure if the override affects both 2056 * the PLL selection and the CLK_OFF bit. 2057 */ 2058 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 2059 return NULL; 2060 2061 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 2062 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 2063 2064 return intel_get_shared_dpll_by_id(i915, id); 2065 } 2066 2067 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 2068 const struct intel_crtc_state *crtc_state) 2069 { 2070 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2071 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 2072 enum port port = encoder->port; 2073 2074 if (drm_WARN_ON(&i915->drm, !pll)) 2075 return; 2076 2077 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 2078 } 2079 2080 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 2081 { 2082 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2083 enum port port = encoder->port; 2084 2085 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2086 } 2087 2088 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 2089 { 2090 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2091 enum port port = encoder->port; 2092 2093 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 2094 } 2095 2096 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 2097 { 2098 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2099 enum port port = encoder->port; 2100 enum intel_dpll_id id; 2101 u32 tmp; 2102 2103 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 2104 2105 switch (tmp & PORT_CLK_SEL_MASK) { 2106 case PORT_CLK_SEL_WRPLL1: 2107 id = DPLL_ID_WRPLL1; 2108 break; 2109 case PORT_CLK_SEL_WRPLL2: 2110 id = DPLL_ID_WRPLL2; 2111 break; 2112 case PORT_CLK_SEL_SPLL: 2113 id = DPLL_ID_SPLL; 2114 break; 2115 case PORT_CLK_SEL_LCPLL_810: 2116 id = DPLL_ID_LCPLL_810; 2117 break; 2118 case PORT_CLK_SEL_LCPLL_1350: 2119 id = DPLL_ID_LCPLL_1350; 2120 break; 2121 case PORT_CLK_SEL_LCPLL_2700: 2122 id = DPLL_ID_LCPLL_2700; 2123 break; 2124 default: 2125 MISSING_CASE(tmp); 2126 fallthrough; 2127 case PORT_CLK_SEL_NONE: 2128 return NULL; 2129 } 2130 2131 return intel_get_shared_dpll_by_id(i915, id); 2132 } 2133 2134 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2135 const struct intel_crtc_state *crtc_state) 2136 { 2137 if (encoder->enable_clock) 2138 encoder->enable_clock(encoder, crtc_state); 2139 } 2140 2141 static void intel_ddi_disable_clock(struct intel_encoder *encoder) 2142 { 2143 if (encoder->disable_clock) 2144 encoder->disable_clock(encoder); 2145 } 2146 2147 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2148 { 2149 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2150 u32 port_mask; 2151 bool ddi_clk_needed; 2152 2153 /* 2154 * In case of DP MST, we sanitize the primary encoder only, not the 2155 * virtual ones. 2156 */ 2157 if (encoder->type == INTEL_OUTPUT_DP_MST) 2158 return; 2159 2160 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2161 u8 pipe_mask; 2162 bool is_mst; 2163 2164 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2165 /* 2166 * In the unlikely case that BIOS enables DP in MST mode, just 2167 * warn since our MST HW readout is incomplete. 2168 */ 2169 if (drm_WARN_ON(&i915->drm, is_mst)) 2170 return; 2171 } 2172 2173 port_mask = BIT(encoder->port); 2174 ddi_clk_needed = encoder->base.crtc; 2175 2176 if (encoder->type == INTEL_OUTPUT_DSI) { 2177 struct intel_encoder *other_encoder; 2178 2179 port_mask = intel_dsi_encoder_ports(encoder); 2180 /* 2181 * Sanity check that we haven't incorrectly registered another 2182 * encoder using any of the ports of this DSI encoder. 2183 */ 2184 for_each_intel_encoder(&i915->drm, other_encoder) { 2185 if (other_encoder == encoder) 2186 continue; 2187 2188 if (drm_WARN_ON(&i915->drm, 2189 port_mask & BIT(other_encoder->port))) 2190 return; 2191 } 2192 /* 2193 * For DSI we keep the ddi clocks gated 2194 * except during enable/disable sequence. 2195 */ 2196 ddi_clk_needed = false; 2197 } 2198 2199 if (ddi_clk_needed || !encoder->disable_clock || 2200 !encoder->is_clock_enabled(encoder)) 2201 return; 2202 2203 drm_notice(&i915->drm, 2204 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2205 encoder->base.base.id, encoder->base.name); 2206 2207 encoder->disable_clock(encoder); 2208 } 2209 2210 static void 2211 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2212 const struct intel_crtc_state *crtc_state) 2213 { 2214 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2215 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); 2216 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 2217 u32 ln0, ln1, pin_assignment; 2218 u8 width; 2219 2220 if (!intel_phy_is_tc(dev_priv, phy) || 2221 dig_port->tc_mode == TC_PORT_TBT_ALT) 2222 return; 2223 2224 if (DISPLAY_VER(dev_priv) >= 12) { 2225 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2226 HIP_INDEX_VAL(tc_port, 0x0)); 2227 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2228 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2229 HIP_INDEX_VAL(tc_port, 0x1)); 2230 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); 2231 } else { 2232 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2233 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2234 } 2235 2236 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2237 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2238 2239 /* DPPATC */ 2240 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2241 width = crtc_state->lane_count; 2242 2243 switch (pin_assignment) { 2244 case 0x0: 2245 drm_WARN_ON(&dev_priv->drm, 2246 dig_port->tc_mode != TC_PORT_LEGACY); 2247 if (width == 1) { 2248 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2249 } else { 2250 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2251 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2252 } 2253 break; 2254 case 0x1: 2255 if (width == 4) { 2256 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2257 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2258 } 2259 break; 2260 case 0x2: 2261 if (width == 2) { 2262 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2263 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2264 } 2265 break; 2266 case 0x3: 2267 case 0x5: 2268 if (width == 1) { 2269 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2270 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2271 } else { 2272 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2273 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2274 } 2275 break; 2276 case 0x4: 2277 case 0x6: 2278 if (width == 1) { 2279 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2280 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2281 } else { 2282 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2283 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2284 } 2285 break; 2286 default: 2287 MISSING_CASE(pin_assignment); 2288 } 2289 2290 if (DISPLAY_VER(dev_priv) >= 12) { 2291 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2292 HIP_INDEX_VAL(tc_port, 0x0)); 2293 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); 2294 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), 2295 HIP_INDEX_VAL(tc_port, 0x1)); 2296 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); 2297 } else { 2298 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2299 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2300 } 2301 } 2302 2303 static enum transcoder 2304 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2305 { 2306 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2307 return crtc_state->mst_master_transcoder; 2308 else 2309 return crtc_state->cpu_transcoder; 2310 } 2311 2312 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2313 const struct intel_crtc_state *crtc_state) 2314 { 2315 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2316 2317 if (DISPLAY_VER(dev_priv) >= 12) 2318 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2319 else 2320 return DP_TP_CTL(encoder->port); 2321 } 2322 2323 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2324 const struct intel_crtc_state *crtc_state) 2325 { 2326 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2327 2328 if (DISPLAY_VER(dev_priv) >= 12) 2329 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2330 else 2331 return DP_TP_STATUS(encoder->port); 2332 } 2333 2334 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2335 const struct intel_crtc_state *crtc_state, 2336 bool enable) 2337 { 2338 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2339 2340 if (!crtc_state->vrr.enable) 2341 return; 2342 2343 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2344 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2345 drm_dbg_kms(&i915->drm, 2346 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2347 enabledisable(enable)); 2348 } 2349 2350 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2351 const struct intel_crtc_state *crtc_state) 2352 { 2353 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2354 2355 if (!crtc_state->fec_enable) 2356 return; 2357 2358 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0) 2359 drm_dbg_kms(&i915->drm, 2360 "Failed to set FEC_READY in the sink\n"); 2361 } 2362 2363 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2364 const struct intel_crtc_state *crtc_state) 2365 { 2366 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2367 struct intel_dp *intel_dp; 2368 u32 val; 2369 2370 if (!crtc_state->fec_enable) 2371 return; 2372 2373 intel_dp = enc_to_intel_dp(encoder); 2374 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2375 val |= DP_TP_CTL_FEC_ENABLE; 2376 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2377 } 2378 2379 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 2380 const struct intel_crtc_state *crtc_state) 2381 { 2382 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2383 struct intel_dp *intel_dp; 2384 u32 val; 2385 2386 if (!crtc_state->fec_enable) 2387 return; 2388 2389 intel_dp = enc_to_intel_dp(encoder); 2390 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2391 val &= ~DP_TP_CTL_FEC_ENABLE; 2392 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2393 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2394 } 2395 2396 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2397 const struct intel_crtc_state *crtc_state) 2398 { 2399 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2400 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2401 enum phy phy = intel_port_to_phy(i915, encoder->port); 2402 2403 if (intel_phy_is_combo(i915, phy)) { 2404 bool lane_reversal = 2405 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2406 2407 intel_combo_phy_power_up_lanes(i915, phy, false, 2408 crtc_state->lane_count, 2409 lane_reversal); 2410 } 2411 } 2412 2413 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2414 struct intel_crtc_state *pipe_config) 2415 { 2416 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2417 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2418 enum pipe pipe = crtc->pipe; 2419 u32 dss1; 2420 2421 if (!HAS_MSO(i915)) 2422 return; 2423 2424 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2425 2426 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2427 if (!pipe_config->splitter.enable) 2428 return; 2429 2430 /* Splitter enable is supported for pipe A only. */ 2431 if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) { 2432 pipe_config->splitter.enable = false; 2433 return; 2434 } 2435 2436 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2437 default: 2438 drm_WARN(&i915->drm, true, 2439 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2440 fallthrough; 2441 case SPLITTER_CONFIGURATION_2_SEGMENT: 2442 pipe_config->splitter.link_count = 2; 2443 break; 2444 case SPLITTER_CONFIGURATION_4_SEGMENT: 2445 pipe_config->splitter.link_count = 4; 2446 break; 2447 } 2448 2449 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2450 } 2451 2452 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2453 { 2454 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2455 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2456 enum pipe pipe = crtc->pipe; 2457 u32 dss1 = 0; 2458 2459 if (!HAS_MSO(i915)) 2460 return; 2461 2462 if (crtc_state->splitter.enable) { 2463 /* Splitter enable is supported for pipe A only. */ 2464 if (drm_WARN_ON(&i915->drm, pipe != PIPE_A)) 2465 return; 2466 2467 dss1 |= SPLITTER_ENABLE; 2468 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2469 if (crtc_state->splitter.link_count == 2) 2470 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2471 else 2472 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2473 } 2474 2475 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2476 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2477 OVERLAP_PIXELS_MASK, dss1); 2478 } 2479 2480 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2481 struct intel_encoder *encoder, 2482 const struct intel_crtc_state *crtc_state, 2483 const struct drm_connector_state *conn_state) 2484 { 2485 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2486 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2487 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2488 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2489 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2490 int level = intel_ddi_dp_level(intel_dp); 2491 2492 intel_dp_set_link_params(intel_dp, 2493 crtc_state->port_clock, 2494 crtc_state->lane_count); 2495 2496 /* 2497 * 1. Enable Power Wells 2498 * 2499 * This was handled at the beginning of intel_atomic_commit_tail(), 2500 * before we called down into this function. 2501 */ 2502 2503 /* 2. Enable Panel Power if PPS is required */ 2504 intel_pps_on(intel_dp); 2505 2506 /* 2507 * 3. For non-TBT Type-C ports, set FIA lane count 2508 * (DFLEXDPSP.DPX4TXLATC) 2509 * 2510 * This was done before tgl_ddi_pre_enable_dp by 2511 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2512 */ 2513 2514 /* 2515 * 4. Enable the port PLL. 2516 * 2517 * The PLL enabling itself was already done before this function by 2518 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2519 * configure the PLL to port mapping here. 2520 */ 2521 intel_ddi_enable_clock(encoder, crtc_state); 2522 2523 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2524 if (!intel_phy_is_tc(dev_priv, phy) || 2525 dig_port->tc_mode != TC_PORT_TBT_ALT) { 2526 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2527 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2528 dig_port->ddi_io_power_domain); 2529 } 2530 2531 /* 6. Program DP_MODE */ 2532 icl_program_mg_dp_mode(dig_port, crtc_state); 2533 2534 /* 2535 * 7. The rest of the below are substeps under the bspec's "Enable and 2536 * Train Display Port" step. Note that steps that are specific to 2537 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2538 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2539 * us when active_mst_links==0, so any steps designated for "single 2540 * stream or multi-stream master transcoder" can just be performed 2541 * unconditionally here. 2542 */ 2543 2544 /* 2545 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2546 * Transcoder. 2547 */ 2548 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2549 2550 /* 2551 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2552 * Transport Select 2553 */ 2554 intel_ddi_config_transcoder_func(encoder, crtc_state); 2555 2556 /* 2557 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2558 * selected 2559 * 2560 * This will be handled by the intel_dp_start_link_train() farther 2561 * down this function. 2562 */ 2563 2564 /* 7.e Configure voltage swing and related IO settings */ 2565 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 2566 2567 /* 2568 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2569 * the used lanes of the DDI. 2570 */ 2571 intel_ddi_power_up_lanes(encoder, crtc_state); 2572 2573 /* 2574 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2575 */ 2576 intel_ddi_mso_configure(crtc_state); 2577 2578 /* 2579 * 7.g Configure and enable DDI_BUF_CTL 2580 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout 2581 * after 500 us. 2582 * 2583 * We only configure what the register value will be here. Actual 2584 * enabling happens during link training farther down. 2585 */ 2586 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2587 2588 if (!is_mst) 2589 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2590 2591 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2592 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); 2593 /* 2594 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2595 * in the FEC_CONFIGURATION register to 1 before initiating link 2596 * training 2597 */ 2598 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2599 2600 intel_dp_check_frl_training(intel_dp); 2601 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2602 2603 /* 2604 * 7.i Follow DisplayPort specification training sequence (see notes for 2605 * failure handling) 2606 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2607 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2608 * (timeout after 800 us) 2609 */ 2610 intel_dp_start_link_train(intel_dp, crtc_state); 2611 2612 /* 7.k Set DP_TP_CTL link training to Normal */ 2613 if (!is_trans_port_sync_mode(crtc_state)) 2614 intel_dp_stop_link_train(intel_dp, crtc_state); 2615 2616 /* 7.l Configure and enable FEC if needed */ 2617 intel_ddi_enable_fec(encoder, crtc_state); 2618 if (!crtc_state->bigjoiner) 2619 intel_dsc_enable(encoder, crtc_state); 2620 } 2621 2622 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2623 struct intel_encoder *encoder, 2624 const struct intel_crtc_state *crtc_state, 2625 const struct drm_connector_state *conn_state) 2626 { 2627 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2628 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2629 enum port port = encoder->port; 2630 enum phy phy = intel_port_to_phy(dev_priv, port); 2631 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2632 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2633 int level = intel_ddi_dp_level(intel_dp); 2634 2635 if (DISPLAY_VER(dev_priv) < 11) 2636 drm_WARN_ON(&dev_priv->drm, 2637 is_mst && (port == PORT_A || port == PORT_E)); 2638 else 2639 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2640 2641 intel_dp_set_link_params(intel_dp, 2642 crtc_state->port_clock, 2643 crtc_state->lane_count); 2644 2645 intel_pps_on(intel_dp); 2646 2647 intel_ddi_enable_clock(encoder, crtc_state); 2648 2649 if (!intel_phy_is_tc(dev_priv, phy) || 2650 dig_port->tc_mode != TC_PORT_TBT_ALT) { 2651 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2652 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2653 dig_port->ddi_io_power_domain); 2654 } 2655 2656 icl_program_mg_dp_mode(dig_port, crtc_state); 2657 2658 if (DISPLAY_VER(dev_priv) >= 11) 2659 icl_ddi_vswing_sequence(encoder, crtc_state, level); 2660 else if (IS_CANNONLAKE(dev_priv)) 2661 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 2662 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2663 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 2664 else 2665 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2666 2667 intel_ddi_power_up_lanes(encoder, crtc_state); 2668 2669 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2670 if (!is_mst) 2671 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2672 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2673 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, 2674 true); 2675 intel_dp_sink_set_fec_ready(intel_dp, crtc_state); 2676 intel_dp_start_link_train(intel_dp, crtc_state); 2677 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2678 !is_trans_port_sync_mode(crtc_state)) 2679 intel_dp_stop_link_train(intel_dp, crtc_state); 2680 2681 intel_ddi_enable_fec(encoder, crtc_state); 2682 2683 if (!is_mst) 2684 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2685 2686 if (!crtc_state->bigjoiner) 2687 intel_dsc_enable(encoder, crtc_state); 2688 } 2689 2690 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2691 struct intel_encoder *encoder, 2692 const struct intel_crtc_state *crtc_state, 2693 const struct drm_connector_state *conn_state) 2694 { 2695 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2696 2697 if (DISPLAY_VER(dev_priv) >= 12) 2698 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2699 else 2700 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2701 2702 /* MST will call a setting of MSA after an allocating of Virtual Channel 2703 * from MST encoder pre_enable callback. 2704 */ 2705 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 2706 intel_ddi_set_dp_msa(crtc_state, conn_state); 2707 2708 intel_dp_set_m_n(crtc_state, M1_N1); 2709 } 2710 } 2711 2712 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2713 struct intel_encoder *encoder, 2714 const struct intel_crtc_state *crtc_state, 2715 const struct drm_connector_state *conn_state) 2716 { 2717 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2718 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2719 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2720 2721 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2722 intel_ddi_enable_clock(encoder, crtc_state); 2723 2724 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2725 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2726 dig_port->ddi_io_power_domain); 2727 2728 icl_program_mg_dp_mode(dig_port, crtc_state); 2729 2730 intel_ddi_enable_pipe_clock(encoder, crtc_state); 2731 2732 dig_port->set_infoframes(encoder, 2733 crtc_state->has_infoframe, 2734 crtc_state, conn_state); 2735 } 2736 2737 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2738 struct intel_encoder *encoder, 2739 const struct intel_crtc_state *crtc_state, 2740 const struct drm_connector_state *conn_state) 2741 { 2742 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2744 enum pipe pipe = crtc->pipe; 2745 2746 /* 2747 * When called from DP MST code: 2748 * - conn_state will be NULL 2749 * - encoder will be the main encoder (ie. mst->primary) 2750 * - the main connector associated with this port 2751 * won't be active or linked to a crtc 2752 * - crtc_state will be the state of the first stream to 2753 * be activated on this port, and it may not be the same 2754 * stream that will be deactivated last, but each stream 2755 * should have a state that is identical when it comes to 2756 * the DP link parameteres 2757 */ 2758 2759 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2760 2761 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2762 2763 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2764 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2765 conn_state); 2766 } else { 2767 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2768 2769 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2770 conn_state); 2771 2772 /* FIXME precompute everything properly */ 2773 /* FIXME how do we turn infoframes off again? */ 2774 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 2775 dig_port->set_infoframes(encoder, 2776 crtc_state->has_infoframe, 2777 crtc_state, conn_state); 2778 } 2779 } 2780 2781 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2782 const struct intel_crtc_state *crtc_state) 2783 { 2784 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2785 enum port port = encoder->port; 2786 bool wait = false; 2787 u32 val; 2788 2789 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2790 if (val & DDI_BUF_CTL_ENABLE) { 2791 val &= ~DDI_BUF_CTL_ENABLE; 2792 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2793 wait = true; 2794 } 2795 2796 if (intel_crtc_has_dp_encoder(crtc_state)) { 2797 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2798 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2799 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2800 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 2801 } 2802 2803 /* Disable FEC in DP Sink */ 2804 intel_ddi_disable_fec_state(encoder, crtc_state); 2805 2806 if (wait) 2807 intel_wait_ddi_buf_idle(dev_priv, port); 2808 } 2809 2810 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 2811 struct intel_encoder *encoder, 2812 const struct intel_crtc_state *old_crtc_state, 2813 const struct drm_connector_state *old_conn_state) 2814 { 2815 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2816 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2817 struct intel_dp *intel_dp = &dig_port->dp; 2818 bool is_mst = intel_crtc_has_type(old_crtc_state, 2819 INTEL_OUTPUT_DP_MST); 2820 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2821 2822 if (!is_mst) 2823 intel_dp_set_infoframes(encoder, false, 2824 old_crtc_state, old_conn_state); 2825 2826 /* 2827 * Power down sink before disabling the port, otherwise we end 2828 * up getting interrupts from the sink on detecting link loss. 2829 */ 2830 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 2831 2832 if (DISPLAY_VER(dev_priv) >= 12) { 2833 if (is_mst) { 2834 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 2835 u32 val; 2836 2837 val = intel_de_read(dev_priv, 2838 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 2839 val &= ~(TGL_TRANS_DDI_PORT_MASK | 2840 TRANS_DDI_MODE_SELECT_MASK); 2841 intel_de_write(dev_priv, 2842 TRANS_DDI_FUNC_CTL(cpu_transcoder), 2843 val); 2844 } 2845 } else { 2846 if (!is_mst) 2847 intel_ddi_disable_pipe_clock(old_crtc_state); 2848 } 2849 2850 intel_disable_ddi_buf(encoder, old_crtc_state); 2851 2852 /* 2853 * From TGL spec: "If single stream or multi-stream master transcoder: 2854 * Configure Transcoder Clock select to direct no clock to the 2855 * transcoder" 2856 */ 2857 if (DISPLAY_VER(dev_priv) >= 12) 2858 intel_ddi_disable_pipe_clock(old_crtc_state); 2859 2860 intel_pps_vdd_on(intel_dp); 2861 intel_pps_off(intel_dp); 2862 2863 if (!intel_phy_is_tc(dev_priv, phy) || 2864 dig_port->tc_mode != TC_PORT_TBT_ALT) 2865 intel_display_power_put(dev_priv, 2866 dig_port->ddi_io_power_domain, 2867 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2868 2869 intel_ddi_disable_clock(encoder); 2870 } 2871 2872 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 2873 struct intel_encoder *encoder, 2874 const struct intel_crtc_state *old_crtc_state, 2875 const struct drm_connector_state *old_conn_state) 2876 { 2877 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2878 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2879 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2880 2881 dig_port->set_infoframes(encoder, false, 2882 old_crtc_state, old_conn_state); 2883 2884 intel_ddi_disable_pipe_clock(old_crtc_state); 2885 2886 intel_disable_ddi_buf(encoder, old_crtc_state); 2887 2888 intel_display_power_put(dev_priv, 2889 dig_port->ddi_io_power_domain, 2890 fetch_and_zero(&dig_port->ddi_io_wakeref)); 2891 2892 intel_ddi_disable_clock(encoder); 2893 2894 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2895 } 2896 2897 static void intel_ddi_post_disable(struct intel_atomic_state *state, 2898 struct intel_encoder *encoder, 2899 const struct intel_crtc_state *old_crtc_state, 2900 const struct drm_connector_state *old_conn_state) 2901 { 2902 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2903 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2904 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 2905 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 2906 2907 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { 2908 intel_crtc_vblank_off(old_crtc_state); 2909 2910 intel_disable_pipe(old_crtc_state); 2911 2912 intel_vrr_disable(old_crtc_state); 2913 2914 intel_ddi_disable_transcoder_func(old_crtc_state); 2915 2916 intel_dsc_disable(old_crtc_state); 2917 2918 if (DISPLAY_VER(dev_priv) >= 9) 2919 skl_scaler_disable(old_crtc_state); 2920 else 2921 ilk_pfit_disable(old_crtc_state); 2922 } 2923 2924 if (old_crtc_state->bigjoiner_linked_crtc) { 2925 struct intel_atomic_state *state = 2926 to_intel_atomic_state(old_crtc_state->uapi.state); 2927 struct intel_crtc *slave = 2928 old_crtc_state->bigjoiner_linked_crtc; 2929 const struct intel_crtc_state *old_slave_crtc_state = 2930 intel_atomic_get_old_crtc_state(state, slave); 2931 2932 intel_crtc_vblank_off(old_slave_crtc_state); 2933 2934 intel_dsc_disable(old_slave_crtc_state); 2935 skl_scaler_disable(old_slave_crtc_state); 2936 } 2937 2938 /* 2939 * When called from DP MST code: 2940 * - old_conn_state will be NULL 2941 * - encoder will be the main encoder (ie. mst->primary) 2942 * - the main connector associated with this port 2943 * won't be active or linked to a crtc 2944 * - old_crtc_state will be the state of the last stream to 2945 * be deactivated on this port, and it may not be the same 2946 * stream that was activated last, but each stream 2947 * should have a state that is identical when it comes to 2948 * the DP link parameteres 2949 */ 2950 2951 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 2952 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 2953 old_conn_state); 2954 else 2955 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 2956 old_conn_state); 2957 2958 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) 2959 intel_display_power_put(dev_priv, 2960 intel_ddi_main_link_aux_domain(dig_port), 2961 fetch_and_zero(&dig_port->aux_wakeref)); 2962 2963 if (is_tc_port) 2964 intel_tc_port_put_link(dig_port); 2965 } 2966 2967 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 2968 struct intel_encoder *encoder, 2969 const struct intel_crtc_state *old_crtc_state, 2970 const struct drm_connector_state *old_conn_state) 2971 { 2972 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2973 u32 val; 2974 2975 /* 2976 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 2977 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 2978 * step 13 is the correct place for it. Step 18 is where it was 2979 * originally before the BUN. 2980 */ 2981 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 2982 val &= ~FDI_RX_ENABLE; 2983 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 2984 2985 intel_disable_ddi_buf(encoder, old_crtc_state); 2986 intel_ddi_disable_clock(encoder); 2987 2988 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); 2989 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 2990 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 2991 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); 2992 2993 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 2994 val &= ~FDI_PCDCLK; 2995 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 2996 2997 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); 2998 val &= ~FDI_RX_PLL_ENABLE; 2999 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); 3000 } 3001 3002 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3003 struct intel_encoder *encoder, 3004 const struct intel_crtc_state *crtc_state) 3005 { 3006 const struct drm_connector_state *conn_state; 3007 struct drm_connector *conn; 3008 int i; 3009 3010 if (!crtc_state->sync_mode_slaves_mask) 3011 return; 3012 3013 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3014 struct intel_encoder *slave_encoder = 3015 to_intel_encoder(conn_state->best_encoder); 3016 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3017 const struct intel_crtc_state *slave_crtc_state; 3018 3019 if (!slave_crtc) 3020 continue; 3021 3022 slave_crtc_state = 3023 intel_atomic_get_new_crtc_state(state, slave_crtc); 3024 3025 if (slave_crtc_state->master_transcoder != 3026 crtc_state->cpu_transcoder) 3027 continue; 3028 3029 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3030 slave_crtc_state); 3031 } 3032 3033 usleep_range(200, 400); 3034 3035 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3036 crtc_state); 3037 } 3038 3039 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3040 struct intel_encoder *encoder, 3041 const struct intel_crtc_state *crtc_state, 3042 const struct drm_connector_state *conn_state) 3043 { 3044 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3045 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3046 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3047 enum port port = encoder->port; 3048 3049 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3050 intel_dp_stop_link_train(intel_dp, crtc_state); 3051 3052 intel_edp_backlight_on(crtc_state, conn_state); 3053 intel_psr_enable(intel_dp, crtc_state, conn_state); 3054 3055 if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) 3056 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3057 3058 intel_edp_drrs_enable(intel_dp, crtc_state); 3059 3060 if (crtc_state->has_audio) 3061 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3062 3063 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3064 } 3065 3066 static i915_reg_t 3067 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3068 enum port port) 3069 { 3070 static const enum transcoder trans[] = { 3071 [PORT_A] = TRANSCODER_EDP, 3072 [PORT_B] = TRANSCODER_A, 3073 [PORT_C] = TRANSCODER_B, 3074 [PORT_D] = TRANSCODER_C, 3075 [PORT_E] = TRANSCODER_A, 3076 }; 3077 3078 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3079 3080 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3081 port = PORT_A; 3082 3083 return CHICKEN_TRANS(trans[port]); 3084 } 3085 3086 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3087 struct intel_encoder *encoder, 3088 const struct intel_crtc_state *crtc_state, 3089 const struct drm_connector_state *conn_state) 3090 { 3091 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3092 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3093 struct drm_connector *connector = conn_state->connector; 3094 int level = intel_ddi_hdmi_level(encoder, crtc_state); 3095 enum port port = encoder->port; 3096 3097 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3098 crtc_state->hdmi_high_tmds_clock_ratio, 3099 crtc_state->hdmi_scrambling)) 3100 drm_dbg_kms(&dev_priv->drm, 3101 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3102 connector->base.id, connector->name); 3103 3104 if (DISPLAY_VER(dev_priv) >= 12) 3105 tgl_ddi_vswing_sequence(encoder, crtc_state, level); 3106 else if (DISPLAY_VER(dev_priv) == 11) 3107 icl_ddi_vswing_sequence(encoder, crtc_state, level); 3108 else if (IS_CANNONLAKE(dev_priv)) 3109 cnl_ddi_vswing_sequence(encoder, crtc_state, level); 3110 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3111 bxt_ddi_vswing_sequence(encoder, crtc_state, level); 3112 else 3113 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state, level); 3114 3115 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 3116 skl_ddi_set_iboost(encoder, crtc_state, level); 3117 3118 /* Display WA #1143: skl,kbl,cfl */ 3119 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3120 /* 3121 * For some reason these chicken bits have been 3122 * stuffed into a transcoder register, event though 3123 * the bits affect a specific DDI port rather than 3124 * a specific transcoder. 3125 */ 3126 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3127 u32 val; 3128 3129 val = intel_de_read(dev_priv, reg); 3130 3131 if (port == PORT_E) 3132 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3133 DDIE_TRAINING_OVERRIDE_VALUE; 3134 else 3135 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3136 DDI_TRAINING_OVERRIDE_VALUE; 3137 3138 intel_de_write(dev_priv, reg, val); 3139 intel_de_posting_read(dev_priv, reg); 3140 3141 udelay(1); 3142 3143 if (port == PORT_E) 3144 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3145 DDIE_TRAINING_OVERRIDE_VALUE); 3146 else 3147 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3148 DDI_TRAINING_OVERRIDE_VALUE); 3149 3150 intel_de_write(dev_priv, reg, val); 3151 } 3152 3153 intel_ddi_power_up_lanes(encoder, crtc_state); 3154 3155 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3156 * are ignored so nothing special needs to be done besides 3157 * enabling the port. 3158 * 3159 * On ADL_P the PHY link rate and lane count must be programmed but 3160 * these are both 0 for HDMI. 3161 */ 3162 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3163 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); 3164 3165 if (crtc_state->has_audio) 3166 intel_audio_codec_enable(encoder, crtc_state, conn_state); 3167 } 3168 3169 static void intel_enable_ddi(struct intel_atomic_state *state, 3170 struct intel_encoder *encoder, 3171 const struct intel_crtc_state *crtc_state, 3172 const struct drm_connector_state *conn_state) 3173 { 3174 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); 3175 3176 if (!crtc_state->bigjoiner_slave) 3177 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3178 3179 intel_vrr_enable(encoder, crtc_state); 3180 3181 intel_enable_pipe(crtc_state); 3182 3183 intel_crtc_vblank_on(crtc_state); 3184 3185 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3186 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3187 else 3188 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3189 3190 /* Enable hdcp if it's desired */ 3191 if (conn_state->content_protection == 3192 DRM_MODE_CONTENT_PROTECTION_DESIRED) 3193 intel_hdcp_enable(to_intel_connector(conn_state->connector), 3194 crtc_state, 3195 (u8)conn_state->hdcp_content_type); 3196 } 3197 3198 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3199 struct intel_encoder *encoder, 3200 const struct intel_crtc_state *old_crtc_state, 3201 const struct drm_connector_state *old_conn_state) 3202 { 3203 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3204 3205 intel_dp->link_trained = false; 3206 3207 if (old_crtc_state->has_audio) 3208 intel_audio_codec_disable(encoder, 3209 old_crtc_state, old_conn_state); 3210 3211 intel_edp_drrs_disable(intel_dp, old_crtc_state); 3212 intel_psr_disable(intel_dp, old_crtc_state); 3213 intel_edp_backlight_off(old_conn_state); 3214 /* Disable the decompression in DP Sink */ 3215 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, 3216 false); 3217 /* Disable Ignore_MSA bit in DP Sink */ 3218 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3219 false); 3220 } 3221 3222 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3223 struct intel_encoder *encoder, 3224 const struct intel_crtc_state *old_crtc_state, 3225 const struct drm_connector_state *old_conn_state) 3226 { 3227 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3228 struct drm_connector *connector = old_conn_state->connector; 3229 3230 if (old_crtc_state->has_audio) 3231 intel_audio_codec_disable(encoder, 3232 old_crtc_state, old_conn_state); 3233 3234 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3235 false, false)) 3236 drm_dbg_kms(&i915->drm, 3237 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3238 connector->base.id, connector->name); 3239 } 3240 3241 static void intel_disable_ddi(struct intel_atomic_state *state, 3242 struct intel_encoder *encoder, 3243 const struct intel_crtc_state *old_crtc_state, 3244 const struct drm_connector_state *old_conn_state) 3245 { 3246 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3247 3248 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3249 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3250 old_conn_state); 3251 else 3252 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3253 old_conn_state); 3254 } 3255 3256 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3257 struct intel_encoder *encoder, 3258 const struct intel_crtc_state *crtc_state, 3259 const struct drm_connector_state *conn_state) 3260 { 3261 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3262 3263 intel_ddi_set_dp_msa(crtc_state, conn_state); 3264 3265 intel_psr_update(intel_dp, crtc_state, conn_state); 3266 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3267 intel_edp_drrs_update(intel_dp, crtc_state); 3268 3269 intel_panel_update_backlight(state, encoder, crtc_state, conn_state); 3270 } 3271 3272 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3273 struct intel_encoder *encoder, 3274 const struct intel_crtc_state *crtc_state, 3275 const struct drm_connector_state *conn_state) 3276 { 3277 3278 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3279 !intel_encoder_is_mst(encoder)) 3280 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3281 conn_state); 3282 3283 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3284 } 3285 3286 static void 3287 intel_ddi_update_prepare(struct intel_atomic_state *state, 3288 struct intel_encoder *encoder, 3289 struct intel_crtc *crtc) 3290 { 3291 struct intel_crtc_state *crtc_state = 3292 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL; 3293 int required_lanes = crtc_state ? crtc_state->lane_count : 1; 3294 3295 drm_WARN_ON(state->base.dev, crtc && crtc->active); 3296 3297 intel_tc_port_get_link(enc_to_dig_port(encoder), 3298 required_lanes); 3299 if (crtc_state && crtc_state->hw.active) 3300 intel_update_active_dpll(state, crtc, encoder); 3301 } 3302 3303 static void 3304 intel_ddi_update_complete(struct intel_atomic_state *state, 3305 struct intel_encoder *encoder, 3306 struct intel_crtc *crtc) 3307 { 3308 intel_tc_port_put_link(enc_to_dig_port(encoder)); 3309 } 3310 3311 static void 3312 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3313 struct intel_encoder *encoder, 3314 const struct intel_crtc_state *crtc_state, 3315 const struct drm_connector_state *conn_state) 3316 { 3317 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3318 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3319 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 3320 bool is_tc_port = intel_phy_is_tc(dev_priv, phy); 3321 3322 if (is_tc_port) 3323 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3324 3325 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { 3326 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref); 3327 dig_port->aux_wakeref = 3328 intel_display_power_get(dev_priv, 3329 intel_ddi_main_link_aux_domain(dig_port)); 3330 } 3331 3332 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT) 3333 /* 3334 * Program the lane count for static/dynamic connections on 3335 * Type-C ports. Skip this step for TBT. 3336 */ 3337 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3338 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3339 bxt_ddi_phy_set_lane_optim_mask(encoder, 3340 crtc_state->lane_lat_optim_mask); 3341 } 3342 3343 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3344 const struct intel_crtc_state *crtc_state) 3345 { 3346 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3348 enum port port = encoder->port; 3349 u32 dp_tp_ctl, ddi_buf_ctl; 3350 bool wait = false; 3351 3352 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3353 3354 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3355 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3356 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3357 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3358 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3359 wait = true; 3360 } 3361 3362 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 3363 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; 3364 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3365 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3366 3367 if (wait) 3368 intel_wait_ddi_buf_idle(dev_priv, port); 3369 } 3370 3371 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3372 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3373 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3374 } else { 3375 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3376 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3377 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3378 } 3379 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3380 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3381 3382 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3383 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3384 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3385 3386 intel_wait_ddi_buf_active(dev_priv, port); 3387 } 3388 3389 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3390 const struct intel_crtc_state *crtc_state, 3391 u8 dp_train_pat) 3392 { 3393 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3394 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3395 u32 temp; 3396 3397 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3398 3399 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3400 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3401 case DP_TRAINING_PATTERN_DISABLE: 3402 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3403 break; 3404 case DP_TRAINING_PATTERN_1: 3405 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3406 break; 3407 case DP_TRAINING_PATTERN_2: 3408 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3409 break; 3410 case DP_TRAINING_PATTERN_3: 3411 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3412 break; 3413 case DP_TRAINING_PATTERN_4: 3414 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3415 break; 3416 } 3417 3418 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3419 } 3420 3421 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3422 const struct intel_crtc_state *crtc_state) 3423 { 3424 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3425 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3426 enum port port = encoder->port; 3427 u32 val; 3428 3429 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3430 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3431 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3432 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); 3433 3434 /* 3435 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3436 * reason we need to set idle transmission mode is to work around a HW 3437 * issue where we enable the pipe while not in idle link-training mode. 3438 * In this case there is requirement to wait for a minimum number of 3439 * idle patterns to be sent. 3440 */ 3441 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3442 return; 3443 3444 if (intel_de_wait_for_set(dev_priv, 3445 dp_tp_status_reg(encoder, crtc_state), 3446 DP_TP_STATUS_IDLE_DONE, 1)) 3447 drm_err(&dev_priv->drm, 3448 "Timed out waiting for DP idle patterns\n"); 3449 } 3450 3451 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3452 enum transcoder cpu_transcoder) 3453 { 3454 if (cpu_transcoder == TRANSCODER_EDP) 3455 return false; 3456 3457 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) 3458 return false; 3459 3460 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3461 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3462 } 3463 3464 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 3465 struct intel_crtc_state *crtc_state) 3466 { 3467 if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000) 3468 crtc_state->min_voltage_level = 2; 3469 else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000) 3470 crtc_state->min_voltage_level = 3; 3471 else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000) 3472 crtc_state->min_voltage_level = 1; 3473 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000) 3474 crtc_state->min_voltage_level = 2; 3475 } 3476 3477 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3478 enum transcoder cpu_transcoder) 3479 { 3480 u32 master_select; 3481 3482 if (DISPLAY_VER(dev_priv) >= 11) { 3483 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3484 3485 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3486 return INVALID_TRANSCODER; 3487 3488 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3489 } else { 3490 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3491 3492 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3493 return INVALID_TRANSCODER; 3494 3495 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3496 } 3497 3498 if (master_select == 0) 3499 return TRANSCODER_EDP; 3500 else 3501 return master_select - 1; 3502 } 3503 3504 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3505 { 3506 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3507 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3508 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3509 enum transcoder cpu_transcoder; 3510 3511 crtc_state->master_transcoder = 3512 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3513 3514 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3515 enum intel_display_power_domain power_domain; 3516 intel_wakeref_t trans_wakeref; 3517 3518 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3519 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3520 power_domain); 3521 3522 if (!trans_wakeref) 3523 continue; 3524 3525 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3526 crtc_state->cpu_transcoder) 3527 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3528 3529 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3530 } 3531 3532 drm_WARN_ON(&dev_priv->drm, 3533 crtc_state->master_transcoder != INVALID_TRANSCODER && 3534 crtc_state->sync_mode_slaves_mask); 3535 } 3536 3537 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3538 struct intel_crtc_state *pipe_config) 3539 { 3540 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3541 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3542 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3543 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3544 u32 temp, flags = 0; 3545 3546 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3547 if (temp & TRANS_DDI_PHSYNC) 3548 flags |= DRM_MODE_FLAG_PHSYNC; 3549 else 3550 flags |= DRM_MODE_FLAG_NHSYNC; 3551 if (temp & TRANS_DDI_PVSYNC) 3552 flags |= DRM_MODE_FLAG_PVSYNC; 3553 else 3554 flags |= DRM_MODE_FLAG_NVSYNC; 3555 3556 pipe_config->hw.adjusted_mode.flags |= flags; 3557 3558 switch (temp & TRANS_DDI_BPC_MASK) { 3559 case TRANS_DDI_BPC_6: 3560 pipe_config->pipe_bpp = 18; 3561 break; 3562 case TRANS_DDI_BPC_8: 3563 pipe_config->pipe_bpp = 24; 3564 break; 3565 case TRANS_DDI_BPC_10: 3566 pipe_config->pipe_bpp = 30; 3567 break; 3568 case TRANS_DDI_BPC_12: 3569 pipe_config->pipe_bpp = 36; 3570 break; 3571 default: 3572 break; 3573 } 3574 3575 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3576 case TRANS_DDI_MODE_SELECT_HDMI: 3577 pipe_config->has_hdmi_sink = true; 3578 3579 pipe_config->infoframes.enable |= 3580 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3581 3582 if (pipe_config->infoframes.enable) 3583 pipe_config->has_infoframe = true; 3584 3585 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3586 pipe_config->hdmi_scrambling = true; 3587 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3588 pipe_config->hdmi_high_tmds_clock_ratio = true; 3589 fallthrough; 3590 case TRANS_DDI_MODE_SELECT_DVI: 3591 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3592 pipe_config->lane_count = 4; 3593 break; 3594 case TRANS_DDI_MODE_SELECT_FDI: 3595 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3596 break; 3597 case TRANS_DDI_MODE_SELECT_DP_SST: 3598 if (encoder->type == INTEL_OUTPUT_EDP) 3599 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3600 else 3601 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3602 pipe_config->lane_count = 3603 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3604 intel_dp_get_m_n(crtc, pipe_config); 3605 3606 if (DISPLAY_VER(dev_priv) >= 11) { 3607 i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); 3608 3609 pipe_config->fec_enable = 3610 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; 3611 3612 drm_dbg_kms(&dev_priv->drm, 3613 "[ENCODER:%d:%s] Fec status: %u\n", 3614 encoder->base.base.id, encoder->base.name, 3615 pipe_config->fec_enable); 3616 } 3617 3618 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) 3619 pipe_config->infoframes.enable |= 3620 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3621 else 3622 pipe_config->infoframes.enable |= 3623 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3624 break; 3625 case TRANS_DDI_MODE_SELECT_DP_MST: 3626 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3627 pipe_config->lane_count = 3628 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3629 3630 if (DISPLAY_VER(dev_priv) >= 12) 3631 pipe_config->mst_master_transcoder = 3632 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3633 3634 intel_dp_get_m_n(crtc, pipe_config); 3635 3636 pipe_config->infoframes.enable |= 3637 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3638 break; 3639 default: 3640 break; 3641 } 3642 } 3643 3644 static void intel_ddi_get_config(struct intel_encoder *encoder, 3645 struct intel_crtc_state *pipe_config) 3646 { 3647 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3648 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3649 3650 /* XXX: DSI transcoder paranoia */ 3651 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3652 return; 3653 3654 if (pipe_config->bigjoiner_slave) { 3655 /* read out pipe settings from master */ 3656 enum transcoder save = pipe_config->cpu_transcoder; 3657 3658 /* Our own transcoder needs to be disabled when reading it in intel_ddi_read_func_ctl() */ 3659 WARN_ON(pipe_config->output_types); 3660 pipe_config->cpu_transcoder = (enum transcoder)pipe_config->bigjoiner_linked_crtc->pipe; 3661 intel_ddi_read_func_ctl(encoder, pipe_config); 3662 pipe_config->cpu_transcoder = save; 3663 } else { 3664 intel_ddi_read_func_ctl(encoder, pipe_config); 3665 } 3666 3667 intel_ddi_mso_get_config(encoder, pipe_config); 3668 3669 pipe_config->has_audio = 3670 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3671 3672 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && 3673 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3674 /* 3675 * This is a big fat ugly hack. 3676 * 3677 * Some machines in UEFI boot mode provide us a VBT that has 18 3678 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3679 * unknown we fail to light up. Yet the same BIOS boots up with 3680 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3681 * max, not what it tells us to use. 3682 * 3683 * Note: This will still be broken if the eDP panel is not lit 3684 * up by the BIOS, and thus we can't get the mode at module 3685 * load. 3686 */ 3687 drm_dbg_kms(&dev_priv->drm, 3688 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3689 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3690 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3691 } 3692 3693 if (!pipe_config->bigjoiner_slave) 3694 ddi_dotclock_get(pipe_config); 3695 3696 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3697 pipe_config->lane_lat_optim_mask = 3698 bxt_ddi_phy_get_lane_lat_optim_mask(encoder); 3699 3700 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3701 3702 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3703 3704 intel_read_infoframe(encoder, pipe_config, 3705 HDMI_INFOFRAME_TYPE_AVI, 3706 &pipe_config->infoframes.avi); 3707 intel_read_infoframe(encoder, pipe_config, 3708 HDMI_INFOFRAME_TYPE_SPD, 3709 &pipe_config->infoframes.spd); 3710 intel_read_infoframe(encoder, pipe_config, 3711 HDMI_INFOFRAME_TYPE_VENDOR, 3712 &pipe_config->infoframes.hdmi); 3713 intel_read_infoframe(encoder, pipe_config, 3714 HDMI_INFOFRAME_TYPE_DRM, 3715 &pipe_config->infoframes.drm); 3716 3717 if (DISPLAY_VER(dev_priv) >= 8) 3718 bdw_get_trans_port_sync_config(pipe_config); 3719 3720 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3721 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3722 3723 intel_psr_get_config(encoder, pipe_config); 3724 } 3725 3726 void intel_ddi_get_clock(struct intel_encoder *encoder, 3727 struct intel_crtc_state *crtc_state, 3728 struct intel_shared_dpll *pll) 3729 { 3730 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3731 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3732 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3733 bool pll_active; 3734 3735 if (drm_WARN_ON(&i915->drm, !pll)) 3736 return; 3737 3738 port_dpll->pll = pll; 3739 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3740 drm_WARN_ON(&i915->drm, !pll_active); 3741 3742 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3743 3744 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3745 &crtc_state->dpll_hw_state); 3746 } 3747 3748 static void adls_ddi_get_config(struct intel_encoder *encoder, 3749 struct intel_crtc_state *crtc_state) 3750 { 3751 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 3752 intel_ddi_get_config(encoder, crtc_state); 3753 } 3754 3755 static void rkl_ddi_get_config(struct intel_encoder *encoder, 3756 struct intel_crtc_state *crtc_state) 3757 { 3758 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 3759 intel_ddi_get_config(encoder, crtc_state); 3760 } 3761 3762 static void dg1_ddi_get_config(struct intel_encoder *encoder, 3763 struct intel_crtc_state *crtc_state) 3764 { 3765 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 3766 intel_ddi_get_config(encoder, crtc_state); 3767 } 3768 3769 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 3770 struct intel_crtc_state *crtc_state) 3771 { 3772 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 3773 intel_ddi_get_config(encoder, crtc_state); 3774 } 3775 3776 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 3777 struct intel_crtc_state *crtc_state, 3778 struct intel_shared_dpll *pll) 3779 { 3780 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3781 enum icl_port_dpll_id port_dpll_id; 3782 struct icl_port_dpll *port_dpll; 3783 bool pll_active; 3784 3785 if (drm_WARN_ON(&i915->drm, !pll)) 3786 return; 3787 3788 if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) 3789 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3790 else 3791 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 3792 3793 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3794 3795 port_dpll->pll = pll; 3796 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 3797 drm_WARN_ON(&i915->drm, !pll_active); 3798 3799 icl_set_active_port_dpll(crtc_state, port_dpll_id); 3800 3801 if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) 3802 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 3803 else 3804 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 3805 &crtc_state->dpll_hw_state); 3806 } 3807 3808 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 3809 struct intel_crtc_state *crtc_state) 3810 { 3811 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 3812 intel_ddi_get_config(encoder, crtc_state); 3813 } 3814 3815 static void cnl_ddi_get_config(struct intel_encoder *encoder, 3816 struct intel_crtc_state *crtc_state) 3817 { 3818 intel_ddi_get_clock(encoder, crtc_state, cnl_ddi_get_pll(encoder)); 3819 intel_ddi_get_config(encoder, crtc_state); 3820 } 3821 3822 static void bxt_ddi_get_config(struct intel_encoder *encoder, 3823 struct intel_crtc_state *crtc_state) 3824 { 3825 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 3826 intel_ddi_get_config(encoder, crtc_state); 3827 } 3828 3829 static void skl_ddi_get_config(struct intel_encoder *encoder, 3830 struct intel_crtc_state *crtc_state) 3831 { 3832 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 3833 intel_ddi_get_config(encoder, crtc_state); 3834 } 3835 3836 void hsw_ddi_get_config(struct intel_encoder *encoder, 3837 struct intel_crtc_state *crtc_state) 3838 { 3839 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 3840 intel_ddi_get_config(encoder, crtc_state); 3841 } 3842 3843 static void intel_ddi_sync_state(struct intel_encoder *encoder, 3844 const struct intel_crtc_state *crtc_state) 3845 { 3846 if (intel_crtc_has_dp_encoder(crtc_state)) 3847 intel_dp_sync_state(encoder, crtc_state); 3848 } 3849 3850 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 3851 struct intel_crtc_state *crtc_state) 3852 { 3853 if (intel_crtc_has_dp_encoder(crtc_state)) 3854 return intel_dp_initial_fastset_check(encoder, crtc_state); 3855 3856 return true; 3857 } 3858 3859 static enum intel_output_type 3860 intel_ddi_compute_output_type(struct intel_encoder *encoder, 3861 struct intel_crtc_state *crtc_state, 3862 struct drm_connector_state *conn_state) 3863 { 3864 switch (conn_state->connector->connector_type) { 3865 case DRM_MODE_CONNECTOR_HDMIA: 3866 return INTEL_OUTPUT_HDMI; 3867 case DRM_MODE_CONNECTOR_eDP: 3868 return INTEL_OUTPUT_EDP; 3869 case DRM_MODE_CONNECTOR_DisplayPort: 3870 return INTEL_OUTPUT_DP; 3871 default: 3872 MISSING_CASE(conn_state->connector->connector_type); 3873 return INTEL_OUTPUT_UNUSED; 3874 } 3875 } 3876 3877 static int intel_ddi_compute_config(struct intel_encoder *encoder, 3878 struct intel_crtc_state *pipe_config, 3879 struct drm_connector_state *conn_state) 3880 { 3881 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3882 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3883 enum port port = encoder->port; 3884 int ret; 3885 3886 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 3887 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3888 3889 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 3890 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 3891 } else { 3892 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 3893 } 3894 3895 if (ret) 3896 return ret; 3897 3898 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 3899 pipe_config->cpu_transcoder == TRANSCODER_EDP) 3900 pipe_config->pch_pfit.force_thru = 3901 pipe_config->pch_pfit.enabled || 3902 pipe_config->crc_enabled; 3903 3904 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3905 pipe_config->lane_lat_optim_mask = 3906 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 3907 3908 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 3909 3910 return 0; 3911 } 3912 3913 static bool mode_equal(const struct drm_display_mode *mode1, 3914 const struct drm_display_mode *mode2) 3915 { 3916 return drm_mode_match(mode1, mode2, 3917 DRM_MODE_MATCH_TIMINGS | 3918 DRM_MODE_MATCH_FLAGS | 3919 DRM_MODE_MATCH_3D_FLAGS) && 3920 mode1->clock == mode2->clock; /* we want an exact match */ 3921 } 3922 3923 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 3924 const struct intel_link_m_n *m_n_2) 3925 { 3926 return m_n_1->tu == m_n_2->tu && 3927 m_n_1->gmch_m == m_n_2->gmch_m && 3928 m_n_1->gmch_n == m_n_2->gmch_n && 3929 m_n_1->link_m == m_n_2->link_m && 3930 m_n_1->link_n == m_n_2->link_n; 3931 } 3932 3933 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 3934 const struct intel_crtc_state *crtc_state2) 3935 { 3936 return crtc_state1->hw.active && crtc_state2->hw.active && 3937 crtc_state1->output_types == crtc_state2->output_types && 3938 crtc_state1->output_format == crtc_state2->output_format && 3939 crtc_state1->lane_count == crtc_state2->lane_count && 3940 crtc_state1->port_clock == crtc_state2->port_clock && 3941 mode_equal(&crtc_state1->hw.adjusted_mode, 3942 &crtc_state2->hw.adjusted_mode) && 3943 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 3944 } 3945 3946 static u8 3947 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 3948 int tile_group_id) 3949 { 3950 struct drm_connector *connector; 3951 const struct drm_connector_state *conn_state; 3952 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 3953 struct intel_atomic_state *state = 3954 to_intel_atomic_state(ref_crtc_state->uapi.state); 3955 u8 transcoders = 0; 3956 int i; 3957 3958 /* 3959 * We don't enable port sync on BDW due to missing w/as and 3960 * due to not having adjusted the modeset sequence appropriately. 3961 */ 3962 if (DISPLAY_VER(dev_priv) < 9) 3963 return 0; 3964 3965 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 3966 return 0; 3967 3968 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 3969 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 3970 const struct intel_crtc_state *crtc_state; 3971 3972 if (!crtc) 3973 continue; 3974 3975 if (!connector->has_tile || 3976 connector->tile_group->id != 3977 tile_group_id) 3978 continue; 3979 crtc_state = intel_atomic_get_new_crtc_state(state, 3980 crtc); 3981 if (!crtcs_port_sync_compatible(ref_crtc_state, 3982 crtc_state)) 3983 continue; 3984 transcoders |= BIT(crtc_state->cpu_transcoder); 3985 } 3986 3987 return transcoders; 3988 } 3989 3990 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 3991 struct intel_crtc_state *crtc_state, 3992 struct drm_connector_state *conn_state) 3993 { 3994 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3995 struct drm_connector *connector = conn_state->connector; 3996 u8 port_sync_transcoders = 0; 3997 3998 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]", 3999 encoder->base.base.id, encoder->base.name, 4000 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4001 4002 if (connector->has_tile) 4003 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4004 connector->tile_group->id); 4005 4006 /* 4007 * EDP Transcoders cannot be ensalved 4008 * make them a master always when present 4009 */ 4010 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4011 crtc_state->master_transcoder = TRANSCODER_EDP; 4012 else 4013 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4014 4015 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4016 crtc_state->master_transcoder = INVALID_TRANSCODER; 4017 crtc_state->sync_mode_slaves_mask = 4018 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4019 } 4020 4021 return 0; 4022 } 4023 4024 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4025 { 4026 struct drm_i915_private *i915 = to_i915(encoder->dev); 4027 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4028 4029 intel_dp_encoder_flush_work(encoder); 4030 intel_display_power_flush_work(i915); 4031 4032 drm_encoder_cleanup(encoder); 4033 if (dig_port) 4034 kfree(dig_port->hdcp_port_data.streams); 4035 kfree(dig_port); 4036 } 4037 4038 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4039 { 4040 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4041 4042 intel_dp->reset_link_params = true; 4043 4044 intel_pps_encoder_reset(intel_dp); 4045 } 4046 4047 static const struct drm_encoder_funcs intel_ddi_funcs = { 4048 .reset = intel_ddi_encoder_reset, 4049 .destroy = intel_ddi_encoder_destroy, 4050 }; 4051 4052 static struct intel_connector * 4053 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4054 { 4055 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4056 struct intel_connector *connector; 4057 enum port port = dig_port->base.port; 4058 4059 connector = intel_connector_alloc(); 4060 if (!connector) 4061 return NULL; 4062 4063 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4064 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4065 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4066 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4067 4068 if (DISPLAY_VER(dev_priv) >= 12) 4069 dig_port->dp.set_signal_levels = tgl_set_signal_levels; 4070 else if (DISPLAY_VER(dev_priv) >= 11) 4071 dig_port->dp.set_signal_levels = icl_set_signal_levels; 4072 else if (IS_CANNONLAKE(dev_priv)) 4073 dig_port->dp.set_signal_levels = cnl_set_signal_levels; 4074 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4075 dig_port->dp.set_signal_levels = bxt_set_signal_levels; 4076 else 4077 dig_port->dp.set_signal_levels = hsw_set_signal_levels; 4078 4079 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4080 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4081 4082 if (!intel_dp_init_connector(dig_port, connector)) { 4083 kfree(connector); 4084 return NULL; 4085 } 4086 4087 return connector; 4088 } 4089 4090 static int modeset_pipe(struct drm_crtc *crtc, 4091 struct drm_modeset_acquire_ctx *ctx) 4092 { 4093 struct drm_atomic_state *state; 4094 struct drm_crtc_state *crtc_state; 4095 int ret; 4096 4097 state = drm_atomic_state_alloc(crtc->dev); 4098 if (!state) 4099 return -ENOMEM; 4100 4101 state->acquire_ctx = ctx; 4102 4103 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4104 if (IS_ERR(crtc_state)) { 4105 ret = PTR_ERR(crtc_state); 4106 goto out; 4107 } 4108 4109 crtc_state->connectors_changed = true; 4110 4111 ret = drm_atomic_commit(state); 4112 out: 4113 drm_atomic_state_put(state); 4114 4115 return ret; 4116 } 4117 4118 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4119 struct drm_modeset_acquire_ctx *ctx) 4120 { 4121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4122 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4123 struct intel_connector *connector = hdmi->attached_connector; 4124 struct i2c_adapter *adapter = 4125 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 4126 struct drm_connector_state *conn_state; 4127 struct intel_crtc_state *crtc_state; 4128 struct intel_crtc *crtc; 4129 u8 config; 4130 int ret; 4131 4132 if (!connector || connector->base.status != connector_status_connected) 4133 return 0; 4134 4135 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4136 ctx); 4137 if (ret) 4138 return ret; 4139 4140 conn_state = connector->base.state; 4141 4142 crtc = to_intel_crtc(conn_state->crtc); 4143 if (!crtc) 4144 return 0; 4145 4146 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4147 if (ret) 4148 return ret; 4149 4150 crtc_state = to_intel_crtc_state(crtc->base.state); 4151 4152 drm_WARN_ON(&dev_priv->drm, 4153 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4154 4155 if (!crtc_state->hw.active) 4156 return 0; 4157 4158 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4159 !crtc_state->hdmi_scrambling) 4160 return 0; 4161 4162 if (conn_state->commit && 4163 !try_wait_for_completion(&conn_state->commit->hw_done)) 4164 return 0; 4165 4166 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); 4167 if (ret < 0) { 4168 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n", 4169 ret); 4170 return 0; 4171 } 4172 4173 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4174 crtc_state->hdmi_high_tmds_clock_ratio && 4175 !!(config & SCDC_SCRAMBLING_ENABLE) == 4176 crtc_state->hdmi_scrambling) 4177 return 0; 4178 4179 /* 4180 * HDMI 2.0 says that one should not send scrambled data 4181 * prior to configuring the sink scrambling, and that 4182 * TMDS clock/data transmission should be suspended when 4183 * changing the TMDS clock rate in the sink. So let's 4184 * just do a full modeset here, even though some sinks 4185 * would be perfectly happy if were to just reconfigure 4186 * the SCDC settings on the fly. 4187 */ 4188 return modeset_pipe(&crtc->base, ctx); 4189 } 4190 4191 static enum intel_hotplug_state 4192 intel_ddi_hotplug(struct intel_encoder *encoder, 4193 struct intel_connector *connector) 4194 { 4195 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4196 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4197 struct intel_dp *intel_dp = &dig_port->dp; 4198 enum phy phy = intel_port_to_phy(i915, encoder->port); 4199 bool is_tc = intel_phy_is_tc(i915, phy); 4200 struct drm_modeset_acquire_ctx ctx; 4201 enum intel_hotplug_state state; 4202 int ret; 4203 4204 if (intel_dp->compliance.test_active && 4205 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4206 intel_dp_phy_test(encoder); 4207 /* just do the PHY test and nothing else */ 4208 return INTEL_HOTPLUG_UNCHANGED; 4209 } 4210 4211 state = intel_encoder_hotplug(encoder, connector); 4212 4213 drm_modeset_acquire_init(&ctx, 0); 4214 4215 for (;;) { 4216 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4217 ret = intel_hdmi_reset_link(encoder, &ctx); 4218 else 4219 ret = intel_dp_retrain_link(encoder, &ctx); 4220 4221 if (ret == -EDEADLK) { 4222 drm_modeset_backoff(&ctx); 4223 continue; 4224 } 4225 4226 break; 4227 } 4228 4229 drm_modeset_drop_locks(&ctx); 4230 drm_modeset_acquire_fini(&ctx); 4231 drm_WARN(encoder->base.dev, ret, 4232 "Acquiring modeset locks failed with %i\n", ret); 4233 4234 /* 4235 * Unpowered type-c dongles can take some time to boot and be 4236 * responsible, so here giving some time to those dongles to power up 4237 * and then retrying the probe. 4238 * 4239 * On many platforms the HDMI live state signal is known to be 4240 * unreliable, so we can't use it to detect if a sink is connected or 4241 * not. Instead we detect if it's connected based on whether we can 4242 * read the EDID or not. That in turn has a problem during disconnect, 4243 * since the HPD interrupt may be raised before the DDC lines get 4244 * disconnected (due to how the required length of DDC vs. HPD 4245 * connector pins are specified) and so we'll still be able to get a 4246 * valid EDID. To solve this schedule another detection cycle if this 4247 * time around we didn't detect any change in the sink's connection 4248 * status. 4249 * 4250 * Type-c connectors which get their HPD signal deasserted then 4251 * reasserted, without unplugging/replugging the sink from the 4252 * connector, introduce a delay until the AUX channel communication 4253 * becomes functional. Retry the detection for 5 seconds on type-c 4254 * connectors to account for this delay. 4255 */ 4256 if (state == INTEL_HOTPLUG_UNCHANGED && 4257 connector->hotplug_retries < (is_tc ? 5 : 1) && 4258 !dig_port->dp.is_mst) 4259 state = INTEL_HOTPLUG_RETRY; 4260 4261 return state; 4262 } 4263 4264 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4265 { 4266 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4267 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin]; 4268 4269 return intel_de_read(dev_priv, SDEISR) & bit; 4270 } 4271 4272 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4273 { 4274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4275 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4276 4277 return intel_de_read(dev_priv, DEISR) & bit; 4278 } 4279 4280 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4281 { 4282 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4283 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin]; 4284 4285 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4286 } 4287 4288 static struct intel_connector * 4289 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4290 { 4291 struct intel_connector *connector; 4292 enum port port = dig_port->base.port; 4293 4294 connector = intel_connector_alloc(); 4295 if (!connector) 4296 return NULL; 4297 4298 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4299 intel_hdmi_init_connector(dig_port, connector); 4300 4301 return connector; 4302 } 4303 4304 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4305 { 4306 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4307 4308 if (dig_port->base.port != PORT_A) 4309 return false; 4310 4311 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4312 return false; 4313 4314 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4315 * supported configuration 4316 */ 4317 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4318 return true; 4319 4320 /* Cannonlake: Most of SKUs don't support DDI_E, and the only 4321 * one who does also have a full A/E split called 4322 * DDI_F what makes DDI_E useless. However for this 4323 * case let's trust VBT info. 4324 */ 4325 if (IS_CANNONLAKE(dev_priv) && 4326 !intel_bios_is_port_present(dev_priv, PORT_E)) 4327 return true; 4328 4329 return false; 4330 } 4331 4332 static int 4333 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4334 { 4335 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4336 enum port port = dig_port->base.port; 4337 int max_lanes = 4; 4338 4339 if (DISPLAY_VER(dev_priv) >= 11) 4340 return max_lanes; 4341 4342 if (port == PORT_A || port == PORT_E) { 4343 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4344 max_lanes = port == PORT_A ? 4 : 0; 4345 else 4346 /* Both A and E share 2 lanes */ 4347 max_lanes = 2; 4348 } 4349 4350 /* 4351 * Some BIOS might fail to set this bit on port A if eDP 4352 * wasn't lit up at boot. Force this bit set when needed 4353 * so we use the proper lane count for our calculations. 4354 */ 4355 if (intel_ddi_a_force_4_lanes(dig_port)) { 4356 drm_dbg_kms(&dev_priv->drm, 4357 "Forcing DDI_A_4_LANES for port A\n"); 4358 dig_port->saved_port_bits |= DDI_A_4_LANES; 4359 max_lanes = 4; 4360 } 4361 4362 return max_lanes; 4363 } 4364 4365 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 4366 { 4367 return i915->hti_state & HDPORT_ENABLED && 4368 i915->hti_state & HDPORT_DDI_USED(phy); 4369 } 4370 4371 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4372 enum port port) 4373 { 4374 if (port >= PORT_D_XELPD) 4375 return HPD_PORT_D + port - PORT_D_XELPD; 4376 else if (port >= PORT_TC1) 4377 return HPD_PORT_TC1 + port - PORT_TC1; 4378 else 4379 return HPD_PORT_A + port - PORT_A; 4380 } 4381 4382 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4383 enum port port) 4384 { 4385 if (port >= PORT_TC1) 4386 return HPD_PORT_C + port - PORT_TC1; 4387 else 4388 return HPD_PORT_A + port - PORT_A; 4389 } 4390 4391 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4392 enum port port) 4393 { 4394 if (port >= PORT_TC1) 4395 return HPD_PORT_TC1 + port - PORT_TC1; 4396 else 4397 return HPD_PORT_A + port - PORT_A; 4398 } 4399 4400 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4401 enum port port) 4402 { 4403 if (HAS_PCH_TGP(dev_priv)) 4404 return tgl_hpd_pin(dev_priv, port); 4405 4406 if (port >= PORT_TC1) 4407 return HPD_PORT_C + port - PORT_TC1; 4408 else 4409 return HPD_PORT_A + port - PORT_A; 4410 } 4411 4412 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4413 enum port port) 4414 { 4415 if (port >= PORT_C) 4416 return HPD_PORT_TC1 + port - PORT_C; 4417 else 4418 return HPD_PORT_A + port - PORT_A; 4419 } 4420 4421 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4422 enum port port) 4423 { 4424 if (port == PORT_D) 4425 return HPD_PORT_A; 4426 4427 if (HAS_PCH_MCC(dev_priv)) 4428 return icl_hpd_pin(dev_priv, port); 4429 4430 return HPD_PORT_A + port - PORT_A; 4431 } 4432 4433 static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv, 4434 enum port port) 4435 { 4436 if (port == PORT_F) 4437 return HPD_PORT_E; 4438 4439 return HPD_PORT_A + port - PORT_A; 4440 } 4441 4442 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4443 { 4444 if (HAS_PCH_TGP(dev_priv)) 4445 return icl_hpd_pin(dev_priv, port); 4446 4447 return HPD_PORT_A + port - PORT_A; 4448 } 4449 4450 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4451 { 4452 if (DISPLAY_VER(i915) >= 12) 4453 return port >= PORT_TC1; 4454 else if (DISPLAY_VER(i915) >= 11) 4455 return port >= PORT_C; 4456 else 4457 return false; 4458 } 4459 4460 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4461 { 4462 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4463 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4464 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4465 enum phy phy = intel_port_to_phy(i915, encoder->port); 4466 4467 intel_dp_encoder_suspend(encoder); 4468 4469 if (!intel_phy_is_tc(i915, phy)) 4470 return; 4471 4472 intel_tc_port_disconnect_phy(dig_port); 4473 } 4474 4475 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4476 { 4477 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4478 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4479 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4480 enum phy phy = intel_port_to_phy(i915, encoder->port); 4481 4482 intel_dp_encoder_shutdown(encoder); 4483 4484 if (!intel_phy_is_tc(i915, phy)) 4485 return; 4486 4487 intel_tc_port_disconnect_phy(dig_port); 4488 } 4489 4490 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4491 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4492 4493 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 4494 { 4495 struct intel_digital_port *dig_port; 4496 struct intel_encoder *encoder; 4497 const struct intel_bios_encoder_data *devdata; 4498 bool init_hdmi, init_dp; 4499 enum phy phy = intel_port_to_phy(dev_priv, port); 4500 4501 /* 4502 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4503 * have taken over some of the PHYs and made them unavailable to the 4504 * driver. In that case we should skip initializing the corresponding 4505 * outputs. 4506 */ 4507 if (hti_uses_phy(dev_priv, phy)) { 4508 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4509 port_name(port), phy_name(phy)); 4510 return; 4511 } 4512 4513 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 4514 if (!devdata) { 4515 drm_dbg_kms(&dev_priv->drm, 4516 "VBT says port %c is not present\n", 4517 port_name(port)); 4518 return; 4519 } 4520 4521 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4522 intel_bios_encoder_supports_hdmi(devdata); 4523 init_dp = intel_bios_encoder_supports_dp(devdata); 4524 4525 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4526 /* 4527 * Lspcon device needs to be driven with DP connector 4528 * with special detection sequence. So make sure DP 4529 * is initialized before lspcon. 4530 */ 4531 init_dp = true; 4532 init_hdmi = false; 4533 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4534 port_name(port)); 4535 } 4536 4537 if (!init_dp && !init_hdmi) { 4538 drm_dbg_kms(&dev_priv->drm, 4539 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4540 port_name(port)); 4541 return; 4542 } 4543 4544 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4545 if (!dig_port) 4546 return; 4547 4548 encoder = &dig_port->base; 4549 encoder->devdata = devdata; 4550 4551 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4552 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4553 DRM_MODE_ENCODER_TMDS, 4554 "DDI %c/PHY %c", 4555 port_name(port - PORT_D_XELPD + PORT_D), 4556 phy_name(phy)); 4557 } else if (DISPLAY_VER(dev_priv) >= 12) { 4558 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4559 4560 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4561 DRM_MODE_ENCODER_TMDS, 4562 "DDI %s%c/PHY %s%c", 4563 port >= PORT_TC1 ? "TC" : "", 4564 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4565 tc_port != TC_PORT_NONE ? "TC" : "", 4566 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4567 } else if (DISPLAY_VER(dev_priv) >= 11) { 4568 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4569 4570 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4571 DRM_MODE_ENCODER_TMDS, 4572 "DDI %c%s/PHY %s%c", 4573 port_name(port), 4574 port >= PORT_C ? " (TC)" : "", 4575 tc_port != TC_PORT_NONE ? "TC" : "", 4576 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4577 } else { 4578 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4579 DRM_MODE_ENCODER_TMDS, 4580 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4581 } 4582 4583 mutex_init(&dig_port->hdcp_mutex); 4584 dig_port->num_hdcp_streams = 0; 4585 4586 encoder->hotplug = intel_ddi_hotplug; 4587 encoder->compute_output_type = intel_ddi_compute_output_type; 4588 encoder->compute_config = intel_ddi_compute_config; 4589 encoder->compute_config_late = intel_ddi_compute_config_late; 4590 encoder->enable = intel_enable_ddi; 4591 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4592 encoder->pre_enable = intel_ddi_pre_enable; 4593 encoder->disable = intel_disable_ddi; 4594 encoder->post_disable = intel_ddi_post_disable; 4595 encoder->update_pipe = intel_ddi_update_pipe; 4596 encoder->get_hw_state = intel_ddi_get_hw_state; 4597 encoder->sync_state = intel_ddi_sync_state; 4598 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4599 encoder->suspend = intel_ddi_encoder_suspend; 4600 encoder->shutdown = intel_ddi_encoder_shutdown; 4601 encoder->get_power_domains = intel_ddi_get_power_domains; 4602 4603 encoder->type = INTEL_OUTPUT_DDI; 4604 encoder->power_domain = intel_port_to_power_domain(port); 4605 encoder->port = port; 4606 encoder->cloneable = 0; 4607 encoder->pipe_mask = ~0; 4608 4609 if (IS_ALDERLAKE_S(dev_priv)) { 4610 encoder->enable_clock = adls_ddi_enable_clock; 4611 encoder->disable_clock = adls_ddi_disable_clock; 4612 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 4613 encoder->get_config = adls_ddi_get_config; 4614 } else if (IS_ROCKETLAKE(dev_priv)) { 4615 encoder->enable_clock = rkl_ddi_enable_clock; 4616 encoder->disable_clock = rkl_ddi_disable_clock; 4617 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 4618 encoder->get_config = rkl_ddi_get_config; 4619 } else if (IS_DG1(dev_priv)) { 4620 encoder->enable_clock = dg1_ddi_enable_clock; 4621 encoder->disable_clock = dg1_ddi_disable_clock; 4622 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 4623 encoder->get_config = dg1_ddi_get_config; 4624 } else if (IS_JSL_EHL(dev_priv)) { 4625 if (intel_ddi_is_tc(dev_priv, port)) { 4626 encoder->enable_clock = jsl_ddi_tc_enable_clock; 4627 encoder->disable_clock = jsl_ddi_tc_disable_clock; 4628 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 4629 encoder->get_config = icl_ddi_combo_get_config; 4630 } else { 4631 encoder->enable_clock = icl_ddi_combo_enable_clock; 4632 encoder->disable_clock = icl_ddi_combo_disable_clock; 4633 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4634 encoder->get_config = icl_ddi_combo_get_config; 4635 } 4636 } else if (DISPLAY_VER(dev_priv) >= 11) { 4637 if (intel_ddi_is_tc(dev_priv, port)) { 4638 encoder->enable_clock = icl_ddi_tc_enable_clock; 4639 encoder->disable_clock = icl_ddi_tc_disable_clock; 4640 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 4641 encoder->get_config = icl_ddi_tc_get_config; 4642 } else { 4643 encoder->enable_clock = icl_ddi_combo_enable_clock; 4644 encoder->disable_clock = icl_ddi_combo_disable_clock; 4645 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 4646 encoder->get_config = icl_ddi_combo_get_config; 4647 } 4648 } else if (IS_CANNONLAKE(dev_priv)) { 4649 encoder->enable_clock = cnl_ddi_enable_clock; 4650 encoder->disable_clock = cnl_ddi_disable_clock; 4651 encoder->is_clock_enabled = cnl_ddi_is_clock_enabled; 4652 encoder->get_config = cnl_ddi_get_config; 4653 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 4654 /* BXT/GLK have fixed PLL->port mapping */ 4655 encoder->get_config = bxt_ddi_get_config; 4656 } else if (DISPLAY_VER(dev_priv) == 9) { 4657 encoder->enable_clock = skl_ddi_enable_clock; 4658 encoder->disable_clock = skl_ddi_disable_clock; 4659 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 4660 encoder->get_config = skl_ddi_get_config; 4661 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 4662 encoder->enable_clock = hsw_ddi_enable_clock; 4663 encoder->disable_clock = hsw_ddi_disable_clock; 4664 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 4665 encoder->get_config = hsw_ddi_get_config; 4666 } 4667 4668 intel_ddi_buf_trans_init(encoder); 4669 4670 if (DISPLAY_VER(dev_priv) >= 13) 4671 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 4672 else if (IS_DG1(dev_priv)) 4673 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 4674 else if (IS_ROCKETLAKE(dev_priv)) 4675 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 4676 else if (DISPLAY_VER(dev_priv) >= 12) 4677 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 4678 else if (IS_JSL_EHL(dev_priv)) 4679 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 4680 else if (DISPLAY_VER(dev_priv) == 11) 4681 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 4682 else if (IS_CANNONLAKE(dev_priv)) 4683 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port); 4684 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 4685 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 4686 else 4687 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 4688 4689 if (DISPLAY_VER(dev_priv) >= 11) 4690 dig_port->saved_port_bits = 4691 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4692 & DDI_BUF_PORT_REVERSAL; 4693 else 4694 dig_port->saved_port_bits = 4695 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 4696 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 4697 4698 if (intel_bios_is_lane_reversal_needed(dev_priv, port)) 4699 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 4700 4701 dig_port->dp.output_reg = INVALID_MMIO_REG; 4702 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 4703 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 4704 4705 if (intel_phy_is_tc(dev_priv, phy)) { 4706 bool is_legacy = 4707 !intel_bios_encoder_supports_typec_usb(devdata) && 4708 !intel_bios_encoder_supports_tbt(devdata); 4709 4710 intel_tc_port_init(dig_port, is_legacy); 4711 4712 encoder->update_prepare = intel_ddi_update_prepare; 4713 encoder->update_complete = intel_ddi_update_complete; 4714 } 4715 4716 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 4717 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + 4718 port - PORT_A; 4719 4720 if (init_dp) { 4721 if (!intel_ddi_init_dp_connector(dig_port)) 4722 goto err; 4723 4724 dig_port->hpd_pulse = intel_dp_hpd_pulse; 4725 4726 /* Splitter enable for eDP MSO is limited to certain pipes. */ 4727 if (dig_port->dp.mso_link_count) { 4728 encoder->pipe_mask = BIT(PIPE_A); 4729 if (IS_ALDERLAKE_P(dev_priv)) 4730 encoder->pipe_mask |= BIT(PIPE_B); 4731 } 4732 } 4733 4734 /* In theory we don't need the encoder->type check, but leave it just in 4735 * case we have some really bad VBTs... */ 4736 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 4737 if (!intel_ddi_init_hdmi_connector(dig_port)) 4738 goto err; 4739 } 4740 4741 if (DISPLAY_VER(dev_priv) >= 11) { 4742 if (intel_phy_is_tc(dev_priv, phy)) 4743 dig_port->connected = intel_tc_port_connected; 4744 else 4745 dig_port->connected = lpt_digital_port_connected; 4746 } else if (DISPLAY_VER(dev_priv) >= 8) { 4747 if (port == PORT_A || IS_GEMINILAKE(dev_priv) || 4748 IS_BROXTON(dev_priv)) 4749 dig_port->connected = bdw_digital_port_connected; 4750 else 4751 dig_port->connected = lpt_digital_port_connected; 4752 } else { 4753 if (port == PORT_A) 4754 dig_port->connected = hsw_digital_port_connected; 4755 else 4756 dig_port->connected = lpt_digital_port_connected; 4757 } 4758 4759 intel_infoframe_init(dig_port); 4760 4761 return; 4762 4763 err: 4764 drm_encoder_cleanup(&encoder->base); 4765 kfree(dig_port); 4766 } 4767