1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <linux/iopoll.h> 29 #include <linux/string_helpers.h> 30 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_privacy_screen_consumer.h> 33 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "icl_dsi.h" 37 #include "intel_audio.h" 38 #include "intel_audio_regs.h" 39 #include "intel_backlight.h" 40 #include "intel_combo_phy.h" 41 #include "intel_combo_phy_regs.h" 42 #include "intel_connector.h" 43 #include "intel_crtc.h" 44 #include "intel_cx0_phy.h" 45 #include "intel_cx0_phy_regs.h" 46 #include "intel_ddi.h" 47 #include "intel_ddi_buf_trans.h" 48 #include "intel_de.h" 49 #include "intel_display_power.h" 50 #include "intel_display_types.h" 51 #include "intel_dkl_phy.h" 52 #include "intel_dkl_phy_regs.h" 53 #include "intel_dp.h" 54 #include "intel_dp_aux.h" 55 #include "intel_dp_link_training.h" 56 #include "intel_dp_mst.h" 57 #include "intel_dp_tunnel.h" 58 #include "intel_dpio_phy.h" 59 #include "intel_dsi.h" 60 #include "intel_fdi.h" 61 #include "intel_fifo_underrun.h" 62 #include "intel_gmbus.h" 63 #include "intel_hdcp.h" 64 #include "intel_hdmi.h" 65 #include "intel_hotplug.h" 66 #include "intel_hti.h" 67 #include "intel_lspcon.h" 68 #include "intel_mg_phy_regs.h" 69 #include "intel_modeset_lock.h" 70 #include "intel_pps.h" 71 #include "intel_psr.h" 72 #include "intel_quirks.h" 73 #include "intel_snps_phy.h" 74 #include "intel_tc.h" 75 #include "intel_vdsc.h" 76 #include "intel_vdsc_regs.h" 77 #include "skl_scaler.h" 78 #include "skl_universal_plane.h" 79 80 static const u8 index_to_dp_signal_levels[] = { 81 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 82 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, 83 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2, 84 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3, 85 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0, 86 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1, 87 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2, 88 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0, 89 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1, 90 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0, 91 }; 92 93 static int intel_ddi_hdmi_level(struct intel_encoder *encoder, 94 const struct intel_ddi_buf_trans *trans) 95 { 96 int level; 97 98 level = intel_bios_hdmi_level_shift(encoder->devdata); 99 if (level < 0) 100 level = trans->hdmi_default_entry; 101 102 return level; 103 } 104 105 static bool has_buf_trans_select(struct drm_i915_private *i915) 106 { 107 return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915); 108 } 109 110 static bool has_iboost(struct drm_i915_private *i915) 111 { 112 return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915); 113 } 114 115 /* 116 * Starting with Haswell, DDI port buffers must be programmed with correct 117 * values in advance. This function programs the correct values for 118 * DP/eDP/FDI use cases. 119 */ 120 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 121 const struct intel_crtc_state *crtc_state) 122 { 123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 124 u32 iboost_bit = 0; 125 int i, n_entries; 126 enum port port = encoder->port; 127 const struct intel_ddi_buf_trans *trans; 128 129 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 130 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 131 return; 132 133 /* If we're boosting the current, set bit 31 of trans1 */ 134 if (has_iboost(dev_priv) && 135 intel_bios_dp_boost_level(encoder->devdata)) 136 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 137 138 for (i = 0; i < n_entries; i++) { 139 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), 140 trans->entries[i].hsw.trans1 | iboost_bit); 141 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), 142 trans->entries[i].hsw.trans2); 143 } 144 } 145 146 /* 147 * Starting with Haswell, DDI port buffers must be programmed with correct 148 * values in advance. This function programs the correct values for 149 * HDMI/DVI use cases. 150 */ 151 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 152 const struct intel_crtc_state *crtc_state) 153 { 154 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 155 int level = intel_ddi_level(encoder, crtc_state, 0); 156 u32 iboost_bit = 0; 157 int n_entries; 158 enum port port = encoder->port; 159 const struct intel_ddi_buf_trans *trans; 160 161 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 162 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 163 return; 164 165 /* If we're boosting the current, set bit 31 of trans1 */ 166 if (has_iboost(dev_priv) && 167 intel_bios_hdmi_boost_level(encoder->devdata)) 168 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; 169 170 /* Entry 9 is for HDMI: */ 171 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), 172 trans->entries[level].hsw.trans1 | iboost_bit); 173 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), 174 trans->entries[level].hsw.trans2); 175 } 176 177 static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) 178 { 179 int ret; 180 181 /* FIXME: find out why Bspec's 100us timeout is too short */ 182 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & 183 XELPDP_PORT_BUF_PHY_IDLE), 10000); 184 if (ret) 185 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", 186 port_name(port)); 187 } 188 189 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 190 enum port port) 191 { 192 if (IS_BROXTON(dev_priv)) { 193 udelay(16); 194 return; 195 } 196 197 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 198 DDI_BUF_IS_IDLE), 8)) 199 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", 200 port_name(port)); 201 } 202 203 static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 204 { 205 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 206 enum port port = encoder->port; 207 int timeout_us; 208 int ret; 209 210 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ 211 if (DISPLAY_VER(dev_priv) < 10) { 212 usleep_range(518, 1000); 213 return; 214 } 215 216 if (DISPLAY_VER(dev_priv) >= 14) { 217 timeout_us = 10000; 218 } else if (IS_DG2(dev_priv)) { 219 timeout_us = 1200; 220 } else if (DISPLAY_VER(dev_priv) >= 12) { 221 if (intel_encoder_is_tc(encoder)) 222 timeout_us = 3000; 223 else 224 timeout_us = 1000; 225 } else { 226 timeout_us = 500; 227 } 228 229 if (DISPLAY_VER(dev_priv) >= 14) 230 ret = _wait_for(!(intel_de_read(dev_priv, 231 XELPDP_PORT_BUF_CTL1(dev_priv, port)) & 232 XELPDP_PORT_BUF_PHY_IDLE), 233 timeout_us, 10, 10); 234 else 235 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 236 timeout_us, 10, 10); 237 238 if (ret) 239 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", 240 port_name(port)); 241 } 242 243 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 244 { 245 switch (pll->info->id) { 246 case DPLL_ID_WRPLL1: 247 return PORT_CLK_SEL_WRPLL1; 248 case DPLL_ID_WRPLL2: 249 return PORT_CLK_SEL_WRPLL2; 250 case DPLL_ID_SPLL: 251 return PORT_CLK_SEL_SPLL; 252 case DPLL_ID_LCPLL_810: 253 return PORT_CLK_SEL_LCPLL_810; 254 case DPLL_ID_LCPLL_1350: 255 return PORT_CLK_SEL_LCPLL_1350; 256 case DPLL_ID_LCPLL_2700: 257 return PORT_CLK_SEL_LCPLL_2700; 258 default: 259 MISSING_CASE(pll->info->id); 260 return PORT_CLK_SEL_NONE; 261 } 262 } 263 264 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, 265 const struct intel_crtc_state *crtc_state) 266 { 267 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 268 int clock = crtc_state->port_clock; 269 const enum intel_dpll_id id = pll->info->id; 270 271 switch (id) { 272 default: 273 /* 274 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used 275 * here, so do warn if this get passed in 276 */ 277 MISSING_CASE(id); 278 return DDI_CLK_SEL_NONE; 279 case DPLL_ID_ICL_TBTPLL: 280 switch (clock) { 281 case 162000: 282 return DDI_CLK_SEL_TBT_162; 283 case 270000: 284 return DDI_CLK_SEL_TBT_270; 285 case 540000: 286 return DDI_CLK_SEL_TBT_540; 287 case 810000: 288 return DDI_CLK_SEL_TBT_810; 289 default: 290 MISSING_CASE(clock); 291 return DDI_CLK_SEL_NONE; 292 } 293 case DPLL_ID_ICL_MGPLL1: 294 case DPLL_ID_ICL_MGPLL2: 295 case DPLL_ID_ICL_MGPLL3: 296 case DPLL_ID_ICL_MGPLL4: 297 case DPLL_ID_TGL_MGPLL5: 298 case DPLL_ID_TGL_MGPLL6: 299 return DDI_CLK_SEL_MG; 300 } 301 } 302 303 static u32 ddi_buf_phy_link_rate(int port_clock) 304 { 305 switch (port_clock) { 306 case 162000: 307 return DDI_BUF_PHY_LINK_RATE(0); 308 case 216000: 309 return DDI_BUF_PHY_LINK_RATE(4); 310 case 243000: 311 return DDI_BUF_PHY_LINK_RATE(5); 312 case 270000: 313 return DDI_BUF_PHY_LINK_RATE(1); 314 case 324000: 315 return DDI_BUF_PHY_LINK_RATE(6); 316 case 432000: 317 return DDI_BUF_PHY_LINK_RATE(7); 318 case 540000: 319 return DDI_BUF_PHY_LINK_RATE(2); 320 case 810000: 321 return DDI_BUF_PHY_LINK_RATE(3); 322 default: 323 MISSING_CASE(port_clock); 324 return DDI_BUF_PHY_LINK_RATE(0); 325 } 326 } 327 328 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, 329 const struct intel_crtc_state *crtc_state) 330 { 331 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 332 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 333 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 334 335 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 336 intel_dp->DP = dig_port->saved_port_bits | 337 DDI_PORT_WIDTH(crtc_state->lane_count) | 338 DDI_BUF_TRANS_SELECT(0); 339 340 if (DISPLAY_VER(i915) >= 14) { 341 if (intel_dp_is_uhbr(crtc_state)) 342 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; 343 else 344 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; 345 } 346 347 if (IS_ALDERLAKE_P(i915) && intel_encoder_is_tc(encoder)) { 348 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); 349 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) 350 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 351 } 352 } 353 354 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, 355 enum port port) 356 { 357 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; 358 359 switch (val) { 360 case DDI_CLK_SEL_NONE: 361 return 0; 362 case DDI_CLK_SEL_TBT_162: 363 return 162000; 364 case DDI_CLK_SEL_TBT_270: 365 return 270000; 366 case DDI_CLK_SEL_TBT_540: 367 return 540000; 368 case DDI_CLK_SEL_TBT_810: 369 return 810000; 370 default: 371 MISSING_CASE(val); 372 return 0; 373 } 374 } 375 376 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 377 { 378 /* CRT dotclock is determined via other means */ 379 if (pipe_config->has_pch_encoder) 380 return; 381 382 pipe_config->hw.adjusted_mode.crtc_clock = 383 intel_crtc_dotclock(pipe_config); 384 } 385 386 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 387 const struct drm_connector_state *conn_state) 388 { 389 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 390 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 391 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 392 u32 temp; 393 394 if (!intel_crtc_has_dp_encoder(crtc_state)) 395 return; 396 397 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); 398 399 temp = DP_MSA_MISC_SYNC_CLOCK; 400 401 switch (crtc_state->pipe_bpp) { 402 case 18: 403 temp |= DP_MSA_MISC_6_BPC; 404 break; 405 case 24: 406 temp |= DP_MSA_MISC_8_BPC; 407 break; 408 case 30: 409 temp |= DP_MSA_MISC_10_BPC; 410 break; 411 case 36: 412 temp |= DP_MSA_MISC_12_BPC; 413 break; 414 default: 415 MISSING_CASE(crtc_state->pipe_bpp); 416 break; 417 } 418 419 /* nonsense combination */ 420 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && 421 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 422 423 if (crtc_state->limited_color_range) 424 temp |= DP_MSA_MISC_COLOR_CEA_RGB; 425 426 /* 427 * As per DP 1.2 spec section 2.3.4.3 while sending 428 * YCBCR 444 signals we should program MSA MISC1/0 fields with 429 * colorspace information. 430 */ 431 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 432 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; 433 434 /* 435 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 436 * of Color Encoding Format and Content Color Gamut] while sending 437 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields 438 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. 439 */ 440 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 441 temp |= DP_MSA_MISC_COLOR_VSC_SDP; 442 443 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); 444 } 445 446 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) 447 { 448 if (master_transcoder == TRANSCODER_EDP) 449 return 0; 450 else 451 return master_transcoder + 1; 452 } 453 454 static void 455 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 456 const struct intel_crtc_state *crtc_state) 457 { 458 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 459 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 460 u32 val = 0; 461 462 if (intel_dp_is_uhbr(crtc_state)) 463 val = TRANS_DP2_128B132B_CHANNEL_CODING; 464 465 intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 466 } 467 468 /* 469 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. 470 * 471 * Only intended to be used by intel_ddi_enable_transcoder_func() and 472 * intel_ddi_config_transcoder_func(). 473 */ 474 static u32 475 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, 476 const struct intel_crtc_state *crtc_state) 477 { 478 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 479 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 480 enum pipe pipe = crtc->pipe; 481 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 482 enum port port = encoder->port; 483 u32 temp; 484 485 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 486 temp = TRANS_DDI_FUNC_ENABLE; 487 if (DISPLAY_VER(dev_priv) >= 12) 488 temp |= TGL_TRANS_DDI_SELECT_PORT(port); 489 else 490 temp |= TRANS_DDI_SELECT_PORT(port); 491 492 switch (crtc_state->pipe_bpp) { 493 default: 494 MISSING_CASE(crtc_state->pipe_bpp); 495 fallthrough; 496 case 18: 497 temp |= TRANS_DDI_BPC_6; 498 break; 499 case 24: 500 temp |= TRANS_DDI_BPC_8; 501 break; 502 case 30: 503 temp |= TRANS_DDI_BPC_10; 504 break; 505 case 36: 506 temp |= TRANS_DDI_BPC_12; 507 break; 508 } 509 510 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 511 temp |= TRANS_DDI_PVSYNC; 512 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 513 temp |= TRANS_DDI_PHSYNC; 514 515 if (cpu_transcoder == TRANSCODER_EDP) { 516 switch (pipe) { 517 default: 518 MISSING_CASE(pipe); 519 fallthrough; 520 case PIPE_A: 521 /* On Haswell, can only use the always-on power well for 522 * eDP when not using the panel fitter, and when not 523 * using motion blur mitigation (which we don't 524 * support). */ 525 if (crtc_state->pch_pfit.force_thru) 526 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 527 else 528 temp |= TRANS_DDI_EDP_INPUT_A_ON; 529 break; 530 case PIPE_B: 531 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 532 break; 533 case PIPE_C: 534 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 535 break; 536 } 537 } 538 539 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 540 if (crtc_state->has_hdmi_sink) 541 temp |= TRANS_DDI_MODE_SELECT_HDMI; 542 else 543 temp |= TRANS_DDI_MODE_SELECT_DVI; 544 545 if (crtc_state->hdmi_scrambling) 546 temp |= TRANS_DDI_HDMI_SCRAMBLING; 547 if (crtc_state->hdmi_high_tmds_clock_ratio) 548 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE; 549 if (DISPLAY_VER(dev_priv) >= 14) 550 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); 551 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 552 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 553 temp |= (crtc_state->fdi_lanes - 1) << 1; 554 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 555 if (intel_dp_is_uhbr(crtc_state)) 556 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B; 557 else 558 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 559 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 560 561 if (DISPLAY_VER(dev_priv) >= 12) { 562 enum transcoder master; 563 564 master = crtc_state->mst_master_transcoder; 565 drm_WARN_ON(&dev_priv->drm, 566 master == INVALID_TRANSCODER); 567 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); 568 } 569 } else { 570 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); 572 } 573 574 if (IS_DISPLAY_VER(dev_priv, 8, 10) && 575 crtc_state->master_transcoder != INVALID_TRANSCODER) { 576 u8 master_select = 577 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); 578 579 temp |= TRANS_DDI_PORT_SYNC_ENABLE | 580 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select); 581 } 582 583 return temp; 584 } 585 586 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 587 const struct intel_crtc_state *crtc_state) 588 { 589 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 590 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 591 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 592 593 if (DISPLAY_VER(dev_priv) >= 11) { 594 enum transcoder master_transcoder = crtc_state->master_transcoder; 595 u32 ctl2 = 0; 596 597 if (master_transcoder != INVALID_TRANSCODER) { 598 u8 master_select = 599 bdw_trans_port_sync_master_select(master_transcoder); 600 601 ctl2 |= PORT_SYNC_MODE_ENABLE | 602 PORT_SYNC_MODE_MASTER_SELECT(master_select); 603 } 604 605 intel_de_write(dev_priv, 606 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); 607 } 608 609 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 610 intel_ddi_transcoder_func_reg_val_get(encoder, 611 crtc_state)); 612 } 613 614 /* 615 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 616 * bit. 617 */ 618 static void 619 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 620 const struct intel_crtc_state *crtc_state) 621 { 622 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 623 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 624 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 625 u32 ctl; 626 627 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 628 ctl &= ~TRANS_DDI_FUNC_ENABLE; 629 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 630 } 631 632 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 633 { 634 struct intel_display *display = to_intel_display(crtc_state); 635 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 636 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 637 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 638 u32 ctl; 639 640 if (DISPLAY_VER(dev_priv) >= 11) 641 intel_de_write(dev_priv, 642 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); 643 644 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 645 646 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); 647 648 ctl &= ~TRANS_DDI_FUNC_ENABLE; 649 650 if (IS_DISPLAY_VER(dev_priv, 8, 10)) 651 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE | 652 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); 653 654 if (DISPLAY_VER(dev_priv) >= 12) { 655 if (!intel_dp_mst_is_master_trans(crtc_state)) { 656 ctl &= ~(TGL_TRANS_DDI_PORT_MASK | 657 TRANS_DDI_MODE_SELECT_MASK); 658 } 659 } else { 660 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); 661 } 662 663 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); 664 665 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 666 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 667 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); 668 /* Quirk time at 100ms for reliable operation */ 669 msleep(100); 670 } 671 } 672 673 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, 674 enum transcoder cpu_transcoder, 675 bool enable, u32 hdcp_mask) 676 { 677 struct drm_device *dev = intel_encoder->base.dev; 678 struct drm_i915_private *dev_priv = to_i915(dev); 679 intel_wakeref_t wakeref; 680 int ret = 0; 681 682 wakeref = intel_display_power_get_if_enabled(dev_priv, 683 intel_encoder->power_domain); 684 if (drm_WARN_ON(dev, !wakeref)) 685 return -ENXIO; 686 687 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 688 hdcp_mask, enable ? hdcp_mask : 0); 689 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 690 return ret; 691 } 692 693 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 694 { 695 struct drm_device *dev = intel_connector->base.dev; 696 struct drm_i915_private *dev_priv = to_i915(dev); 697 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 698 int type = intel_connector->base.connector_type; 699 enum port port = encoder->port; 700 enum transcoder cpu_transcoder; 701 intel_wakeref_t wakeref; 702 enum pipe pipe = 0; 703 u32 tmp; 704 bool ret; 705 706 wakeref = intel_display_power_get_if_enabled(dev_priv, 707 encoder->power_domain); 708 if (!wakeref) 709 return false; 710 711 if (!encoder->get_hw_state(encoder, &pipe)) { 712 ret = false; 713 goto out; 714 } 715 716 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 717 cpu_transcoder = TRANSCODER_EDP; 718 else 719 cpu_transcoder = (enum transcoder) pipe; 720 721 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 722 723 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 724 case TRANS_DDI_MODE_SELECT_HDMI: 725 case TRANS_DDI_MODE_SELECT_DVI: 726 ret = type == DRM_MODE_CONNECTOR_HDMIA; 727 break; 728 729 case TRANS_DDI_MODE_SELECT_DP_SST: 730 ret = type == DRM_MODE_CONNECTOR_eDP || 731 type == DRM_MODE_CONNECTOR_DisplayPort; 732 break; 733 734 case TRANS_DDI_MODE_SELECT_DP_MST: 735 /* if the transcoder is in MST state then 736 * connector isn't connected */ 737 ret = false; 738 break; 739 740 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 741 if (HAS_DP20(dev_priv)) 742 /* 128b/132b */ 743 ret = false; 744 else 745 /* FDI */ 746 ret = type == DRM_MODE_CONNECTOR_VGA; 747 break; 748 749 default: 750 ret = false; 751 break; 752 } 753 754 out: 755 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 756 757 return ret; 758 } 759 760 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 761 u8 *pipe_mask, bool *is_dp_mst) 762 { 763 struct drm_device *dev = encoder->base.dev; 764 struct drm_i915_private *dev_priv = to_i915(dev); 765 enum port port = encoder->port; 766 intel_wakeref_t wakeref; 767 enum pipe p; 768 u32 tmp; 769 u8 mst_pipe_mask; 770 771 *pipe_mask = 0; 772 *is_dp_mst = false; 773 774 wakeref = intel_display_power_get_if_enabled(dev_priv, 775 encoder->power_domain); 776 if (!wakeref) 777 return; 778 779 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 780 if (!(tmp & DDI_BUF_CTL_ENABLE)) 781 goto out; 782 783 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { 784 tmp = intel_de_read(dev_priv, 785 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 786 787 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 788 default: 789 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK); 790 fallthrough; 791 case TRANS_DDI_EDP_INPUT_A_ON: 792 case TRANS_DDI_EDP_INPUT_A_ONOFF: 793 *pipe_mask = BIT(PIPE_A); 794 break; 795 case TRANS_DDI_EDP_INPUT_B_ONOFF: 796 *pipe_mask = BIT(PIPE_B); 797 break; 798 case TRANS_DDI_EDP_INPUT_C_ONOFF: 799 *pipe_mask = BIT(PIPE_C); 800 break; 801 } 802 803 goto out; 804 } 805 806 mst_pipe_mask = 0; 807 for_each_pipe(dev_priv, p) { 808 enum transcoder cpu_transcoder = (enum transcoder)p; 809 unsigned int port_mask, ddi_select; 810 intel_wakeref_t trans_wakeref; 811 812 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 813 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 814 if (!trans_wakeref) 815 continue; 816 817 if (DISPLAY_VER(dev_priv) >= 12) { 818 port_mask = TGL_TRANS_DDI_PORT_MASK; 819 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port); 820 } else { 821 port_mask = TRANS_DDI_PORT_MASK; 822 ddi_select = TRANS_DDI_SELECT_PORT(port); 823 } 824 825 tmp = intel_de_read(dev_priv, 826 TRANS_DDI_FUNC_CTL(cpu_transcoder)); 827 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), 828 trans_wakeref); 829 830 if ((tmp & port_mask) != ddi_select) 831 continue; 832 833 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 834 (HAS_DP20(dev_priv) && 835 (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 836 mst_pipe_mask |= BIT(p); 837 838 *pipe_mask |= BIT(p); 839 } 840 841 if (!*pipe_mask) 842 drm_dbg_kms(&dev_priv->drm, 843 "No pipe for [ENCODER:%d:%s] found\n", 844 encoder->base.base.id, encoder->base.name); 845 846 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { 847 drm_dbg_kms(&dev_priv->drm, 848 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n", 849 encoder->base.base.id, encoder->base.name, 850 *pipe_mask); 851 *pipe_mask = BIT(ffs(*pipe_mask) - 1); 852 } 853 854 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) 855 drm_dbg_kms(&dev_priv->drm, 856 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", 857 encoder->base.base.id, encoder->base.name, 858 *pipe_mask, mst_pipe_mask); 859 else 860 *is_dp_mst = mst_pipe_mask; 861 862 out: 863 if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) { 864 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); 865 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | 866 BXT_PHY_LANE_POWERDOWN_ACK | 867 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) 868 drm_err(&dev_priv->drm, 869 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n", 870 encoder->base.base.id, encoder->base.name, tmp); 871 } 872 873 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 874 } 875 876 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 877 enum pipe *pipe) 878 { 879 u8 pipe_mask; 880 bool is_mst; 881 882 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 883 884 if (is_mst || !pipe_mask) 885 return false; 886 887 *pipe = ffs(pipe_mask) - 1; 888 889 return true; 890 } 891 892 static enum intel_display_power_domain 893 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, 894 const struct intel_crtc_state *crtc_state) 895 { 896 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 897 898 /* 899 * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with 900 * DC states enabled at the same time, while for driver initiated AUX 901 * transfers we need the same AUX IOs to be powered but with DC states 902 * disabled. Accordingly use the AUX_IO_<port> power domain here which 903 * leaves DC states enabled. 904 * 905 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require 906 * AUX IO to be enabled, but all these require DC_OFF to be enabled as 907 * well, so we can acquire a wider AUX_<port> power domain reference 908 * instead of a specific AUX_IO_<port> reference without powering up any 909 * extra wells. 910 */ 911 if (intel_encoder_can_psr(&dig_port->base)) 912 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); 913 else if (DISPLAY_VER(i915) < 14 && 914 (intel_crtc_has_dp_encoder(crtc_state) || 915 intel_encoder_is_tc(&dig_port->base))) 916 return intel_aux_power_domain(dig_port); 917 else 918 return POWER_DOMAIN_INVALID; 919 } 920 921 static void 922 main_link_aux_power_domain_get(struct intel_digital_port *dig_port, 923 const struct intel_crtc_state *crtc_state) 924 { 925 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 926 enum intel_display_power_domain domain = 927 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 928 929 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); 930 931 if (domain == POWER_DOMAIN_INVALID) 932 return; 933 934 dig_port->aux_wakeref = intel_display_power_get(i915, domain); 935 } 936 937 static void 938 main_link_aux_power_domain_put(struct intel_digital_port *dig_port, 939 const struct intel_crtc_state *crtc_state) 940 { 941 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 942 enum intel_display_power_domain domain = 943 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 944 intel_wakeref_t wf; 945 946 wf = fetch_and_zero(&dig_port->aux_wakeref); 947 if (!wf) 948 return; 949 950 intel_display_power_put(i915, domain, wf); 951 } 952 953 static void intel_ddi_get_power_domains(struct intel_encoder *encoder, 954 struct intel_crtc_state *crtc_state) 955 { 956 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 957 struct intel_digital_port *dig_port; 958 959 /* 960 * TODO: Add support for MST encoders. Atm, the following should never 961 * happen since fake-MST encoders don't set their get_power_domains() 962 * hook. 963 */ 964 if (drm_WARN_ON(&dev_priv->drm, 965 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) 966 return; 967 968 dig_port = enc_to_dig_port(encoder); 969 970 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 971 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 972 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 973 dig_port->ddi_io_power_domain); 974 } 975 976 main_link_aux_power_domain_get(dig_port, crtc_state); 977 } 978 979 void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder, 980 const struct intel_crtc_state *crtc_state) 981 { 982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 983 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 984 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 985 enum phy phy = intel_encoder_to_phy(encoder); 986 u32 val; 987 988 if (cpu_transcoder == TRANSCODER_EDP) 989 return; 990 991 if (DISPLAY_VER(dev_priv) >= 13) 992 val = TGL_TRANS_CLK_SEL_PORT(phy); 993 else if (DISPLAY_VER(dev_priv) >= 12) 994 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); 995 else 996 val = TRANS_CLK_SEL_PORT(encoder->port); 997 998 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 999 } 1000 1001 void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state) 1002 { 1003 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1004 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1005 u32 val; 1006 1007 if (cpu_transcoder == TRANSCODER_EDP) 1008 return; 1009 1010 if (DISPLAY_VER(dev_priv) >= 12) 1011 val = TGL_TRANS_CLK_SEL_DISABLED; 1012 else 1013 val = TRANS_CLK_SEL_DISABLED; 1014 1015 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val); 1016 } 1017 1018 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, 1019 enum port port, u8 iboost) 1020 { 1021 u32 tmp; 1022 1023 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); 1024 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); 1025 if (iboost) 1026 tmp |= iboost << BALANCE_LEG_SHIFT(port); 1027 else 1028 tmp |= BALANCE_LEG_DISABLE(port); 1029 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); 1030 } 1031 1032 static void skl_ddi_set_iboost(struct intel_encoder *encoder, 1033 const struct intel_crtc_state *crtc_state, 1034 int level) 1035 { 1036 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1037 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1038 u8 iboost; 1039 1040 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1041 iboost = intel_bios_hdmi_boost_level(encoder->devdata); 1042 else 1043 iboost = intel_bios_dp_boost_level(encoder->devdata); 1044 1045 if (iboost == 0) { 1046 const struct intel_ddi_buf_trans *trans; 1047 int n_entries; 1048 1049 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1050 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1051 return; 1052 1053 iboost = trans->entries[level].hsw.i_boost; 1054 } 1055 1056 /* Make sure that the requested I_boost is valid */ 1057 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 1058 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); 1059 return; 1060 } 1061 1062 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); 1063 1064 if (encoder->port == PORT_A && dig_port->max_lanes == 4) 1065 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); 1066 } 1067 1068 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 1069 const struct intel_crtc_state *crtc_state) 1070 { 1071 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1073 int n_entries; 1074 1075 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1076 1077 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) 1078 n_entries = 1; 1079 if (drm_WARN_ON(&dev_priv->drm, 1080 n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) 1081 n_entries = ARRAY_SIZE(index_to_dp_signal_levels); 1082 1083 return index_to_dp_signal_levels[n_entries - 1] & 1084 DP_TRAIN_VOLTAGE_SWING_MASK; 1085 } 1086 1087 /* 1088 * We assume that the full set of pre-emphasis values can be 1089 * used on all DDI platforms. Should that change we need to 1090 * rethink this code. 1091 */ 1092 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) 1093 { 1094 return DP_TRAIN_PRE_EMPH_LEVEL_3; 1095 } 1096 1097 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, 1098 int lane) 1099 { 1100 if (crtc_state->port_clock > 600000) 1101 return 0; 1102 1103 if (crtc_state->lane_count == 4) 1104 return lane >= 1 ? LOADGEN_SELECT : 0; 1105 else 1106 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0; 1107 } 1108 1109 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, 1110 const struct intel_crtc_state *crtc_state) 1111 { 1112 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1113 const struct intel_ddi_buf_trans *trans; 1114 enum phy phy = intel_encoder_to_phy(encoder); 1115 int n_entries, ln; 1116 u32 val; 1117 1118 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1119 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1120 return; 1121 1122 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { 1123 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1124 1125 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED; 1126 intel_dp->hobl_active = is_hobl_buf_trans(trans); 1127 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, 1128 intel_dp->hobl_active ? val : 0); 1129 } 1130 1131 /* Set PORT_TX_DW5 */ 1132 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1133 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | 1134 TAP2_DISABLE | TAP3_DISABLE); 1135 val |= SCALING_MODE_SEL(0x2); 1136 val |= RTERM_SELECT(0x6); 1137 val |= TAP3_DISABLE; 1138 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1139 1140 /* Program PORT_TX_DW2 */ 1141 for (ln = 0; ln < 4; ln++) { 1142 int level = intel_ddi_level(encoder, crtc_state, ln); 1143 1144 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), 1145 SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK, 1146 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | 1147 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | 1148 RCOMP_SCALAR(0x98)); 1149 } 1150 1151 /* Program PORT_TX_DW4 */ 1152 /* We cannot write to GRP. It would overwrite individual loadgen. */ 1153 for (ln = 0; ln < 4; ln++) { 1154 int level = intel_ddi_level(encoder, crtc_state, ln); 1155 1156 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1157 POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK, 1158 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | 1159 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | 1160 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); 1161 } 1162 1163 /* Program PORT_TX_DW7 */ 1164 for (ln = 0; ln < 4; ln++) { 1165 int level = intel_ddi_level(encoder, crtc_state, ln); 1166 1167 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), 1168 N_SCALAR_MASK, 1169 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); 1170 } 1171 } 1172 1173 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, 1174 const struct intel_crtc_state *crtc_state) 1175 { 1176 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1177 enum phy phy = intel_encoder_to_phy(encoder); 1178 u32 val; 1179 int ln; 1180 1181 /* 1182 * 1. If port type is eDP or DP, 1183 * set PORT_PCS_DW1 cmnkeeper_enable to 1b, 1184 * else clear to 0b. 1185 */ 1186 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); 1187 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1188 val &= ~COMMON_KEEPER_EN; 1189 else 1190 val |= COMMON_KEEPER_EN; 1191 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); 1192 1193 /* 2. Program loadgen select */ 1194 /* 1195 * Program PORT_TX_DW4 depending on Bit rate and used lanes 1196 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) 1197 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) 1198 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) 1199 */ 1200 for (ln = 0; ln < 4; ln++) { 1201 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), 1202 LOADGEN_SELECT, 1203 icl_combo_phy_loadgen_select(crtc_state, ln)); 1204 } 1205 1206 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ 1207 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 1208 0, SUS_CLOCK_CONFIG); 1209 1210 /* 4. Clear training enable to change swing values */ 1211 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1212 val &= ~TX_TRAINING_EN; 1213 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1214 1215 /* 5. Program swing and de-emphasis */ 1216 icl_ddi_combo_vswing_program(encoder, crtc_state); 1217 1218 /* 6. Set training enable to trigger update */ 1219 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); 1220 val |= TX_TRAINING_EN; 1221 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); 1222 } 1223 1224 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, 1225 const struct intel_crtc_state *crtc_state) 1226 { 1227 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1228 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1229 const struct intel_ddi_buf_trans *trans; 1230 int n_entries, ln; 1231 1232 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1233 return; 1234 1235 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1236 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1237 return; 1238 1239 for (ln = 0; ln < 2; ln++) { 1240 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), 1241 CRI_USE_FS32, 0); 1242 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), 1243 CRI_USE_FS32, 0); 1244 } 1245 1246 /* Program MG_TX_SWINGCTRL with values from vswing table */ 1247 for (ln = 0; ln < 2; ln++) { 1248 int level; 1249 1250 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1251 1252 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), 1253 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1254 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1255 1256 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1257 1258 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), 1259 CRI_TXDEEMPH_OVERRIDE_17_12_MASK, 1260 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); 1261 } 1262 1263 /* Program MG_TX_DRVCTRL with values from vswing table */ 1264 for (ln = 0; ln < 2; ln++) { 1265 int level; 1266 1267 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1268 1269 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), 1270 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1271 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1272 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1273 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1274 CRI_TXDEEMPH_OVERRIDE_EN); 1275 1276 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1277 1278 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), 1279 CRI_TXDEEMPH_OVERRIDE_11_6_MASK | 1280 CRI_TXDEEMPH_OVERRIDE_5_0_MASK, 1281 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | 1282 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | 1283 CRI_TXDEEMPH_OVERRIDE_EN); 1284 1285 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ 1286 } 1287 1288 /* 1289 * Program MG_CLKHUB<LN, port being used> with value from frequency table 1290 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the 1291 * values from table for which TX1 and TX2 enabled. 1292 */ 1293 for (ln = 0; ln < 2; ln++) { 1294 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port), 1295 CFG_LOW_RATE_LKREN_EN, 1296 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); 1297 } 1298 1299 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ 1300 for (ln = 0; ln < 2; ln++) { 1301 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port), 1302 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1303 CFG_AMI_CK_DIV_OVERRIDE_EN, 1304 crtc_state->port_clock > 500000 ? 1305 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1306 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1307 1308 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port), 1309 CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK | 1310 CFG_AMI_CK_DIV_OVERRIDE_EN, 1311 crtc_state->port_clock > 500000 ? 1312 CFG_AMI_CK_DIV_OVERRIDE_VAL(1) | 1313 CFG_AMI_CK_DIV_OVERRIDE_EN : 0); 1314 } 1315 1316 /* Program MG_TX_PISO_READLOAD with values from vswing table */ 1317 for (ln = 0; ln < 2; ln++) { 1318 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), 1319 0, CRI_CALCINIT); 1320 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), 1321 0, CRI_CALCINIT); 1322 } 1323 } 1324 1325 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, 1326 const struct intel_crtc_state *crtc_state) 1327 { 1328 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1329 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1330 const struct intel_ddi_buf_trans *trans; 1331 int n_entries, ln; 1332 1333 if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 1334 return; 1335 1336 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1337 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 1338 return; 1339 1340 for (ln = 0; ln < 2; ln++) { 1341 int level; 1342 1343 intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); 1344 1345 level = intel_ddi_level(encoder, crtc_state, 2*ln+0); 1346 1347 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), 1348 DKL_TX_PRESHOOT_COEFF_MASK | 1349 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1350 DKL_TX_VSWING_CONTROL_MASK, 1351 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1352 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1353 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1354 1355 level = intel_ddi_level(encoder, crtc_state, 2*ln+1); 1356 1357 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), 1358 DKL_TX_PRESHOOT_COEFF_MASK | 1359 DKL_TX_DE_EMPAHSIS_COEFF_MASK | 1360 DKL_TX_VSWING_CONTROL_MASK, 1361 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | 1362 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | 1363 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); 1364 1365 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1366 DKL_TX_DP20BITMODE, 0); 1367 1368 if (IS_ALDERLAKE_P(dev_priv)) { 1369 u32 val; 1370 1371 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1372 if (ln == 0) { 1373 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1374 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2); 1375 } else { 1376 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3); 1377 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3); 1378 } 1379 } else { 1380 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0); 1381 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); 1382 } 1383 1384 intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), 1385 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | 1386 DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, 1387 val); 1388 } 1389 } 1390 } 1391 1392 static int translate_signal_level(struct intel_dp *intel_dp, 1393 u8 signal_levels) 1394 { 1395 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1396 int i; 1397 1398 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) { 1399 if (index_to_dp_signal_levels[i] == signal_levels) 1400 return i; 1401 } 1402 1403 drm_WARN(&i915->drm, 1, 1404 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", 1405 signal_levels); 1406 1407 return 0; 1408 } 1409 1410 static int intel_ddi_dp_level(struct intel_dp *intel_dp, 1411 const struct intel_crtc_state *crtc_state, 1412 int lane) 1413 { 1414 u8 train_set = intel_dp->train_set[lane]; 1415 1416 if (intel_dp_is_uhbr(crtc_state)) { 1417 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; 1418 } else { 1419 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1420 DP_TRAIN_PRE_EMPHASIS_MASK); 1421 1422 return translate_signal_level(intel_dp, signal_levels); 1423 } 1424 } 1425 1426 int intel_ddi_level(struct intel_encoder *encoder, 1427 const struct intel_crtc_state *crtc_state, 1428 int lane) 1429 { 1430 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1431 const struct intel_ddi_buf_trans *trans; 1432 int level, n_entries; 1433 1434 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 1435 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) 1436 return 0; 1437 1438 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1439 level = intel_ddi_hdmi_level(encoder, trans); 1440 else 1441 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, 1442 lane); 1443 1444 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) 1445 level = n_entries - 1; 1446 1447 return level; 1448 } 1449 1450 static void 1451 hsw_set_signal_levels(struct intel_encoder *encoder, 1452 const struct intel_crtc_state *crtc_state) 1453 { 1454 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1455 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1456 int level = intel_ddi_level(encoder, crtc_state, 0); 1457 enum port port = encoder->port; 1458 u32 signal_levels; 1459 1460 if (has_iboost(dev_priv)) 1461 skl_ddi_set_iboost(encoder, crtc_state, level); 1462 1463 /* HDMI ignores the rest */ 1464 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1465 return; 1466 1467 signal_levels = DDI_BUF_TRANS_SELECT(level); 1468 1469 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", 1470 signal_levels); 1471 1472 intel_dp->DP &= ~DDI_BUF_EMP_MASK; 1473 intel_dp->DP |= signal_levels; 1474 1475 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 1476 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 1477 } 1478 1479 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1480 u32 clk_sel_mask, u32 clk_sel, u32 clk_off) 1481 { 1482 mutex_lock(&i915->display.dpll.lock); 1483 1484 intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); 1485 1486 /* 1487 * "This step and the step before must be 1488 * done with separate register writes." 1489 */ 1490 intel_de_rmw(i915, reg, clk_off, 0); 1491 1492 mutex_unlock(&i915->display.dpll.lock); 1493 } 1494 1495 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg, 1496 u32 clk_off) 1497 { 1498 mutex_lock(&i915->display.dpll.lock); 1499 1500 intel_de_rmw(i915, reg, 0, clk_off); 1501 1502 mutex_unlock(&i915->display.dpll.lock); 1503 } 1504 1505 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg, 1506 u32 clk_off) 1507 { 1508 return !(intel_de_read(i915, reg) & clk_off); 1509 } 1510 1511 static struct intel_shared_dpll * 1512 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, 1513 u32 clk_sel_mask, u32 clk_sel_shift) 1514 { 1515 enum intel_dpll_id id; 1516 1517 id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; 1518 1519 return intel_get_shared_dpll_by_id(i915, id); 1520 } 1521 1522 static void adls_ddi_enable_clock(struct intel_encoder *encoder, 1523 const struct intel_crtc_state *crtc_state) 1524 { 1525 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1526 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1527 enum phy phy = intel_encoder_to_phy(encoder); 1528 1529 if (drm_WARN_ON(&i915->drm, !pll)) 1530 return; 1531 1532 _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1533 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1534 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), 1535 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1536 } 1537 1538 static void adls_ddi_disable_clock(struct intel_encoder *encoder) 1539 { 1540 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1541 enum phy phy = intel_encoder_to_phy(encoder); 1542 1543 _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy), 1544 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1545 } 1546 1547 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 1548 { 1549 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1550 enum phy phy = intel_encoder_to_phy(encoder); 1551 1552 return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy), 1553 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1554 } 1555 1556 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) 1557 { 1558 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1559 enum phy phy = intel_encoder_to_phy(encoder); 1560 1561 return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), 1562 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), 1563 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); 1564 } 1565 1566 static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 1567 const struct intel_crtc_state *crtc_state) 1568 { 1569 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1570 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1571 enum phy phy = intel_encoder_to_phy(encoder); 1572 1573 if (drm_WARN_ON(&i915->drm, !pll)) 1574 return; 1575 1576 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1577 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1578 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1579 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1580 } 1581 1582 static void rkl_ddi_disable_clock(struct intel_encoder *encoder) 1583 { 1584 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1585 enum phy phy = intel_encoder_to_phy(encoder); 1586 1587 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1588 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1589 } 1590 1591 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1592 { 1593 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1594 enum phy phy = intel_encoder_to_phy(encoder); 1595 1596 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1597 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1598 } 1599 1600 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) 1601 { 1602 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1603 enum phy phy = intel_encoder_to_phy(encoder); 1604 1605 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1606 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1607 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1608 } 1609 1610 static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 1611 const struct intel_crtc_state *crtc_state) 1612 { 1613 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1614 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1615 enum phy phy = intel_encoder_to_phy(encoder); 1616 1617 if (drm_WARN_ON(&i915->drm, !pll)) 1618 return; 1619 1620 /* 1621 * If we fail this, something went very wrong: first 2 PLLs should be 1622 * used by first 2 phys and last 2 PLLs by last phys 1623 */ 1624 if (drm_WARN_ON(&i915->drm, 1625 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || 1626 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) 1627 return; 1628 1629 _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1630 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1631 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1632 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1633 } 1634 1635 static void dg1_ddi_disable_clock(struct intel_encoder *encoder) 1636 { 1637 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1638 enum phy phy = intel_encoder_to_phy(encoder); 1639 1640 _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy), 1641 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1642 } 1643 1644 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 1645 { 1646 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1647 enum phy phy = intel_encoder_to_phy(encoder); 1648 1649 return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy), 1650 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1651 } 1652 1653 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) 1654 { 1655 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1656 enum phy phy = intel_encoder_to_phy(encoder); 1657 enum intel_dpll_id id; 1658 u32 val; 1659 1660 val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); 1661 val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 1662 val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); 1663 id = val; 1664 1665 /* 1666 * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A 1667 * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one 1668 * bit for phy C and D. 1669 */ 1670 if (phy >= PHY_C) 1671 id += DPLL_ID_DG1_DPLL2; 1672 1673 return intel_get_shared_dpll_by_id(i915, id); 1674 } 1675 1676 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 1677 const struct intel_crtc_state *crtc_state) 1678 { 1679 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1680 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1681 enum phy phy = intel_encoder_to_phy(encoder); 1682 1683 if (drm_WARN_ON(&i915->drm, !pll)) 1684 return; 1685 1686 _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0, 1687 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1688 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), 1689 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1690 } 1691 1692 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) 1693 { 1694 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1695 enum phy phy = intel_encoder_to_phy(encoder); 1696 1697 _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0, 1698 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1699 } 1700 1701 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 1702 { 1703 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1704 enum phy phy = intel_encoder_to_phy(encoder); 1705 1706 return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0, 1707 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)); 1708 } 1709 1710 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) 1711 { 1712 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1713 enum phy phy = intel_encoder_to_phy(encoder); 1714 1715 return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, 1716 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), 1717 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); 1718 } 1719 1720 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1721 const struct intel_crtc_state *crtc_state) 1722 { 1723 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1724 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1725 enum port port = encoder->port; 1726 1727 if (drm_WARN_ON(&i915->drm, !pll)) 1728 return; 1729 1730 /* 1731 * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. 1732 * MG does not exist, but the programming is required to ungate DDIC and DDID." 1733 */ 1734 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG); 1735 1736 icl_ddi_combo_enable_clock(encoder, crtc_state); 1737 } 1738 1739 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1740 { 1741 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1742 enum port port = encoder->port; 1743 1744 icl_ddi_combo_disable_clock(encoder); 1745 1746 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1747 } 1748 1749 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1750 { 1751 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1752 enum port port = encoder->port; 1753 u32 tmp; 1754 1755 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1756 1757 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1758 return false; 1759 1760 return icl_ddi_combo_is_clock_enabled(encoder); 1761 } 1762 1763 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 1764 const struct intel_crtc_state *crtc_state) 1765 { 1766 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1767 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1768 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1769 enum port port = encoder->port; 1770 1771 if (drm_WARN_ON(&i915->drm, !pll)) 1772 return; 1773 1774 intel_de_write(i915, DDI_CLK_SEL(port), 1775 icl_pll_to_ddi_clk_sel(encoder, crtc_state)); 1776 1777 mutex_lock(&i915->display.dpll.lock); 1778 1779 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1780 ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0); 1781 1782 mutex_unlock(&i915->display.dpll.lock); 1783 } 1784 1785 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) 1786 { 1787 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1788 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1789 enum port port = encoder->port; 1790 1791 mutex_lock(&i915->display.dpll.lock); 1792 1793 intel_de_rmw(i915, ICL_DPCLKA_CFGCR0, 1794 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1795 1796 mutex_unlock(&i915->display.dpll.lock); 1797 1798 intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); 1799 } 1800 1801 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 1802 { 1803 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1804 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1805 enum port port = encoder->port; 1806 u32 tmp; 1807 1808 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1809 1810 if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE) 1811 return false; 1812 1813 tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0); 1814 1815 return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)); 1816 } 1817 1818 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) 1819 { 1820 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1821 enum tc_port tc_port = intel_encoder_to_tc(encoder); 1822 enum port port = encoder->port; 1823 enum intel_dpll_id id; 1824 u32 tmp; 1825 1826 tmp = intel_de_read(i915, DDI_CLK_SEL(port)); 1827 1828 switch (tmp & DDI_CLK_SEL_MASK) { 1829 case DDI_CLK_SEL_TBT_162: 1830 case DDI_CLK_SEL_TBT_270: 1831 case DDI_CLK_SEL_TBT_540: 1832 case DDI_CLK_SEL_TBT_810: 1833 id = DPLL_ID_ICL_TBTPLL; 1834 break; 1835 case DDI_CLK_SEL_MG: 1836 id = icl_tc_port_to_pll_id(tc_port); 1837 break; 1838 default: 1839 MISSING_CASE(tmp); 1840 fallthrough; 1841 case DDI_CLK_SEL_NONE: 1842 return NULL; 1843 } 1844 1845 return intel_get_shared_dpll_by_id(i915, id); 1846 } 1847 1848 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) 1849 { 1850 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1851 enum intel_dpll_id id; 1852 1853 switch (encoder->port) { 1854 case PORT_A: 1855 id = DPLL_ID_SKL_DPLL0; 1856 break; 1857 case PORT_B: 1858 id = DPLL_ID_SKL_DPLL1; 1859 break; 1860 case PORT_C: 1861 id = DPLL_ID_SKL_DPLL2; 1862 break; 1863 default: 1864 MISSING_CASE(encoder->port); 1865 return NULL; 1866 } 1867 1868 return intel_get_shared_dpll_by_id(i915, id); 1869 } 1870 1871 static void skl_ddi_enable_clock(struct intel_encoder *encoder, 1872 const struct intel_crtc_state *crtc_state) 1873 { 1874 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1875 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1876 enum port port = encoder->port; 1877 1878 if (drm_WARN_ON(&i915->drm, !pll)) 1879 return; 1880 1881 mutex_lock(&i915->display.dpll.lock); 1882 1883 intel_de_rmw(i915, DPLL_CTRL2, 1884 DPLL_CTRL2_DDI_CLK_OFF(port) | 1885 DPLL_CTRL2_DDI_CLK_SEL_MASK(port), 1886 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | 1887 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 1888 1889 mutex_unlock(&i915->display.dpll.lock); 1890 } 1891 1892 static void skl_ddi_disable_clock(struct intel_encoder *encoder) 1893 { 1894 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1895 enum port port = encoder->port; 1896 1897 mutex_lock(&i915->display.dpll.lock); 1898 1899 intel_de_rmw(i915, DPLL_CTRL2, 1900 0, DPLL_CTRL2_DDI_CLK_OFF(port)); 1901 1902 mutex_unlock(&i915->display.dpll.lock); 1903 } 1904 1905 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 1906 { 1907 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1908 enum port port = encoder->port; 1909 1910 /* 1911 * FIXME Not sure if the override affects both 1912 * the PLL selection and the CLK_OFF bit. 1913 */ 1914 return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)); 1915 } 1916 1917 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) 1918 { 1919 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1920 enum port port = encoder->port; 1921 enum intel_dpll_id id; 1922 u32 tmp; 1923 1924 tmp = intel_de_read(i915, DPLL_CTRL2); 1925 1926 /* 1927 * FIXME Not sure if the override affects both 1928 * the PLL selection and the CLK_OFF bit. 1929 */ 1930 if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0) 1931 return NULL; 1932 1933 id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 1934 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 1935 1936 return intel_get_shared_dpll_by_id(i915, id); 1937 } 1938 1939 void hsw_ddi_enable_clock(struct intel_encoder *encoder, 1940 const struct intel_crtc_state *crtc_state) 1941 { 1942 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1943 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 1944 enum port port = encoder->port; 1945 1946 if (drm_WARN_ON(&i915->drm, !pll)) 1947 return; 1948 1949 intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); 1950 } 1951 1952 void hsw_ddi_disable_clock(struct intel_encoder *encoder) 1953 { 1954 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1955 enum port port = encoder->port; 1956 1957 intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 1958 } 1959 1960 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 1961 { 1962 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1963 enum port port = encoder->port; 1964 1965 return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE; 1966 } 1967 1968 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) 1969 { 1970 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1971 enum port port = encoder->port; 1972 enum intel_dpll_id id; 1973 u32 tmp; 1974 1975 tmp = intel_de_read(i915, PORT_CLK_SEL(port)); 1976 1977 switch (tmp & PORT_CLK_SEL_MASK) { 1978 case PORT_CLK_SEL_WRPLL1: 1979 id = DPLL_ID_WRPLL1; 1980 break; 1981 case PORT_CLK_SEL_WRPLL2: 1982 id = DPLL_ID_WRPLL2; 1983 break; 1984 case PORT_CLK_SEL_SPLL: 1985 id = DPLL_ID_SPLL; 1986 break; 1987 case PORT_CLK_SEL_LCPLL_810: 1988 id = DPLL_ID_LCPLL_810; 1989 break; 1990 case PORT_CLK_SEL_LCPLL_1350: 1991 id = DPLL_ID_LCPLL_1350; 1992 break; 1993 case PORT_CLK_SEL_LCPLL_2700: 1994 id = DPLL_ID_LCPLL_2700; 1995 break; 1996 default: 1997 MISSING_CASE(tmp); 1998 fallthrough; 1999 case PORT_CLK_SEL_NONE: 2000 return NULL; 2001 } 2002 2003 return intel_get_shared_dpll_by_id(i915, id); 2004 } 2005 2006 void intel_ddi_enable_clock(struct intel_encoder *encoder, 2007 const struct intel_crtc_state *crtc_state) 2008 { 2009 if (encoder->enable_clock) 2010 encoder->enable_clock(encoder, crtc_state); 2011 } 2012 2013 void intel_ddi_disable_clock(struct intel_encoder *encoder) 2014 { 2015 if (encoder->disable_clock) 2016 encoder->disable_clock(encoder); 2017 } 2018 2019 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 2020 { 2021 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2022 u32 port_mask; 2023 bool ddi_clk_needed; 2024 2025 /* 2026 * In case of DP MST, we sanitize the primary encoder only, not the 2027 * virtual ones. 2028 */ 2029 if (encoder->type == INTEL_OUTPUT_DP_MST) 2030 return; 2031 2032 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { 2033 u8 pipe_mask; 2034 bool is_mst; 2035 2036 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); 2037 /* 2038 * In the unlikely case that BIOS enables DP in MST mode, just 2039 * warn since our MST HW readout is incomplete. 2040 */ 2041 if (drm_WARN_ON(&i915->drm, is_mst)) 2042 return; 2043 } 2044 2045 port_mask = BIT(encoder->port); 2046 ddi_clk_needed = encoder->base.crtc; 2047 2048 if (encoder->type == INTEL_OUTPUT_DSI) { 2049 struct intel_encoder *other_encoder; 2050 2051 port_mask = intel_dsi_encoder_ports(encoder); 2052 /* 2053 * Sanity check that we haven't incorrectly registered another 2054 * encoder using any of the ports of this DSI encoder. 2055 */ 2056 for_each_intel_encoder(&i915->drm, other_encoder) { 2057 if (other_encoder == encoder) 2058 continue; 2059 2060 if (drm_WARN_ON(&i915->drm, 2061 port_mask & BIT(other_encoder->port))) 2062 return; 2063 } 2064 /* 2065 * For DSI we keep the ddi clocks gated 2066 * except during enable/disable sequence. 2067 */ 2068 ddi_clk_needed = false; 2069 } 2070 2071 if (ddi_clk_needed || !encoder->is_clock_enabled || 2072 !encoder->is_clock_enabled(encoder)) 2073 return; 2074 2075 drm_notice(&i915->drm, 2076 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", 2077 encoder->base.base.id, encoder->base.name); 2078 2079 encoder->disable_clock(encoder); 2080 } 2081 2082 static void 2083 icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 2084 const struct intel_crtc_state *crtc_state) 2085 { 2086 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2087 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); 2088 u32 ln0, ln1, pin_assignment; 2089 u8 width; 2090 2091 if (!intel_encoder_is_tc(&dig_port->base) || 2092 intel_tc_port_in_tbt_alt_mode(dig_port)) 2093 return; 2094 2095 if (DISPLAY_VER(dev_priv) >= 12) { 2096 ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); 2097 ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); 2098 } else { 2099 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); 2100 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); 2101 } 2102 2103 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2104 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); 2105 2106 /* DPPATC */ 2107 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); 2108 width = crtc_state->lane_count; 2109 2110 switch (pin_assignment) { 2111 case 0x0: 2112 drm_WARN_ON(&dev_priv->drm, 2113 !intel_tc_port_in_legacy_mode(dig_port)); 2114 if (width == 1) { 2115 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2116 } else { 2117 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2118 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2119 } 2120 break; 2121 case 0x1: 2122 if (width == 4) { 2123 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2124 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2125 } 2126 break; 2127 case 0x2: 2128 if (width == 2) { 2129 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2130 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2131 } 2132 break; 2133 case 0x3: 2134 case 0x5: 2135 if (width == 1) { 2136 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2137 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2138 } else { 2139 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2140 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2141 } 2142 break; 2143 case 0x4: 2144 case 0x6: 2145 if (width == 1) { 2146 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE; 2147 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; 2148 } else { 2149 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE; 2150 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE; 2151 } 2152 break; 2153 default: 2154 MISSING_CASE(pin_assignment); 2155 } 2156 2157 if (DISPLAY_VER(dev_priv) >= 12) { 2158 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); 2159 intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); 2160 } else { 2161 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); 2162 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); 2163 } 2164 } 2165 2166 static enum transcoder 2167 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) 2168 { 2169 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2170 return crtc_state->mst_master_transcoder; 2171 else 2172 return crtc_state->cpu_transcoder; 2173 } 2174 2175 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 2176 const struct intel_crtc_state *crtc_state) 2177 { 2178 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2179 2180 if (DISPLAY_VER(dev_priv) >= 12) 2181 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); 2182 else 2183 return DP_TP_CTL(encoder->port); 2184 } 2185 2186 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2187 const struct intel_crtc_state *crtc_state) 2188 { 2189 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2190 2191 if (DISPLAY_VER(dev_priv) >= 12) 2192 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); 2193 else 2194 return DP_TP_STATUS(encoder->port); 2195 } 2196 2197 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, 2198 const struct intel_crtc_state *crtc_state, 2199 bool enable) 2200 { 2201 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2202 2203 if (!crtc_state->vrr.enable) 2204 return; 2205 2206 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, 2207 enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) 2208 drm_dbg_kms(&i915->drm, 2209 "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", 2210 str_enable_disable(enable)); 2211 } 2212 2213 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, 2214 const struct intel_crtc_state *crtc_state, 2215 bool enable) 2216 { 2217 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2218 2219 if (!crtc_state->fec_enable) 2220 return; 2221 2222 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, 2223 enable ? DP_FEC_READY : 0) <= 0) 2224 drm_dbg_kms(&i915->drm, "Failed to set FEC_READY to %s in the sink\n", 2225 enable ? "enabled" : "disabled"); 2226 2227 if (enable && 2228 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, 2229 DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0) 2230 drm_dbg_kms(&i915->drm, "Failed to clear FEC detected flags\n"); 2231 } 2232 2233 static int read_fec_detected_status(struct drm_dp_aux *aux) 2234 { 2235 int ret; 2236 u8 status; 2237 2238 ret = drm_dp_dpcd_readb(aux, DP_FEC_STATUS, &status); 2239 if (ret < 0) 2240 return ret; 2241 2242 return status; 2243 } 2244 2245 static void wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled) 2246 { 2247 struct drm_i915_private *i915 = to_i915(aux->drm_dev); 2248 int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED; 2249 int status; 2250 int err; 2251 2252 err = readx_poll_timeout(read_fec_detected_status, aux, status, 2253 status & mask || status < 0, 2254 10000, 200000); 2255 2256 if (!err && status >= 0) 2257 return; 2258 2259 if (err == -ETIMEDOUT) 2260 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", 2261 str_enabled_disabled(enabled)); 2262 else 2263 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); 2264 } 2265 2266 void intel_ddi_wait_for_fec_status(struct intel_encoder *encoder, 2267 const struct intel_crtc_state *crtc_state, 2268 bool enabled) 2269 { 2270 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 2271 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2272 int ret; 2273 2274 if (!crtc_state->fec_enable) 2275 return; 2276 2277 if (enabled) 2278 ret = intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 2279 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2280 else 2281 ret = intel_de_wait_for_clear(i915, dp_tp_status_reg(encoder, crtc_state), 2282 DP_TP_STATUS_FEC_ENABLE_LIVE, 1); 2283 2284 if (ret) 2285 drm_err(&i915->drm, 2286 "Timeout waiting for FEC live state to get %s\n", 2287 str_enabled_disabled(enabled)); 2288 2289 /* 2290 * At least the Synoptics MST hub doesn't set the detected flag for 2291 * FEC decoding disabling so skip waiting for that. 2292 */ 2293 if (enabled) 2294 wait_for_fec_detected(&intel_dp->aux, enabled); 2295 } 2296 2297 static void intel_ddi_enable_fec(struct intel_encoder *encoder, 2298 const struct intel_crtc_state *crtc_state) 2299 { 2300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2301 2302 if (!crtc_state->fec_enable) 2303 return; 2304 2305 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2306 0, DP_TP_CTL_FEC_ENABLE); 2307 } 2308 2309 static void intel_ddi_disable_fec(struct intel_encoder *encoder, 2310 const struct intel_crtc_state *crtc_state) 2311 { 2312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2313 2314 if (!crtc_state->fec_enable) 2315 return; 2316 2317 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2318 DP_TP_CTL_FEC_ENABLE, 0); 2319 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 2320 } 2321 2322 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, 2323 const struct intel_crtc_state *crtc_state) 2324 { 2325 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2326 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2327 2328 if (intel_encoder_is_combo(encoder)) { 2329 enum phy phy = intel_encoder_to_phy(encoder); 2330 bool lane_reversal = 2331 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2332 2333 intel_combo_phy_power_up_lanes(i915, phy, false, 2334 crtc_state->lane_count, 2335 lane_reversal); 2336 } 2337 } 2338 2339 /* 2340 * Splitter enable for eDP MSO is limited to certain pipes, on certain 2341 * platforms. 2342 */ 2343 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915) 2344 { 2345 if (DISPLAY_VER(i915) > 20) 2346 return ~0; 2347 else if (IS_ALDERLAKE_P(i915)) 2348 return BIT(PIPE_A) | BIT(PIPE_B); 2349 else 2350 return BIT(PIPE_A); 2351 } 2352 2353 static void intel_ddi_mso_get_config(struct intel_encoder *encoder, 2354 struct intel_crtc_state *pipe_config) 2355 { 2356 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 2357 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2358 enum pipe pipe = crtc->pipe; 2359 u32 dss1; 2360 2361 if (!HAS_MSO(i915)) 2362 return; 2363 2364 dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); 2365 2366 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; 2367 if (!pipe_config->splitter.enable) 2368 return; 2369 2370 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { 2371 pipe_config->splitter.enable = false; 2372 return; 2373 } 2374 2375 switch (dss1 & SPLITTER_CONFIGURATION_MASK) { 2376 default: 2377 drm_WARN(&i915->drm, true, 2378 "Invalid splitter configuration, dss1=0x%08x\n", dss1); 2379 fallthrough; 2380 case SPLITTER_CONFIGURATION_2_SEGMENT: 2381 pipe_config->splitter.link_count = 2; 2382 break; 2383 case SPLITTER_CONFIGURATION_4_SEGMENT: 2384 pipe_config->splitter.link_count = 4; 2385 break; 2386 } 2387 2388 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); 2389 } 2390 2391 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) 2392 { 2393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2394 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2395 enum pipe pipe = crtc->pipe; 2396 u32 dss1 = 0; 2397 2398 if (!HAS_MSO(i915)) 2399 return; 2400 2401 if (crtc_state->splitter.enable) { 2402 dss1 |= SPLITTER_ENABLE; 2403 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); 2404 if (crtc_state->splitter.link_count == 2) 2405 dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT; 2406 else 2407 dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT; 2408 } 2409 2410 intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe), 2411 SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK | 2412 OVERLAP_PIXELS_MASK, dss1); 2413 } 2414 2415 static u8 mtl_get_port_width(u8 lane_count) 2416 { 2417 switch (lane_count) { 2418 case 1: 2419 return 0; 2420 case 2: 2421 return 1; 2422 case 3: 2423 return 4; 2424 case 4: 2425 return 3; 2426 default: 2427 MISSING_CASE(lane_count); 2428 return 4; 2429 } 2430 } 2431 2432 static void 2433 mtl_ddi_enable_d2d(struct intel_encoder *encoder) 2434 { 2435 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2436 enum port port = encoder->port; 2437 i915_reg_t reg; 2438 u32 set_bits, wait_bits; 2439 2440 if (DISPLAY_VER(dev_priv) >= 20) { 2441 reg = DDI_BUF_CTL(port); 2442 set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2443 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2444 } else { 2445 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2446 set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2447 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2448 } 2449 2450 intel_de_rmw(dev_priv, reg, 0, set_bits); 2451 if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) { 2452 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", 2453 port_name(port)); 2454 } 2455 } 2456 2457 static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, 2458 const struct intel_crtc_state *crtc_state) 2459 { 2460 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2461 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2462 enum port port = encoder->port; 2463 u32 val; 2464 2465 val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)); 2466 val &= ~XELPDP_PORT_WIDTH_MASK; 2467 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); 2468 2469 val &= ~XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK; 2470 if (intel_dp_is_uhbr(crtc_state)) 2471 val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; 2472 else 2473 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2474 2475 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2476 val |= XELPDP_PORT_REVERSAL; 2477 2478 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val); 2479 } 2480 2481 static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder) 2482 { 2483 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2484 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2485 u32 val; 2486 2487 val = intel_tc_port_in_tbt_alt_mode(dig_port) ? 2488 XELPDP_PORT_BUF_IO_SELECT_TBT : 0; 2489 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), 2490 XELPDP_PORT_BUF_IO_SELECT_TBT, val); 2491 } 2492 2493 static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2494 struct intel_encoder *encoder, 2495 const struct intel_crtc_state *crtc_state, 2496 const struct drm_connector_state *conn_state) 2497 { 2498 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2499 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2500 2501 intel_dp_set_link_params(intel_dp, 2502 crtc_state->port_clock, 2503 crtc_state->lane_count); 2504 2505 /* 2506 * We only configure what the register value will be here. Actual 2507 * enabling happens during link training farther down. 2508 */ 2509 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2510 2511 /* 2512 * 1. Enable Power Wells 2513 * 2514 * This was handled at the beginning of intel_atomic_commit_tail(), 2515 * before we called down into this function. 2516 */ 2517 2518 /* 2. PMdemand was already set */ 2519 2520 /* 3. Select Thunderbolt */ 2521 mtl_port_buf_ctl_io_selection(encoder); 2522 2523 /* 4. Enable Panel Power if PPS is required */ 2524 intel_pps_on(intel_dp); 2525 2526 /* 5. Enable the port PLL */ 2527 intel_ddi_enable_clock(encoder, crtc_state); 2528 2529 /* 2530 * 6.a Configure Transcoder Clock Select to direct the Port clock to the 2531 * Transcoder. 2532 */ 2533 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2534 2535 /* 2536 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2537 */ 2538 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2539 2540 /* 2541 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2542 * Transport Select 2543 */ 2544 intel_ddi_config_transcoder_func(encoder, crtc_state); 2545 2546 /* 2547 * 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2548 */ 2549 intel_ddi_mso_configure(crtc_state); 2550 2551 if (!is_mst) 2552 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2553 2554 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2555 if (!is_mst) 2556 intel_dp_sink_enable_decompression(state, 2557 to_intel_connector(conn_state->connector), 2558 crtc_state); 2559 2560 /* 2561 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2562 * in the FEC_CONFIGURATION register to 1 before initiating link 2563 * training 2564 */ 2565 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2566 2567 intel_dp_check_frl_training(intel_dp); 2568 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2569 2570 /* 2571 * 6. The rest of the below are substeps under the bspec's "Enable and 2572 * Train Display Port" step. Note that steps that are specific to 2573 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2574 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2575 * us when active_mst_links==0, so any steps designated for "single 2576 * stream or multi-stream master transcoder" can just be performed 2577 * unconditionally here. 2578 * 2579 * mtl_ddi_prepare_link_retrain() that is called by 2580 * intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h, 2581 * 6.i and 6.j 2582 * 2583 * 6.k Follow DisplayPort specification training sequence (see notes for 2584 * failure handling) 2585 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2586 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2587 * (timeout after 800 us) 2588 */ 2589 intel_dp_start_link_train(intel_dp, crtc_state); 2590 2591 /* 6.n Set DP_TP_CTL link training to Normal */ 2592 if (!is_trans_port_sync_mode(crtc_state)) 2593 intel_dp_stop_link_train(intel_dp, crtc_state); 2594 2595 /* 6.o Configure and enable FEC if needed */ 2596 intel_ddi_enable_fec(encoder, crtc_state); 2597 2598 if (!is_mst) 2599 intel_dsc_dp_pps_write(encoder, crtc_state); 2600 } 2601 2602 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 2603 struct intel_encoder *encoder, 2604 const struct intel_crtc_state *crtc_state, 2605 const struct drm_connector_state *conn_state) 2606 { 2607 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2609 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2610 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2611 2612 intel_dp_set_link_params(intel_dp, 2613 crtc_state->port_clock, 2614 crtc_state->lane_count); 2615 2616 /* 2617 * We only configure what the register value will be here. Actual 2618 * enabling happens during link training farther down. 2619 */ 2620 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2621 2622 /* 2623 * 1. Enable Power Wells 2624 * 2625 * This was handled at the beginning of intel_atomic_commit_tail(), 2626 * before we called down into this function. 2627 */ 2628 2629 /* 2. Enable Panel Power if PPS is required */ 2630 intel_pps_on(intel_dp); 2631 2632 /* 2633 * 3. For non-TBT Type-C ports, set FIA lane count 2634 * (DFLEXDPSP.DPX4TXLATC) 2635 * 2636 * This was done before tgl_ddi_pre_enable_dp by 2637 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). 2638 */ 2639 2640 /* 2641 * 4. Enable the port PLL. 2642 * 2643 * The PLL enabling itself was already done before this function by 2644 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only 2645 * configure the PLL to port mapping here. 2646 */ 2647 intel_ddi_enable_clock(encoder, crtc_state); 2648 2649 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ 2650 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2651 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2652 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2653 dig_port->ddi_io_power_domain); 2654 } 2655 2656 /* 6. Program DP_MODE */ 2657 icl_program_mg_dp_mode(dig_port, crtc_state); 2658 2659 /* 2660 * 7. The rest of the below are substeps under the bspec's "Enable and 2661 * Train Display Port" step. Note that steps that are specific to 2662 * MST will be handled by intel_mst_pre_enable_dp() before/after it 2663 * calls into this function. Also intel_mst_pre_enable_dp() only calls 2664 * us when active_mst_links==0, so any steps designated for "single 2665 * stream or multi-stream master transcoder" can just be performed 2666 * unconditionally here. 2667 */ 2668 2669 /* 2670 * 7.a Configure Transcoder Clock Select to direct the Port clock to the 2671 * Transcoder. 2672 */ 2673 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2674 2675 if (HAS_DP20(dev_priv)) 2676 intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2677 2678 /* 2679 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2680 * Transport Select 2681 */ 2682 intel_ddi_config_transcoder_func(encoder, crtc_state); 2683 2684 /* 2685 * 7.c Configure & enable DP_TP_CTL with link training pattern 1 2686 * selected 2687 * 2688 * This will be handled by the intel_dp_start_link_train() farther 2689 * down this function. 2690 */ 2691 2692 /* 7.e Configure voltage swing and related IO settings */ 2693 encoder->set_signal_levels(encoder, crtc_state); 2694 2695 /* 2696 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up 2697 * the used lanes of the DDI. 2698 */ 2699 intel_ddi_power_up_lanes(encoder, crtc_state); 2700 2701 /* 2702 * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. 2703 */ 2704 intel_ddi_mso_configure(crtc_state); 2705 2706 if (!is_mst) 2707 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2708 2709 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2710 if (!is_mst) 2711 intel_dp_sink_enable_decompression(state, 2712 to_intel_connector(conn_state->connector), 2713 crtc_state); 2714 /* 2715 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit 2716 * in the FEC_CONFIGURATION register to 1 before initiating link 2717 * training 2718 */ 2719 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2720 2721 intel_dp_check_frl_training(intel_dp); 2722 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 2723 2724 /* 2725 * 7.i Follow DisplayPort specification training sequence (see notes for 2726 * failure handling) 2727 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle 2728 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) 2729 * (timeout after 800 us) 2730 */ 2731 intel_dp_start_link_train(intel_dp, crtc_state); 2732 2733 /* 7.k Set DP_TP_CTL link training to Normal */ 2734 if (!is_trans_port_sync_mode(crtc_state)) 2735 intel_dp_stop_link_train(intel_dp, crtc_state); 2736 2737 /* 7.l Configure and enable FEC if needed */ 2738 intel_ddi_enable_fec(encoder, crtc_state); 2739 2740 if (!is_mst) 2741 intel_dsc_dp_pps_write(encoder, crtc_state); 2742 } 2743 2744 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 2745 struct intel_encoder *encoder, 2746 const struct intel_crtc_state *crtc_state, 2747 const struct drm_connector_state *conn_state) 2748 { 2749 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2750 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2751 enum port port = encoder->port; 2752 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2753 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); 2754 2755 if (DISPLAY_VER(dev_priv) < 11) 2756 drm_WARN_ON(&dev_priv->drm, 2757 is_mst && (port == PORT_A || port == PORT_E)); 2758 else 2759 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); 2760 2761 intel_dp_set_link_params(intel_dp, 2762 crtc_state->port_clock, 2763 crtc_state->lane_count); 2764 2765 /* 2766 * We only configure what the register value will be here. Actual 2767 * enabling happens during link training farther down. 2768 */ 2769 intel_ddi_init_dp_buf_reg(encoder, crtc_state); 2770 2771 intel_pps_on(intel_dp); 2772 2773 intel_ddi_enable_clock(encoder, crtc_state); 2774 2775 if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { 2776 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2777 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2778 dig_port->ddi_io_power_domain); 2779 } 2780 2781 icl_program_mg_dp_mode(dig_port, crtc_state); 2782 2783 if (has_buf_trans_select(dev_priv)) 2784 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 2785 2786 encoder->set_signal_levels(encoder, crtc_state); 2787 2788 intel_ddi_power_up_lanes(encoder, crtc_state); 2789 2790 if (!is_mst) 2791 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 2792 intel_dp_configure_protocol_converter(intel_dp, crtc_state); 2793 if (!is_mst) 2794 intel_dp_sink_enable_decompression(state, 2795 to_intel_connector(conn_state->connector), 2796 crtc_state); 2797 intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); 2798 intel_dp_start_link_train(intel_dp, crtc_state); 2799 if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && 2800 !is_trans_port_sync_mode(crtc_state)) 2801 intel_dp_stop_link_train(intel_dp, crtc_state); 2802 2803 intel_ddi_enable_fec(encoder, crtc_state); 2804 2805 if (!is_mst) { 2806 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2807 intel_dsc_dp_pps_write(encoder, crtc_state); 2808 } 2809 } 2810 2811 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 2812 struct intel_encoder *encoder, 2813 const struct intel_crtc_state *crtc_state, 2814 const struct drm_connector_state *conn_state) 2815 { 2816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2817 2818 if (HAS_DP20(dev_priv)) 2819 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2820 crtc_state); 2821 2822 /* Panel replay has to be enabled in sink dpcd before link training. */ 2823 if (crtc_state->has_panel_replay) 2824 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2825 2826 if (DISPLAY_VER(dev_priv) >= 14) 2827 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2828 else if (DISPLAY_VER(dev_priv) >= 12) 2829 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2830 else 2831 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2832 2833 /* MST will call a setting of MSA after an allocating of Virtual Channel 2834 * from MST encoder pre_enable callback. 2835 */ 2836 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 2837 intel_ddi_set_dp_msa(crtc_state, conn_state); 2838 } 2839 2840 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, 2841 struct intel_encoder *encoder, 2842 const struct intel_crtc_state *crtc_state, 2843 const struct drm_connector_state *conn_state) 2844 { 2845 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2846 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2847 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2848 2849 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2850 intel_ddi_enable_clock(encoder, crtc_state); 2851 2852 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); 2853 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, 2854 dig_port->ddi_io_power_domain); 2855 2856 icl_program_mg_dp_mode(dig_port, crtc_state); 2857 2858 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2859 2860 dig_port->set_infoframes(encoder, 2861 crtc_state->has_infoframe, 2862 crtc_state, conn_state); 2863 } 2864 2865 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2866 struct intel_encoder *encoder, 2867 const struct intel_crtc_state *crtc_state, 2868 const struct drm_connector_state *conn_state) 2869 { 2870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2871 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2872 enum pipe pipe = crtc->pipe; 2873 2874 /* 2875 * When called from DP MST code: 2876 * - conn_state will be NULL 2877 * - encoder will be the main encoder (ie. mst->primary) 2878 * - the main connector associated with this port 2879 * won't be active or linked to a crtc 2880 * - crtc_state will be the state of the first stream to 2881 * be activated on this port, and it may not be the same 2882 * stream that will be deactivated last, but each stream 2883 * should have a state that is identical when it comes to 2884 * the DP link parameteres 2885 */ 2886 2887 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2888 2889 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 2890 2891 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2892 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, 2893 conn_state); 2894 } else { 2895 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2896 2897 intel_ddi_pre_enable_dp(state, encoder, crtc_state, 2898 conn_state); 2899 2900 /* FIXME precompute everything properly */ 2901 /* FIXME how do we turn infoframes off again? */ 2902 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 2903 dig_port->set_infoframes(encoder, 2904 crtc_state->has_infoframe, 2905 crtc_state, conn_state); 2906 } 2907 } 2908 2909 static void 2910 mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) 2911 { 2912 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2913 enum port port = encoder->port; 2914 i915_reg_t reg; 2915 u32 clr_bits, wait_bits; 2916 2917 if (DISPLAY_VER(dev_priv) >= 20) { 2918 reg = DDI_BUF_CTL(port); 2919 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 2920 wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE; 2921 } else { 2922 reg = XELPDP_PORT_BUF_CTL1(dev_priv, port); 2923 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; 2924 wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE; 2925 } 2926 2927 intel_de_rmw(dev_priv, reg, clr_bits, 0); 2928 if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100)) 2929 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", 2930 port_name(port)); 2931 } 2932 2933 static void mtl_disable_ddi_buf(struct intel_encoder *encoder, 2934 const struct intel_crtc_state *crtc_state) 2935 { 2936 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2937 enum port port = encoder->port; 2938 u32 val; 2939 2940 /* 3.b Clear DDI_CTL_DE Enable to 0. */ 2941 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2942 if (val & DDI_BUF_CTL_ENABLE) { 2943 val &= ~DDI_BUF_CTL_ENABLE; 2944 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2945 2946 /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ 2947 mtl_wait_ddi_buf_idle(dev_priv, port); 2948 } 2949 2950 /* 3.d Disable D2D Link */ 2951 mtl_ddi_disable_d2d_link(encoder); 2952 2953 /* 3.e Disable DP_TP_CTL */ 2954 if (intel_crtc_has_dp_encoder(crtc_state)) { 2955 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2956 DP_TP_CTL_ENABLE, 0); 2957 } 2958 } 2959 2960 static void disable_ddi_buf(struct intel_encoder *encoder, 2961 const struct intel_crtc_state *crtc_state) 2962 { 2963 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2964 enum port port = encoder->port; 2965 bool wait = false; 2966 u32 val; 2967 2968 val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 2969 if (val & DDI_BUF_CTL_ENABLE) { 2970 val &= ~DDI_BUF_CTL_ENABLE; 2971 intel_de_write(dev_priv, DDI_BUF_CTL(port), val); 2972 wait = true; 2973 } 2974 2975 if (intel_crtc_has_dp_encoder(crtc_state)) 2976 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 2977 DP_TP_CTL_ENABLE, 0); 2978 2979 intel_ddi_disable_fec(encoder, crtc_state); 2980 2981 if (wait) 2982 intel_wait_ddi_buf_idle(dev_priv, port); 2983 } 2984 2985 static void intel_disable_ddi_buf(struct intel_encoder *encoder, 2986 const struct intel_crtc_state *crtc_state) 2987 { 2988 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2989 2990 if (DISPLAY_VER(dev_priv) >= 14) { 2991 mtl_disable_ddi_buf(encoder, crtc_state); 2992 2993 /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ 2994 intel_ddi_disable_fec(encoder, crtc_state); 2995 } else { 2996 disable_ddi_buf(encoder, crtc_state); 2997 } 2998 2999 intel_ddi_wait_for_fec_status(encoder, crtc_state, false); 3000 } 3001 3002 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, 3003 struct intel_encoder *encoder, 3004 const struct intel_crtc_state *old_crtc_state, 3005 const struct drm_connector_state *old_conn_state) 3006 { 3007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3008 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3009 struct intel_dp *intel_dp = &dig_port->dp; 3010 intel_wakeref_t wakeref; 3011 bool is_mst = intel_crtc_has_type(old_crtc_state, 3012 INTEL_OUTPUT_DP_MST); 3013 3014 if (!is_mst) 3015 intel_dp_set_infoframes(encoder, false, 3016 old_crtc_state, old_conn_state); 3017 3018 /* 3019 * Power down sink before disabling the port, otherwise we end 3020 * up getting interrupts from the sink on detecting link loss. 3021 */ 3022 intel_dp_set_power(intel_dp, DP_SET_POWER_D3); 3023 3024 if (DISPLAY_VER(dev_priv) >= 12) { 3025 if (is_mst) { 3026 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 3027 3028 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), 3029 TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 3030 0); 3031 } 3032 } else { 3033 if (!is_mst) 3034 intel_ddi_disable_transcoder_clock(old_crtc_state); 3035 } 3036 3037 intel_disable_ddi_buf(encoder, old_crtc_state); 3038 3039 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3040 3041 /* 3042 * From TGL spec: "If single stream or multi-stream master transcoder: 3043 * Configure Transcoder Clock select to direct no clock to the 3044 * transcoder" 3045 */ 3046 if (DISPLAY_VER(dev_priv) >= 12) 3047 intel_ddi_disable_transcoder_clock(old_crtc_state); 3048 3049 intel_pps_vdd_on(intel_dp); 3050 intel_pps_off(intel_dp); 3051 3052 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3053 3054 if (wakeref) 3055 intel_display_power_put(dev_priv, 3056 dig_port->ddi_io_power_domain, 3057 wakeref); 3058 3059 intel_ddi_disable_clock(encoder); 3060 3061 /* De-select Thunderbolt */ 3062 if (DISPLAY_VER(dev_priv) >= 14) 3063 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), 3064 XELPDP_PORT_BUF_IO_SELECT_TBT, 0); 3065 } 3066 3067 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, 3068 struct intel_encoder *encoder, 3069 const struct intel_crtc_state *old_crtc_state, 3070 const struct drm_connector_state *old_conn_state) 3071 { 3072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3073 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3074 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3075 intel_wakeref_t wakeref; 3076 3077 dig_port->set_infoframes(encoder, false, 3078 old_crtc_state, old_conn_state); 3079 3080 if (DISPLAY_VER(dev_priv) < 12) 3081 intel_ddi_disable_transcoder_clock(old_crtc_state); 3082 3083 intel_disable_ddi_buf(encoder, old_crtc_state); 3084 3085 if (DISPLAY_VER(dev_priv) >= 12) 3086 intel_ddi_disable_transcoder_clock(old_crtc_state); 3087 3088 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); 3089 if (wakeref) 3090 intel_display_power_put(dev_priv, 3091 dig_port->ddi_io_power_domain, 3092 wakeref); 3093 3094 intel_ddi_disable_clock(encoder); 3095 3096 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 3097 } 3098 3099 static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state, 3100 struct intel_encoder *encoder, 3101 const struct intel_crtc_state *old_crtc_state, 3102 const struct drm_connector_state *old_conn_state) 3103 { 3104 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3105 struct intel_crtc *pipe_crtc; 3106 3107 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 3108 intel_crtc_joined_pipe_mask(old_crtc_state)) { 3109 const struct intel_crtc_state *old_pipe_crtc_state = 3110 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3111 3112 intel_crtc_vblank_off(old_pipe_crtc_state); 3113 } 3114 3115 intel_disable_transcoder(old_crtc_state); 3116 3117 intel_ddi_disable_transcoder_func(old_crtc_state); 3118 3119 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, 3120 intel_crtc_joined_pipe_mask(old_crtc_state)) { 3121 const struct intel_crtc_state *old_pipe_crtc_state = 3122 intel_atomic_get_old_crtc_state(state, pipe_crtc); 3123 3124 intel_dsc_disable(old_pipe_crtc_state); 3125 3126 if (DISPLAY_VER(dev_priv) >= 9) 3127 skl_scaler_disable(old_pipe_crtc_state); 3128 else 3129 ilk_pfit_disable(old_pipe_crtc_state); 3130 } 3131 } 3132 3133 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3134 struct intel_encoder *encoder, 3135 const struct intel_crtc_state *old_crtc_state, 3136 const struct drm_connector_state *old_conn_state) 3137 { 3138 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 3139 intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state, 3140 old_conn_state); 3141 3142 /* 3143 * When called from DP MST code: 3144 * - old_conn_state will be NULL 3145 * - encoder will be the main encoder (ie. mst->primary) 3146 * - the main connector associated with this port 3147 * won't be active or linked to a crtc 3148 * - old_crtc_state will be the state of the last stream to 3149 * be deactivated on this port, and it may not be the same 3150 * stream that was activated last, but each stream 3151 * should have a state that is identical when it comes to 3152 * the DP link parameteres 3153 */ 3154 3155 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3156 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, 3157 old_conn_state); 3158 else 3159 intel_ddi_post_disable_dp(state, encoder, old_crtc_state, 3160 old_conn_state); 3161 } 3162 3163 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3164 struct intel_encoder *encoder, 3165 const struct intel_crtc_state *old_crtc_state, 3166 const struct drm_connector_state *old_conn_state) 3167 { 3168 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3169 3170 main_link_aux_power_domain_put(dig_port, old_crtc_state); 3171 3172 if (intel_encoder_is_tc(encoder)) 3173 intel_tc_port_put_link(dig_port); 3174 } 3175 3176 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, 3177 struct intel_encoder *encoder, 3178 const struct intel_crtc_state *crtc_state) 3179 { 3180 const struct drm_connector_state *conn_state; 3181 struct drm_connector *conn; 3182 int i; 3183 3184 if (!crtc_state->sync_mode_slaves_mask) 3185 return; 3186 3187 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 3188 struct intel_encoder *slave_encoder = 3189 to_intel_encoder(conn_state->best_encoder); 3190 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); 3191 const struct intel_crtc_state *slave_crtc_state; 3192 3193 if (!slave_crtc) 3194 continue; 3195 3196 slave_crtc_state = 3197 intel_atomic_get_new_crtc_state(state, slave_crtc); 3198 3199 if (slave_crtc_state->master_transcoder != 3200 crtc_state->cpu_transcoder) 3201 continue; 3202 3203 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), 3204 slave_crtc_state); 3205 } 3206 3207 usleep_range(200, 400); 3208 3209 intel_dp_stop_link_train(enc_to_intel_dp(encoder), 3210 crtc_state); 3211 } 3212 3213 static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3214 struct intel_encoder *encoder, 3215 const struct intel_crtc_state *crtc_state, 3216 const struct drm_connector_state *conn_state) 3217 { 3218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3219 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3220 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3221 enum port port = encoder->port; 3222 3223 if (port == PORT_A && DISPLAY_VER(dev_priv) < 9) 3224 intel_dp_stop_link_train(intel_dp, crtc_state); 3225 3226 drm_connector_update_privacy_screen(conn_state); 3227 intel_edp_backlight_on(crtc_state, conn_state); 3228 3229 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) 3230 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3231 3232 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3233 } 3234 3235 /* FIXME bad home for this function */ 3236 i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 3237 enum transcoder cpu_transcoder) 3238 { 3239 return DISPLAY_VER(i915) >= 14 ? 3240 MTL_CHICKEN_TRANS(cpu_transcoder) : 3241 CHICKEN_TRANS(cpu_transcoder); 3242 } 3243 3244 static i915_reg_t 3245 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3246 enum port port) 3247 { 3248 static const enum transcoder trans[] = { 3249 [PORT_A] = TRANSCODER_EDP, 3250 [PORT_B] = TRANSCODER_A, 3251 [PORT_C] = TRANSCODER_B, 3252 [PORT_D] = TRANSCODER_C, 3253 [PORT_E] = TRANSCODER_A, 3254 }; 3255 3256 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3257 3258 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3259 port = PORT_A; 3260 3261 return CHICKEN_TRANS(trans[port]); 3262 } 3263 3264 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3265 struct intel_encoder *encoder, 3266 const struct intel_crtc_state *crtc_state, 3267 const struct drm_connector_state *conn_state) 3268 { 3269 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3270 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3271 struct drm_connector *connector = conn_state->connector; 3272 enum port port = encoder->port; 3273 u32 buf_ctl; 3274 3275 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3276 crtc_state->hdmi_high_tmds_clock_ratio, 3277 crtc_state->hdmi_scrambling)) 3278 drm_dbg_kms(&dev_priv->drm, 3279 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", 3280 connector->base.id, connector->name); 3281 3282 if (has_buf_trans_select(dev_priv)) 3283 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); 3284 3285 /* e. Enable D2D Link for C10/C20 Phy */ 3286 if (DISPLAY_VER(dev_priv) >= 14) 3287 mtl_ddi_enable_d2d(encoder); 3288 3289 encoder->set_signal_levels(encoder, crtc_state); 3290 3291 /* Display WA #1143: skl,kbl,cfl */ 3292 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) { 3293 /* 3294 * For some reason these chicken bits have been 3295 * stuffed into a transcoder register, event though 3296 * the bits affect a specific DDI port rather than 3297 * a specific transcoder. 3298 */ 3299 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3300 u32 val; 3301 3302 val = intel_de_read(dev_priv, reg); 3303 3304 if (port == PORT_E) 3305 val |= DDIE_TRAINING_OVERRIDE_ENABLE | 3306 DDIE_TRAINING_OVERRIDE_VALUE; 3307 else 3308 val |= DDI_TRAINING_OVERRIDE_ENABLE | 3309 DDI_TRAINING_OVERRIDE_VALUE; 3310 3311 intel_de_write(dev_priv, reg, val); 3312 intel_de_posting_read(dev_priv, reg); 3313 3314 udelay(1); 3315 3316 if (port == PORT_E) 3317 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE | 3318 DDIE_TRAINING_OVERRIDE_VALUE); 3319 else 3320 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | 3321 DDI_TRAINING_OVERRIDE_VALUE); 3322 3323 intel_de_write(dev_priv, reg, val); 3324 } 3325 3326 intel_ddi_power_up_lanes(encoder, crtc_state); 3327 3328 /* In HDMI/DVI mode, the port width, and swing/emphasis values 3329 * are ignored so nothing special needs to be done besides 3330 * enabling the port. 3331 * 3332 * On ADL_P the PHY link rate and lane count must be programmed but 3333 * these are both 0 for HDMI. 3334 * 3335 * But MTL onwards HDMI2.1 is supported and in TMDS mode this 3336 * is filled with lane count, already set in the crtc_state. 3337 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3338 */ 3339 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3340 if (DISPLAY_VER(dev_priv) >= 14) { 3341 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3342 u32 port_buf = 0; 3343 3344 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3345 3346 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3347 port_buf |= XELPDP_PORT_REVERSAL; 3348 3349 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), 3350 XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); 3351 3352 buf_ctl |= DDI_PORT_WIDTH(lane_count); 3353 3354 if (DISPLAY_VER(dev_priv) >= 20) 3355 buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3356 } else if (IS_ALDERLAKE_P(dev_priv) && intel_encoder_is_tc(encoder)) { 3357 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); 3358 buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; 3359 } 3360 3361 intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); 3362 3363 intel_wait_ddi_buf_active(encoder); 3364 } 3365 3366 static void intel_enable_ddi(struct intel_atomic_state *state, 3367 struct intel_encoder *encoder, 3368 const struct intel_crtc_state *crtc_state, 3369 const struct drm_connector_state *conn_state) 3370 { 3371 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3372 struct intel_crtc *pipe_crtc; 3373 3374 intel_ddi_enable_transcoder_func(encoder, crtc_state); 3375 3376 /* Enable/Disable DP2.0 SDP split config before transcoder */ 3377 intel_audio_sdp_split_update(crtc_state); 3378 3379 intel_enable_transcoder(crtc_state); 3380 3381 intel_ddi_wait_for_fec_status(encoder, crtc_state, true); 3382 3383 for_each_intel_crtc_in_pipe_mask_reverse(&i915->drm, pipe_crtc, 3384 intel_crtc_joined_pipe_mask(crtc_state)) { 3385 const struct intel_crtc_state *pipe_crtc_state = 3386 intel_atomic_get_new_crtc_state(state, pipe_crtc); 3387 3388 intel_crtc_vblank_on(pipe_crtc_state); 3389 } 3390 3391 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3392 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3393 else 3394 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3395 3396 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3397 3398 } 3399 3400 static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3401 struct intel_encoder *encoder, 3402 const struct intel_crtc_state *old_crtc_state, 3403 const struct drm_connector_state *old_conn_state) 3404 { 3405 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3406 struct intel_connector *connector = 3407 to_intel_connector(old_conn_state->connector); 3408 3409 intel_dp->link_trained = false; 3410 3411 intel_psr_disable(intel_dp, old_crtc_state); 3412 intel_edp_backlight_off(old_conn_state); 3413 /* Disable the decompression in DP Sink */ 3414 intel_dp_sink_disable_decompression(state, 3415 connector, old_crtc_state); 3416 /* Disable Ignore_MSA bit in DP Sink */ 3417 intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, 3418 false); 3419 } 3420 3421 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3422 struct intel_encoder *encoder, 3423 const struct intel_crtc_state *old_crtc_state, 3424 const struct drm_connector_state *old_conn_state) 3425 { 3426 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3427 struct drm_connector *connector = old_conn_state->connector; 3428 3429 if (!intel_hdmi_handle_sink_scrambling(encoder, connector, 3430 false, false)) 3431 drm_dbg_kms(&i915->drm, 3432 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n", 3433 connector->base.id, connector->name); 3434 } 3435 3436 static void intel_disable_ddi(struct intel_atomic_state *state, 3437 struct intel_encoder *encoder, 3438 const struct intel_crtc_state *old_crtc_state, 3439 const struct drm_connector_state *old_conn_state) 3440 { 3441 intel_tc_port_link_cancel_reset_work(enc_to_dig_port(encoder)); 3442 3443 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3444 3445 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3446 intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3447 old_conn_state); 3448 else 3449 intel_disable_ddi_dp(state, encoder, old_crtc_state, 3450 old_conn_state); 3451 } 3452 3453 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 3454 struct intel_encoder *encoder, 3455 const struct intel_crtc_state *crtc_state, 3456 const struct drm_connector_state *conn_state) 3457 { 3458 intel_ddi_set_dp_msa(crtc_state, conn_state); 3459 3460 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); 3461 3462 intel_backlight_update(state, encoder, crtc_state, conn_state); 3463 drm_connector_update_privacy_screen(conn_state); 3464 } 3465 3466 void intel_ddi_update_pipe(struct intel_atomic_state *state, 3467 struct intel_encoder *encoder, 3468 const struct intel_crtc_state *crtc_state, 3469 const struct drm_connector_state *conn_state) 3470 { 3471 3472 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 3473 !intel_encoder_is_mst(encoder)) 3474 intel_ddi_update_pipe_dp(state, encoder, crtc_state, 3475 conn_state); 3476 3477 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); 3478 } 3479 3480 void intel_ddi_update_active_dpll(struct intel_atomic_state *state, 3481 struct intel_encoder *encoder, 3482 struct intel_crtc *crtc) 3483 { 3484 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3485 const struct intel_crtc_state *crtc_state = 3486 intel_atomic_get_new_crtc_state(state, crtc); 3487 struct intel_crtc *pipe_crtc; 3488 3489 /* FIXME: Add MTL pll_mgr */ 3490 if (DISPLAY_VER(i915) >= 14 || !intel_encoder_is_tc(encoder)) 3491 return; 3492 3493 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, 3494 intel_crtc_joined_pipe_mask(crtc_state)) 3495 intel_update_active_dpll(state, pipe_crtc, encoder); 3496 } 3497 3498 static void 3499 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3500 struct intel_encoder *encoder, 3501 const struct intel_crtc_state *crtc_state, 3502 const struct drm_connector_state *conn_state) 3503 { 3504 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3505 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3506 bool is_tc_port = intel_encoder_is_tc(encoder); 3507 3508 if (is_tc_port) { 3509 struct intel_crtc *master_crtc = 3510 to_intel_crtc(crtc_state->uapi.crtc); 3511 3512 intel_tc_port_get_link(dig_port, crtc_state->lane_count); 3513 intel_ddi_update_active_dpll(state, encoder, master_crtc); 3514 } 3515 3516 main_link_aux_power_domain_get(dig_port, crtc_state); 3517 3518 if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) 3519 /* 3520 * Program the lane count for static/dynamic connections on 3521 * Type-C ports. Skip this step for TBT. 3522 */ 3523 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); 3524 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3525 bxt_dpio_phy_set_lane_optim_mask(encoder, 3526 crtc_state->lane_lat_optim_mask); 3527 } 3528 3529 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) 3530 { 3531 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3532 enum tc_port tc_port = intel_encoder_to_tc(encoder); 3533 int ln; 3534 3535 for (ln = 0; ln < 2; ln++) 3536 intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); 3537 } 3538 3539 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3540 const struct intel_crtc_state *crtc_state) 3541 { 3542 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3543 struct intel_encoder *encoder = &dig_port->base; 3544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3545 enum port port = encoder->port; 3546 u32 dp_tp_ctl; 3547 3548 /* 3549 * TODO: To train with only a different voltage swing entry is not 3550 * necessary disable and enable port 3551 */ 3552 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3553 if (dp_tp_ctl & DP_TP_CTL_ENABLE) 3554 mtl_disable_ddi_buf(encoder, crtc_state); 3555 3556 /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ 3557 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3558 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3559 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3560 } else { 3561 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3562 if (crtc_state->enhanced_framing) 3563 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3564 } 3565 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3566 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3567 3568 /* 6.f Enable D2D Link */ 3569 mtl_ddi_enable_d2d(encoder); 3570 3571 /* 6.g Configure voltage swing and related IO settings */ 3572 encoder->set_signal_levels(encoder, crtc_state); 3573 3574 /* 6.h Configure PORT_BUF_CTL1 */ 3575 mtl_port_buf_ctl_program(encoder, crtc_state); 3576 3577 /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ 3578 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3579 if (DISPLAY_VER(dev_priv) >= 20) 3580 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; 3581 3582 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3583 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3584 3585 /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ 3586 intel_wait_ddi_buf_active(encoder); 3587 } 3588 3589 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 3590 const struct intel_crtc_state *crtc_state) 3591 { 3592 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3593 struct intel_encoder *encoder = &dig_port->base; 3594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3595 enum port port = encoder->port; 3596 u32 dp_tp_ctl, ddi_buf_ctl; 3597 bool wait = false; 3598 3599 dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3600 3601 if (dp_tp_ctl & DP_TP_CTL_ENABLE) { 3602 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 3603 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { 3604 intel_de_write(dev_priv, DDI_BUF_CTL(port), 3605 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); 3606 wait = true; 3607 } 3608 3609 dp_tp_ctl &= ~DP_TP_CTL_ENABLE; 3610 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3611 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3612 3613 if (wait) 3614 intel_wait_ddi_buf_idle(dev_priv, port); 3615 } 3616 3617 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; 3618 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { 3619 dp_tp_ctl |= DP_TP_CTL_MODE_MST; 3620 } else { 3621 dp_tp_ctl |= DP_TP_CTL_MODE_SST; 3622 if (crtc_state->enhanced_framing) 3623 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3624 } 3625 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); 3626 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3627 3628 if (IS_ALDERLAKE_P(dev_priv) && 3629 (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) 3630 adlp_tbt_to_dp_alt_switch_wa(encoder); 3631 3632 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 3633 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); 3634 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); 3635 3636 intel_wait_ddi_buf_active(encoder); 3637 } 3638 3639 static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 3640 const struct intel_crtc_state *crtc_state, 3641 u8 dp_train_pat) 3642 { 3643 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3645 u32 temp; 3646 3647 temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); 3648 3649 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3650 switch (intel_dp_training_pattern_symbol(dp_train_pat)) { 3651 case DP_TRAINING_PATTERN_DISABLE: 3652 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3653 break; 3654 case DP_TRAINING_PATTERN_1: 3655 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3656 break; 3657 case DP_TRAINING_PATTERN_2: 3658 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3659 break; 3660 case DP_TRAINING_PATTERN_3: 3661 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3662 break; 3663 case DP_TRAINING_PATTERN_4: 3664 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3665 break; 3666 } 3667 3668 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); 3669 } 3670 3671 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 3672 const struct intel_crtc_state *crtc_state) 3673 { 3674 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3675 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3676 enum port port = encoder->port; 3677 3678 intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), 3679 DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE); 3680 3681 /* 3682 * Until TGL on PORT_A we can have only eDP in SST mode. There the only 3683 * reason we need to set idle transmission mode is to work around a HW 3684 * issue where we enable the pipe while not in idle link-training mode. 3685 * In this case there is requirement to wait for a minimum number of 3686 * idle patterns to be sent. 3687 */ 3688 if (port == PORT_A && DISPLAY_VER(dev_priv) < 12) 3689 return; 3690 3691 if (intel_de_wait_for_set(dev_priv, 3692 dp_tp_status_reg(encoder, crtc_state), 3693 DP_TP_STATUS_IDLE_DONE, 2)) 3694 drm_err(&dev_priv->drm, 3695 "Timed out waiting for DP idle patterns\n"); 3696 } 3697 3698 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, 3699 enum transcoder cpu_transcoder) 3700 { 3701 if (cpu_transcoder == TRANSCODER_EDP) 3702 return false; 3703 3704 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) 3705 return false; 3706 3707 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & 3708 AUDIO_OUTPUT_ENABLE(cpu_transcoder); 3709 } 3710 3711 static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3712 { 3713 if (crtc_state->port_clock > 594000) 3714 return 2; 3715 else 3716 return 0; 3717 } 3718 3719 static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3720 { 3721 if (crtc_state->port_clock > 594000) 3722 return 3; 3723 else 3724 return 0; 3725 } 3726 3727 static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state) 3728 { 3729 if (crtc_state->port_clock > 594000) 3730 return 1; 3731 else 3732 return 0; 3733 } 3734 3735 void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state) 3736 { 3737 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3738 3739 if (DISPLAY_VER(dev_priv) >= 14) 3740 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3741 else if (DISPLAY_VER(dev_priv) >= 12) 3742 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); 3743 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 3744 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); 3745 else if (DISPLAY_VER(dev_priv) >= 11) 3746 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); 3747 } 3748 3749 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv, 3750 enum transcoder cpu_transcoder) 3751 { 3752 u32 master_select; 3753 3754 if (DISPLAY_VER(dev_priv) >= 11) { 3755 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); 3756 3757 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) 3758 return INVALID_TRANSCODER; 3759 3760 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); 3761 } else { 3762 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3763 3764 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) 3765 return INVALID_TRANSCODER; 3766 3767 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl); 3768 } 3769 3770 if (master_select == 0) 3771 return TRANSCODER_EDP; 3772 else 3773 return master_select - 1; 3774 } 3775 3776 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) 3777 { 3778 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 3779 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | 3780 BIT(TRANSCODER_C) | BIT(TRANSCODER_D); 3781 enum transcoder cpu_transcoder; 3782 3783 crtc_state->master_transcoder = 3784 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); 3785 3786 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) { 3787 enum intel_display_power_domain power_domain; 3788 intel_wakeref_t trans_wakeref; 3789 3790 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3791 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, 3792 power_domain); 3793 3794 if (!trans_wakeref) 3795 continue; 3796 3797 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == 3798 crtc_state->cpu_transcoder) 3799 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); 3800 3801 intel_display_power_put(dev_priv, power_domain, trans_wakeref); 3802 } 3803 3804 drm_WARN_ON(&dev_priv->drm, 3805 crtc_state->master_transcoder != INVALID_TRANSCODER && 3806 crtc_state->sync_mode_slaves_mask); 3807 } 3808 3809 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3810 struct intel_crtc_state *pipe_config) 3811 { 3812 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3813 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3814 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3815 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3816 u32 temp, flags = 0; 3817 3818 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3819 if (temp & TRANS_DDI_PHSYNC) 3820 flags |= DRM_MODE_FLAG_PHSYNC; 3821 else 3822 flags |= DRM_MODE_FLAG_NHSYNC; 3823 if (temp & TRANS_DDI_PVSYNC) 3824 flags |= DRM_MODE_FLAG_PVSYNC; 3825 else 3826 flags |= DRM_MODE_FLAG_NVSYNC; 3827 3828 pipe_config->hw.adjusted_mode.flags |= flags; 3829 3830 switch (temp & TRANS_DDI_BPC_MASK) { 3831 case TRANS_DDI_BPC_6: 3832 pipe_config->pipe_bpp = 18; 3833 break; 3834 case TRANS_DDI_BPC_8: 3835 pipe_config->pipe_bpp = 24; 3836 break; 3837 case TRANS_DDI_BPC_10: 3838 pipe_config->pipe_bpp = 30; 3839 break; 3840 case TRANS_DDI_BPC_12: 3841 pipe_config->pipe_bpp = 36; 3842 break; 3843 default: 3844 break; 3845 } 3846 3847 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3848 case TRANS_DDI_MODE_SELECT_HDMI: 3849 pipe_config->has_hdmi_sink = true; 3850 3851 pipe_config->infoframes.enable |= 3852 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3853 3854 if (pipe_config->infoframes.enable) 3855 pipe_config->has_infoframe = true; 3856 3857 if (temp & TRANS_DDI_HDMI_SCRAMBLING) 3858 pipe_config->hdmi_scrambling = true; 3859 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3860 pipe_config->hdmi_high_tmds_clock_ratio = true; 3861 fallthrough; 3862 case TRANS_DDI_MODE_SELECT_DVI: 3863 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 3864 if (DISPLAY_VER(dev_priv) >= 14) 3865 pipe_config->lane_count = 3866 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3867 else 3868 pipe_config->lane_count = 4; 3869 break; 3870 case TRANS_DDI_MODE_SELECT_DP_SST: 3871 if (encoder->type == INTEL_OUTPUT_EDP) 3872 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3873 else 3874 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3875 pipe_config->lane_count = 3876 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3877 3878 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3879 &pipe_config->dp_m_n); 3880 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 3881 &pipe_config->dp_m2_n2); 3882 3883 pipe_config->enhanced_framing = 3884 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3885 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3886 3887 if (DISPLAY_VER(dev_priv) >= 11) 3888 pipe_config->fec_enable = 3889 intel_de_read(dev_priv, 3890 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3891 3892 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3893 pipe_config->infoframes.enable |= 3894 intel_lspcon_infoframes_enabled(encoder, pipe_config); 3895 else 3896 pipe_config->infoframes.enable |= 3897 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3898 break; 3899 case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 3900 if (!HAS_DP20(dev_priv)) { 3901 /* FDI */ 3902 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3903 pipe_config->enhanced_framing = 3904 intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 3905 DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3906 break; 3907 } 3908 fallthrough; /* 128b/132b */ 3909 case TRANS_DDI_MODE_SELECT_DP_MST: 3910 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3911 pipe_config->lane_count = 3912 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3913 3914 if (DISPLAY_VER(dev_priv) >= 12) 3915 pipe_config->mst_master_transcoder = 3916 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 3917 3918 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 3919 &pipe_config->dp_m_n); 3920 3921 if (DISPLAY_VER(dev_priv) >= 11) 3922 pipe_config->fec_enable = 3923 intel_de_read(dev_priv, 3924 dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 3925 3926 pipe_config->infoframes.enable |= 3927 intel_hdmi_infoframes_enabled(encoder, pipe_config); 3928 break; 3929 default: 3930 break; 3931 } 3932 } 3933 3934 static void intel_ddi_get_config(struct intel_encoder *encoder, 3935 struct intel_crtc_state *pipe_config) 3936 { 3937 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3938 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3939 3940 /* XXX: DSI transcoder paranoia */ 3941 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) 3942 return; 3943 3944 intel_ddi_read_func_ctl(encoder, pipe_config); 3945 3946 intel_ddi_mso_get_config(encoder, pipe_config); 3947 3948 pipe_config->has_audio = 3949 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); 3950 3951 if (encoder->type == INTEL_OUTPUT_EDP) 3952 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); 3953 3954 ddi_dotclock_get(pipe_config); 3955 3956 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 3957 pipe_config->lane_lat_optim_mask = 3958 bxt_dpio_phy_get_lane_lat_optim_mask(encoder); 3959 3960 intel_ddi_compute_min_voltage_level(pipe_config); 3961 3962 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 3963 3964 intel_read_infoframe(encoder, pipe_config, 3965 HDMI_INFOFRAME_TYPE_AVI, 3966 &pipe_config->infoframes.avi); 3967 intel_read_infoframe(encoder, pipe_config, 3968 HDMI_INFOFRAME_TYPE_SPD, 3969 &pipe_config->infoframes.spd); 3970 intel_read_infoframe(encoder, pipe_config, 3971 HDMI_INFOFRAME_TYPE_VENDOR, 3972 &pipe_config->infoframes.hdmi); 3973 intel_read_infoframe(encoder, pipe_config, 3974 HDMI_INFOFRAME_TYPE_DRM, 3975 &pipe_config->infoframes.drm); 3976 3977 if (DISPLAY_VER(dev_priv) >= 8) 3978 bdw_get_trans_port_sync_config(pipe_config); 3979 3980 intel_psr_get_config(encoder, pipe_config); 3981 3982 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); 3983 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); 3984 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); 3985 3986 intel_audio_codec_get_config(encoder, pipe_config); 3987 } 3988 3989 void intel_ddi_get_clock(struct intel_encoder *encoder, 3990 struct intel_crtc_state *crtc_state, 3991 struct intel_shared_dpll *pll) 3992 { 3993 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 3994 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; 3995 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 3996 bool pll_active; 3997 3998 if (drm_WARN_ON(&i915->drm, !pll)) 3999 return; 4000 4001 port_dpll->pll = pll; 4002 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4003 drm_WARN_ON(&i915->drm, !pll_active); 4004 4005 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4006 4007 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4008 &crtc_state->dpll_hw_state); 4009 } 4010 4011 static void mtl_ddi_get_config(struct intel_encoder *encoder, 4012 struct intel_crtc_state *crtc_state) 4013 { 4014 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4015 4016 if (intel_tc_port_in_tbt_alt_mode(dig_port)) { 4017 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4018 } else { 4019 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4020 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4021 } 4022 4023 intel_ddi_get_config(encoder, crtc_state); 4024 } 4025 4026 static void dg2_ddi_get_config(struct intel_encoder *encoder, 4027 struct intel_crtc_state *crtc_state) 4028 { 4029 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); 4030 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); 4031 4032 intel_ddi_get_config(encoder, crtc_state); 4033 } 4034 4035 static void adls_ddi_get_config(struct intel_encoder *encoder, 4036 struct intel_crtc_state *crtc_state) 4037 { 4038 intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); 4039 intel_ddi_get_config(encoder, crtc_state); 4040 } 4041 4042 static void rkl_ddi_get_config(struct intel_encoder *encoder, 4043 struct intel_crtc_state *crtc_state) 4044 { 4045 intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); 4046 intel_ddi_get_config(encoder, crtc_state); 4047 } 4048 4049 static void dg1_ddi_get_config(struct intel_encoder *encoder, 4050 struct intel_crtc_state *crtc_state) 4051 { 4052 intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); 4053 intel_ddi_get_config(encoder, crtc_state); 4054 } 4055 4056 static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 4057 struct intel_crtc_state *crtc_state) 4058 { 4059 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4060 intel_ddi_get_config(encoder, crtc_state); 4061 } 4062 4063 static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll) 4064 { 4065 return pll->info->id == DPLL_ID_ICL_TBTPLL; 4066 } 4067 4068 static enum icl_port_dpll_id 4069 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 4070 const struct intel_crtc_state *crtc_state) 4071 { 4072 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4073 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; 4074 4075 if (drm_WARN_ON(&i915->drm, !pll)) 4076 return ICL_PORT_DPLL_DEFAULT; 4077 4078 if (icl_ddi_tc_pll_is_tbt(pll)) 4079 return ICL_PORT_DPLL_DEFAULT; 4080 else 4081 return ICL_PORT_DPLL_MG_PHY; 4082 } 4083 4084 enum icl_port_dpll_id 4085 intel_ddi_port_pll_type(struct intel_encoder *encoder, 4086 const struct intel_crtc_state *crtc_state) 4087 { 4088 if (!encoder->port_pll_type) 4089 return ICL_PORT_DPLL_DEFAULT; 4090 4091 return encoder->port_pll_type(encoder, crtc_state); 4092 } 4093 4094 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 4095 struct intel_crtc_state *crtc_state, 4096 struct intel_shared_dpll *pll) 4097 { 4098 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4099 enum icl_port_dpll_id port_dpll_id; 4100 struct icl_port_dpll *port_dpll; 4101 bool pll_active; 4102 4103 if (drm_WARN_ON(&i915->drm, !pll)) 4104 return; 4105 4106 if (icl_ddi_tc_pll_is_tbt(pll)) 4107 port_dpll_id = ICL_PORT_DPLL_DEFAULT; 4108 else 4109 port_dpll_id = ICL_PORT_DPLL_MG_PHY; 4110 4111 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4112 4113 port_dpll->pll = pll; 4114 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); 4115 drm_WARN_ON(&i915->drm, !pll_active); 4116 4117 icl_set_active_port_dpll(crtc_state, port_dpll_id); 4118 4119 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) 4120 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); 4121 else 4122 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, 4123 &crtc_state->dpll_hw_state); 4124 } 4125 4126 static void icl_ddi_tc_get_config(struct intel_encoder *encoder, 4127 struct intel_crtc_state *crtc_state) 4128 { 4129 icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); 4130 intel_ddi_get_config(encoder, crtc_state); 4131 } 4132 4133 static void bxt_ddi_get_config(struct intel_encoder *encoder, 4134 struct intel_crtc_state *crtc_state) 4135 { 4136 intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); 4137 intel_ddi_get_config(encoder, crtc_state); 4138 } 4139 4140 static void skl_ddi_get_config(struct intel_encoder *encoder, 4141 struct intel_crtc_state *crtc_state) 4142 { 4143 intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); 4144 intel_ddi_get_config(encoder, crtc_state); 4145 } 4146 4147 void hsw_ddi_get_config(struct intel_encoder *encoder, 4148 struct intel_crtc_state *crtc_state) 4149 { 4150 intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); 4151 intel_ddi_get_config(encoder, crtc_state); 4152 } 4153 4154 static void intel_ddi_sync_state(struct intel_encoder *encoder, 4155 const struct intel_crtc_state *crtc_state) 4156 { 4157 if (intel_encoder_is_tc(encoder)) 4158 intel_tc_port_sanitize_mode(enc_to_dig_port(encoder), 4159 crtc_state); 4160 4161 if (intel_encoder_is_dp(encoder)) 4162 intel_dp_sync_state(encoder, crtc_state); 4163 } 4164 4165 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, 4166 struct intel_crtc_state *crtc_state) 4167 { 4168 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4169 bool fastset = true; 4170 4171 if (intel_encoder_is_tc(encoder)) { 4172 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", 4173 encoder->base.base.id, encoder->base.name); 4174 crtc_state->uapi.mode_changed = true; 4175 fastset = false; 4176 } 4177 4178 if (intel_crtc_has_dp_encoder(crtc_state) && 4179 !intel_dp_initial_fastset_check(encoder, crtc_state)) 4180 fastset = false; 4181 4182 return fastset; 4183 } 4184 4185 static enum intel_output_type 4186 intel_ddi_compute_output_type(struct intel_encoder *encoder, 4187 struct intel_crtc_state *crtc_state, 4188 struct drm_connector_state *conn_state) 4189 { 4190 switch (conn_state->connector->connector_type) { 4191 case DRM_MODE_CONNECTOR_HDMIA: 4192 return INTEL_OUTPUT_HDMI; 4193 case DRM_MODE_CONNECTOR_eDP: 4194 return INTEL_OUTPUT_EDP; 4195 case DRM_MODE_CONNECTOR_DisplayPort: 4196 return INTEL_OUTPUT_DP; 4197 default: 4198 MISSING_CASE(conn_state->connector->connector_type); 4199 return INTEL_OUTPUT_UNUSED; 4200 } 4201 } 4202 4203 static int intel_ddi_compute_config(struct intel_encoder *encoder, 4204 struct intel_crtc_state *pipe_config, 4205 struct drm_connector_state *conn_state) 4206 { 4207 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 4208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4209 enum port port = encoder->port; 4210 int ret; 4211 4212 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) 4213 pipe_config->cpu_transcoder = TRANSCODER_EDP; 4214 4215 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { 4216 pipe_config->has_hdmi_sink = 4217 intel_hdmi_compute_has_hdmi_sink(encoder, pipe_config, conn_state); 4218 4219 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); 4220 } else { 4221 ret = intel_dp_compute_config(encoder, pipe_config, conn_state); 4222 } 4223 4224 if (ret) 4225 return ret; 4226 4227 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && 4228 pipe_config->cpu_transcoder == TRANSCODER_EDP) 4229 pipe_config->pch_pfit.force_thru = 4230 pipe_config->pch_pfit.enabled || 4231 pipe_config->crc_enabled; 4232 4233 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4234 pipe_config->lane_lat_optim_mask = 4235 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 4236 4237 intel_ddi_compute_min_voltage_level(pipe_config); 4238 4239 return 0; 4240 } 4241 4242 static bool mode_equal(const struct drm_display_mode *mode1, 4243 const struct drm_display_mode *mode2) 4244 { 4245 return drm_mode_match(mode1, mode2, 4246 DRM_MODE_MATCH_TIMINGS | 4247 DRM_MODE_MATCH_FLAGS | 4248 DRM_MODE_MATCH_3D_FLAGS) && 4249 mode1->clock == mode2->clock; /* we want an exact match */ 4250 } 4251 4252 static bool m_n_equal(const struct intel_link_m_n *m_n_1, 4253 const struct intel_link_m_n *m_n_2) 4254 { 4255 return m_n_1->tu == m_n_2->tu && 4256 m_n_1->data_m == m_n_2->data_m && 4257 m_n_1->data_n == m_n_2->data_n && 4258 m_n_1->link_m == m_n_2->link_m && 4259 m_n_1->link_n == m_n_2->link_n; 4260 } 4261 4262 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, 4263 const struct intel_crtc_state *crtc_state2) 4264 { 4265 /* 4266 * FIXME the modeset sequence is currently wrong and 4267 * can't deal with bigjoiner + port sync at the same time. 4268 */ 4269 return crtc_state1->hw.active && crtc_state2->hw.active && 4270 !crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes && 4271 crtc_state1->output_types == crtc_state2->output_types && 4272 crtc_state1->output_format == crtc_state2->output_format && 4273 crtc_state1->lane_count == crtc_state2->lane_count && 4274 crtc_state1->port_clock == crtc_state2->port_clock && 4275 mode_equal(&crtc_state1->hw.adjusted_mode, 4276 &crtc_state2->hw.adjusted_mode) && 4277 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); 4278 } 4279 4280 static u8 4281 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, 4282 int tile_group_id) 4283 { 4284 struct drm_connector *connector; 4285 const struct drm_connector_state *conn_state; 4286 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); 4287 struct intel_atomic_state *state = 4288 to_intel_atomic_state(ref_crtc_state->uapi.state); 4289 u8 transcoders = 0; 4290 int i; 4291 4292 /* 4293 * We don't enable port sync on BDW due to missing w/as and 4294 * due to not having adjusted the modeset sequence appropriately. 4295 */ 4296 if (DISPLAY_VER(dev_priv) < 9) 4297 return 0; 4298 4299 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) 4300 return 0; 4301 4302 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 4303 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); 4304 const struct intel_crtc_state *crtc_state; 4305 4306 if (!crtc) 4307 continue; 4308 4309 if (!connector->has_tile || 4310 connector->tile_group->id != 4311 tile_group_id) 4312 continue; 4313 crtc_state = intel_atomic_get_new_crtc_state(state, 4314 crtc); 4315 if (!crtcs_port_sync_compatible(ref_crtc_state, 4316 crtc_state)) 4317 continue; 4318 transcoders |= BIT(crtc_state->cpu_transcoder); 4319 } 4320 4321 return transcoders; 4322 } 4323 4324 static int intel_ddi_compute_config_late(struct intel_encoder *encoder, 4325 struct intel_crtc_state *crtc_state, 4326 struct drm_connector_state *conn_state) 4327 { 4328 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 4329 struct drm_connector *connector = conn_state->connector; 4330 u8 port_sync_transcoders = 0; 4331 4332 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", 4333 encoder->base.base.id, encoder->base.name, 4334 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); 4335 4336 if (connector->has_tile) 4337 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, 4338 connector->tile_group->id); 4339 4340 /* 4341 * EDP Transcoders cannot be ensalved 4342 * make them a master always when present 4343 */ 4344 if (port_sync_transcoders & BIT(TRANSCODER_EDP)) 4345 crtc_state->master_transcoder = TRANSCODER_EDP; 4346 else 4347 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; 4348 4349 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { 4350 crtc_state->master_transcoder = INVALID_TRANSCODER; 4351 crtc_state->sync_mode_slaves_mask = 4352 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); 4353 } 4354 4355 return 0; 4356 } 4357 4358 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) 4359 { 4360 struct drm_i915_private *i915 = to_i915(encoder->dev); 4361 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4362 4363 intel_dp_encoder_flush_work(encoder); 4364 if (intel_encoder_is_tc(&dig_port->base)) 4365 intel_tc_port_cleanup(dig_port); 4366 intel_display_power_flush_work(i915); 4367 4368 drm_encoder_cleanup(encoder); 4369 kfree(dig_port->hdcp_port_data.streams); 4370 kfree(dig_port); 4371 } 4372 4373 static void intel_ddi_encoder_reset(struct drm_encoder *encoder) 4374 { 4375 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); 4376 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4377 4378 intel_dp->reset_link_params = true; 4379 4380 intel_pps_encoder_reset(intel_dp); 4381 4382 if (intel_encoder_is_tc(&dig_port->base)) 4383 intel_tc_port_init_mode(dig_port); 4384 } 4385 4386 static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder) 4387 { 4388 struct intel_encoder *encoder = to_intel_encoder(_encoder); 4389 4390 intel_tc_port_link_reset(enc_to_dig_port(encoder)); 4391 4392 return 0; 4393 } 4394 4395 static const struct drm_encoder_funcs intel_ddi_funcs = { 4396 .reset = intel_ddi_encoder_reset, 4397 .destroy = intel_ddi_encoder_destroy, 4398 .late_register = intel_ddi_encoder_late_register, 4399 }; 4400 4401 static struct intel_connector * 4402 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 4403 { 4404 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4405 struct intel_connector *connector; 4406 enum port port = dig_port->base.port; 4407 4408 connector = intel_connector_alloc(); 4409 if (!connector) 4410 return NULL; 4411 4412 dig_port->dp.output_reg = DDI_BUF_CTL(port); 4413 if (DISPLAY_VER(i915) >= 14) 4414 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; 4415 else 4416 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; 4417 dig_port->dp.set_link_train = intel_ddi_set_link_train; 4418 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; 4419 4420 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; 4421 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; 4422 4423 if (!intel_dp_init_connector(dig_port, connector)) { 4424 kfree(connector); 4425 return NULL; 4426 } 4427 4428 if (dig_port->base.type == INTEL_OUTPUT_EDP) { 4429 struct drm_device *dev = dig_port->base.base.dev; 4430 struct drm_privacy_screen *privacy_screen; 4431 4432 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); 4433 if (!IS_ERR(privacy_screen)) { 4434 drm_connector_attach_privacy_screen_provider(&connector->base, 4435 privacy_screen); 4436 } else if (PTR_ERR(privacy_screen) != -ENODEV) { 4437 drm_warn(dev, "Error getting privacy-screen\n"); 4438 } 4439 } 4440 4441 return connector; 4442 } 4443 4444 static int modeset_pipe(struct drm_crtc *crtc, 4445 struct drm_modeset_acquire_ctx *ctx) 4446 { 4447 struct drm_atomic_state *state; 4448 struct drm_crtc_state *crtc_state; 4449 int ret; 4450 4451 state = drm_atomic_state_alloc(crtc->dev); 4452 if (!state) 4453 return -ENOMEM; 4454 4455 state->acquire_ctx = ctx; 4456 to_intel_atomic_state(state)->internal = true; 4457 4458 crtc_state = drm_atomic_get_crtc_state(state, crtc); 4459 if (IS_ERR(crtc_state)) { 4460 ret = PTR_ERR(crtc_state); 4461 goto out; 4462 } 4463 4464 crtc_state->connectors_changed = true; 4465 4466 ret = drm_atomic_commit(state); 4467 out: 4468 drm_atomic_state_put(state); 4469 4470 return ret; 4471 } 4472 4473 static int intel_hdmi_reset_link(struct intel_encoder *encoder, 4474 struct drm_modeset_acquire_ctx *ctx) 4475 { 4476 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4477 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 4478 struct intel_connector *connector = hdmi->attached_connector; 4479 struct i2c_adapter *ddc = connector->base.ddc; 4480 struct drm_connector_state *conn_state; 4481 struct intel_crtc_state *crtc_state; 4482 struct intel_crtc *crtc; 4483 u8 config; 4484 int ret; 4485 4486 if (connector->base.status != connector_status_connected) 4487 return 0; 4488 4489 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4490 ctx); 4491 if (ret) 4492 return ret; 4493 4494 conn_state = connector->base.state; 4495 4496 crtc = to_intel_crtc(conn_state->crtc); 4497 if (!crtc) 4498 return 0; 4499 4500 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4501 if (ret) 4502 return ret; 4503 4504 crtc_state = to_intel_crtc_state(crtc->base.state); 4505 4506 drm_WARN_ON(&dev_priv->drm, 4507 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); 4508 4509 if (!crtc_state->hw.active) 4510 return 0; 4511 4512 if (!crtc_state->hdmi_high_tmds_clock_ratio && 4513 !crtc_state->hdmi_scrambling) 4514 return 0; 4515 4516 if (conn_state->commit && 4517 !try_wait_for_completion(&conn_state->commit->hw_done)) 4518 return 0; 4519 4520 ret = drm_scdc_readb(ddc, SCDC_TMDS_CONFIG, &config); 4521 if (ret < 0) { 4522 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", 4523 connector->base.base.id, connector->base.name, ret); 4524 return 0; 4525 } 4526 4527 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) == 4528 crtc_state->hdmi_high_tmds_clock_ratio && 4529 !!(config & SCDC_SCRAMBLING_ENABLE) == 4530 crtc_state->hdmi_scrambling) 4531 return 0; 4532 4533 /* 4534 * HDMI 2.0 says that one should not send scrambled data 4535 * prior to configuring the sink scrambling, and that 4536 * TMDS clock/data transmission should be suspended when 4537 * changing the TMDS clock rate in the sink. So let's 4538 * just do a full modeset here, even though some sinks 4539 * would be perfectly happy if were to just reconfigure 4540 * the SCDC settings on the fly. 4541 */ 4542 return modeset_pipe(&crtc->base, ctx); 4543 } 4544 4545 static enum intel_hotplug_state 4546 intel_ddi_hotplug(struct intel_encoder *encoder, 4547 struct intel_connector *connector) 4548 { 4549 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4550 struct intel_dp *intel_dp = &dig_port->dp; 4551 bool is_tc = intel_encoder_is_tc(encoder); 4552 struct drm_modeset_acquire_ctx ctx; 4553 enum intel_hotplug_state state; 4554 int ret; 4555 4556 if (intel_dp->compliance.test_active && 4557 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { 4558 intel_dp_phy_test(encoder); 4559 /* just do the PHY test and nothing else */ 4560 return INTEL_HOTPLUG_UNCHANGED; 4561 } 4562 4563 state = intel_encoder_hotplug(encoder, connector); 4564 4565 if (!intel_tc_port_link_reset(dig_port)) { 4566 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) { 4567 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) 4568 ret = intel_hdmi_reset_link(encoder, &ctx); 4569 else 4570 ret = intel_dp_retrain_link(encoder, &ctx); 4571 } 4572 4573 drm_WARN_ON(encoder->base.dev, ret); 4574 } 4575 4576 /* 4577 * Unpowered type-c dongles can take some time to boot and be 4578 * responsible, so here giving some time to those dongles to power up 4579 * and then retrying the probe. 4580 * 4581 * On many platforms the HDMI live state signal is known to be 4582 * unreliable, so we can't use it to detect if a sink is connected or 4583 * not. Instead we detect if it's connected based on whether we can 4584 * read the EDID or not. That in turn has a problem during disconnect, 4585 * since the HPD interrupt may be raised before the DDC lines get 4586 * disconnected (due to how the required length of DDC vs. HPD 4587 * connector pins are specified) and so we'll still be able to get a 4588 * valid EDID. To solve this schedule another detection cycle if this 4589 * time around we didn't detect any change in the sink's connection 4590 * status. 4591 * 4592 * Type-c connectors which get their HPD signal deasserted then 4593 * reasserted, without unplugging/replugging the sink from the 4594 * connector, introduce a delay until the AUX channel communication 4595 * becomes functional. Retry the detection for 5 seconds on type-c 4596 * connectors to account for this delay. 4597 */ 4598 if (state == INTEL_HOTPLUG_UNCHANGED && 4599 connector->hotplug_retries < (is_tc ? 5 : 1) && 4600 !dig_port->dp.is_mst) 4601 state = INTEL_HOTPLUG_RETRY; 4602 4603 return state; 4604 } 4605 4606 static bool lpt_digital_port_connected(struct intel_encoder *encoder) 4607 { 4608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4609 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; 4610 4611 return intel_de_read(dev_priv, SDEISR) & bit; 4612 } 4613 4614 static bool hsw_digital_port_connected(struct intel_encoder *encoder) 4615 { 4616 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4617 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4618 4619 return intel_de_read(dev_priv, DEISR) & bit; 4620 } 4621 4622 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 4623 { 4624 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4625 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; 4626 4627 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; 4628 } 4629 4630 static struct intel_connector * 4631 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) 4632 { 4633 struct intel_connector *connector; 4634 enum port port = dig_port->base.port; 4635 4636 connector = intel_connector_alloc(); 4637 if (!connector) 4638 return NULL; 4639 4640 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 4641 intel_hdmi_init_connector(dig_port, connector); 4642 4643 return connector; 4644 } 4645 4646 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 4647 { 4648 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4649 4650 if (dig_port->base.port != PORT_A) 4651 return false; 4652 4653 if (dig_port->saved_port_bits & DDI_A_4_LANES) 4654 return false; 4655 4656 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only 4657 * supported configuration 4658 */ 4659 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 4660 return true; 4661 4662 return false; 4663 } 4664 4665 static int 4666 intel_ddi_max_lanes(struct intel_digital_port *dig_port) 4667 { 4668 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 4669 enum port port = dig_port->base.port; 4670 int max_lanes = 4; 4671 4672 if (DISPLAY_VER(dev_priv) >= 11) 4673 return max_lanes; 4674 4675 if (port == PORT_A || port == PORT_E) { 4676 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 4677 max_lanes = port == PORT_A ? 4 : 0; 4678 else 4679 /* Both A and E share 2 lanes */ 4680 max_lanes = 2; 4681 } 4682 4683 /* 4684 * Some BIOS might fail to set this bit on port A if eDP 4685 * wasn't lit up at boot. Force this bit set when needed 4686 * so we use the proper lane count for our calculations. 4687 */ 4688 if (intel_ddi_a_force_4_lanes(dig_port)) { 4689 drm_dbg_kms(&dev_priv->drm, 4690 "Forcing DDI_A_4_LANES for port A\n"); 4691 dig_port->saved_port_bits |= DDI_A_4_LANES; 4692 max_lanes = 4; 4693 } 4694 4695 return max_lanes; 4696 } 4697 4698 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv, 4699 enum port port) 4700 { 4701 if (port >= PORT_D_XELPD) 4702 return HPD_PORT_D + port - PORT_D_XELPD; 4703 else if (port >= PORT_TC1) 4704 return HPD_PORT_TC1 + port - PORT_TC1; 4705 else 4706 return HPD_PORT_A + port - PORT_A; 4707 } 4708 4709 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv, 4710 enum port port) 4711 { 4712 if (port >= PORT_TC1) 4713 return HPD_PORT_C + port - PORT_TC1; 4714 else 4715 return HPD_PORT_A + port - PORT_A; 4716 } 4717 4718 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv, 4719 enum port port) 4720 { 4721 if (port >= PORT_TC1) 4722 return HPD_PORT_TC1 + port - PORT_TC1; 4723 else 4724 return HPD_PORT_A + port - PORT_A; 4725 } 4726 4727 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv, 4728 enum port port) 4729 { 4730 if (HAS_PCH_TGP(dev_priv)) 4731 return tgl_hpd_pin(dev_priv, port); 4732 4733 if (port >= PORT_TC1) 4734 return HPD_PORT_C + port - PORT_TC1; 4735 else 4736 return HPD_PORT_A + port - PORT_A; 4737 } 4738 4739 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv, 4740 enum port port) 4741 { 4742 if (port >= PORT_C) 4743 return HPD_PORT_TC1 + port - PORT_C; 4744 else 4745 return HPD_PORT_A + port - PORT_A; 4746 } 4747 4748 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv, 4749 enum port port) 4750 { 4751 if (port == PORT_D) 4752 return HPD_PORT_A; 4753 4754 if (HAS_PCH_TGP(dev_priv)) 4755 return icl_hpd_pin(dev_priv, port); 4756 4757 return HPD_PORT_A + port - PORT_A; 4758 } 4759 4760 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port) 4761 { 4762 if (HAS_PCH_TGP(dev_priv)) 4763 return icl_hpd_pin(dev_priv, port); 4764 4765 return HPD_PORT_A + port - PORT_A; 4766 } 4767 4768 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port) 4769 { 4770 if (DISPLAY_VER(i915) >= 12) 4771 return port >= PORT_TC1; 4772 else if (DISPLAY_VER(i915) >= 11) 4773 return port >= PORT_C; 4774 else 4775 return false; 4776 } 4777 4778 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) 4779 { 4780 intel_dp_encoder_suspend(encoder); 4781 } 4782 4783 static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) 4784 { 4785 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4786 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4787 4788 intel_tc_port_suspend(dig_port); 4789 } 4790 4791 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) 4792 { 4793 intel_dp_encoder_shutdown(encoder); 4794 intel_hdmi_encoder_shutdown(encoder); 4795 } 4796 4797 static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder) 4798 { 4799 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 4800 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4801 4802 intel_tc_port_cleanup(dig_port); 4803 } 4804 4805 #define port_tc_name(port) ((port) - PORT_TC1 + '1') 4806 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') 4807 4808 static bool port_strap_detected(struct drm_i915_private *i915, enum port port) 4809 { 4810 /* straps not used on skl+ */ 4811 if (DISPLAY_VER(i915) >= 9) 4812 return true; 4813 4814 switch (port) { 4815 case PORT_A: 4816 return intel_de_read(i915, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; 4817 case PORT_B: 4818 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED; 4819 case PORT_C: 4820 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED; 4821 case PORT_D: 4822 return intel_de_read(i915, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED; 4823 case PORT_E: 4824 return true; /* no strap for DDI-E */ 4825 default: 4826 MISSING_CASE(port); 4827 return false; 4828 } 4829 } 4830 4831 static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp) 4832 { 4833 return init_dp || intel_encoder_is_tc(encoder); 4834 } 4835 4836 static bool assert_has_icl_dsi(struct drm_i915_private *i915) 4837 { 4838 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && 4839 !IS_TIGERLAKE(i915) && DISPLAY_VER(i915) != 11, 4840 "Platform does not support DSI\n"); 4841 } 4842 4843 static bool port_in_use(struct drm_i915_private *i915, enum port port) 4844 { 4845 struct intel_encoder *encoder; 4846 4847 for_each_intel_encoder(&i915->drm, encoder) { 4848 /* FIXME what about second port for dual link DSI? */ 4849 if (encoder->port == port) 4850 return true; 4851 } 4852 4853 return false; 4854 } 4855 4856 void intel_ddi_init(struct drm_i915_private *dev_priv, 4857 const struct intel_bios_encoder_data *devdata) 4858 { 4859 struct intel_digital_port *dig_port; 4860 struct intel_encoder *encoder; 4861 bool init_hdmi, init_dp; 4862 enum port port; 4863 enum phy phy; 4864 4865 port = intel_bios_encoder_port(devdata); 4866 if (port == PORT_NONE) 4867 return; 4868 4869 if (!port_strap_detected(dev_priv, port)) { 4870 drm_dbg_kms(&dev_priv->drm, 4871 "Port %c strap not detected\n", port_name(port)); 4872 return; 4873 } 4874 4875 if (!assert_port_valid(dev_priv, port)) 4876 return; 4877 4878 if (port_in_use(dev_priv, port)) { 4879 drm_dbg_kms(&dev_priv->drm, 4880 "Port %c already claimed\n", port_name(port)); 4881 return; 4882 } 4883 4884 if (intel_bios_encoder_supports_dsi(devdata)) { 4885 /* BXT/GLK handled elsewhere, for now at least */ 4886 if (!assert_has_icl_dsi(dev_priv)) 4887 return; 4888 4889 icl_dsi_init(dev_priv, devdata); 4890 return; 4891 } 4892 4893 phy = intel_port_to_phy(dev_priv, port); 4894 4895 /* 4896 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may 4897 * have taken over some of the PHYs and made them unavailable to the 4898 * driver. In that case we should skip initializing the corresponding 4899 * outputs. 4900 */ 4901 if (intel_hti_uses_phy(dev_priv, phy)) { 4902 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4903 port_name(port), phy_name(phy)); 4904 return; 4905 } 4906 4907 init_hdmi = intel_bios_encoder_supports_dvi(devdata) || 4908 intel_bios_encoder_supports_hdmi(devdata); 4909 init_dp = intel_bios_encoder_supports_dp(devdata); 4910 4911 if (intel_bios_encoder_is_lspcon(devdata)) { 4912 /* 4913 * Lspcon device needs to be driven with DP connector 4914 * with special detection sequence. So make sure DP 4915 * is initialized before lspcon. 4916 */ 4917 init_dp = true; 4918 init_hdmi = false; 4919 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", 4920 port_name(port)); 4921 } 4922 4923 if (!init_dp && !init_hdmi) { 4924 drm_dbg_kms(&dev_priv->drm, 4925 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 4926 port_name(port)); 4927 return; 4928 } 4929 4930 if (intel_phy_is_snps(dev_priv, phy) && 4931 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { 4932 drm_dbg_kms(&dev_priv->drm, 4933 "SNPS PHY %c failed to calibrate, proceeding anyway\n", 4934 phy_name(phy)); 4935 } 4936 4937 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 4938 if (!dig_port) 4939 return; 4940 4941 dig_port->aux_ch = AUX_CH_NONE; 4942 4943 encoder = &dig_port->base; 4944 encoder->devdata = devdata; 4945 4946 if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) { 4947 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4948 DRM_MODE_ENCODER_TMDS, 4949 "DDI %c/PHY %c", 4950 port_name(port - PORT_D_XELPD + PORT_D), 4951 phy_name(phy)); 4952 } else if (DISPLAY_VER(dev_priv) >= 12) { 4953 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4954 4955 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4956 DRM_MODE_ENCODER_TMDS, 4957 "DDI %s%c/PHY %s%c", 4958 port >= PORT_TC1 ? "TC" : "", 4959 port >= PORT_TC1 ? port_tc_name(port) : port_name(port), 4960 tc_port != TC_PORT_NONE ? "TC" : "", 4961 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4962 } else if (DISPLAY_VER(dev_priv) >= 11) { 4963 enum tc_port tc_port = intel_port_to_tc(dev_priv, port); 4964 4965 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4966 DRM_MODE_ENCODER_TMDS, 4967 "DDI %c%s/PHY %s%c", 4968 port_name(port), 4969 port >= PORT_C ? " (TC)" : "", 4970 tc_port != TC_PORT_NONE ? "TC" : "", 4971 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 4972 } else { 4973 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, 4974 DRM_MODE_ENCODER_TMDS, 4975 "DDI %c/PHY %c", port_name(port), phy_name(phy)); 4976 } 4977 4978 mutex_init(&dig_port->hdcp_mutex); 4979 dig_port->num_hdcp_streams = 0; 4980 4981 encoder->hotplug = intel_ddi_hotplug; 4982 encoder->compute_output_type = intel_ddi_compute_output_type; 4983 encoder->compute_config = intel_ddi_compute_config; 4984 encoder->compute_config_late = intel_ddi_compute_config_late; 4985 encoder->enable = intel_enable_ddi; 4986 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 4987 encoder->pre_enable = intel_ddi_pre_enable; 4988 encoder->disable = intel_disable_ddi; 4989 encoder->post_pll_disable = intel_ddi_post_pll_disable; 4990 encoder->post_disable = intel_ddi_post_disable; 4991 encoder->update_pipe = intel_ddi_update_pipe; 4992 encoder->audio_enable = intel_audio_codec_enable; 4993 encoder->audio_disable = intel_audio_codec_disable; 4994 encoder->get_hw_state = intel_ddi_get_hw_state; 4995 encoder->sync_state = intel_ddi_sync_state; 4996 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; 4997 encoder->suspend = intel_ddi_encoder_suspend; 4998 encoder->shutdown = intel_ddi_encoder_shutdown; 4999 encoder->get_power_domains = intel_ddi_get_power_domains; 5000 5001 encoder->type = INTEL_OUTPUT_DDI; 5002 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 5003 encoder->port = port; 5004 encoder->cloneable = 0; 5005 encoder->pipe_mask = ~0; 5006 5007 if (DISPLAY_VER(dev_priv) >= 14) { 5008 encoder->enable_clock = intel_mtl_pll_enable; 5009 encoder->disable_clock = intel_mtl_pll_disable; 5010 encoder->port_pll_type = intel_mtl_port_pll_type; 5011 encoder->get_config = mtl_ddi_get_config; 5012 } else if (IS_DG2(dev_priv)) { 5013 encoder->enable_clock = intel_mpllb_enable; 5014 encoder->disable_clock = intel_mpllb_disable; 5015 encoder->get_config = dg2_ddi_get_config; 5016 } else if (IS_ALDERLAKE_S(dev_priv)) { 5017 encoder->enable_clock = adls_ddi_enable_clock; 5018 encoder->disable_clock = adls_ddi_disable_clock; 5019 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; 5020 encoder->get_config = adls_ddi_get_config; 5021 } else if (IS_ROCKETLAKE(dev_priv)) { 5022 encoder->enable_clock = rkl_ddi_enable_clock; 5023 encoder->disable_clock = rkl_ddi_disable_clock; 5024 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; 5025 encoder->get_config = rkl_ddi_get_config; 5026 } else if (IS_DG1(dev_priv)) { 5027 encoder->enable_clock = dg1_ddi_enable_clock; 5028 encoder->disable_clock = dg1_ddi_disable_clock; 5029 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; 5030 encoder->get_config = dg1_ddi_get_config; 5031 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 5032 if (intel_ddi_is_tc(dev_priv, port)) { 5033 encoder->enable_clock = jsl_ddi_tc_enable_clock; 5034 encoder->disable_clock = jsl_ddi_tc_disable_clock; 5035 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; 5036 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5037 encoder->get_config = icl_ddi_combo_get_config; 5038 } else { 5039 encoder->enable_clock = icl_ddi_combo_enable_clock; 5040 encoder->disable_clock = icl_ddi_combo_disable_clock; 5041 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5042 encoder->get_config = icl_ddi_combo_get_config; 5043 } 5044 } else if (DISPLAY_VER(dev_priv) >= 11) { 5045 if (intel_ddi_is_tc(dev_priv, port)) { 5046 encoder->enable_clock = icl_ddi_tc_enable_clock; 5047 encoder->disable_clock = icl_ddi_tc_disable_clock; 5048 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; 5049 encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5050 encoder->get_config = icl_ddi_tc_get_config; 5051 } else { 5052 encoder->enable_clock = icl_ddi_combo_enable_clock; 5053 encoder->disable_clock = icl_ddi_combo_disable_clock; 5054 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; 5055 encoder->get_config = icl_ddi_combo_get_config; 5056 } 5057 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5058 /* BXT/GLK have fixed PLL->port mapping */ 5059 encoder->get_config = bxt_ddi_get_config; 5060 } else if (DISPLAY_VER(dev_priv) == 9) { 5061 encoder->enable_clock = skl_ddi_enable_clock; 5062 encoder->disable_clock = skl_ddi_disable_clock; 5063 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; 5064 encoder->get_config = skl_ddi_get_config; 5065 } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { 5066 encoder->enable_clock = hsw_ddi_enable_clock; 5067 encoder->disable_clock = hsw_ddi_disable_clock; 5068 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; 5069 encoder->get_config = hsw_ddi_get_config; 5070 } 5071 5072 if (DISPLAY_VER(dev_priv) >= 14) { 5073 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; 5074 } else if (IS_DG2(dev_priv)) { 5075 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; 5076 } else if (DISPLAY_VER(dev_priv) >= 12) { 5077 if (intel_encoder_is_combo(encoder)) 5078 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5079 else 5080 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; 5081 } else if (DISPLAY_VER(dev_priv) >= 11) { 5082 if (intel_encoder_is_combo(encoder)) 5083 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; 5084 else 5085 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; 5086 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5087 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; 5088 } else { 5089 encoder->set_signal_levels = hsw_set_signal_levels; 5090 } 5091 5092 intel_ddi_buf_trans_init(encoder); 5093 5094 if (DISPLAY_VER(dev_priv) >= 13) 5095 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); 5096 else if (IS_DG1(dev_priv)) 5097 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); 5098 else if (IS_ROCKETLAKE(dev_priv)) 5099 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); 5100 else if (DISPLAY_VER(dev_priv) >= 12) 5101 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); 5102 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) 5103 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); 5104 else if (DISPLAY_VER(dev_priv) == 11) 5105 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); 5106 else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) 5107 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); 5108 else 5109 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5110 5111 if (DISPLAY_VER(dev_priv) >= 11) 5112 dig_port->saved_port_bits = 5113 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5114 & DDI_BUF_PORT_REVERSAL; 5115 else 5116 dig_port->saved_port_bits = 5117 intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5118 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5119 5120 if (intel_bios_encoder_lane_reversal(devdata)) 5121 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 5122 5123 dig_port->dp.output_reg = INVALID_MMIO_REG; 5124 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); 5125 5126 if (need_aux_ch(encoder, init_dp)) { 5127 dig_port->aux_ch = intel_dp_aux_ch(encoder); 5128 if (dig_port->aux_ch == AUX_CH_NONE) 5129 goto err; 5130 } 5131 5132 if (intel_encoder_is_tc(encoder)) { 5133 bool is_legacy = 5134 !intel_bios_encoder_supports_typec_usb(devdata) && 5135 !intel_bios_encoder_supports_tbt(devdata); 5136 5137 if (!is_legacy && init_hdmi) { 5138 is_legacy = !init_dp; 5139 5140 drm_dbg_kms(&dev_priv->drm, 5141 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", 5142 port_name(port), 5143 str_yes_no(init_dp), 5144 is_legacy ? "legacy" : "non-legacy"); 5145 } 5146 5147 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; 5148 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; 5149 5150 dig_port->lock = intel_tc_port_lock; 5151 dig_port->unlock = intel_tc_port_unlock; 5152 5153 if (intel_tc_port_init(dig_port, is_legacy) < 0) 5154 goto err; 5155 } 5156 5157 drm_WARN_ON(&dev_priv->drm, port > PORT_I); 5158 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); 5159 5160 if (DISPLAY_VER(dev_priv) >= 11) { 5161 if (intel_encoder_is_tc(encoder)) 5162 dig_port->connected = intel_tc_port_connected; 5163 else 5164 dig_port->connected = lpt_digital_port_connected; 5165 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 5166 dig_port->connected = bdw_digital_port_connected; 5167 } else if (DISPLAY_VER(dev_priv) == 9) { 5168 dig_port->connected = lpt_digital_port_connected; 5169 } else if (IS_BROADWELL(dev_priv)) { 5170 if (port == PORT_A) 5171 dig_port->connected = bdw_digital_port_connected; 5172 else 5173 dig_port->connected = lpt_digital_port_connected; 5174 } else if (IS_HASWELL(dev_priv)) { 5175 if (port == PORT_A) 5176 dig_port->connected = hsw_digital_port_connected; 5177 else 5178 dig_port->connected = lpt_digital_port_connected; 5179 } 5180 5181 intel_infoframe_init(dig_port); 5182 5183 if (init_dp) { 5184 if (!intel_ddi_init_dp_connector(dig_port)) 5185 goto err; 5186 5187 dig_port->hpd_pulse = intel_dp_hpd_pulse; 5188 5189 if (dig_port->dp.mso_link_count) 5190 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); 5191 } 5192 5193 /* 5194 * In theory we don't need the encoder->type check, 5195 * but leave it just in case we have some really bad VBTs... 5196 */ 5197 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 5198 if (!intel_ddi_init_hdmi_connector(dig_port)) 5199 goto err; 5200 } 5201 5202 return; 5203 5204 err: 5205 drm_encoder_cleanup(&encoder->base); 5206 kfree(dig_port); 5207 } 5208