1*ac930babSVille Syrjälä /* SPDX-License-Identifier: MIT */ 2*ac930babSVille Syrjälä /* 3*ac930babSVille Syrjälä * Copyright © 2025 Intel Corporation 4*ac930babSVille Syrjälä */ 5*ac930babSVille Syrjälä 6*ac930babSVille Syrjälä #ifndef __INTEL_DBUF_BW_H__ 7*ac930babSVille Syrjälä #define __INTEL_DBUF_BW_H__ 8*ac930babSVille Syrjälä 9*ac930babSVille Syrjälä #include <drm/drm_atomic.h> 10*ac930babSVille Syrjälä 11*ac930babSVille Syrjälä struct intel_atomic_state; 12*ac930babSVille Syrjälä struct intel_dbuf_bw_state; 13*ac930babSVille Syrjälä struct intel_crtc; 14*ac930babSVille Syrjälä struct intel_display; 15*ac930babSVille Syrjälä struct intel_global_state; 16*ac930babSVille Syrjälä 17*ac930babSVille Syrjälä struct intel_dbuf_bw_state * 18*ac930babSVille Syrjälä to_intel_dbuf_bw_state(struct intel_global_state *obj_state); 19*ac930babSVille Syrjälä 20*ac930babSVille Syrjälä struct intel_dbuf_bw_state * 21*ac930babSVille Syrjälä intel_atomic_get_old_dbuf_bw_state(struct intel_atomic_state *state); 22*ac930babSVille Syrjälä 23*ac930babSVille Syrjälä struct intel_dbuf_bw_state * 24*ac930babSVille Syrjälä intel_atomic_get_new_dbuf_bw_state(struct intel_atomic_state *state); 25*ac930babSVille Syrjälä 26*ac930babSVille Syrjälä struct intel_dbuf_bw_state * 27*ac930babSVille Syrjälä intel_atomic_get_dbuf_bw_state(struct intel_atomic_state *state); 28*ac930babSVille Syrjälä 29*ac930babSVille Syrjälä int intel_dbuf_bw_init(struct intel_display *display); 30*ac930babSVille Syrjälä int intel_dbuf_bw_calc_min_cdclk(struct intel_atomic_state *state, 31*ac930babSVille Syrjälä bool *need_cdclk_calc); 32*ac930babSVille Syrjälä int intel_dbuf_bw_min_cdclk(struct intel_display *display, 33*ac930babSVille Syrjälä const struct intel_dbuf_bw_state *dbuf_bw_state); 34*ac930babSVille Syrjälä void intel_dbuf_bw_update_hw_state(struct intel_display *display); 35*ac930babSVille Syrjälä void intel_dbuf_bw_crtc_disable_noatomic(struct intel_crtc *crtc); 36*ac930babSVille Syrjälä 37*ac930babSVille Syrjälä #endif /* __INTEL_DBUF_BW_H__ */ 38