1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_CX0_PHY_REGS_H__ 7 #define __INTEL_CX0_PHY_REGS_H__ 8 9 #include "intel_display_limits.h" 10 #include "intel_display_reg_defs.h" 11 12 /* DDI Buffer Control */ 13 #define _DDI_CLK_VALFREQ_A 0x64030 14 #define _DDI_CLK_VALFREQ_B 0x64130 15 #define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) 16 17 /* 18 * Wrapper macro to convert from port number to the index used in some of the 19 * registers. For Display version 20 and above it converts the port number to a 20 * single range, starting with the TC offsets. When used together with 21 * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second 22 * range. Example: 23 * 24 * PORT_TC1 -> PORT_TC1 25 * PORT_TC2 -> PORT_TC2 26 * PORT_TC3 -> PORT_TC3 27 * PORT_TC4 -> PORT_TC4 28 * PORT_A -> PORT_TC4 + 1 29 * PORT_B -> PORT_TC4 + 2 30 * ... 31 */ 32 #define __xe2lpd_port_idx(port) \ 33 (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A) 34 35 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040 36 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140 37 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240 38 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440 39 #define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 40 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ 41 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ 42 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ 43 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4) 44 #define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \ 45 (DISPLAY_VER(i915__) >= 20 ? \ 46 _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \ 47 _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)) 48 #define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31) 49 #define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27) 50 #define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1) 51 #define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2) 52 #define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3) 53 #define XELPDP_PORT_P2P_TRANSACTION_PENDING REG_BIT(24) 54 #define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16) 55 #define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val) 56 #define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15) 57 #define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0) 58 #define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val) 59 60 #define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 61 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ 62 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ 63 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ 64 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8) 65 #define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \ 66 (DISPLAY_VER(i915__) >= 20 ? \ 67 _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \ 68 _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) 69 #define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31) 70 #define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27) 71 #define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4 72 #define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5 73 #define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16) 74 #define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val) 75 #define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15) 76 77 #define XELPDP_MSGBUS_TIMEOUT_SLOW 1 78 #define XELPDP_MSGBUS_TIMEOUT_FAST_US 2 79 #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200 80 #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20 81 #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100 82 #define XELPDP_PORT_RESET_START_TIMEOUT_US 5 83 #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US 100 84 #define XELPDP_PORT_RESET_END_TIMEOUT 15 85 #define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1 86 87 #define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004 88 #define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104 89 #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200 90 #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400 91 #define _XELPDP_PORT_BUF_CTL1(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 92 _XELPDP_PORT_BUF_CTL1_LN0_A, \ 93 _XELPDP_PORT_BUF_CTL1_LN0_B, \ 94 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ 95 _XELPDP_PORT_BUF_CTL1_LN0_USBC2)) 96 #define XELPDP_PORT_BUF_CTL1(i915__, port) \ 97 (DISPLAY_VER(i915__) >= 20 ? \ 98 _XELPDP_PORT_BUF_CTL1(__xe2lpd_port_idx(port)) : \ 99 _XELPDP_PORT_BUF_CTL1(port)) 100 #define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29) 101 #define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28) 102 #define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24) 103 #define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK REG_GENMASK(19, 18) 104 #define XELPDP_PORT_BUF_PORT_DATA_10BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0) 105 #define XELPDP_PORT_BUF_PORT_DATA_20BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1) 106 #define XELPDP_PORT_BUF_PORT_DATA_40BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2) 107 #define XELPDP_PORT_REVERSAL REG_BIT(16) 108 #define XE3PLPDP_PHY_MODE_MASK REG_GENMASK(15, 12) 109 #define XE3PLPDP_PHY_MODE_DP REG_FIELD_PREP(XE3PLPDP_PHY_MODE_MASK, 0x3) 110 #define XELPDP_PORT_BUF_IO_SELECT_TBT REG_BIT(11) 111 #define XELPDP_PORT_BUF_PHY_IDLE REG_BIT(7) 112 #define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6) 113 #define XELPDP_TCSS_POWER_REQUEST REG_BIT(5) 114 #define XELPDP_TCSS_POWER_STATE REG_BIT(4) 115 #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1) 116 #define XELPDP_PORT_WIDTH(width) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, \ 117 ((width) == 3 ? 4 : (width) - 1)) 118 119 #define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 120 _XELPDP_PORT_BUF_CTL1_LN0_A, \ 121 _XELPDP_PORT_BUF_CTL1_LN0_B, \ 122 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ 123 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4) 124 #define XELPDP_PORT_BUF_CTL2(i915__, port) \ 125 (DISPLAY_VER(i915__) >= 20 ? \ 126 _XELPDP_PORT_BUF_CTL2(__xe2lpd_port_idx(port)) : \ 127 _XELPDP_PORT_BUF_CTL2(port)) 128 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) 129 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) 130 #define XE3PLPDP_LANE_PHY_PULSE_STATUS(lane) _PICK(lane, REG_BIT(27), REG_BIT(26)) 131 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) 132 #define _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20) 133 #define _XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val) 134 #define _XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16) 135 #define _XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val) 136 #define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \ 137 _XELPDP_LANE0_POWERDOWN_NEW_STATE(val), \ 138 _XELPDP_LANE1_POWERDOWN_NEW_STATE(val)) 139 #define XELPDP_LANE_POWERDOWN_NEW_STATE_MASK REG_GENMASK(3, 0) 140 #define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4) 141 #define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val) 142 143 #define _XELPDP_PORT_BUF_CTL3(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 144 _XELPDP_PORT_BUF_CTL1_LN0_A, \ 145 _XELPDP_PORT_BUF_CTL1_LN0_B, \ 146 _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ 147 _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8) 148 #define XELPDP_PORT_BUF_CTL3(i915__, port) \ 149 (DISPLAY_VER(i915__) >= 20 ? \ 150 _XELPDP_PORT_BUF_CTL3(__xe2lpd_port_idx(port)) : \ 151 _XELPDP_PORT_BUF_CTL3(port)) 152 #define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8) 153 #define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val) 154 #define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0) 155 #define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val) 156 #define XELPDP_P0_STATE_ACTIVE 0x0 157 #define XELPDP_P2_STATE_READY 0x2 158 #define XE3PLPD_P4_STATE_DISABLE 0x4 159 #define XELPDP_P2PG_STATE_DISABLE 0x9 160 #define XELPDP_P4PG_STATE_DISABLE 0xC 161 #define XELPDP_P2_STATE_RESET 0x2 162 163 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_A 0x640d8 164 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_B 0x641d8 165 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1 0x16f258 166 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2 0x16f458 167 #define _XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ 168 _XELPDP_PORT_MSGBUS_TIMER_LN0_A, \ 169 _XELPDP_PORT_MSGBUS_TIMER_LN0_B, \ 170 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1, \ 171 _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2) + (lane) * 4) 172 #define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane) \ 173 (DISPLAY_VER(i915__) >= 20 ? \ 174 _XELPDP_PORT_MSGBUS_TIMER(__xe2lpd_port_idx(port), lane) : \ 175 _XELPDP_PORT_MSGBUS_TIMER(port, lane)) 176 #define XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT REG_BIT(31) 177 #define XELPDP_PORT_MSGBUS_TIMER_VAL_MASK REG_GENMASK(23, 0) 178 #define XELPDP_PORT_MSGBUS_TIMER_VAL REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, 0xa000) 179 180 #define _XELPDP_PORT_CLOCK_CTL_A 0x640E0 181 #define _XELPDP_PORT_CLOCK_CTL_B 0x641E0 182 #define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260 183 #define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460 184 #define _XELPDP_PORT_CLOCK_CTL(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ 185 _XELPDP_PORT_CLOCK_CTL_A, \ 186 _XELPDP_PORT_CLOCK_CTL_B, \ 187 _XELPDP_PORT_CLOCK_CTL_USBC1, \ 188 _XELPDP_PORT_CLOCK_CTL_USBC2)) 189 #define XELPDP_PORT_CLOCK_CTL(i915__, port) \ 190 (DISPLAY_VER(i915__) >= 20 ? \ 191 _XELPDP_PORT_CLOCK_CTL(__xe2lpd_port_idx(port)) : \ 192 _XELPDP_PORT_CLOCK_CTL(port)) 193 #define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4)) 194 #define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4)) 195 #define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4)) 196 #define XELPDP_LANE_PCLK_REFCLK_ACK(lane) REG_BIT(28 - ((lane) * 4)) 197 198 #define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19) 199 #define XELPDP_TBT_CLOCK_ACK REG_BIT(18) 200 #define _XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12) 201 #define _XE3_DDI_CLOCK_SELECT_MASK REG_GENMASK(16, 12) 202 #define XELPDP_DDI_CLOCK_SELECT_MASK(display) (DISPLAY_VER(display) >= 30 ? \ 203 _XE3_DDI_CLOCK_SELECT_MASK : _XELPDP_DDI_CLOCK_SELECT_MASK) 204 #define XELPDP_DDI_CLOCK_SELECT_PREP(display, val) (DISPLAY_VER(display) >= 30 ? \ 205 REG_FIELD_PREP(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \ 206 REG_FIELD_PREP(_XELPDP_DDI_CLOCK_SELECT_MASK, (val))) 207 #define XELPDP_DDI_CLOCK_SELECT_GET(display, val) (DISPLAY_VER(display) >= 30 ? \ 208 REG_FIELD_GET(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \ 209 REG_FIELD_GET(_XELPDP_DDI_CLOCK_SELECT_MASK, (val))) 210 211 #define XELPDP_DDI_CLOCK_SELECT_NONE 0x0 212 #define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8 213 #define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9 214 #define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc 215 #define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd 216 #define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe 217 #define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf 218 #define XELPDP_DDI_CLOCK_SELECT_TBT_312_5 0x18 219 #define XELPDP_DDI_CLOCK_SELECT_TBT_625 0x19 220 #define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10) 221 #define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8) 222 #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1) 223 #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0) 224 225 #define TCSS_DISP_MAILBOX_IN_CMD _MMIO(0x161300) 226 #define TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY REG_BIT(31) 227 #define TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK REG_GENMASK(7, 0) 228 #define TCSS_DISP_MAILBOX_IN_CMD_DATA(val) REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, val) 229 230 #define TCSS_DISP_MAILBOX_IN_DATA _MMIO(0x161304) 231 232 /* C10 Vendor Registers */ 233 #define PHY_C10_VDR_PLL(idx) (0xC00 + (idx)) 234 #define C10_PLL0_SSC_EN REG_BIT8(0) 235 #define C10_PLL0_DIVCLK_EN REG_BIT8(1) 236 #define C10_PLL0_DIV5CLK_EN REG_BIT8(2) 237 #define C10_PLL0_WORDDIV2_EN REG_BIT8(3) 238 #define C10_PLL0_FRACEN REG_BIT8(4) 239 #define C10_PLL0_PMIX_EN REG_BIT8(5) 240 #define C10_PLL0_ANA_FREQ_VCO_MASK REG_GENMASK8(7, 6) 241 #define C10_PLL1_DIV_MULTIPLIER_MASK REG_GENMASK8(7, 0) 242 #define C10_PLL2_MULTIPLIERL_MASK REG_GENMASK8(7, 0) 243 #define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0) 244 #define C10_PLL8_SSC_UP_SPREAD REG_BIT8(5) 245 #define C10_PLL9_FRACN_DENL_MASK REG_GENMASK8(7, 0) 246 #define C10_PLL10_FRACN_DENH_MASK REG_GENMASK8(7, 0) 247 #define C10_PLL11_FRACN_QUOT_L_MASK REG_GENMASK8(7, 0) 248 #define C10_PLL12_FRACN_QUOT_H_MASK REG_GENMASK8(7, 0) 249 #define C10_PLL13_FRACN_REM_L_MASK REG_GENMASK8(7, 0) 250 #define C10_PLL14_FRACN_REM_H_MASK REG_GENMASK8(7, 0) 251 #define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0) 252 #define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3) 253 #define C10_PLL15_PIXELCLKDIV_MASK REG_GENMASK8(7, 6) 254 #define C10_PLL16_ANA_CPINT REG_GENMASK8(6, 0) 255 #define C10_PLL16_ANA_CPINTGS_L REG_BIT8(7) 256 #define C10_PLL17_ANA_CPINTGS_H_MASK REG_GENMASK8(5, 0) 257 #define C10_PLL17_ANA_CPPROP_L_MASK REG_GENMASK8(7, 6) 258 #define C10_PLL18_ANA_CPPROP_H_MASK REG_GENMASK8(4, 0) 259 #define C10_PLL18_ANA_CPPROPGS_L_MASK REG_GENMASK8(7, 5) 260 #define C10_PLL19_ANA_CPPROPGS_H_MASK REG_GENMASK8(3, 0) 261 #define C10_PLL19_ANA_V2I_MASK REG_GENMASK8(5, 4) 262 263 #define PHY_C10_VDR_CMN(idx) (0xC20 + (idx)) 264 #define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1) 265 #define C10_CMN0_REF_CLK_MPLLB_DIV REG_FIELD_PREP(REG_GENMASK(7, 5), 1) 266 #define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5) 267 #define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val) 268 #define PHY_C10_VDR_TX(idx) (0xC30 + (idx)) 269 #define C10_TX0_TX_MPLLB_SEL REG_BIT(4) 270 #define C10_TX1_TERMCTL_MASK REG_GENMASK8(7, 5) 271 #define C10_TX1_TERMCTL(val) REG_FIELD_PREP8(C10_TX1_TERMCTL_MASK, val) 272 #define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1) 273 #define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2) 274 #define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1) 275 #define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0) 276 #define PHY_C10_VDR_CUSTOM_WIDTH 0xD02 277 #define C10_VDR_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) 278 #define C10_VDR_CUSTOM_WIDTH_8_10 REG_FIELD_PREP(C10_VDR_CUSTOM_WIDTH_MASK, 0) 279 #define PHY_C10_VDR_OVRD 0xD71 280 #define PHY_C10_VDR_OVRD_TX1 REG_BIT8(0) 281 #define PHY_C10_VDR_OVRD_TX2 REG_BIT8(2) 282 #define PHY_C10_VDR_PRE_OVRD_TX1 0xD80 283 #define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0) 284 #define C10_PHY_OVRD_LEVEL(val) REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val) 285 #define PHY_CX0_VDROVRD_CTL(lane, tx, control) \ 286 (PHY_C10_VDR_PRE_OVRD_TX1 + \ 287 ((lane) ^ (tx)) * 0x10 + (control)) 288 289 /* PIPE SPEC Defined Registers */ 290 #define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control)) 291 #define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6) 292 293 #define PHY_CMN1_CONTROL(tx, control) (0x800 + ((tx) - 1) * 0x200 + (control)) 294 #define CONTROL0_MAC_TRANSMIT_LFPS REG_BIT(1) 295 296 /* C20 Registers */ 297 #define PHY_C20_WR_ADDRESS_L 0xC02 298 #define PHY_C20_WR_ADDRESS_H 0xC03 299 #define PHY_C20_WR_DATA_L 0xC04 300 #define PHY_C20_WR_DATA_H 0xC05 301 #define PHY_C20_RD_ADDRESS_L 0xC06 302 #define PHY_C20_RD_ADDRESS_H 0xC07 303 #define PHY_C20_RD_DATA_L 0xC08 304 #define PHY_C20_RD_DATA_H 0xC09 305 #define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00 306 #define PHY_C20_IS_HDMI_FRL REG_BIT8(7) 307 #define PHY_C20_IS_DP REG_BIT8(6) 308 #define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1) 309 #define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val) 310 #define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0) 311 #define PHY_C20_VDR_HDMI_RATE 0xD01 312 #define PHY_C20_HDMI_RATE_MASK REG_GENMASK8(1, 0) 313 #define PHY_C20_HDMI_RATE(val) REG_FIELD_PREP8(PHY_C20_HDMI_RATE_MASK, val) 314 #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02 315 #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) 316 #define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val) 317 318 #define _MTL_C20_A_TX_CNTX_CFG 0xCF2E 319 #define _MTL_C20_B_TX_CNTX_CFG 0xCF2A 320 #define _MTL_C20_A_CMN_CNTX_CFG 0xCDAA 321 #define _MTL_C20_B_CMN_CNTX_CFG 0xCDA5 322 #define _MTL_C20_A_MPLLA_CFG 0xCCF0 323 #define _MTL_C20_B_MPLLA_CFG 0xCCE5 324 #define _MTL_C20_A_MPLLB_CFG 0xCB5A 325 #define _MTL_C20_B_MPLLB_CFG 0xCB4E 326 327 #define _XE2HPD_C20_A_TX_CNTX_CFG 0xCF5E 328 #define _XE2HPD_C20_B_TX_CNTX_CFG 0xCF5A 329 #define _XE2HPD_C20_A_CMN_CNTX_CFG 0xCE8E 330 #define _XE2HPD_C20_B_CMN_CNTX_CFG 0xCE89 331 #define _XE2HPD_C20_A_MPLLA_CFG 0xCE58 332 #define _XE2HPD_C20_B_MPLLA_CFG 0xCE4D 333 #define _XE2HPD_C20_A_MPLLB_CFG 0xCCC2 334 #define _XE2HPD_C20_B_MPLLB_CFG 0xCCB6 335 336 #define _IS_XE2HPD_C20(i915) (DISPLAY_VERx100(i915) == 1401) 337 338 #define PHY_C20_A_TX_CNTX_CFG(i915, idx) \ 339 ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx)) 340 #define PHY_C20_B_TX_CNTX_CFG(i915, idx) \ 341 ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx)) 342 #define C20_PHY_TX_RATE REG_GENMASK(2, 0) 343 #define C20_PHY_TX_MISC_MASK REG_GENMASK16(7, 0) 344 #define C20_PHY_TX_MISC(val) REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val)) 345 #define C20_PHY_TX_DCC_CAL_RANGE_MASK REG_GENMASK16(11, 8) 346 #define C20_PHY_TX_DCC_CAL_RANGE(val) \ 347 REG_FIELD_PREP16(C20_PHY_TX_DCC_CAL_RANGE_MASK, (val)) 348 #define C20_PHY_TX_DCC_BYPASS REG_BIT(12) 349 #define C20_PHY_TX_TERM_CTL_MASK REG_GENMASK16(15, 13) 350 #define C20_PHY_TX_TERM_CTL(val) REG_FIELD_PREP16(C20_PHY_TX_TERM_CTL_MASK, (val)) 351 352 #define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \ 353 ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx)) 354 #define PHY_C20_B_CMN_CNTX_CFG(i915, idx) \ 355 ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_CMN_CNTX_CFG : _MTL_C20_B_CMN_CNTX_CFG) - (idx)) 356 #define PHY_C20_A_MPLLA_CNTX_CFG(i915, idx) \ 357 ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLA_CFG : _MTL_C20_A_MPLLA_CFG) - (idx)) 358 #define PHY_C20_B_MPLLA_CNTX_CFG(i915, idx) \ 359 ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLA_CFG : _MTL_C20_B_MPLLA_CFG) - (idx)) 360 #define C20_MPLLA_FRACEN REG_BIT(14) 361 #define C20_FB_CLK_DIV4_EN REG_BIT(13) 362 #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8) 363 364 #define PHY_C20_A_MPLLB_CNTX_CFG(i915, idx) \ 365 ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLB_CFG : _MTL_C20_A_MPLLB_CFG) - (idx)) 366 #define PHY_C20_B_MPLLB_CNTX_CFG(i915, idx) \ 367 ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLB_CFG : _MTL_C20_B_MPLLB_CFG) - (idx)) 368 369 #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13) 370 #define C20_MPLLB_FRACEN REG_BIT(13) 371 #define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10) 372 #define C20_MULTIPLIER_MASK REG_GENMASK(11, 0) 373 #define C20_PHY_USE_MPLLB REG_BIT(7) 374 375 /* C20 Phy VSwing Masks */ 376 #define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0) 377 #define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val) 378 379 #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx)) 380 381 /* C20 HDMI computed pll definitions */ 382 #define REFCLK_38_4_MHZ 38400000 383 #define CLOCK_4999MHZ 4999999999 384 #define CLOCK_9999MHZ 9999999999 385 #define DATARATE_3000000000 3000000000 386 #define DATARATE_3500000000 3500000000 387 #define DATARATE_4000000000 4000000000 388 #define MPLL_FRACN_DEN 0xFFFF 389 390 #define SSC_UP_SPREAD REG_BIT16(9) 391 #define WORD_CLK_DIV REG_BIT16(8) 392 393 #define MPLL_TX_CLK_DIV(val) REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val) 394 #define MPLL_MULTIPLIER(val) REG_FIELD_PREP16(C20_MULTIPLIER_MASK, val) 395 396 #define MPLLB_ANA_FREQ_VCO_0 0 397 #define MPLLB_ANA_FREQ_VCO_1 1 398 #define MPLLB_ANA_FREQ_VCO_2 2 399 #define MPLLB_ANA_FREQ_VCO_3 3 400 #define MPLLB_ANA_FREQ_VCO_MASK REG_GENMASK16(15, 14) 401 #define MPLLB_ANA_FREQ_VCO(val) REG_FIELD_PREP16(MPLLB_ANA_FREQ_VCO_MASK, val) 402 403 #define MPLL_DIV_MULTIPLIER_MASK REG_GENMASK16(7, 0) 404 #define MPLL_DIV_MULTIPLIER(val) REG_FIELD_PREP16(MPLL_DIV_MULTIPLIER_MASK, val) 405 406 #define CAL_DAC_CODE_31 31 407 #define CAL_DAC_CODE_MASK REG_GENMASK16(14, 10) 408 #define CAL_DAC_CODE(val) REG_FIELD_PREP16(CAL_DAC_CODE_MASK, val) 409 410 #define CP_INT_GS_28 28 411 #define CP_INT_GS_MASK REG_GENMASK16(6, 0) 412 #define CP_INT_GS(val) REG_FIELD_PREP16(CP_INT_GS_MASK, val) 413 414 #define CP_PROP_GS_30 30 415 #define CP_PROP_GS_MASK REG_GENMASK16(13, 7) 416 #define CP_PROP_GS(val) REG_FIELD_PREP16(CP_PROP_GS_MASK, val) 417 418 #define CP_INT_6 6 419 #define CP_INT_MASK REG_GENMASK16(6, 0) 420 #define CP_INT(val) REG_FIELD_PREP16(CP_INT_MASK, val) 421 422 #define CP_PROP_20 20 423 #define CP_PROP_MASK REG_GENMASK16(13, 7) 424 #define CP_PROP(val) REG_FIELD_PREP16(CP_PROP_MASK, val) 425 426 #define V2I_2 2 427 #define V2I_MASK REG_GENMASK16(15, 14) 428 #define V2I(val) REG_FIELD_PREP16(V2I_MASK, val) 429 430 #define HDMI_DIV_1 1 431 #define HDMI_DIV_MASK REG_GENMASK16(2, 0) 432 #define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val) 433 434 #define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68) 435 #define EDP_ON_TYPEC REG_BIT(31) 436 437 #endif /* __INTEL_CX0_REG_DEFS_H__ */ 438