1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_CX0_PHY_H__ 7 #define __INTEL_CX0_PHY_H__ 8 9 #include <linux/types.h> 10 11 #define MB_WRITE_COMMITTED true 12 #define MB_WRITE_UNCOMMITTED false 13 14 enum icl_port_dpll_id; 15 struct intel_atomic_state; 16 struct intel_c10pll_state; 17 struct intel_c20pll_state; 18 struct intel_crtc; 19 struct intel_crtc_state; 20 struct intel_cx0pll_state; 21 struct intel_display; 22 struct intel_encoder; 23 struct intel_hdmi; 24 25 void intel_clear_response_ready_flag(struct intel_encoder *encoder, 26 int lane); 27 bool intel_encoder_is_c10phy(struct intel_encoder *encoder); 28 void intel_mtl_pll_enable(struct intel_encoder *encoder, 29 const struct intel_crtc_state *crtc_state); 30 void intel_mtl_pll_disable(struct intel_encoder *encoder); 31 enum icl_port_dpll_id 32 intel_mtl_port_pll_type(struct intel_encoder *encoder, 33 const struct intel_crtc_state *crtc_state); 34 35 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder); 36 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, 37 struct intel_cx0pll_state *pll_state); 38 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, 39 const struct intel_cx0pll_state *pll_state); 40 41 void intel_cx0pll_dump_hw_state(struct intel_display *display, 42 const struct intel_cx0pll_state *hw_state); 43 void intel_cx0pll_state_verify(struct intel_atomic_state *state, 44 struct intel_crtc *crtc); 45 bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, 46 const struct intel_cx0pll_state *b); 47 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 48 const struct intel_crtc_state *crtc_state); 49 void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, 50 u8 lane_mask, u8 state); 51 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); 52 void intel_cx0_setup_powerdown(struct intel_encoder *encoder); 53 bool intel_cx0_is_hdmi_frl(u32 clock); 54 u8 intel_cx0_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr); 55 void intel_cx0_rmw(struct intel_encoder *encoder, 56 u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed); 57 void intel_cx0_write(struct intel_encoder *encoder, 58 u8 lane_mask, u16 addr, u8 data, bool committed); 59 int intel_cx0_wait_for_ack(struct intel_encoder *encoder, 60 int command, int lane, u32 *val); 61 void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane); 62 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); 63 void intel_cx0_pll_power_save_wa(struct intel_display *display); 64 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, 65 const struct intel_crtc_state *crtc_state); 66 void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, 67 const struct intel_crtc_state *crtc_state); 68 void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder); 69 70 #endif /* __INTEL_CX0_PHY_H__ */ 71