xref: /linux/drivers/gpu/drm/i915/display/intel_cx0_phy.h (revision 6e7fd890f1d6ac83805409e9c346240de2705584)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef __INTEL_CX0_PHY_H__
7 #define __INTEL_CX0_PHY_H__
8 
9 #include <linux/types.h>
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 
13 enum icl_port_dpll_id;
14 struct drm_i915_private;
15 struct intel_atomic_state;
16 struct intel_c10pll_state;
17 struct intel_c20pll_state;
18 struct intel_cx0pll_state;
19 struct intel_crtc;
20 struct intel_crtc_state;
21 struct intel_encoder;
22 struct intel_hdmi;
23 
24 bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
25 void intel_mtl_pll_enable(struct intel_encoder *encoder,
26 			  const struct intel_crtc_state *crtc_state);
27 void intel_mtl_pll_disable(struct intel_encoder *encoder);
28 enum icl_port_dpll_id
29 intel_mtl_port_pll_type(struct intel_encoder *encoder,
30 			const struct intel_crtc_state *crtc_state);
31 
32 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
33 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
34 				   struct intel_cx0pll_state *pll_state);
35 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
36 				 const struct intel_cx0pll_state *pll_state);
37 
38 void intel_cx0pll_dump_hw_state(struct drm_i915_private *dev_priv,
39 				const struct intel_cx0pll_state *hw_state);
40 void intel_cx0pll_state_verify(struct intel_atomic_state *state,
41 			       struct intel_crtc *crtc);
42 bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
43 				   const struct intel_cx0pll_state *b);
44 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
45 				     const struct intel_crtc_state *crtc_state);
46 int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
47 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
48 
49 #endif /* __INTEL_CX0_PHY_H__ */
50