1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_CX0_PHY_H__ 7 #define __INTEL_CX0_PHY_H__ 8 9 #include <linux/types.h> 10 11 #define MB_WRITE_COMMITTED true 12 #define MB_WRITE_UNCOMMITTED false 13 14 struct drm_printer; 15 enum icl_port_dpll_id; 16 struct intel_atomic_state; 17 struct intel_c10pll_state; 18 struct intel_c20pll_state; 19 struct intel_crtc; 20 struct intel_crtc_state; 21 struct intel_cx0pll_state; 22 struct intel_display; 23 struct intel_dpll; 24 struct intel_dpll_hw_state; 25 struct intel_encoder; 26 struct intel_hdmi; 27 28 void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder, 29 int lane); 30 bool intel_encoder_is_c10phy(struct intel_encoder *encoder); 31 int intel_readout_lane_count(struct intel_encoder *encoder, int lane0, int lane1); 32 void intel_mtl_pll_enable(struct intel_encoder *encoder, 33 struct intel_dpll *pll, 34 const struct intel_dpll_hw_state *dpll_hw_state); 35 void intel_mtl_pll_disable(struct intel_encoder *encoder); 36 enum icl_port_dpll_id 37 intel_mtl_port_pll_type(struct intel_encoder *encoder, 38 const struct intel_crtc_state *crtc_state); 39 void intel_mtl_pll_enable_clock(struct intel_encoder *encoder, 40 const struct intel_crtc_state *crtc_state); 41 void intel_mtl_pll_disable_clock(struct intel_encoder *encoder); 42 void intel_mtl_pll_disable_clock(struct intel_encoder *encoder); 43 void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, 44 int port_clock); 45 void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder); 46 47 int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state, 48 struct intel_encoder *encoder, 49 struct intel_dpll_hw_state *hw_state); 50 bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, 51 struct intel_cx0pll_state *pll_state); 52 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, 53 const struct intel_cx0pll_state *pll_state); 54 55 void intel_cx0pll_dump_hw_state(struct drm_printer *p, 56 const struct intel_cx0pll_state *hw_state); 57 bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, 58 const struct intel_cx0pll_state *b); 59 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 60 const struct intel_crtc_state *crtc_state); 61 void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, 62 u8 lane_mask, u8 state); 63 void intel_cx0_setup_powerdown(struct intel_encoder *encoder); 64 bool intel_cx0_is_hdmi_frl(u32 clock); 65 u8 intel_cx0_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr); 66 void intel_cx0_rmw(struct intel_encoder *encoder, 67 u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed); 68 void intel_cx0_write(struct intel_encoder *encoder, 69 u8 lane_mask, u16 addr, u8 data, bool committed); 70 int intel_cx0_wait_for_ack(struct intel_encoder *encoder, 71 int command, int lane, u32 *val); 72 void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane); 73 74 void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state); 75 bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display, 76 struct intel_dpll *pll, 77 struct intel_dpll_hw_state *hw_state); 78 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); 79 80 void intel_cx0pll_verify_plls(struct intel_display *display); 81 void intel_cx0_pll_power_save_wa(struct intel_display *display); 82 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, 83 const struct intel_crtc_state *crtc_state); 84 void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, 85 const struct intel_crtc_state *crtc_state); 86 void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder); 87 88 #endif /* __INTEL_CX0_PHY_H__ */ 89