1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <drm/drm_edid.h> 7 #include <drm/drm_eld.h> 8 #include <drm/drm_print.h> 9 10 #include "intel_crtc_state_dump.h" 11 #include "intel_display_core.h" 12 #include "intel_display_types.h" 13 #include "intel_hdmi.h" 14 #include "intel_vblank.h" 15 #include "intel_vdsc.h" 16 #include "intel_vrr.h" 17 18 static void intel_dump_crtc_timings(struct drm_printer *p, 19 const struct drm_display_mode *mode) 20 { 21 drm_printf(p, "crtc timings: clock=%d, " 22 "hd=%d hb=%d-%d hs=%d-%d ht=%d, " 23 "vd=%d vb=%d-%d vs=%d-%d vt=%d, " 24 "flags=0x%x\n", 25 mode->crtc_clock, 26 mode->crtc_hdisplay, mode->crtc_hblank_start, mode->crtc_hblank_end, 27 mode->crtc_hsync_start, mode->crtc_hsync_end, mode->crtc_htotal, 28 mode->crtc_vdisplay, mode->crtc_vblank_start, mode->crtc_vblank_end, 29 mode->crtc_vsync_start, mode->crtc_vsync_end, mode->crtc_vtotal, 30 mode->flags); 31 } 32 33 static void 34 intel_dump_m_n_config(struct drm_printer *p, 35 const struct intel_crtc_state *pipe_config, 36 const char *id, unsigned int lane_count, 37 const struct intel_link_m_n *m_n) 38 { 39 drm_printf(p, "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 40 id, lane_count, 41 m_n->data_m, m_n->data_n, 42 m_n->link_m, m_n->link_n, m_n->tu); 43 } 44 45 static void 46 intel_dump_infoframe(struct intel_display *display, 47 const union hdmi_infoframe *frame) 48 { 49 if (!drm_debug_enabled(DRM_UT_KMS)) 50 return; 51 52 hdmi_infoframe_log(KERN_DEBUG, display->drm->dev, frame); 53 } 54 55 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 56 57 static const char * const output_type_str[] = { 58 OUTPUT_TYPE(UNUSED), 59 OUTPUT_TYPE(ANALOG), 60 OUTPUT_TYPE(DVO), 61 OUTPUT_TYPE(SDVO), 62 OUTPUT_TYPE(LVDS), 63 OUTPUT_TYPE(TVOUT), 64 OUTPUT_TYPE(HDMI), 65 OUTPUT_TYPE(DP), 66 OUTPUT_TYPE(EDP), 67 OUTPUT_TYPE(DSI), 68 OUTPUT_TYPE(DDI), 69 OUTPUT_TYPE(DP_MST), 70 }; 71 72 #undef OUTPUT_TYPE 73 74 static void snprintf_output_types(char *buf, size_t len, 75 unsigned int output_types) 76 { 77 char *str = buf; 78 int i; 79 80 str[0] = '\0'; 81 82 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 83 int r; 84 85 if ((output_types & BIT(i)) == 0) 86 continue; 87 88 r = snprintf(str, len, "%s%s", 89 str != buf ? "," : "", output_type_str[i]); 90 if (r >= len) 91 break; 92 str += r; 93 len -= r; 94 95 output_types &= ~BIT(i); 96 } 97 98 WARN_ON_ONCE(output_types != 0); 99 } 100 101 static const char * const output_format_str[] = { 102 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 103 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 104 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 105 }; 106 107 const char *intel_output_format_name(enum intel_output_format format) 108 { 109 if (format >= ARRAY_SIZE(output_format_str)) 110 return "invalid"; 111 return output_format_str[format]; 112 } 113 114 static void intel_dump_plane_state(struct drm_printer *p, 115 const struct intel_plane_state *plane_state) 116 { 117 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 118 const struct drm_framebuffer *fb = plane_state->hw.fb; 119 120 if (!fb) { 121 drm_printf(p, "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 122 plane->base.base.id, plane->base.name, 123 str_yes_no(plane_state->uapi.visible)); 124 return; 125 } 126 127 drm_printf(p, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 128 plane->base.base.id, plane->base.name, 129 fb->base.id, fb->width, fb->height, &fb->format->format, 130 fb->modifier, str_yes_no(plane_state->uapi.visible)); 131 drm_printf(p, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n", 132 plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter); 133 if (plane_state->uapi.visible) 134 drm_printf(p, "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 135 DRM_RECT_FP_ARG(&plane_state->uapi.src), 136 DRM_RECT_ARG(&plane_state->uapi.dst)); 137 } 138 139 static void 140 ilk_dump_csc(struct intel_display *display, 141 struct drm_printer *p, 142 const char *name, 143 const struct intel_csc_matrix *csc) 144 { 145 int i; 146 147 drm_printf(p, "%s: pre offsets: 0x%04x 0x%04x 0x%04x\n", name, 148 csc->preoff[0], csc->preoff[1], csc->preoff[2]); 149 150 for (i = 0; i < 3; i++) 151 drm_printf(p, "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name, 152 csc->coeff[3 * i + 0], 153 csc->coeff[3 * i + 1], 154 csc->coeff[3 * i + 2]); 155 156 if (DISPLAY_VER(display) < 7) 157 return; 158 159 drm_printf(p, "%s: post offsets: 0x%04x 0x%04x 0x%04x\n", name, 160 csc->postoff[0], csc->postoff[1], csc->postoff[2]); 161 } 162 163 static void 164 vlv_dump_csc(struct drm_printer *p, const char *name, 165 const struct intel_csc_matrix *csc) 166 { 167 int i; 168 169 for (i = 0; i < 3; i++) 170 drm_printf(p, "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name, 171 csc->coeff[3 * i + 0], 172 csc->coeff[3 * i + 1], 173 csc->coeff[3 * i + 2]); 174 } 175 176 void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, 177 struct intel_atomic_state *state, 178 const char *context) 179 { 180 struct intel_display *display = to_intel_display(pipe_config); 181 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 182 const struct intel_plane_state *plane_state; 183 struct intel_plane *plane; 184 struct drm_printer p; 185 char buf[64]; 186 int i; 187 188 if (!drm_debug_enabled(DRM_UT_KMS)) 189 return; 190 191 p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL); 192 193 drm_printf(&p, "[CRTC:%d:%s] enable: %s [%s]\n", 194 crtc->base.base.id, crtc->base.name, 195 str_yes_no(pipe_config->hw.enable), context); 196 197 if (!pipe_config->hw.enable) 198 goto dump_planes; 199 200 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 201 drm_printf(&p, "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n", 202 str_yes_no(pipe_config->hw.active), 203 buf, pipe_config->output_types, 204 intel_output_format_name(pipe_config->output_format), 205 intel_output_format_name(pipe_config->sink_format)); 206 207 drm_printf(&p, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 208 transcoder_name(pipe_config->cpu_transcoder), 209 pipe_config->pipe_bpp, pipe_config->dither); 210 211 drm_printf(&p, "MST master transcoder: %s\n", 212 transcoder_name(pipe_config->mst_master_transcoder)); 213 214 drm_printf(&p, "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 215 transcoder_name(pipe_config->master_transcoder), 216 pipe_config->sync_mode_slaves_mask); 217 218 drm_printf(&p, "joiner: %s, pipes: 0x%x\n", 219 intel_crtc_is_joiner_secondary(pipe_config) ? "secondary" : 220 intel_crtc_is_joiner_primary(pipe_config) ? "primary" : "no", 221 pipe_config->joiner_pipes); 222 223 drm_printf(&p, "splitter: %s, link count %d, overlap %d\n", 224 str_enabled_disabled(pipe_config->splitter.enable), 225 pipe_config->splitter.link_count, 226 pipe_config->splitter.pixel_overlap); 227 228 if (pipe_config->has_pch_encoder) 229 intel_dump_m_n_config(&p, pipe_config, "fdi", 230 pipe_config->fdi_lanes, 231 &pipe_config->fdi_m_n); 232 233 if (intel_crtc_has_dp_encoder(pipe_config)) { 234 intel_dump_m_n_config(&p, pipe_config, "dp m_n", 235 pipe_config->lane_count, 236 &pipe_config->dp_m_n); 237 intel_dump_m_n_config(&p, pipe_config, "dp m2_n2", 238 pipe_config->lane_count, 239 &pipe_config->dp_m2_n2); 240 drm_printf(&p, "fec: %s, enhanced framing: %s\n", 241 str_enabled_disabled(pipe_config->fec_enable), 242 str_enabled_disabled(pipe_config->enhanced_framing)); 243 244 drm_printf(&p, "sdp split: %s\n", 245 str_enabled_disabled(pipe_config->sdp_split_enable)); 246 247 drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n", 248 str_enabled_disabled(pipe_config->has_psr && 249 !pipe_config->has_panel_replay), 250 str_enabled_disabled(pipe_config->has_sel_update), 251 str_enabled_disabled(pipe_config->has_panel_replay), 252 str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); 253 drm_printf(&p, "minimum HBlank: %d\n", pipe_config->min_hblank); 254 } 255 256 drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 257 pipe_config->has_audio, pipe_config->has_infoframe, 258 pipe_config->infoframes.enable); 259 260 if (pipe_config->infoframes.enable & 261 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 262 drm_printf(&p, "GCP: 0x%x\n", pipe_config->infoframes.gcp); 263 if (pipe_config->infoframes.enable & 264 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 265 intel_dump_infoframe(display, &pipe_config->infoframes.avi); 266 if (pipe_config->infoframes.enable & 267 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 268 intel_dump_infoframe(display, &pipe_config->infoframes.spd); 269 if (pipe_config->infoframes.enable & 270 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 271 intel_dump_infoframe(display, &pipe_config->infoframes.hdmi); 272 if (pipe_config->infoframes.enable & 273 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 274 intel_dump_infoframe(display, &pipe_config->infoframes.drm); 275 if (pipe_config->infoframes.enable & 276 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 277 intel_dump_infoframe(display, &pipe_config->infoframes.drm); 278 if (pipe_config->infoframes.enable & 279 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 280 drm_dp_vsc_sdp_log(&p, &pipe_config->infoframes.vsc); 281 if (pipe_config->infoframes.enable & 282 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) 283 drm_dp_as_sdp_log(&p, &pipe_config->infoframes.as_sdp); 284 285 if (pipe_config->has_audio) 286 drm_print_hex_dump(&p, "ELD: ", pipe_config->eld, 287 drm_eld_size(pipe_config->eld)); 288 289 drm_printf(&p, "scanline offset: %d\n", 290 intel_crtc_scanline_offset(pipe_config)); 291 292 drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d\n", 293 pipe_config->hw.adjusted_mode.crtc_vblank_start - 294 pipe_config->hw.adjusted_mode.crtc_vdisplay, 295 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 296 297 drm_printf(&p, "vrr: %s, fixed rr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n", 298 str_yes_no(pipe_config->vrr.enable), 299 str_yes_no(intel_vrr_is_fixed_rr(pipe_config)), 300 pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.flipline, 301 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 302 pipe_config->vrr.vsync_start, pipe_config->vrr.vsync_end); 303 304 drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n", 305 intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config), 306 intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config)); 307 308 drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n", 309 DRM_MODE_ARG(&pipe_config->hw.mode)); 310 drm_printf(&p, "adjusted mode: " DRM_MODE_FMT "\n", 311 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 312 intel_dump_crtc_timings(&p, &pipe_config->hw.adjusted_mode); 313 drm_printf(&p, "pipe mode: " DRM_MODE_FMT "\n", 314 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 315 intel_dump_crtc_timings(&p, &pipe_config->hw.pipe_mode); 316 drm_printf(&p, "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 317 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 318 pipe_config->pixel_rate); 319 320 drm_printf(&p, "linetime: %d, ips linetime: %d\n", 321 pipe_config->linetime, pipe_config->ips_linetime); 322 323 if (DISPLAY_VER(display) >= 9) 324 drm_printf(&p, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n", 325 crtc->num_scalers, 326 pipe_config->scaler_state.scaler_users, 327 pipe_config->scaler_state.scaler_id, 328 pipe_config->hw.scaling_filter); 329 330 if (HAS_GMCH(display)) 331 drm_printf(&p, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 332 pipe_config->gmch_pfit.control, 333 pipe_config->gmch_pfit.pgm_ratios, 334 pipe_config->gmch_pfit.lvds_border_bits); 335 else 336 drm_printf(&p, "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 337 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 338 str_enabled_disabled(pipe_config->pch_pfit.enabled), 339 str_yes_no(pipe_config->pch_pfit.force_thru)); 340 341 drm_printf(&p, "ips: %i, double wide: %i, drrs: %i\n", 342 pipe_config->ips_enabled, pipe_config->double_wide, 343 pipe_config->has_drrs); 344 345 intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state); 346 347 if (display->platform.cherryview) 348 drm_printf(&p, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 349 pipe_config->cgm_mode, pipe_config->gamma_mode, 350 pipe_config->gamma_enable, pipe_config->csc_enable); 351 else 352 drm_printf(&p, "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 353 pipe_config->csc_mode, pipe_config->gamma_mode, 354 pipe_config->gamma_enable, pipe_config->csc_enable); 355 356 drm_printf(&p, "pre csc lut: %s%d entries, post csc lut: %d entries\n", 357 pipe_config->pre_csc_lut && pipe_config->pre_csc_lut == 358 display->color.glk_linear_degamma_lut ? "(linear) " : "", 359 pipe_config->pre_csc_lut ? 360 drm_color_lut_size(pipe_config->pre_csc_lut) : 0, 361 pipe_config->post_csc_lut ? 362 drm_color_lut_size(pipe_config->post_csc_lut) : 0); 363 364 if (DISPLAY_VER(display) >= 11) 365 ilk_dump_csc(display, &p, "output csc", &pipe_config->output_csc); 366 367 if (!HAS_GMCH(display)) 368 ilk_dump_csc(display, &p, "pipe csc", &pipe_config->csc); 369 else if (display->platform.cherryview) 370 vlv_dump_csc(&p, "cgm csc", &pipe_config->csc); 371 else if (display->platform.valleyview) 372 vlv_dump_csc(&p, "wgc csc", &pipe_config->csc); 373 374 intel_vdsc_state_dump(&p, 0, pipe_config); 375 376 dump_planes: 377 if (!state) 378 return; 379 380 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 381 if (plane->pipe == crtc->pipe) 382 intel_dump_plane_state(&p, plane_state); 383 } 384 } 385