1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <drm/drm_edid.h> 7 #include <drm/drm_eld.h> 8 9 #include "i915_drv.h" 10 #include "intel_crtc_state_dump.h" 11 #include "intel_display_types.h" 12 #include "intel_hdmi.h" 13 #include "intel_vdsc.h" 14 #include "intel_vrr.h" 15 16 static void intel_dump_crtc_timings(struct drm_printer *p, 17 const struct drm_display_mode *mode) 18 { 19 drm_printf(p, "crtc timings: clock=%d, " 20 "hd=%d hb=%d-%d hs=%d-%d ht=%d, " 21 "vd=%d vb=%d-%d vs=%d-%d vt=%d, " 22 "flags=0x%x\n", 23 mode->crtc_clock, 24 mode->crtc_hdisplay, mode->crtc_hblank_start, mode->crtc_hblank_end, 25 mode->crtc_hsync_start, mode->crtc_hsync_end, mode->crtc_htotal, 26 mode->crtc_vdisplay, mode->crtc_vblank_start, mode->crtc_vblank_end, 27 mode->crtc_vsync_start, mode->crtc_vsync_end, mode->crtc_vtotal, 28 mode->flags); 29 } 30 31 static void 32 intel_dump_m_n_config(struct drm_printer *p, 33 const struct intel_crtc_state *pipe_config, 34 const char *id, unsigned int lane_count, 35 const struct intel_link_m_n *m_n) 36 { 37 drm_printf(p, "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 38 id, lane_count, 39 m_n->data_m, m_n->data_n, 40 m_n->link_m, m_n->link_n, m_n->tu); 41 } 42 43 static void 44 intel_dump_infoframe(struct drm_i915_private *i915, 45 const union hdmi_infoframe *frame) 46 { 47 if (!drm_debug_enabled(DRM_UT_KMS)) 48 return; 49 50 hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame); 51 } 52 53 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 54 55 static const char * const output_type_str[] = { 56 OUTPUT_TYPE(UNUSED), 57 OUTPUT_TYPE(ANALOG), 58 OUTPUT_TYPE(DVO), 59 OUTPUT_TYPE(SDVO), 60 OUTPUT_TYPE(LVDS), 61 OUTPUT_TYPE(TVOUT), 62 OUTPUT_TYPE(HDMI), 63 OUTPUT_TYPE(DP), 64 OUTPUT_TYPE(EDP), 65 OUTPUT_TYPE(DSI), 66 OUTPUT_TYPE(DDI), 67 OUTPUT_TYPE(DP_MST), 68 }; 69 70 #undef OUTPUT_TYPE 71 72 static void snprintf_output_types(char *buf, size_t len, 73 unsigned int output_types) 74 { 75 char *str = buf; 76 int i; 77 78 str[0] = '\0'; 79 80 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 81 int r; 82 83 if ((output_types & BIT(i)) == 0) 84 continue; 85 86 r = snprintf(str, len, "%s%s", 87 str != buf ? "," : "", output_type_str[i]); 88 if (r >= len) 89 break; 90 str += r; 91 len -= r; 92 93 output_types &= ~BIT(i); 94 } 95 96 WARN_ON_ONCE(output_types != 0); 97 } 98 99 static const char * const output_format_str[] = { 100 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 101 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 102 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 103 }; 104 105 const char *intel_output_format_name(enum intel_output_format format) 106 { 107 if (format >= ARRAY_SIZE(output_format_str)) 108 return "invalid"; 109 return output_format_str[format]; 110 } 111 112 static void intel_dump_plane_state(struct drm_printer *p, 113 const struct intel_plane_state *plane_state) 114 { 115 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 116 const struct drm_framebuffer *fb = plane_state->hw.fb; 117 118 if (!fb) { 119 drm_printf(p, "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 120 plane->base.base.id, plane->base.name, 121 str_yes_no(plane_state->uapi.visible)); 122 return; 123 } 124 125 drm_printf(p, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 126 plane->base.base.id, plane->base.name, 127 fb->base.id, fb->width, fb->height, &fb->format->format, 128 fb->modifier, str_yes_no(plane_state->uapi.visible)); 129 drm_printf(p, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n", 130 plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter); 131 if (plane_state->uapi.visible) 132 drm_printf(p, "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 133 DRM_RECT_FP_ARG(&plane_state->uapi.src), 134 DRM_RECT_ARG(&plane_state->uapi.dst)); 135 } 136 137 static void 138 ilk_dump_csc(struct drm_i915_private *i915, 139 struct drm_printer *p, 140 const char *name, 141 const struct intel_csc_matrix *csc) 142 { 143 int i; 144 145 drm_printf(p, "%s: pre offsets: 0x%04x 0x%04x 0x%04x\n", name, 146 csc->preoff[0], csc->preoff[1], csc->preoff[2]); 147 148 for (i = 0; i < 3; i++) 149 drm_printf(p, "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name, 150 csc->coeff[3 * i + 0], 151 csc->coeff[3 * i + 1], 152 csc->coeff[3 * i + 2]); 153 154 if (DISPLAY_VER(i915) < 7) 155 return; 156 157 drm_printf(p, "%s: post offsets: 0x%04x 0x%04x 0x%04x\n", name, 158 csc->postoff[0], csc->postoff[1], csc->postoff[2]); 159 } 160 161 static void 162 vlv_dump_csc(struct drm_printer *p, const char *name, 163 const struct intel_csc_matrix *csc) 164 { 165 int i; 166 167 for (i = 0; i < 3; i++) 168 drm_printf(p, "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name, 169 csc->coeff[3 * i + 0], 170 csc->coeff[3 * i + 1], 171 csc->coeff[3 * i + 2]); 172 } 173 174 void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, 175 struct intel_atomic_state *state, 176 const char *context) 177 { 178 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 179 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 180 const struct intel_plane_state *plane_state; 181 struct intel_plane *plane; 182 struct drm_printer p; 183 char buf[64]; 184 int i; 185 186 if (!drm_debug_enabled(DRM_UT_KMS)) 187 return; 188 189 p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL); 190 191 drm_printf(&p, "[CRTC:%d:%s] enable: %s [%s]\n", 192 crtc->base.base.id, crtc->base.name, 193 str_yes_no(pipe_config->hw.enable), context); 194 195 if (!pipe_config->hw.enable) 196 goto dump_planes; 197 198 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 199 drm_printf(&p, "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n", 200 str_yes_no(pipe_config->hw.active), 201 buf, pipe_config->output_types, 202 intel_output_format_name(pipe_config->output_format), 203 intel_output_format_name(pipe_config->sink_format)); 204 205 drm_printf(&p, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 206 transcoder_name(pipe_config->cpu_transcoder), 207 pipe_config->pipe_bpp, pipe_config->dither); 208 209 drm_printf(&p, "MST master transcoder: %s\n", 210 transcoder_name(pipe_config->mst_master_transcoder)); 211 212 drm_printf(&p, "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 213 transcoder_name(pipe_config->master_transcoder), 214 pipe_config->sync_mode_slaves_mask); 215 216 drm_printf(&p, "joiner: %s, pipes: 0x%x\n", 217 intel_crtc_is_joiner_secondary(pipe_config) ? "secondary" : 218 intel_crtc_is_joiner_primary(pipe_config) ? "primary" : "no", 219 pipe_config->joiner_pipes); 220 221 drm_printf(&p, "splitter: %s, link count %d, overlap %d\n", 222 str_enabled_disabled(pipe_config->splitter.enable), 223 pipe_config->splitter.link_count, 224 pipe_config->splitter.pixel_overlap); 225 226 if (pipe_config->has_pch_encoder) 227 intel_dump_m_n_config(&p, pipe_config, "fdi", 228 pipe_config->fdi_lanes, 229 &pipe_config->fdi_m_n); 230 231 if (intel_crtc_has_dp_encoder(pipe_config)) { 232 intel_dump_m_n_config(&p, pipe_config, "dp m_n", 233 pipe_config->lane_count, 234 &pipe_config->dp_m_n); 235 intel_dump_m_n_config(&p, pipe_config, "dp m2_n2", 236 pipe_config->lane_count, 237 &pipe_config->dp_m2_n2); 238 drm_printf(&p, "fec: %s, enhanced framing: %s\n", 239 str_enabled_disabled(pipe_config->fec_enable), 240 str_enabled_disabled(pipe_config->enhanced_framing)); 241 242 drm_printf(&p, "sdp split: %s\n", 243 str_enabled_disabled(pipe_config->sdp_split_enable)); 244 245 drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n", 246 str_enabled_disabled(pipe_config->has_psr && 247 !pipe_config->has_panel_replay), 248 str_enabled_disabled(pipe_config->has_sel_update), 249 str_enabled_disabled(pipe_config->has_panel_replay), 250 str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); 251 } 252 253 drm_printf(&p, "framestart delay: %d, MSA timing delay: %d\n", 254 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 255 256 drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 257 pipe_config->has_audio, pipe_config->has_infoframe, 258 pipe_config->infoframes.enable); 259 260 if (pipe_config->infoframes.enable & 261 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 262 drm_printf(&p, "GCP: 0x%x\n", pipe_config->infoframes.gcp); 263 if (pipe_config->infoframes.enable & 264 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 265 intel_dump_infoframe(i915, &pipe_config->infoframes.avi); 266 if (pipe_config->infoframes.enable & 267 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 268 intel_dump_infoframe(i915, &pipe_config->infoframes.spd); 269 if (pipe_config->infoframes.enable & 270 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 271 intel_dump_infoframe(i915, &pipe_config->infoframes.hdmi); 272 if (pipe_config->infoframes.enable & 273 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 274 intel_dump_infoframe(i915, &pipe_config->infoframes.drm); 275 if (pipe_config->infoframes.enable & 276 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 277 intel_dump_infoframe(i915, &pipe_config->infoframes.drm); 278 if (pipe_config->infoframes.enable & 279 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 280 drm_dp_vsc_sdp_log(&p, &pipe_config->infoframes.vsc); 281 if (pipe_config->infoframes.enable & 282 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) 283 drm_dp_as_sdp_log(&p, &pipe_config->infoframes.as_sdp); 284 285 if (pipe_config->has_audio) 286 drm_print_hex_dump(&p, "ELD: ", pipe_config->eld, 287 drm_eld_size(pipe_config->eld)); 288 289 drm_printf(&p, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 290 str_yes_no(pipe_config->vrr.enable), 291 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 292 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 293 pipe_config->vrr.flipline, 294 intel_vrr_vmin_vblank_start(pipe_config), 295 intel_vrr_vmax_vblank_start(pipe_config)); 296 297 drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n", 298 DRM_MODE_ARG(&pipe_config->hw.mode)); 299 drm_printf(&p, "adjusted mode: " DRM_MODE_FMT "\n", 300 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 301 intel_dump_crtc_timings(&p, &pipe_config->hw.adjusted_mode); 302 drm_printf(&p, "pipe mode: " DRM_MODE_FMT "\n", 303 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 304 intel_dump_crtc_timings(&p, &pipe_config->hw.pipe_mode); 305 drm_printf(&p, "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 306 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 307 pipe_config->pixel_rate); 308 309 drm_printf(&p, "linetime: %d, ips linetime: %d\n", 310 pipe_config->linetime, pipe_config->ips_linetime); 311 312 if (DISPLAY_VER(i915) >= 9) 313 drm_printf(&p, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n", 314 crtc->num_scalers, 315 pipe_config->scaler_state.scaler_users, 316 pipe_config->scaler_state.scaler_id, 317 pipe_config->hw.scaling_filter); 318 319 if (HAS_GMCH(i915)) 320 drm_printf(&p, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 321 pipe_config->gmch_pfit.control, 322 pipe_config->gmch_pfit.pgm_ratios, 323 pipe_config->gmch_pfit.lvds_border_bits); 324 else 325 drm_printf(&p, "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 326 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 327 str_enabled_disabled(pipe_config->pch_pfit.enabled), 328 str_yes_no(pipe_config->pch_pfit.force_thru)); 329 330 drm_printf(&p, "ips: %i, double wide: %i, drrs: %i\n", 331 pipe_config->ips_enabled, pipe_config->double_wide, 332 pipe_config->has_drrs); 333 334 intel_dpll_dump_hw_state(i915, &p, &pipe_config->dpll_hw_state); 335 336 if (IS_CHERRYVIEW(i915)) 337 drm_printf(&p, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 338 pipe_config->cgm_mode, pipe_config->gamma_mode, 339 pipe_config->gamma_enable, pipe_config->csc_enable); 340 else 341 drm_printf(&p, "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 342 pipe_config->csc_mode, pipe_config->gamma_mode, 343 pipe_config->gamma_enable, pipe_config->csc_enable); 344 345 drm_printf(&p, "pre csc lut: %s%d entries, post csc lut: %d entries\n", 346 pipe_config->pre_csc_lut && pipe_config->pre_csc_lut == 347 i915->display.color.glk_linear_degamma_lut ? "(linear) " : "", 348 pipe_config->pre_csc_lut ? 349 drm_color_lut_size(pipe_config->pre_csc_lut) : 0, 350 pipe_config->post_csc_lut ? 351 drm_color_lut_size(pipe_config->post_csc_lut) : 0); 352 353 if (DISPLAY_VER(i915) >= 11) 354 ilk_dump_csc(i915, &p, "output csc", &pipe_config->output_csc); 355 356 if (!HAS_GMCH(i915)) 357 ilk_dump_csc(i915, &p, "pipe csc", &pipe_config->csc); 358 else if (IS_CHERRYVIEW(i915)) 359 vlv_dump_csc(&p, "cgm csc", &pipe_config->csc); 360 else if (IS_VALLEYVIEW(i915)) 361 vlv_dump_csc(&p, "wgc csc", &pipe_config->csc); 362 363 intel_vdsc_state_dump(&p, 0, pipe_config); 364 365 dump_planes: 366 if (!state) 367 return; 368 369 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 370 if (plane->pipe == crtc->pipe) 371 intel_dump_plane_state(&p, plane_state); 372 } 373 } 374