1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include <drm/drm_edid.h> 7 #include <drm/drm_eld.h> 8 9 #include "i915_drv.h" 10 #include "intel_crtc_state_dump.h" 11 #include "intel_display_types.h" 12 #include "intel_hdmi.h" 13 #include "intel_vrr.h" 14 15 static void intel_dump_crtc_timings(struct drm_printer *p, 16 const struct drm_display_mode *mode) 17 { 18 drm_printf(p, "crtc timings: clock=%d, " 19 "hd=%d hb=%d-%d hs=%d-%d ht=%d, " 20 "vd=%d vb=%d-%d vs=%d-%d vt=%d, " 21 "flags=0x%x\n", 22 mode->crtc_clock, 23 mode->crtc_hdisplay, mode->crtc_hblank_start, mode->crtc_hblank_end, 24 mode->crtc_hsync_start, mode->crtc_hsync_end, mode->crtc_htotal, 25 mode->crtc_vdisplay, mode->crtc_vblank_start, mode->crtc_vblank_end, 26 mode->crtc_vsync_start, mode->crtc_vsync_end, mode->crtc_vtotal, 27 mode->flags); 28 } 29 30 static void 31 intel_dump_m_n_config(struct drm_printer *p, 32 const struct intel_crtc_state *pipe_config, 33 const char *id, unsigned int lane_count, 34 const struct intel_link_m_n *m_n) 35 { 36 drm_printf(p, "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n", 37 id, lane_count, 38 m_n->data_m, m_n->data_n, 39 m_n->link_m, m_n->link_n, m_n->tu); 40 } 41 42 static void 43 intel_dump_infoframe(struct drm_i915_private *i915, 44 const union hdmi_infoframe *frame) 45 { 46 if (!drm_debug_enabled(DRM_UT_KMS)) 47 return; 48 49 hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame); 50 } 51 52 static void 53 intel_dump_buffer(const char *prefix, const u8 *buf, size_t len) 54 { 55 if (!drm_debug_enabled(DRM_UT_KMS)) 56 return; 57 58 print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_NONE, 59 16, 0, buf, len, false); 60 } 61 62 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 63 64 static const char * const output_type_str[] = { 65 OUTPUT_TYPE(UNUSED), 66 OUTPUT_TYPE(ANALOG), 67 OUTPUT_TYPE(DVO), 68 OUTPUT_TYPE(SDVO), 69 OUTPUT_TYPE(LVDS), 70 OUTPUT_TYPE(TVOUT), 71 OUTPUT_TYPE(HDMI), 72 OUTPUT_TYPE(DP), 73 OUTPUT_TYPE(EDP), 74 OUTPUT_TYPE(DSI), 75 OUTPUT_TYPE(DDI), 76 OUTPUT_TYPE(DP_MST), 77 }; 78 79 #undef OUTPUT_TYPE 80 81 static void snprintf_output_types(char *buf, size_t len, 82 unsigned int output_types) 83 { 84 char *str = buf; 85 int i; 86 87 str[0] = '\0'; 88 89 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) { 90 int r; 91 92 if ((output_types & BIT(i)) == 0) 93 continue; 94 95 r = snprintf(str, len, "%s%s", 96 str != buf ? "," : "", output_type_str[i]); 97 if (r >= len) 98 break; 99 str += r; 100 len -= r; 101 102 output_types &= ~BIT(i); 103 } 104 105 WARN_ON_ONCE(output_types != 0); 106 } 107 108 static const char * const output_format_str[] = { 109 [INTEL_OUTPUT_FORMAT_RGB] = "RGB", 110 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", 111 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", 112 }; 113 114 const char *intel_output_format_name(enum intel_output_format format) 115 { 116 if (format >= ARRAY_SIZE(output_format_str)) 117 return "invalid"; 118 return output_format_str[format]; 119 } 120 121 static void intel_dump_plane_state(struct drm_printer *p, 122 const struct intel_plane_state *plane_state) 123 { 124 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 125 const struct drm_framebuffer *fb = plane_state->hw.fb; 126 127 if (!fb) { 128 drm_printf(p, "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", 129 plane->base.base.id, plane->base.name, 130 str_yes_no(plane_state->uapi.visible)); 131 return; 132 } 133 134 drm_printf(p, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n", 135 plane->base.base.id, plane->base.name, 136 fb->base.id, fb->width, fb->height, &fb->format->format, 137 fb->modifier, str_yes_no(plane_state->uapi.visible)); 138 drm_printf(p, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n", 139 plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter); 140 if (plane_state->uapi.visible) 141 drm_printf(p, "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", 142 DRM_RECT_FP_ARG(&plane_state->uapi.src), 143 DRM_RECT_ARG(&plane_state->uapi.dst)); 144 } 145 146 static void 147 ilk_dump_csc(struct drm_i915_private *i915, 148 struct drm_printer *p, 149 const char *name, 150 const struct intel_csc_matrix *csc) 151 { 152 int i; 153 154 drm_printf(p, "%s: pre offsets: 0x%04x 0x%04x 0x%04x\n", name, 155 csc->preoff[0], csc->preoff[1], csc->preoff[2]); 156 157 for (i = 0; i < 3; i++) 158 drm_printf(p, "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name, 159 csc->coeff[3 * i + 0], 160 csc->coeff[3 * i + 1], 161 csc->coeff[3 * i + 2]); 162 163 if (DISPLAY_VER(i915) < 7) 164 return; 165 166 drm_printf(p, "%s: post offsets: 0x%04x 0x%04x 0x%04x\n", name, 167 csc->postoff[0], csc->postoff[1], csc->postoff[2]); 168 } 169 170 static void 171 vlv_dump_csc(struct drm_printer *p, const char *name, 172 const struct intel_csc_matrix *csc) 173 { 174 int i; 175 176 for (i = 0; i < 3; i++) 177 drm_printf(p, "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name, 178 csc->coeff[3 * i + 0], 179 csc->coeff[3 * i + 1], 180 csc->coeff[3 * i + 2]); 181 } 182 183 void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, 184 struct intel_atomic_state *state, 185 const char *context) 186 { 187 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 188 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 189 const struct intel_plane_state *plane_state; 190 struct intel_plane *plane; 191 struct drm_printer p; 192 char buf[64]; 193 int i; 194 195 if (!drm_debug_enabled(DRM_UT_KMS)) 196 return; 197 198 p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL); 199 200 drm_printf(&p, "[CRTC:%d:%s] enable: %s [%s]\n", 201 crtc->base.base.id, crtc->base.name, 202 str_yes_no(pipe_config->hw.enable), context); 203 204 if (!pipe_config->hw.enable) 205 goto dump_planes; 206 207 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); 208 drm_printf(&p, "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n", 209 str_yes_no(pipe_config->hw.active), 210 buf, pipe_config->output_types, 211 intel_output_format_name(pipe_config->output_format), 212 intel_output_format_name(pipe_config->sink_format)); 213 214 drm_printf(&p, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", 215 transcoder_name(pipe_config->cpu_transcoder), 216 pipe_config->pipe_bpp, pipe_config->dither); 217 218 drm_printf(&p, "MST master transcoder: %s\n", 219 transcoder_name(pipe_config->mst_master_transcoder)); 220 221 drm_printf(&p, "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n", 222 transcoder_name(pipe_config->master_transcoder), 223 pipe_config->sync_mode_slaves_mask); 224 225 drm_printf(&p, "joiner: %s, pipes: 0x%x\n", 226 intel_crtc_is_joiner_secondary(pipe_config) ? "secondary" : 227 intel_crtc_is_joiner_primary(pipe_config) ? "primary" : "no", 228 pipe_config->joiner_pipes); 229 230 drm_printf(&p, "splitter: %s, link count %d, overlap %d\n", 231 str_enabled_disabled(pipe_config->splitter.enable), 232 pipe_config->splitter.link_count, 233 pipe_config->splitter.pixel_overlap); 234 235 if (pipe_config->has_pch_encoder) 236 intel_dump_m_n_config(&p, pipe_config, "fdi", 237 pipe_config->fdi_lanes, 238 &pipe_config->fdi_m_n); 239 240 if (intel_crtc_has_dp_encoder(pipe_config)) { 241 intel_dump_m_n_config(&p, pipe_config, "dp m_n", 242 pipe_config->lane_count, 243 &pipe_config->dp_m_n); 244 intel_dump_m_n_config(&p, pipe_config, "dp m2_n2", 245 pipe_config->lane_count, 246 &pipe_config->dp_m2_n2); 247 drm_printf(&p, "fec: %s, enhanced framing: %s\n", 248 str_enabled_disabled(pipe_config->fec_enable), 249 str_enabled_disabled(pipe_config->enhanced_framing)); 250 251 drm_printf(&p, "sdp split: %s\n", 252 str_enabled_disabled(pipe_config->sdp_split_enable)); 253 254 drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n", 255 str_enabled_disabled(pipe_config->has_psr && 256 !pipe_config->has_panel_replay), 257 str_enabled_disabled(pipe_config->has_sel_update), 258 str_enabled_disabled(pipe_config->has_panel_replay), 259 str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); 260 } 261 262 drm_printf(&p, "framestart delay: %d, MSA timing delay: %d\n", 263 pipe_config->framestart_delay, pipe_config->msa_timing_delay); 264 265 drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", 266 pipe_config->has_audio, pipe_config->has_infoframe, 267 pipe_config->infoframes.enable); 268 269 if (pipe_config->infoframes.enable & 270 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) 271 drm_printf(&p, "GCP: 0x%x\n", pipe_config->infoframes.gcp); 272 if (pipe_config->infoframes.enable & 273 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) 274 intel_dump_infoframe(i915, &pipe_config->infoframes.avi); 275 if (pipe_config->infoframes.enable & 276 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) 277 intel_dump_infoframe(i915, &pipe_config->infoframes.spd); 278 if (pipe_config->infoframes.enable & 279 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) 280 intel_dump_infoframe(i915, &pipe_config->infoframes.hdmi); 281 if (pipe_config->infoframes.enable & 282 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) 283 intel_dump_infoframe(i915, &pipe_config->infoframes.drm); 284 if (pipe_config->infoframes.enable & 285 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) 286 intel_dump_infoframe(i915, &pipe_config->infoframes.drm); 287 if (pipe_config->infoframes.enable & 288 intel_hdmi_infoframe_enable(DP_SDP_VSC)) 289 drm_dp_vsc_sdp_log(&p, &pipe_config->infoframes.vsc); 290 if (pipe_config->infoframes.enable & 291 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)) 292 drm_dp_as_sdp_log(&p, &pipe_config->infoframes.as_sdp); 293 294 if (pipe_config->has_audio) 295 intel_dump_buffer("ELD: ", pipe_config->eld, 296 drm_eld_size(pipe_config->eld)); 297 298 drm_printf(&p, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 299 str_yes_no(pipe_config->vrr.enable), 300 pipe_config->vrr.vmin, pipe_config->vrr.vmax, 301 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, 302 pipe_config->vrr.flipline, 303 intel_vrr_vmin_vblank_start(pipe_config), 304 intel_vrr_vmax_vblank_start(pipe_config)); 305 306 drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n", 307 DRM_MODE_ARG(&pipe_config->hw.mode)); 308 drm_printf(&p, "adjusted mode: " DRM_MODE_FMT "\n", 309 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode)); 310 intel_dump_crtc_timings(&p, &pipe_config->hw.adjusted_mode); 311 drm_printf(&p, "pipe mode: " DRM_MODE_FMT "\n", 312 DRM_MODE_ARG(&pipe_config->hw.pipe_mode)); 313 intel_dump_crtc_timings(&p, &pipe_config->hw.pipe_mode); 314 drm_printf(&p, "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n", 315 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), 316 pipe_config->pixel_rate); 317 318 drm_printf(&p, "linetime: %d, ips linetime: %d\n", 319 pipe_config->linetime, pipe_config->ips_linetime); 320 321 if (DISPLAY_VER(i915) >= 9) 322 drm_printf(&p, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n", 323 crtc->num_scalers, 324 pipe_config->scaler_state.scaler_users, 325 pipe_config->scaler_state.scaler_id, 326 pipe_config->hw.scaling_filter); 327 328 if (HAS_GMCH(i915)) 329 drm_printf(&p, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", 330 pipe_config->gmch_pfit.control, 331 pipe_config->gmch_pfit.pgm_ratios, 332 pipe_config->gmch_pfit.lvds_border_bits); 333 else 334 drm_printf(&p, "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n", 335 DRM_RECT_ARG(&pipe_config->pch_pfit.dst), 336 str_enabled_disabled(pipe_config->pch_pfit.enabled), 337 str_yes_no(pipe_config->pch_pfit.force_thru)); 338 339 drm_printf(&p, "ips: %i, double wide: %i, drrs: %i\n", 340 pipe_config->ips_enabled, pipe_config->double_wide, 341 pipe_config->has_drrs); 342 343 intel_dpll_dump_hw_state(i915, &p, &pipe_config->dpll_hw_state); 344 345 if (IS_CHERRYVIEW(i915)) 346 drm_printf(&p, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 347 pipe_config->cgm_mode, pipe_config->gamma_mode, 348 pipe_config->gamma_enable, pipe_config->csc_enable); 349 else 350 drm_printf(&p, "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", 351 pipe_config->csc_mode, pipe_config->gamma_mode, 352 pipe_config->gamma_enable, pipe_config->csc_enable); 353 354 drm_printf(&p, "pre csc lut: %s%d entries, post csc lut: %d entries\n", 355 pipe_config->pre_csc_lut && pipe_config->pre_csc_lut == 356 i915->display.color.glk_linear_degamma_lut ? "(linear) " : "", 357 pipe_config->pre_csc_lut ? 358 drm_color_lut_size(pipe_config->pre_csc_lut) : 0, 359 pipe_config->post_csc_lut ? 360 drm_color_lut_size(pipe_config->post_csc_lut) : 0); 361 362 if (DISPLAY_VER(i915) >= 11) 363 ilk_dump_csc(i915, &p, "output csc", &pipe_config->output_csc); 364 365 if (!HAS_GMCH(i915)) 366 ilk_dump_csc(i915, &p, "pipe csc", &pipe_config->csc); 367 else if (IS_CHERRYVIEW(i915)) 368 vlv_dump_csc(&p, "cgm csc", &pipe_config->csc); 369 else if (IS_VALLEYVIEW(i915)) 370 vlv_dump_csc(&p, "wgc csc", &pipe_config->csc); 371 372 dump_planes: 373 if (!state) 374 return; 375 376 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 377 if (plane->pipe == crtc->pipe) 378 intel_dump_plane_state(&p, plane_state); 379 } 380 } 381