1c458e4dbSVille Syrjälä /* SPDX-License-Identifier: MIT */ 2c458e4dbSVille Syrjälä /* 3c458e4dbSVille Syrjälä * Copyright © 2024 Intel Corporation 4c458e4dbSVille Syrjälä */ 5c458e4dbSVille Syrjälä 6c458e4dbSVille Syrjälä #ifndef __INTEL_CRT_REGS_H__ 7c458e4dbSVille Syrjälä #define __INTEL_CRT_REGS_H__ 8c458e4dbSVille Syrjälä 9c458e4dbSVille Syrjälä #include "intel_display_reg_defs.h" 10c458e4dbSVille Syrjälä 11c458e4dbSVille Syrjälä #define ADPA _MMIO(0x61100) 12c458e4dbSVille Syrjälä #define PCH_ADPA _MMIO(0xe1100) 13c458e4dbSVille Syrjälä #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 14c458e4dbSVille Syrjälä #define ADPA_DAC_ENABLE REG_BIT(31) 15c458e4dbSVille Syrjälä #define ADPA_PIPE_SEL_MASK REG_BIT(30) 16c458e4dbSVille Syrjälä #define ADPA_PIPE_SEL(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK, (pipe)) 17c458e4dbSVille Syrjälä #define ADPA_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29) 18c458e4dbSVille Syrjälä #define ADPA_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK_CPT, (pipe)) 19c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_MONITOR_MASK REG_GENMASK(25, 24) 20c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_MONITOR_NONE REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 0) 21c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_MONITOR_COLOR REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 3) 22c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_MONITOR_MONO REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 2) 23c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_ENABLE REG_BIT(23) 24c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_PERIOD_MASK REG_BIT(22) 25c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_PERIOD_64 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 0) 26c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_PERIOD_128 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 1) 27c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_WARMUP_MASK REG_BIT(21) 28c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_WARMUP_5MS REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 0) 29c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_WARMUP_10MS REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 1) 30c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_SAMPLE_MASK REG_BIT(20) 31c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_SAMPLE_2S REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 0) 32c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_SAMPLE_4S REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 1) 33c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_VOLTAGE_MASK REG_GENMASK(19, 18) 34c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_VOLTAGE_40 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 0) 35c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_VOLTAGE_50 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 1) 36c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_VOLTAGE_60 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 2) 37c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_VOLTAGE_70 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 3) 38c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_VOLREF_MASK REG_BIT(17) 39c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_VOLREF_325MV REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 0) 40c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_VOLREF_475MV REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 1) 41c458e4dbSVille Syrjälä #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER REG_BIT(16) 42c458e4dbSVille Syrjälä #define ADPA_USE_VGA_HVPOLARITY REG_BIT(15) 43c458e4dbSVille Syrjälä #define ADPA_HSYNC_CNTL_DISABLE REG_BIT(11) 44c458e4dbSVille Syrjälä #define ADPA_VSYNC_CNTL_DISABLE REG_BIT(10) 45c458e4dbSVille Syrjälä #define ADPA_VSYNC_ACTIVE_HIGH REG_BIT(4) 46c458e4dbSVille Syrjälä #define ADPA_HSYNC_ACTIVE_HIGH REG_BIT(3) 47c458e4dbSVille Syrjälä 48*4821e26aSJani Nikula #define _VGA_MSR_WRITE _MMIO(0x3c2) 49*4821e26aSJani Nikula 50c458e4dbSVille Syrjälä #endif /* __INTEL_CRT_REGS_H__ */ 51