1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 #include <video/vga.h> 37 38 #include "intel_connector.h" 39 #include "intel_crt.h" 40 #include "intel_crt_regs.h" 41 #include "intel_crtc.h" 42 #include "intel_ddi.h" 43 #include "intel_ddi_buf_trans.h" 44 #include "intel_de.h" 45 #include "intel_display_driver.h" 46 #include "intel_display_regs.h" 47 #include "intel_display_types.h" 48 #include "intel_fdi.h" 49 #include "intel_fdi_regs.h" 50 #include "intel_fifo_underrun.h" 51 #include "intel_gmbus.h" 52 #include "intel_hotplug.h" 53 #include "intel_hotplug_irq.h" 54 #include "intel_link_bw.h" 55 #include "intel_load_detect.h" 56 #include "intel_pch_display.h" 57 #include "intel_pch_refclk.h" 58 #include "intel_pfit.h" 59 #include "intel_vga.h" 60 61 /* Here's the desired hotplug mode */ 62 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_ENABLE | \ 63 ADPA_CRT_HOTPLUG_PERIOD_128 | \ 64 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 65 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 66 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 67 ADPA_CRT_HOTPLUG_VOLREF_325MV) 68 #define ADPA_HOTPLUG_MASK (ADPA_CRT_HOTPLUG_MONITOR_MASK | \ 69 ADPA_CRT_HOTPLUG_ENABLE | \ 70 ADPA_CRT_HOTPLUG_PERIOD_MASK | \ 71 ADPA_CRT_HOTPLUG_WARMUP_MASK | \ 72 ADPA_CRT_HOTPLUG_SAMPLE_MASK | \ 73 ADPA_CRT_HOTPLUG_VOLTAGE_MASK | \ 74 ADPA_CRT_HOTPLUG_VOLREF_MASK | \ 75 ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 76 77 struct intel_crt { 78 struct intel_encoder base; 79 bool force_hotplug_required; 80 i915_reg_t adpa_reg; 81 }; 82 83 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 84 { 85 return container_of(encoder, struct intel_crt, base); 86 } 87 88 static struct intel_crt *intel_attached_crt(struct intel_connector *connector) 89 { 90 return intel_encoder_to_crt(intel_attached_encoder(connector)); 91 } 92 93 bool intel_crt_port_enabled(struct intel_display *display, 94 i915_reg_t adpa_reg, enum pipe *pipe) 95 { 96 u32 val; 97 98 val = intel_de_read(display, adpa_reg); 99 100 /* asserts want to know the pipe even if the port is disabled */ 101 if (HAS_PCH_CPT(display)) 102 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val); 103 else 104 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val); 105 106 return val & ADPA_DAC_ENABLE; 107 } 108 109 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 110 enum pipe *pipe) 111 { 112 struct intel_display *display = to_intel_display(encoder); 113 struct intel_crt *crt = intel_encoder_to_crt(encoder); 114 struct ref_tracker *wakeref; 115 bool ret; 116 117 wakeref = intel_display_power_get_if_enabled(display, 118 encoder->power_domain); 119 if (!wakeref) 120 return false; 121 122 ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); 123 124 intel_display_power_put(display, encoder->power_domain, wakeref); 125 126 return ret; 127 } 128 129 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 130 { 131 struct intel_display *display = to_intel_display(encoder); 132 struct intel_crt *crt = intel_encoder_to_crt(encoder); 133 u32 tmp, flags = 0; 134 135 tmp = intel_de_read(display, crt->adpa_reg); 136 137 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 138 flags |= DRM_MODE_FLAG_PHSYNC; 139 else 140 flags |= DRM_MODE_FLAG_NHSYNC; 141 142 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 143 flags |= DRM_MODE_FLAG_PVSYNC; 144 else 145 flags |= DRM_MODE_FLAG_NVSYNC; 146 147 return flags; 148 } 149 150 static void intel_crt_get_config(struct intel_encoder *encoder, 151 struct intel_crtc_state *crtc_state) 152 { 153 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 154 155 crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 156 157 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; 158 } 159 160 static void hsw_crt_get_config(struct intel_encoder *encoder, 161 struct intel_crtc_state *crtc_state) 162 { 163 lpt_pch_get_config(crtc_state); 164 165 hsw_ddi_get_config(encoder, crtc_state); 166 167 crtc_state->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 168 DRM_MODE_FLAG_NHSYNC | 169 DRM_MODE_FLAG_PVSYNC | 170 DRM_MODE_FLAG_NVSYNC); 171 crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 172 } 173 174 /* Note: The caller is required to filter out dpms modes not supported by the 175 * platform. */ 176 static void intel_crt_set_dpms(struct intel_encoder *encoder, 177 const struct intel_crtc_state *crtc_state, 178 int mode) 179 { 180 struct intel_display *display = to_intel_display(encoder); 181 struct intel_crt *crt = intel_encoder_to_crt(encoder); 182 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 183 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 184 u32 adpa; 185 186 if (DISPLAY_VER(display) >= 5) 187 adpa = ADPA_HOTPLUG_BITS; 188 else 189 adpa = 0; 190 191 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 192 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 193 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 194 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 195 196 /* For CPT allow 3 pipe config, for others just use A or B */ 197 if (HAS_PCH_LPT(display)) 198 ; /* Those bits don't exist here */ 199 else if (HAS_PCH_CPT(display)) 200 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); 201 else 202 adpa |= ADPA_PIPE_SEL(crtc->pipe); 203 204 if (!HAS_PCH_SPLIT(display)) 205 intel_de_write(display, BCLRPAT(display, crtc->pipe), 0); 206 207 switch (mode) { 208 case DRM_MODE_DPMS_ON: 209 adpa |= ADPA_DAC_ENABLE; 210 break; 211 case DRM_MODE_DPMS_STANDBY: 212 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 213 break; 214 case DRM_MODE_DPMS_SUSPEND: 215 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 216 break; 217 case DRM_MODE_DPMS_OFF: 218 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 219 break; 220 } 221 222 intel_de_write(display, crt->adpa_reg, adpa); 223 } 224 225 static void intel_disable_crt(struct intel_atomic_state *state, 226 struct intel_encoder *encoder, 227 const struct intel_crtc_state *old_crtc_state, 228 const struct drm_connector_state *old_conn_state) 229 { 230 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 231 } 232 233 static void pch_disable_crt(struct intel_atomic_state *state, 234 struct intel_encoder *encoder, 235 const struct intel_crtc_state *old_crtc_state, 236 const struct drm_connector_state *old_conn_state) 237 { 238 } 239 240 static void pch_post_disable_crt(struct intel_atomic_state *state, 241 struct intel_encoder *encoder, 242 const struct intel_crtc_state *old_crtc_state, 243 const struct drm_connector_state *old_conn_state) 244 { 245 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state); 246 } 247 248 static void hsw_disable_crt(struct intel_atomic_state *state, 249 struct intel_encoder *encoder, 250 const struct intel_crtc_state *old_crtc_state, 251 const struct drm_connector_state *old_conn_state) 252 { 253 struct intel_display *display = to_intel_display(encoder); 254 255 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); 256 257 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 258 } 259 260 static void hsw_post_disable_crt(struct intel_atomic_state *state, 261 struct intel_encoder *encoder, 262 const struct intel_crtc_state *old_crtc_state, 263 const struct drm_connector_state *old_conn_state) 264 { 265 struct intel_display *display = to_intel_display(encoder); 266 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 267 268 intel_crtc_vblank_off(old_crtc_state); 269 270 intel_disable_transcoder(old_crtc_state); 271 272 intel_ddi_disable_transcoder_func(old_crtc_state); 273 274 ilk_pfit_disable(old_crtc_state); 275 276 intel_ddi_disable_transcoder_clock(old_crtc_state); 277 278 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state); 279 280 lpt_pch_disable(state, crtc); 281 282 hsw_fdi_disable(encoder); 283 284 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); 285 286 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 287 } 288 289 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state, 290 struct intel_encoder *encoder, 291 const struct intel_crtc_state *crtc_state, 292 const struct drm_connector_state *conn_state) 293 { 294 struct intel_display *display = to_intel_display(encoder); 295 296 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); 297 298 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 299 } 300 301 static void hsw_pre_enable_crt(struct intel_atomic_state *state, 302 struct intel_encoder *encoder, 303 const struct intel_crtc_state *crtc_state, 304 const struct drm_connector_state *conn_state) 305 { 306 struct intel_display *display = to_intel_display(encoder); 307 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 308 enum pipe pipe = crtc->pipe; 309 310 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); 311 312 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 313 314 hsw_fdi_link_train(encoder, crtc_state); 315 316 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 317 } 318 319 static void hsw_enable_crt(struct intel_atomic_state *state, 320 struct intel_encoder *encoder, 321 const struct intel_crtc_state *crtc_state, 322 const struct drm_connector_state *conn_state) 323 { 324 struct intel_display *display = to_intel_display(encoder); 325 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 326 enum pipe pipe = crtc->pipe; 327 328 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); 329 330 intel_ddi_enable_transcoder_func(encoder, crtc_state); 331 332 intel_enable_transcoder(crtc_state); 333 334 lpt_pch_enable(state, crtc); 335 336 intel_crtc_vblank_on(crtc_state); 337 338 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 339 340 intel_crtc_wait_for_next_vblank(crtc); 341 intel_crtc_wait_for_next_vblank(crtc); 342 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 343 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 344 } 345 346 static void intel_enable_crt(struct intel_atomic_state *state, 347 struct intel_encoder *encoder, 348 const struct intel_crtc_state *crtc_state, 349 const struct drm_connector_state *conn_state) 350 { 351 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 352 } 353 354 static enum drm_mode_status 355 intel_crt_mode_valid(struct drm_connector *connector, 356 const struct drm_display_mode *mode) 357 { 358 struct intel_display *display = to_intel_display(connector->dev); 359 int max_dotclk = display->cdclk.max_dotclk_freq; 360 enum drm_mode_status status; 361 int max_clock; 362 363 status = intel_cpu_transcoder_mode_valid(display, mode); 364 if (status != MODE_OK) 365 return status; 366 367 if (mode->clock < 25000) 368 return MODE_CLOCK_LOW; 369 370 if (HAS_PCH_LPT(display)) 371 max_clock = 180000; 372 else if (display->platform.valleyview) 373 /* 374 * 270 MHz due to current DPLL limits, 375 * DAC limit supposedly 355 MHz. 376 */ 377 max_clock = 270000; 378 else if (IS_DISPLAY_VER(display, 3, 4)) 379 max_clock = 400000; 380 else 381 max_clock = 350000; 382 if (mode->clock > max_clock) 383 return MODE_CLOCK_HIGH; 384 385 if (mode->clock > max_dotclk) 386 return MODE_CLOCK_HIGH; 387 388 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 389 if (HAS_PCH_LPT(display) && 390 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) 391 return MODE_CLOCK_HIGH; 392 393 /* HSW/BDW FDI limited to 4k */ 394 if (mode->hdisplay > 4096) 395 return MODE_H_ILLEGAL; 396 397 return MODE_OK; 398 } 399 400 static int intel_crt_compute_config(struct intel_encoder *encoder, 401 struct intel_crtc_state *crtc_state, 402 struct drm_connector_state *conn_state) 403 { 404 struct drm_display_mode *adjusted_mode = 405 &crtc_state->hw.adjusted_mode; 406 407 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 408 return -EINVAL; 409 410 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 411 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 412 413 return 0; 414 } 415 416 static int pch_crt_compute_config(struct intel_encoder *encoder, 417 struct intel_crtc_state *crtc_state, 418 struct drm_connector_state *conn_state) 419 { 420 struct drm_display_mode *adjusted_mode = 421 &crtc_state->hw.adjusted_mode; 422 423 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 424 return -EINVAL; 425 426 crtc_state->has_pch_encoder = true; 427 if (!intel_link_bw_compute_pipe_bpp(crtc_state)) 428 return -EINVAL; 429 430 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 431 432 return 0; 433 } 434 435 static int hsw_crt_compute_config(struct intel_encoder *encoder, 436 struct intel_crtc_state *crtc_state, 437 struct drm_connector_state *conn_state) 438 { 439 struct intel_display *display = to_intel_display(encoder); 440 struct drm_display_mode *adjusted_mode = 441 &crtc_state->hw.adjusted_mode; 442 443 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 444 return -EINVAL; 445 446 /* HSW/BDW FDI limited to 4k */ 447 if (adjusted_mode->crtc_hdisplay > 4096 || 448 adjusted_mode->crtc_hblank_start > 4096) 449 return -EINVAL; 450 451 crtc_state->has_pch_encoder = true; 452 if (!intel_link_bw_compute_pipe_bpp(crtc_state)) 453 return -EINVAL; 454 455 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 456 457 /* LPT FDI RX only supports 8bpc. */ 458 if (HAS_PCH_LPT(display)) { 459 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ 460 if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) { 461 drm_dbg_kms(display->drm, 462 "LPT only supports 24bpp\n"); 463 return -EINVAL; 464 } 465 466 crtc_state->pipe_bpp = 24; 467 } 468 469 /* FDI must always be 2.7 GHz */ 470 crtc_state->port_clock = 135000 * 2; 471 472 crtc_state->enhanced_framing = true; 473 474 adjusted_mode->crtc_clock = lpt_iclkip(crtc_state); 475 476 return 0; 477 } 478 479 static bool ilk_crt_detect_hotplug(struct drm_connector *connector) 480 { 481 struct intel_display *display = to_intel_display(connector->dev); 482 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 483 u32 adpa; 484 bool ret; 485 486 /* The first time through, trigger an explicit detection cycle */ 487 if (crt->force_hotplug_required) { 488 bool turn_off_dac = HAS_PCH_SPLIT(display); 489 u32 save_adpa; 490 491 crt->force_hotplug_required = false; 492 493 save_adpa = adpa = intel_de_read(display, crt->adpa_reg); 494 drm_dbg_kms(display->drm, 495 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 496 497 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 498 if (turn_off_dac) 499 adpa &= ~ADPA_DAC_ENABLE; 500 501 intel_de_write(display, crt->adpa_reg, adpa); 502 503 if (intel_de_wait_for_clear_ms(display, 504 crt->adpa_reg, 505 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 506 1000)) 507 drm_dbg_kms(display->drm, 508 "timed out waiting for FORCE_TRIGGER"); 509 510 if (turn_off_dac) { 511 intel_de_write(display, crt->adpa_reg, save_adpa); 512 intel_de_posting_read(display, crt->adpa_reg); 513 } 514 } 515 516 /* Check the status to see if both blue and green are on now */ 517 adpa = intel_de_read(display, crt->adpa_reg); 518 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 519 ret = true; 520 else 521 ret = false; 522 drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n", 523 adpa, ret); 524 525 return ret; 526 } 527 528 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 529 { 530 struct intel_display *display = to_intel_display(connector->dev); 531 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 532 u32 adpa; 533 bool ret; 534 u32 save_adpa; 535 536 /* 537 * Doing a force trigger causes a hpd interrupt to get sent, which can 538 * get us stuck in a loop if we're polling: 539 * - We enable power wells and reset the ADPA 540 * - output_poll_exec does force probe on VGA, triggering a hpd 541 * - HPD handler waits for poll to unlock dev->mode_config.mutex 542 * - output_poll_exec shuts off the ADPA, unlocks 543 * dev->mode_config.mutex 544 * - HPD handler runs, resets ADPA and brings us back to the start 545 * 546 * Just disable HPD interrupts here to prevent this 547 */ 548 intel_hpd_block(&crt->base); 549 550 save_adpa = adpa = intel_de_read(display, crt->adpa_reg); 551 drm_dbg_kms(display->drm, 552 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 553 554 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 555 556 intel_de_write(display, crt->adpa_reg, adpa); 557 558 if (intel_de_wait_for_clear_ms(display, crt->adpa_reg, 559 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { 560 drm_dbg_kms(display->drm, 561 "timed out waiting for FORCE_TRIGGER"); 562 intel_de_write(display, crt->adpa_reg, save_adpa); 563 } 564 565 /* Check the status to see if both blue and green are on now */ 566 adpa = intel_de_read(display, crt->adpa_reg); 567 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 568 ret = true; 569 else 570 ret = false; 571 572 drm_dbg_kms(display->drm, 573 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 574 575 intel_hpd_clear_and_unblock(&crt->base); 576 577 return ret; 578 } 579 580 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 581 { 582 struct intel_display *display = to_intel_display(connector->dev); 583 u32 stat; 584 bool ret = false; 585 int i, tries = 0; 586 587 if (HAS_PCH_SPLIT(display)) 588 return ilk_crt_detect_hotplug(connector); 589 590 if (display->platform.valleyview) 591 return valleyview_crt_detect_hotplug(connector); 592 593 /* 594 * On 4 series desktop, CRT detect sequence need to be done twice 595 * to get a reliable result. 596 */ 597 598 if (display->platform.g45) 599 tries = 2; 600 else 601 tries = 1; 602 603 for (i = 0; i < tries ; i++) { 604 /* turn on the FORCE_DETECT */ 605 i915_hotplug_interrupt_update(display, 606 CRT_HOTPLUG_FORCE_DETECT, 607 CRT_HOTPLUG_FORCE_DETECT); 608 /* wait for FORCE_DETECT to go off */ 609 if (intel_de_wait_for_clear_ms(display, PORT_HOTPLUG_EN(display), 610 CRT_HOTPLUG_FORCE_DETECT, 1000)) 611 drm_dbg_kms(display->drm, 612 "timed out waiting for FORCE_DETECT to go off"); 613 } 614 615 stat = intel_de_read(display, PORT_HOTPLUG_STAT(display)); 616 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 617 ret = true; 618 619 /* clear the interrupt we just generated, if any */ 620 intel_de_write(display, PORT_HOTPLUG_STAT(display), 621 CRT_HOTPLUG_INT_STATUS); 622 623 i915_hotplug_interrupt_update(display, CRT_HOTPLUG_FORCE_DETECT, 0); 624 625 return ret; 626 } 627 628 static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector, 629 struct i2c_adapter *ddc) 630 { 631 const struct drm_edid *drm_edid; 632 633 drm_edid = drm_edid_read_ddc(connector, ddc); 634 635 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 636 drm_dbg_kms(connector->dev, 637 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 638 intel_gmbus_force_bit(ddc, true); 639 drm_edid = drm_edid_read_ddc(connector, ddc); 640 intel_gmbus_force_bit(ddc, false); 641 } 642 643 return drm_edid; 644 } 645 646 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 647 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 648 struct i2c_adapter *ddc) 649 { 650 const struct drm_edid *drm_edid; 651 int ret; 652 653 drm_edid = intel_crt_get_edid(connector, ddc); 654 if (!drm_edid) 655 return 0; 656 657 ret = intel_connector_update_modes(connector, drm_edid); 658 659 drm_edid_free(drm_edid); 660 661 return ret; 662 } 663 664 static bool intel_crt_detect_ddc(struct drm_connector *connector) 665 { 666 struct intel_display *display = to_intel_display(connector->dev); 667 const struct drm_edid *drm_edid; 668 bool ret = false; 669 670 drm_edid = intel_crt_get_edid(connector, connector->ddc); 671 672 if (drm_edid) { 673 /* 674 * This may be a DVI-I connector with a shared DDC 675 * link between analog and digital outputs, so we 676 * have to check the EDID input spec of the attached device. 677 */ 678 if (drm_edid_is_digital(drm_edid)) { 679 drm_dbg_kms(display->drm, 680 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 681 } else { 682 drm_dbg_kms(display->drm, 683 "CRT detected via DDC:0x50 [EDID]\n"); 684 ret = true; 685 } 686 } else { 687 drm_dbg_kms(display->drm, 688 "CRT not detected via DDC:0x50 [no valid EDID found]\n"); 689 } 690 691 drm_edid_free(drm_edid); 692 693 return ret; 694 } 695 696 static bool intel_crt_sense_above_threshold(struct intel_display *display) 697 { 698 return intel_vga_read(display, VGA_IS0_R, true) & (1 << 4); 699 } 700 701 static enum drm_connector_status 702 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) 703 { 704 struct intel_display *display = to_intel_display(&crt->base); 705 enum transcoder cpu_transcoder = (enum transcoder)pipe; 706 u32 save_bclrpat; 707 u32 save_vtotal; 708 u32 vtotal, vactive; 709 u32 vsample; 710 u32 vblank, vblank_start, vblank_end; 711 u32 dsl; 712 enum drm_connector_status status; 713 714 drm_dbg_kms(display->drm, "starting load-detect on CRT\n"); 715 716 save_bclrpat = intel_de_read(display, 717 BCLRPAT(display, cpu_transcoder)); 718 save_vtotal = intel_de_read(display, 719 TRANS_VTOTAL(display, cpu_transcoder)); 720 vblank = intel_de_read(display, 721 TRANS_VBLANK(display, cpu_transcoder)); 722 723 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; 724 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; 725 726 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; 727 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; 728 729 /* Set the border color to purple. */ 730 intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050); 731 732 if (DISPLAY_VER(display) != 2) { 733 u32 transconf = intel_de_read(display, 734 TRANSCONF(display, cpu_transcoder)); 735 736 intel_de_write(display, TRANSCONF(display, cpu_transcoder), 737 transconf | TRANSCONF_FORCE_BORDER); 738 intel_de_posting_read(display, 739 TRANSCONF(display, cpu_transcoder)); 740 /* 741 * Wait for next Vblank to substitute 742 * border color for Color info. 743 */ 744 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 745 746 status = intel_crt_sense_above_threshold(display) ? 747 connector_status_connected : 748 connector_status_disconnected; 749 750 intel_de_write(display, TRANSCONF(display, cpu_transcoder), 751 transconf); 752 } else { 753 bool restore_vblank = false; 754 int count, detect; 755 756 /* 757 * If there isn't any border, add some. 758 * Yes, this will flicker 759 */ 760 if (vblank_start <= vactive && vblank_end >= vtotal) { 761 u32 vsync = intel_de_read(display, 762 TRANS_VSYNC(display, cpu_transcoder)); 763 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; 764 765 vblank_start = vsync_start; 766 intel_de_write(display, 767 TRANS_VBLANK(display, cpu_transcoder), 768 VBLANK_START(vblank_start - 1) | 769 VBLANK_END(vblank_end - 1)); 770 restore_vblank = true; 771 } 772 /* sample in the vertical border, selecting the larger one */ 773 if (vblank_start - vactive >= vtotal - vblank_end) 774 vsample = (vblank_start + vactive) >> 1; 775 else 776 vsample = (vtotal + vblank_end) >> 1; 777 778 /* 779 * Wait for the border to be displayed 780 */ 781 while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive) 782 ; 783 while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample) 784 ; 785 /* 786 * Watch sense for an entire scanline 787 */ 788 detect = 0; 789 count = 0; 790 do { 791 count++; 792 if (intel_crt_sense_above_threshold(display)) 793 detect++; 794 } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl)); 795 796 /* restore vblank if necessary */ 797 if (restore_vblank) 798 intel_de_write(display, 799 TRANS_VBLANK(display, cpu_transcoder), 800 vblank); 801 /* 802 * If more than 3/4 of the scanline detected a monitor, 803 * then it is assumed to be present. This works even on i830, 804 * where there isn't any way to force the border color across 805 * the screen 806 */ 807 status = detect * 4 > count * 3 ? 808 connector_status_connected : 809 connector_status_disconnected; 810 } 811 812 /* Restore previous settings */ 813 intel_de_write(display, BCLRPAT(display, cpu_transcoder), 814 save_bclrpat); 815 816 return status; 817 } 818 819 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 820 { 821 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 822 return 1; 823 } 824 825 static const struct dmi_system_id intel_spurious_crt_detect[] = { 826 { 827 .callback = intel_spurious_crt_detect_dmi_callback, 828 .ident = "ACER ZGB", 829 .matches = { 830 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 831 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 832 }, 833 }, 834 { 835 .callback = intel_spurious_crt_detect_dmi_callback, 836 .ident = "Intel DZ77BH-55K", 837 .matches = { 838 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 839 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 840 }, 841 }, 842 { } 843 }; 844 845 static int 846 intel_crt_detect(struct drm_connector *connector, 847 struct drm_modeset_acquire_ctx *ctx, 848 bool force) 849 { 850 struct intel_display *display = to_intel_display(connector->dev); 851 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 852 struct intel_encoder *encoder = &crt->base; 853 struct drm_atomic_state *state; 854 struct ref_tracker *wakeref; 855 int status; 856 857 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n", 858 connector->base.id, connector->name, 859 force); 860 861 if (!intel_display_device_enabled(display)) 862 return connector_status_disconnected; 863 864 if (!intel_display_driver_check_access(display)) 865 return connector->status; 866 867 if (display->params.load_detect_test) { 868 wakeref = intel_display_power_get(display, encoder->power_domain); 869 goto load_detect; 870 } 871 872 /* Skip machines without VGA that falsely report hotplug events */ 873 if (dmi_check_system(intel_spurious_crt_detect)) 874 return connector_status_disconnected; 875 876 wakeref = intel_display_power_get(display, encoder->power_domain); 877 878 if (HAS_HOTPLUG(display)) { 879 /* We can not rely on the HPD pin always being correctly wired 880 * up, for example many KVM do not pass it through, and so 881 * only trust an assertion that the monitor is connected. 882 */ 883 if (intel_crt_detect_hotplug(connector)) { 884 drm_dbg_kms(display->drm, 885 "CRT detected via hotplug\n"); 886 status = connector_status_connected; 887 goto out; 888 } else 889 drm_dbg_kms(display->drm, 890 "CRT not detected via hotplug\n"); 891 } 892 893 if (intel_crt_detect_ddc(connector)) { 894 status = connector_status_connected; 895 goto out; 896 } 897 898 /* Load detection is broken on HPD capable machines. Whoever wants a 899 * broken monitor (without edid) to work behind a broken kvm (that fails 900 * to have the right resistors for HP detection) needs to fix this up. 901 * For now just bail out. */ 902 if (HAS_HOTPLUG(display)) { 903 status = connector_status_disconnected; 904 goto out; 905 } 906 907 load_detect: 908 if (!force) { 909 status = connector->status; 910 goto out; 911 } 912 913 /* for pre-945g platforms use load detect */ 914 state = intel_load_detect_get_pipe(connector, ctx); 915 if (IS_ERR(state)) { 916 status = PTR_ERR(state); 917 } else if (!state) { 918 status = connector_status_unknown; 919 } else { 920 if (intel_crt_detect_ddc(connector)) 921 status = connector_status_connected; 922 else if (DISPLAY_VER(display) < 4) 923 status = intel_crt_load_detect(crt, 924 to_intel_crtc(connector->state->crtc)->pipe); 925 else if (display->params.load_detect_test) 926 status = connector_status_disconnected; 927 else 928 status = connector_status_unknown; 929 intel_load_detect_release_pipe(connector, state, ctx); 930 } 931 932 out: 933 intel_display_power_put(display, encoder->power_domain, wakeref); 934 935 return status; 936 } 937 938 static int intel_crt_get_modes(struct drm_connector *connector) 939 { 940 struct intel_display *display = to_intel_display(connector->dev); 941 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 942 struct intel_encoder *encoder = &crt->base; 943 struct ref_tracker *wakeref; 944 struct i2c_adapter *ddc; 945 int ret; 946 947 if (!intel_display_driver_check_access(display)) 948 return drm_edid_connector_add_modes(connector); 949 950 wakeref = intel_display_power_get(display, encoder->power_domain); 951 952 ret = intel_crt_ddc_get_modes(connector, connector->ddc); 953 if (ret || !display->platform.g4x) 954 goto out; 955 956 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 957 ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB); 958 ret = intel_crt_ddc_get_modes(connector, ddc); 959 960 out: 961 intel_display_power_put(display, encoder->power_domain, wakeref); 962 963 return ret; 964 } 965 966 void intel_crt_reset(struct drm_encoder *encoder) 967 { 968 struct intel_display *display = to_intel_display(encoder->dev); 969 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 970 971 if (DISPLAY_VER(display) >= 5) { 972 u32 adpa; 973 974 adpa = intel_de_read(display, crt->adpa_reg); 975 adpa &= ~ADPA_HOTPLUG_MASK; 976 adpa |= ADPA_HOTPLUG_BITS; 977 intel_de_write(display, crt->adpa_reg, adpa); 978 intel_de_posting_read(display, crt->adpa_reg); 979 980 drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa); 981 crt->force_hotplug_required = true; 982 } 983 984 } 985 986 /* 987 * Routines for controlling stuff on the analog port 988 */ 989 990 static const struct drm_connector_funcs intel_crt_connector_funcs = { 991 .fill_modes = drm_helper_probe_single_connector_modes, 992 .late_register = intel_connector_register, 993 .early_unregister = intel_connector_unregister, 994 .destroy = intel_connector_destroy, 995 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 996 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 997 }; 998 999 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 1000 .detect_ctx = intel_crt_detect, 1001 .mode_valid = intel_crt_mode_valid, 1002 .get_modes = intel_crt_get_modes, 1003 }; 1004 1005 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 1006 .reset = intel_crt_reset, 1007 .destroy = intel_encoder_destroy, 1008 }; 1009 1010 void intel_crt_init(struct intel_display *display) 1011 { 1012 struct intel_connector *connector; 1013 struct intel_crt *crt; 1014 i915_reg_t adpa_reg; 1015 u8 ddc_pin; 1016 u32 adpa; 1017 1018 if (HAS_PCH_SPLIT(display)) 1019 adpa_reg = PCH_ADPA; 1020 else if (display->platform.valleyview) 1021 adpa_reg = VLV_ADPA; 1022 else 1023 adpa_reg = ADPA; 1024 1025 adpa = intel_de_read(display, adpa_reg); 1026 if ((adpa & ADPA_DAC_ENABLE) == 0) { 1027 /* 1028 * On some machines (some IVB at least) CRT can be 1029 * fused off, but there's no known fuse bit to 1030 * indicate that. On these machine the ADPA register 1031 * works normally, except the DAC enable bit won't 1032 * take. So the only way to tell is attempt to enable 1033 * it and see what happens. 1034 */ 1035 intel_de_write(display, adpa_reg, 1036 adpa | ADPA_DAC_ENABLE | 1037 ADPA_HSYNC_CNTL_DISABLE | 1038 ADPA_VSYNC_CNTL_DISABLE); 1039 if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0) 1040 return; 1041 intel_de_write(display, adpa_reg, adpa); 1042 } 1043 1044 crt = kzalloc_obj(struct intel_crt); 1045 if (!crt) 1046 return; 1047 1048 connector = intel_connector_alloc(); 1049 if (!connector) { 1050 kfree(crt); 1051 return; 1052 } 1053 1054 ddc_pin = display->vbt.crt_ddc_pin; 1055 1056 drm_connector_init_with_ddc(display->drm, &connector->base, 1057 &intel_crt_connector_funcs, 1058 DRM_MODE_CONNECTOR_VGA, 1059 intel_gmbus_get_adapter(display, ddc_pin)); 1060 1061 drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs, 1062 DRM_MODE_ENCODER_DAC, "CRT"); 1063 1064 intel_connector_attach_encoder(connector, &crt->base); 1065 1066 crt->base.type = INTEL_OUTPUT_ANALOG; 1067 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); 1068 if (display->platform.i830) 1069 crt->base.pipe_mask = BIT(PIPE_A); 1070 else 1071 crt->base.pipe_mask = ~0; 1072 1073 if (DISPLAY_VER(display) != 2) 1074 connector->base.interlace_allowed = true; 1075 1076 crt->adpa_reg = adpa_reg; 1077 1078 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; 1079 1080 if (HAS_HOTPLUG(display) && 1081 !dmi_check_system(intel_spurious_crt_detect)) { 1082 crt->base.hpd_pin = HPD_CRT; 1083 crt->base.hotplug = intel_encoder_hotplug; 1084 connector->polled = DRM_CONNECTOR_POLL_HPD; 1085 } else { 1086 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1087 } 1088 connector->base.polled = connector->polled; 1089 1090 if (HAS_DDI(display)) { 1091 assert_port_valid(display, PORT_E); 1092 1093 crt->base.port = PORT_E; 1094 crt->base.get_config = hsw_crt_get_config; 1095 crt->base.get_hw_state = intel_ddi_get_hw_state; 1096 crt->base.compute_config = hsw_crt_compute_config; 1097 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; 1098 crt->base.pre_enable = hsw_pre_enable_crt; 1099 crt->base.enable = hsw_enable_crt; 1100 crt->base.disable = hsw_disable_crt; 1101 crt->base.post_disable = hsw_post_disable_crt; 1102 crt->base.enable_clock = hsw_ddi_enable_clock; 1103 crt->base.disable_clock = hsw_ddi_disable_clock; 1104 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; 1105 1106 intel_ddi_buf_trans_init(&crt->base); 1107 } else { 1108 if (HAS_PCH_SPLIT(display)) { 1109 crt->base.compute_config = pch_crt_compute_config; 1110 crt->base.disable = pch_disable_crt; 1111 crt->base.post_disable = pch_post_disable_crt; 1112 } else { 1113 crt->base.compute_config = intel_crt_compute_config; 1114 crt->base.disable = intel_disable_crt; 1115 } 1116 crt->base.port = PORT_NONE; 1117 crt->base.get_config = intel_crt_get_config; 1118 crt->base.get_hw_state = intel_crt_get_hw_state; 1119 crt->base.enable = intel_enable_crt; 1120 } 1121 connector->get_hw_state = intel_connector_get_hw_state; 1122 1123 drm_connector_helper_add(&connector->base, &intel_crt_connector_helper_funcs); 1124 1125 /* 1126 * TODO: find a proper way to discover whether we need to set the the 1127 * polarity and link reversal bits or not, instead of relying on the 1128 * BIOS. 1129 */ 1130 if (HAS_PCH_LPT(display)) { 1131 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 1132 FDI_RX_LINK_REVERSAL_OVERRIDE; 1133 1134 display->fdi.rx_config = intel_de_read(display, 1135 FDI_RX_CTL(PIPE_A)) & fdi_config; 1136 } 1137 1138 intel_crt_reset(&crt->base.base); 1139 } 1140