1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 #include <video/vga.h> 37 38 #include "intel_connector.h" 39 #include "intel_crt.h" 40 #include "intel_crt_regs.h" 41 #include "intel_crtc.h" 42 #include "intel_ddi.h" 43 #include "intel_ddi_buf_trans.h" 44 #include "intel_de.h" 45 #include "intel_display_driver.h" 46 #include "intel_display_regs.h" 47 #include "intel_display_types.h" 48 #include "intel_fdi.h" 49 #include "intel_fdi_regs.h" 50 #include "intel_fifo_underrun.h" 51 #include "intel_gmbus.h" 52 #include "intel_hotplug.h" 53 #include "intel_hotplug_irq.h" 54 #include "intel_link_bw.h" 55 #include "intel_load_detect.h" 56 #include "intel_pch_display.h" 57 #include "intel_pch_refclk.h" 58 #include "intel_pfit.h" 59 #include "intel_vga.h" 60 61 /* Here's the desired hotplug mode */ 62 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_ENABLE | \ 63 ADPA_CRT_HOTPLUG_PERIOD_128 | \ 64 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 65 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 66 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 67 ADPA_CRT_HOTPLUG_VOLREF_325MV) 68 #define ADPA_HOTPLUG_MASK (ADPA_CRT_HOTPLUG_MONITOR_MASK | \ 69 ADPA_CRT_HOTPLUG_ENABLE | \ 70 ADPA_CRT_HOTPLUG_PERIOD_MASK | \ 71 ADPA_CRT_HOTPLUG_WARMUP_MASK | \ 72 ADPA_CRT_HOTPLUG_SAMPLE_MASK | \ 73 ADPA_CRT_HOTPLUG_VOLTAGE_MASK | \ 74 ADPA_CRT_HOTPLUG_VOLREF_MASK | \ 75 ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 76 77 struct intel_crt { 78 struct intel_encoder base; 79 bool force_hotplug_required; 80 intel_reg_t adpa_reg; 81 }; 82 83 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 84 { 85 return container_of(encoder, struct intel_crt, base); 86 } 87 88 static struct intel_crt *intel_attached_crt(struct intel_connector *connector) 89 { 90 return intel_encoder_to_crt(intel_attached_encoder(connector)); 91 } 92 93 bool intel_crt_port_enabled(struct intel_display *display, 94 intel_reg_t adpa_reg, enum pipe *pipe) 95 { 96 u32 val; 97 98 val = intel_de_read(display, adpa_reg); 99 100 /* asserts want to know the pipe even if the port is disabled */ 101 if (HAS_PCH_CPT(display)) 102 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val); 103 else 104 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val); 105 106 return val & ADPA_DAC_ENABLE; 107 } 108 109 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 110 enum pipe *pipe) 111 { 112 struct intel_display *display = to_intel_display(encoder); 113 struct intel_crt *crt = intel_encoder_to_crt(encoder); 114 struct ref_tracker *wakeref; 115 bool ret; 116 117 wakeref = intel_display_power_get_if_enabled(display, 118 encoder->power_domain); 119 if (!wakeref) 120 return false; 121 122 ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); 123 124 intel_display_power_put(display, encoder->power_domain, wakeref); 125 126 return ret; 127 } 128 129 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 130 { 131 struct intel_display *display = to_intel_display(encoder); 132 struct intel_crt *crt = intel_encoder_to_crt(encoder); 133 u32 tmp, flags = 0; 134 135 tmp = intel_de_read(display, crt->adpa_reg); 136 137 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 138 flags |= DRM_MODE_FLAG_PHSYNC; 139 else 140 flags |= DRM_MODE_FLAG_NHSYNC; 141 142 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 143 flags |= DRM_MODE_FLAG_PVSYNC; 144 else 145 flags |= DRM_MODE_FLAG_NVSYNC; 146 147 return flags; 148 } 149 150 static void intel_crt_get_config(struct intel_encoder *encoder, 151 struct intel_crtc_state *crtc_state) 152 { 153 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 154 155 crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 156 157 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; 158 } 159 160 static void hsw_crt_get_config(struct intel_encoder *encoder, 161 struct intel_crtc_state *crtc_state) 162 { 163 lpt_pch_get_config(crtc_state); 164 165 hsw_ddi_get_config(encoder, crtc_state); 166 167 crtc_state->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 168 DRM_MODE_FLAG_NHSYNC | 169 DRM_MODE_FLAG_PVSYNC | 170 DRM_MODE_FLAG_NVSYNC); 171 crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 172 } 173 174 /* Note: The caller is required to filter out dpms modes not supported by the 175 * platform. */ 176 static void intel_crt_set_dpms(struct intel_encoder *encoder, 177 const struct intel_crtc_state *crtc_state, 178 int mode) 179 { 180 struct intel_display *display = to_intel_display(encoder); 181 struct intel_crt *crt = intel_encoder_to_crt(encoder); 182 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 183 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 184 u32 adpa; 185 186 if (DISPLAY_VER(display) >= 5) 187 adpa = ADPA_HOTPLUG_BITS; 188 else 189 adpa = 0; 190 191 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 192 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 193 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 194 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 195 196 /* For CPT allow 3 pipe config, for others just use A or B */ 197 if (HAS_PCH_LPT(display)) 198 ; /* Those bits don't exist here */ 199 else if (HAS_PCH_CPT(display)) 200 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); 201 else 202 adpa |= ADPA_PIPE_SEL(crtc->pipe); 203 204 if (!HAS_PCH_SPLIT(display)) 205 intel_de_write(display, BCLRPAT(display, crtc->pipe), 0); 206 207 switch (mode) { 208 case DRM_MODE_DPMS_ON: 209 adpa |= ADPA_DAC_ENABLE; 210 break; 211 case DRM_MODE_DPMS_STANDBY: 212 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 213 break; 214 case DRM_MODE_DPMS_SUSPEND: 215 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 216 break; 217 case DRM_MODE_DPMS_OFF: 218 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 219 break; 220 } 221 222 intel_de_write(display, crt->adpa_reg, adpa); 223 } 224 225 static void intel_disable_crt(struct intel_atomic_state *state, 226 struct intel_encoder *encoder, 227 const struct intel_crtc_state *old_crtc_state, 228 const struct drm_connector_state *old_conn_state) 229 { 230 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 231 } 232 233 static void pch_disable_crt(struct intel_atomic_state *state, 234 struct intel_encoder *encoder, 235 const struct intel_crtc_state *old_crtc_state, 236 const struct drm_connector_state *old_conn_state) 237 { 238 } 239 240 static void pch_post_disable_crt(struct intel_atomic_state *state, 241 struct intel_encoder *encoder, 242 const struct intel_crtc_state *old_crtc_state, 243 const struct drm_connector_state *old_conn_state) 244 { 245 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state); 246 } 247 248 static void hsw_disable_crt(struct intel_atomic_state *state, 249 struct intel_encoder *encoder, 250 const struct intel_crtc_state *old_crtc_state, 251 const struct drm_connector_state *old_conn_state) 252 { 253 struct intel_display *display = to_intel_display(encoder); 254 255 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); 256 257 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 258 } 259 260 static void hsw_post_disable_crt(struct intel_atomic_state *state, 261 struct intel_encoder *encoder, 262 const struct intel_crtc_state *old_crtc_state, 263 const struct drm_connector_state *old_conn_state) 264 { 265 struct intel_display *display = to_intel_display(encoder); 266 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 267 268 intel_crtc_vblank_off(old_crtc_state); 269 270 intel_disable_transcoder(old_crtc_state); 271 272 intel_ddi_disable_transcoder_func(old_crtc_state); 273 274 ilk_pfit_disable(old_crtc_state); 275 276 intel_ddi_disable_transcoder_clock(old_crtc_state); 277 278 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state); 279 280 lpt_pch_disable(state, crtc); 281 282 hsw_fdi_disable(encoder); 283 284 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); 285 286 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 287 } 288 289 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state, 290 struct intel_encoder *encoder, 291 const struct intel_crtc_state *crtc_state, 292 const struct drm_connector_state *conn_state) 293 { 294 struct intel_display *display = to_intel_display(encoder); 295 296 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); 297 298 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 299 } 300 301 static void hsw_pre_enable_crt(struct intel_atomic_state *state, 302 struct intel_encoder *encoder, 303 const struct intel_crtc_state *crtc_state, 304 const struct drm_connector_state *conn_state) 305 { 306 struct intel_display *display = to_intel_display(encoder); 307 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 308 enum pipe pipe = crtc->pipe; 309 310 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); 311 312 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 313 314 hsw_fdi_link_train(encoder, crtc_state); 315 316 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 317 } 318 319 static void hsw_enable_crt(struct intel_atomic_state *state, 320 struct intel_encoder *encoder, 321 const struct intel_crtc_state *crtc_state, 322 const struct drm_connector_state *conn_state) 323 { 324 struct intel_display *display = to_intel_display(encoder); 325 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 326 enum pipe pipe = crtc->pipe; 327 328 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); 329 330 intel_ddi_enable_transcoder_func(encoder, crtc_state); 331 332 intel_enable_transcoder(crtc_state); 333 334 lpt_pch_enable(state, crtc); 335 336 intel_crtc_vblank_on(crtc_state); 337 338 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 339 340 intel_crtc_wait_for_next_vblank(crtc); 341 intel_crtc_wait_for_next_vblank(crtc); 342 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 343 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 344 } 345 346 static void intel_enable_crt(struct intel_atomic_state *state, 347 struct intel_encoder *encoder, 348 const struct intel_crtc_state *crtc_state, 349 const struct drm_connector_state *conn_state) 350 { 351 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 352 } 353 354 static enum drm_mode_status 355 intel_crt_mode_valid(struct drm_connector *connector, 356 const struct drm_display_mode *mode) 357 { 358 struct intel_display *display = to_intel_display(connector->dev); 359 int max_dotclk = display->cdclk.max_dotclk_freq; 360 enum drm_mode_status status; 361 int max_clock; 362 363 status = intel_cpu_transcoder_mode_valid(display, mode); 364 if (status != MODE_OK) 365 return status; 366 367 if (mode->clock < 25000) 368 return MODE_CLOCK_LOW; 369 370 if (HAS_PCH_LPT(display)) 371 max_clock = 180000; 372 else if (display->platform.valleyview) 373 /* 374 * 270 MHz due to current DPLL limits, 375 * DAC limit supposedly 355 MHz. 376 */ 377 max_clock = 270000; 378 else if (IS_DISPLAY_VER(display, 3, 4)) 379 max_clock = 400000; 380 else 381 max_clock = 350000; 382 if (mode->clock > max_clock) 383 return MODE_CLOCK_HIGH; 384 385 if (mode->clock > max_dotclk) 386 return MODE_CLOCK_HIGH; 387 388 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 389 if (HAS_PCH_LPT(display) && 390 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) 391 return MODE_CLOCK_HIGH; 392 393 /* HSW/BDW FDI limited to 4k */ 394 if (mode->hdisplay > 4096) 395 return MODE_H_ILLEGAL; 396 397 return MODE_OK; 398 } 399 400 static int intel_crt_compute_config(struct intel_atomic_state *state, 401 struct intel_encoder *encoder, 402 struct intel_crtc_state *crtc_state, 403 struct drm_connector_state *conn_state) 404 { 405 struct drm_display_mode *adjusted_mode = 406 &crtc_state->hw.adjusted_mode; 407 408 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 409 return -EINVAL; 410 411 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 412 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 413 414 return 0; 415 } 416 417 static int pch_crt_compute_config(struct intel_atomic_state *state, 418 struct intel_encoder *encoder, 419 struct intel_crtc_state *crtc_state, 420 struct drm_connector_state *conn_state) 421 { 422 struct drm_display_mode *adjusted_mode = 423 &crtc_state->hw.adjusted_mode; 424 425 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 426 return -EINVAL; 427 428 crtc_state->has_pch_encoder = true; 429 if (!intel_link_bw_compute_pipe_bpp(crtc_state)) 430 return -EINVAL; 431 432 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 433 434 return 0; 435 } 436 437 static int hsw_crt_compute_config(struct intel_atomic_state *state, 438 struct intel_encoder *encoder, 439 struct intel_crtc_state *crtc_state, 440 struct drm_connector_state *conn_state) 441 { 442 struct intel_display *display = to_intel_display(encoder); 443 struct drm_display_mode *adjusted_mode = 444 &crtc_state->hw.adjusted_mode; 445 446 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 447 return -EINVAL; 448 449 /* HSW/BDW FDI limited to 4k */ 450 if (adjusted_mode->crtc_hdisplay > 4096 || 451 adjusted_mode->crtc_hblank_start > 4096) 452 return -EINVAL; 453 454 crtc_state->has_pch_encoder = true; 455 if (!intel_link_bw_compute_pipe_bpp(crtc_state)) 456 return -EINVAL; 457 458 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 459 460 /* LPT FDI RX only supports 8bpc. */ 461 if (HAS_PCH_LPT(display)) { 462 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ 463 if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) { 464 drm_dbg_kms(display->drm, 465 "LPT only supports 24bpp\n"); 466 return -EINVAL; 467 } 468 469 crtc_state->pipe_bpp = 24; 470 } 471 472 /* FDI must always be 2.7 GHz */ 473 crtc_state->port_clock = 135000 * 2; 474 475 crtc_state->enhanced_framing = true; 476 477 adjusted_mode->crtc_clock = lpt_iclkip(crtc_state); 478 479 return 0; 480 } 481 482 static bool ilk_crt_detect_hotplug(struct drm_connector *connector) 483 { 484 struct intel_display *display = to_intel_display(connector->dev); 485 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 486 u32 adpa; 487 bool ret; 488 489 /* The first time through, trigger an explicit detection cycle */ 490 if (crt->force_hotplug_required) { 491 bool turn_off_dac = HAS_PCH_SPLIT(display); 492 u32 save_adpa; 493 494 crt->force_hotplug_required = false; 495 496 save_adpa = adpa = intel_de_read(display, crt->adpa_reg); 497 drm_dbg_kms(display->drm, 498 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 499 500 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 501 if (turn_off_dac) 502 adpa &= ~ADPA_DAC_ENABLE; 503 504 intel_de_write(display, crt->adpa_reg, adpa); 505 506 if (intel_de_wait_for_clear_ms(display, 507 crt->adpa_reg, 508 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 509 1000)) 510 drm_dbg_kms(display->drm, 511 "timed out waiting for FORCE_TRIGGER"); 512 513 if (turn_off_dac) { 514 intel_de_write(display, crt->adpa_reg, save_adpa); 515 intel_de_posting_read(display, crt->adpa_reg); 516 } 517 } 518 519 /* Check the status to see if both blue and green are on now */ 520 adpa = intel_de_read(display, crt->adpa_reg); 521 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 522 ret = true; 523 else 524 ret = false; 525 drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n", 526 adpa, ret); 527 528 return ret; 529 } 530 531 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 532 { 533 struct intel_display *display = to_intel_display(connector->dev); 534 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 535 u32 adpa; 536 bool ret; 537 u32 save_adpa; 538 539 /* 540 * Doing a force trigger causes a hpd interrupt to get sent, which can 541 * get us stuck in a loop if we're polling: 542 * - We enable power wells and reset the ADPA 543 * - output_poll_exec does force probe on VGA, triggering a hpd 544 * - HPD handler waits for poll to unlock dev->mode_config.mutex 545 * - output_poll_exec shuts off the ADPA, unlocks 546 * dev->mode_config.mutex 547 * - HPD handler runs, resets ADPA and brings us back to the start 548 * 549 * Just disable HPD interrupts here to prevent this 550 */ 551 intel_hpd_block(&crt->base); 552 553 save_adpa = adpa = intel_de_read(display, crt->adpa_reg); 554 drm_dbg_kms(display->drm, 555 "trigger hotplug detect cycle: adpa=0x%x\n", adpa); 556 557 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 558 559 intel_de_write(display, crt->adpa_reg, adpa); 560 561 if (intel_de_wait_for_clear_ms(display, crt->adpa_reg, 562 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { 563 drm_dbg_kms(display->drm, 564 "timed out waiting for FORCE_TRIGGER"); 565 intel_de_write(display, crt->adpa_reg, save_adpa); 566 } 567 568 /* Check the status to see if both blue and green are on now */ 569 adpa = intel_de_read(display, crt->adpa_reg); 570 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 571 ret = true; 572 else 573 ret = false; 574 575 drm_dbg_kms(display->drm, 576 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 577 578 intel_hpd_clear_and_unblock(&crt->base); 579 580 return ret; 581 } 582 583 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 584 { 585 struct intel_display *display = to_intel_display(connector->dev); 586 u32 stat; 587 bool ret = false; 588 int i, tries = 0; 589 590 if (HAS_PCH_SPLIT(display)) 591 return ilk_crt_detect_hotplug(connector); 592 593 if (display->platform.valleyview) 594 return valleyview_crt_detect_hotplug(connector); 595 596 /* 597 * On 4 series desktop, CRT detect sequence need to be done twice 598 * to get a reliable result. 599 */ 600 601 if (display->platform.g45) 602 tries = 2; 603 else 604 tries = 1; 605 606 for (i = 0; i < tries ; i++) { 607 /* turn on the FORCE_DETECT */ 608 i915_hotplug_interrupt_update(display, 609 CRT_HOTPLUG_FORCE_DETECT, 610 CRT_HOTPLUG_FORCE_DETECT); 611 /* wait for FORCE_DETECT to go off */ 612 if (intel_de_wait_for_clear_ms(display, PORT_HOTPLUG_EN(display), 613 CRT_HOTPLUG_FORCE_DETECT, 1000)) 614 drm_dbg_kms(display->drm, 615 "timed out waiting for FORCE_DETECT to go off"); 616 } 617 618 stat = intel_de_read(display, PORT_HOTPLUG_STAT(display)); 619 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 620 ret = true; 621 622 /* clear the interrupt we just generated, if any */ 623 intel_de_write(display, PORT_HOTPLUG_STAT(display), 624 CRT_HOTPLUG_INT_STATUS); 625 626 i915_hotplug_interrupt_update(display, CRT_HOTPLUG_FORCE_DETECT, 0); 627 628 return ret; 629 } 630 631 static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector, 632 struct i2c_adapter *ddc) 633 { 634 const struct drm_edid *drm_edid; 635 636 drm_edid = drm_edid_read_ddc(connector, ddc); 637 638 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 639 drm_dbg_kms(connector->dev, 640 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 641 intel_gmbus_force_bit(ddc, true); 642 drm_edid = drm_edid_read_ddc(connector, ddc); 643 intel_gmbus_force_bit(ddc, false); 644 } 645 646 return drm_edid; 647 } 648 649 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 650 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 651 struct i2c_adapter *ddc) 652 { 653 const struct drm_edid *drm_edid; 654 int ret; 655 656 drm_edid = intel_crt_get_edid(connector, ddc); 657 if (!drm_edid) 658 return 0; 659 660 ret = intel_connector_update_modes(connector, drm_edid); 661 662 drm_edid_free(drm_edid); 663 664 return ret; 665 } 666 667 static bool intel_crt_detect_ddc(struct drm_connector *connector) 668 { 669 struct intel_display *display = to_intel_display(connector->dev); 670 const struct drm_edid *drm_edid; 671 bool ret = false; 672 673 drm_edid = intel_crt_get_edid(connector, connector->ddc); 674 675 if (drm_edid) { 676 /* 677 * This may be a DVI-I connector with a shared DDC 678 * link between analog and digital outputs, so we 679 * have to check the EDID input spec of the attached device. 680 */ 681 if (drm_edid_is_digital(drm_edid)) { 682 drm_dbg_kms(display->drm, 683 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 684 } else { 685 drm_dbg_kms(display->drm, 686 "CRT detected via DDC:0x50 [EDID]\n"); 687 ret = true; 688 } 689 } else { 690 drm_dbg_kms(display->drm, 691 "CRT not detected via DDC:0x50 [no valid EDID found]\n"); 692 } 693 694 drm_edid_free(drm_edid); 695 696 return ret; 697 } 698 699 static bool intel_crt_sense_above_threshold(struct intel_display *display) 700 { 701 return intel_vga_read(display, VGA_IS0_R, true) & (1 << 4); 702 } 703 704 static enum drm_connector_status 705 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) 706 { 707 struct intel_display *display = to_intel_display(&crt->base); 708 enum transcoder cpu_transcoder = (enum transcoder)pipe; 709 u32 save_bclrpat; 710 u32 save_vtotal; 711 u32 vtotal, vactive; 712 u32 vsample; 713 u32 vblank, vblank_start, vblank_end; 714 u32 dsl; 715 enum drm_connector_status status; 716 717 drm_dbg_kms(display->drm, "starting load-detect on CRT\n"); 718 719 save_bclrpat = intel_de_read(display, 720 BCLRPAT(display, cpu_transcoder)); 721 save_vtotal = intel_de_read(display, 722 TRANS_VTOTAL(display, cpu_transcoder)); 723 vblank = intel_de_read(display, 724 TRANS_VBLANK(display, cpu_transcoder)); 725 726 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; 727 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; 728 729 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; 730 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; 731 732 /* Set the border color to purple. */ 733 intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050); 734 735 if (DISPLAY_VER(display) != 2) { 736 u32 transconf = intel_de_read(display, 737 TRANSCONF(display, cpu_transcoder)); 738 739 intel_de_write(display, TRANSCONF(display, cpu_transcoder), 740 transconf | TRANSCONF_FORCE_BORDER); 741 intel_de_posting_read(display, 742 TRANSCONF(display, cpu_transcoder)); 743 /* 744 * Wait for next Vblank to substitute 745 * border color for Color info. 746 */ 747 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 748 749 status = intel_crt_sense_above_threshold(display) ? 750 connector_status_connected : 751 connector_status_disconnected; 752 753 intel_de_write(display, TRANSCONF(display, cpu_transcoder), 754 transconf); 755 } else { 756 bool restore_vblank = false; 757 int count, detect; 758 759 /* 760 * If there isn't any border, add some. 761 * Yes, this will flicker 762 */ 763 if (vblank_start <= vactive && vblank_end >= vtotal) { 764 u32 vsync = intel_de_read(display, 765 TRANS_VSYNC(display, cpu_transcoder)); 766 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; 767 768 vblank_start = vsync_start; 769 intel_de_write(display, 770 TRANS_VBLANK(display, cpu_transcoder), 771 VBLANK_START(vblank_start - 1) | 772 VBLANK_END(vblank_end - 1)); 773 restore_vblank = true; 774 } 775 /* sample in the vertical border, selecting the larger one */ 776 if (vblank_start - vactive >= vtotal - vblank_end) 777 vsample = (vblank_start + vactive) >> 1; 778 else 779 vsample = (vtotal + vblank_end) >> 1; 780 781 /* 782 * Wait for the border to be displayed 783 */ 784 while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive) 785 ; 786 while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample) 787 ; 788 /* 789 * Watch sense for an entire scanline 790 */ 791 detect = 0; 792 count = 0; 793 do { 794 count++; 795 if (intel_crt_sense_above_threshold(display)) 796 detect++; 797 } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl)); 798 799 /* restore vblank if necessary */ 800 if (restore_vblank) 801 intel_de_write(display, 802 TRANS_VBLANK(display, cpu_transcoder), 803 vblank); 804 /* 805 * If more than 3/4 of the scanline detected a monitor, 806 * then it is assumed to be present. This works even on i830, 807 * where there isn't any way to force the border color across 808 * the screen 809 */ 810 status = detect * 4 > count * 3 ? 811 connector_status_connected : 812 connector_status_disconnected; 813 } 814 815 /* Restore previous settings */ 816 intel_de_write(display, BCLRPAT(display, cpu_transcoder), 817 save_bclrpat); 818 819 return status; 820 } 821 822 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 823 { 824 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 825 return 1; 826 } 827 828 static const struct dmi_system_id intel_spurious_crt_detect[] = { 829 { 830 .callback = intel_spurious_crt_detect_dmi_callback, 831 .ident = "ACER ZGB", 832 .matches = { 833 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 834 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 835 }, 836 }, 837 { 838 .callback = intel_spurious_crt_detect_dmi_callback, 839 .ident = "Intel DZ77BH-55K", 840 .matches = { 841 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 842 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 843 }, 844 }, 845 { } 846 }; 847 848 static int 849 intel_crt_detect(struct drm_connector *connector, 850 struct drm_modeset_acquire_ctx *ctx, 851 bool force) 852 { 853 struct intel_display *display = to_intel_display(connector->dev); 854 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 855 struct intel_encoder *encoder = &crt->base; 856 struct drm_atomic_commit *state; 857 struct ref_tracker *wakeref; 858 int status; 859 860 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n", 861 connector->base.id, connector->name, 862 force); 863 864 if (!intel_display_device_enabled(display)) 865 return connector_status_disconnected; 866 867 if (!intel_display_driver_check_access(display)) 868 return connector->status; 869 870 if (display->params.load_detect_test) { 871 wakeref = intel_display_power_get(display, encoder->power_domain); 872 goto load_detect; 873 } 874 875 /* Skip machines without VGA that falsely report hotplug events */ 876 if (dmi_check_system(intel_spurious_crt_detect)) 877 return connector_status_disconnected; 878 879 wakeref = intel_display_power_get(display, encoder->power_domain); 880 881 if (HAS_HOTPLUG(display)) { 882 /* We can not rely on the HPD pin always being correctly wired 883 * up, for example many KVM do not pass it through, and so 884 * only trust an assertion that the monitor is connected. 885 */ 886 if (intel_crt_detect_hotplug(connector)) { 887 drm_dbg_kms(display->drm, 888 "CRT detected via hotplug\n"); 889 status = connector_status_connected; 890 goto out; 891 } else 892 drm_dbg_kms(display->drm, 893 "CRT not detected via hotplug\n"); 894 } 895 896 if (intel_crt_detect_ddc(connector)) { 897 status = connector_status_connected; 898 goto out; 899 } 900 901 /* Load detection is broken on HPD capable machines. Whoever wants a 902 * broken monitor (without edid) to work behind a broken kvm (that fails 903 * to have the right resistors for HP detection) needs to fix this up. 904 * For now just bail out. */ 905 if (HAS_HOTPLUG(display)) { 906 status = connector_status_disconnected; 907 goto out; 908 } 909 910 load_detect: 911 if (!force) { 912 status = connector->status; 913 goto out; 914 } 915 916 /* for pre-945g platforms use load detect */ 917 state = intel_load_detect_get_pipe(connector, ctx); 918 if (IS_ERR(state)) { 919 status = PTR_ERR(state); 920 } else if (!state) { 921 status = connector_status_unknown; 922 } else { 923 if (intel_crt_detect_ddc(connector)) 924 status = connector_status_connected; 925 else if (DISPLAY_VER(display) < 4) 926 status = intel_crt_load_detect(crt, 927 to_intel_crtc(connector->state->crtc)->pipe); 928 else if (display->params.load_detect_test) 929 status = connector_status_disconnected; 930 else 931 status = connector_status_unknown; 932 intel_load_detect_release_pipe(connector, state, ctx); 933 } 934 935 out: 936 intel_display_power_put(display, encoder->power_domain, wakeref); 937 938 return status; 939 } 940 941 static int intel_crt_get_modes(struct drm_connector *connector) 942 { 943 struct intel_display *display = to_intel_display(connector->dev); 944 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 945 struct intel_encoder *encoder = &crt->base; 946 struct ref_tracker *wakeref; 947 struct i2c_adapter *ddc; 948 int ret; 949 950 if (!intel_display_driver_check_access(display)) 951 return drm_edid_connector_add_modes(connector); 952 953 wakeref = intel_display_power_get(display, encoder->power_domain); 954 955 ret = intel_crt_ddc_get_modes(connector, connector->ddc); 956 if (ret || !display->platform.g4x) 957 goto out; 958 959 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 960 ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB); 961 ret = intel_crt_ddc_get_modes(connector, ddc); 962 963 out: 964 intel_display_power_put(display, encoder->power_domain, wakeref); 965 966 return ret; 967 } 968 969 void intel_crt_reset(struct drm_encoder *encoder) 970 { 971 struct intel_display *display = to_intel_display(encoder->dev); 972 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 973 974 if (DISPLAY_VER(display) >= 5) { 975 u32 adpa; 976 977 adpa = intel_de_read(display, crt->adpa_reg); 978 adpa &= ~ADPA_HOTPLUG_MASK; 979 adpa |= ADPA_HOTPLUG_BITS; 980 intel_de_write(display, crt->adpa_reg, adpa); 981 intel_de_posting_read(display, crt->adpa_reg); 982 983 drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa); 984 crt->force_hotplug_required = true; 985 } 986 987 } 988 989 /* 990 * Routines for controlling stuff on the analog port 991 */ 992 993 static const struct drm_connector_funcs intel_crt_connector_funcs = { 994 .fill_modes = drm_helper_probe_single_connector_modes, 995 .late_register = intel_connector_register, 996 .early_unregister = intel_connector_unregister, 997 .destroy = intel_connector_destroy, 998 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 999 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1000 }; 1001 1002 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 1003 .detect_ctx = intel_crt_detect, 1004 .mode_valid = intel_crt_mode_valid, 1005 .get_modes = intel_crt_get_modes, 1006 }; 1007 1008 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 1009 .reset = intel_crt_reset, 1010 .destroy = intel_encoder_destroy, 1011 }; 1012 1013 void intel_crt_init(struct intel_display *display) 1014 { 1015 struct intel_connector *connector; 1016 struct intel_crt *crt; 1017 intel_reg_t adpa_reg; 1018 u8 ddc_pin; 1019 u32 adpa; 1020 1021 if (HAS_PCH_SPLIT(display)) 1022 adpa_reg = PCH_ADPA; 1023 else if (display->platform.valleyview) 1024 adpa_reg = VLV_ADPA; 1025 else 1026 adpa_reg = ADPA; 1027 1028 adpa = intel_de_read(display, adpa_reg); 1029 if ((adpa & ADPA_DAC_ENABLE) == 0) { 1030 /* 1031 * On some machines (some IVB at least) CRT can be 1032 * fused off, but there's no known fuse bit to 1033 * indicate that. On these machine the ADPA register 1034 * works normally, except the DAC enable bit won't 1035 * take. So the only way to tell is attempt to enable 1036 * it and see what happens. 1037 */ 1038 intel_de_write(display, adpa_reg, 1039 adpa | ADPA_DAC_ENABLE | 1040 ADPA_HSYNC_CNTL_DISABLE | 1041 ADPA_VSYNC_CNTL_DISABLE); 1042 if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0) 1043 return; 1044 intel_de_write(display, adpa_reg, adpa); 1045 } 1046 1047 crt = kzalloc_obj(struct intel_crt); 1048 if (!crt) 1049 return; 1050 1051 connector = intel_connector_alloc(); 1052 if (!connector) { 1053 kfree(crt); 1054 return; 1055 } 1056 1057 ddc_pin = display->vbt.crt_ddc_pin; 1058 1059 drm_connector_init_with_ddc(display->drm, &connector->base, 1060 &intel_crt_connector_funcs, 1061 DRM_MODE_CONNECTOR_VGA, 1062 intel_gmbus_get_adapter(display, ddc_pin)); 1063 1064 drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs, 1065 DRM_MODE_ENCODER_DAC, "CRT"); 1066 1067 intel_connector_attach_encoder(connector, &crt->base); 1068 1069 crt->base.type = INTEL_OUTPUT_ANALOG; 1070 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); 1071 if (display->platform.i830) 1072 crt->base.pipe_mask = BIT(PIPE_A); 1073 else 1074 crt->base.pipe_mask = ~0; 1075 1076 if (DISPLAY_VER(display) != 2) 1077 connector->base.interlace_allowed = true; 1078 1079 crt->adpa_reg = adpa_reg; 1080 1081 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; 1082 1083 if (HAS_HOTPLUG(display) && 1084 !dmi_check_system(intel_spurious_crt_detect)) { 1085 crt->base.hpd_pin = HPD_CRT; 1086 crt->base.hotplug = intel_encoder_hotplug; 1087 connector->polled = DRM_CONNECTOR_POLL_HPD; 1088 } else { 1089 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1090 } 1091 connector->base.polled = connector->polled; 1092 1093 if (HAS_DDI(display)) { 1094 assert_port_valid(display, PORT_E); 1095 1096 crt->base.port = PORT_E; 1097 crt->base.get_config = hsw_crt_get_config; 1098 crt->base.get_hw_state = intel_ddi_get_hw_state; 1099 crt->base.compute_config = hsw_crt_compute_config; 1100 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; 1101 crt->base.pre_enable = hsw_pre_enable_crt; 1102 crt->base.enable = hsw_enable_crt; 1103 crt->base.disable = hsw_disable_crt; 1104 crt->base.post_disable = hsw_post_disable_crt; 1105 crt->base.enable_clock = hsw_ddi_enable_clock; 1106 crt->base.disable_clock = hsw_ddi_disable_clock; 1107 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; 1108 1109 intel_ddi_buf_trans_init(&crt->base); 1110 } else { 1111 if (HAS_PCH_SPLIT(display)) { 1112 crt->base.compute_config = pch_crt_compute_config; 1113 crt->base.disable = pch_disable_crt; 1114 crt->base.post_disable = pch_post_disable_crt; 1115 } else { 1116 crt->base.compute_config = intel_crt_compute_config; 1117 crt->base.disable = intel_disable_crt; 1118 } 1119 crt->base.port = PORT_NONE; 1120 crt->base.get_config = intel_crt_get_config; 1121 crt->base.get_hw_state = intel_crt_get_hw_state; 1122 crt->base.enable = intel_enable_crt; 1123 } 1124 connector->get_hw_state = intel_connector_get_hw_state; 1125 1126 drm_connector_helper_add(&connector->base, &intel_crt_connector_helper_funcs); 1127 1128 /* 1129 * TODO: find a proper way to discover whether we need to set the the 1130 * polarity and link reversal bits or not, instead of relying on the 1131 * BIOS. 1132 */ 1133 if (HAS_PCH_LPT(display)) { 1134 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 1135 FDI_RX_LINK_REVERSAL_OVERRIDE; 1136 1137 display->fdi.rx_config = intel_de_read(display, 1138 FDI_RX_CTL(PIPE_A)) & fdi_config; 1139 } 1140 1141 intel_crt_reset(&crt->base.base); 1142 } 1143