1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_COMBO_PHY_REGS__ 7 #define __INTEL_COMBO_PHY_REGS__ 8 9 #include "i915_reg_defs.h" 10 11 #define _ICL_COMBOPHY_A 0x162000 12 #define _ICL_COMBOPHY_B 0x6C000 13 #define _EHL_COMBOPHY_C 0x160000 14 #define _RKL_COMBOPHY_D 0x161000 15 #define _ADL_COMBOPHY_E 0x16B000 16 17 #define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \ 18 _ICL_COMBOPHY_B, \ 19 _EHL_COMBOPHY_C, \ 20 _RKL_COMBOPHY_D, \ 21 _ADL_COMBOPHY_E) 22 23 /* ICL Port CL_DW registers */ 24 #define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ 25 4 * (dw)) 26 27 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) 28 #define CL_POWER_DOWN_ENABLE REG_BIT(4) 29 #define SUS_CLOCK_CONFIG REG_GENMASK(1, 0) 30 31 #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy)) 32 #define PG_SEQ_DELAY_OVERRIDE_MASK REG_GENMASK(26, 25) 33 #define PG_SEQ_DELAY_OVERRIDE_ENABLE REG_BIT(24) 34 #define PWR_DOWN_LN_MASK REG_GENMASK(7, 4) 35 #define PWR_UP_ALL_LANES REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x0) 36 #define PWR_DOWN_LN_3_2_1 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xe) 37 #define PWR_DOWN_LN_3_2 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xc) 38 #define PWR_DOWN_LN_3 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x8) 39 #define PWR_DOWN_LN_2_1_0 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x7) 40 #define PWR_DOWN_LN_1_0 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0x3) 41 #define PWR_DOWN_LN_3_1 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xa) 42 #define PWR_DOWN_LN_3_1_0 REG_FIELD_PREP(PWR_DOWN_LN_MASK, 0xb) 43 #define EDP4K2K_MODE_OVRD_EN REG_BIT(3) 44 #define EDP4K2K_MODE_OVRD_OPTIMIZED REG_BIT(2) 45 46 #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy)) 47 #define ICL_LANE_ENABLE_AUX REG_BIT(0) 48 49 /* ICL Port COMP_DW registers */ 50 #define _ICL_PORT_COMP 0x100 51 #define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \ 52 _ICL_PORT_COMP + 4 * (dw)) 53 54 #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy)) 55 #define COMP_INIT REG_BIT(31) 56 57 #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy)) 58 59 #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy)) 60 #define PROCESS_INFO_MASK REG_GENMASK(28, 26) 61 #define PROCESS_INFO_DOT_0 REG_FIELD_PREP(PROCESS_INFO_MASK, 0) 62 #define PROCESS_INFO_DOT_1 REG_FIELD_PREP(PROCESS_INFO_MASK, 1) 63 #define PROCESS_INFO_DOT_4 REG_FIELD_PREP(PROCESS_INFO_MASK, 2) 64 #define VOLTAGE_INFO_MASK REG_GENMASK(25, 24) 65 #define VOLTAGE_INFO_0_85V REG_FIELD_PREP(VOLTAGE_INFO_MASK, 0) 66 #define VOLTAGE_INFO_0_95V REG_FIELD_PREP(VOLTAGE_INFO_MASK, 1) 67 #define VOLTAGE_INFO_1_05V REG_FIELD_PREP(VOLTAGE_INFO_MASK, 2) 68 69 #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy)) 70 #define IREFGEN REG_BIT(24) 71 72 #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy)) 73 74 #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy)) 75 76 /* ICL Port PCS registers */ 77 #define _ICL_PORT_PCS_AUX 0x300 78 #define _ICL_PORT_PCS_GRP 0x600 79 #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100) 80 #define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ 81 _ICL_PORT_PCS_AUX + 4 * (dw)) 82 #define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ 83 _ICL_PORT_PCS_GRP + 4 * (dw)) 84 #define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ 85 _ICL_PORT_PCS_LN(ln) + 4 * (dw)) 86 #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy)) 87 #define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy)) 88 #define ICL_PORT_PCS_DW1_LN(ln, phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, ln, phy)) 89 #define DCC_MODE_SELECT_MASK REG_GENMASK(21, 20) 90 #define RUN_DCC_ONCE REG_FIELD_PREP(DCC_MODE_SELECT_MASK, 0) 91 #define COMMON_KEEPER_EN REG_BIT(26) 92 #define LATENCY_OPTIM_MASK REG_GENMASK(3, 2) 93 #define LATENCY_OPTIM_VAL(x) REG_FIELD_PREP(LATENCY_OPTIM_MASK, (x)) 94 95 /* ICL Port TX registers */ 96 #define _ICL_PORT_TX_AUX 0x380 97 #define _ICL_PORT_TX_GRP 0x680 98 #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100) 99 100 #define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \ 101 _ICL_PORT_TX_AUX + 4 * (dw)) 102 #define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \ 103 _ICL_PORT_TX_GRP + 4 * (dw)) 104 #define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \ 105 _ICL_PORT_TX_LN(ln) + 4 * (dw)) 106 107 #define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy)) 108 #define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy)) 109 #define ICL_PORT_TX_DW2_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(2, ln, phy)) 110 #define SWING_SEL_UPPER_MASK REG_BIT(15) 111 #define SWING_SEL_UPPER(x) REG_FIELD_PREP(SWING_SEL_UPPER_MASK, (x) >> 3) 112 #define SWING_SEL_LOWER_MASK REG_GENMASK(13, 11) 113 #define SWING_SEL_LOWER(x) REG_FIELD_PREP(SWING_SEL_LOWER_MASK, (x) & 0x7) 114 #define FRC_LATENCY_OPTIM_MASK REG_GENMASK(10, 8) 115 #define FRC_LATENCY_OPTIM_VAL(x) REG_FIELD_PREP(FRC_LATENCY_OPTIM_MASK, (x)) 116 #define RCOMP_SCALAR_MASK REG_GENMASK(7, 0) 117 #define RCOMP_SCALAR(x) REG_FIELD_PREP(RCOMP_SCALAR_MASK, (x)) 118 119 #define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy)) 120 #define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy)) 121 #define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy)) 122 #define LOADGEN_SELECT REG_BIT(31) 123 #define POST_CURSOR_1_MASK REG_GENMASK(17, 12) 124 #define POST_CURSOR_1(x) REG_FIELD_PREP(POST_CURSOR_1_MASK, (x)) 125 #define POST_CURSOR_2_MASK REG_GENMASK(11, 6) 126 #define POST_CURSOR_2(x) REG_FIELD_PREP(POST_CURSOR_2_MASK, (x)) 127 #define CURSOR_COEFF_MASK REG_GENMASK(5, 0) 128 #define CURSOR_COEFF(x) REG_FIELD_PREP(CURSOR_COEFF_MASK, (x)) 129 130 #define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy)) 131 #define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy)) 132 #define ICL_PORT_TX_DW5_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(5, ln, phy)) 133 #define TX_TRAINING_EN REG_BIT(31) 134 #define TAP2_DISABLE REG_BIT(30) 135 #define TAP3_DISABLE REG_BIT(29) 136 #define SCALING_MODE_SEL_MASK REG_GENMASK(20, 18) 137 #define SCALING_MODE_SEL(x) REG_FIELD_PREP(SCALING_MODE_SEL_MASK, (x)) 138 #define RTERM_SELECT_MASK REG_GENMASK(5, 3) 139 #define RTERM_SELECT(x) REG_FIELD_PREP(RTERM_SELECT_MASK, (x)) 140 141 #define ICL_PORT_TX_DW6_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(6, phy)) 142 #define ICL_PORT_TX_DW6_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(6, phy)) 143 #define ICL_PORT_TX_DW6_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(6, ln, phy)) 144 #define O_FUNC_OVRD_EN REG_BIT(7) 145 #define O_LDO_REF_SEL_CRI REG_GENMASK(6, 1) 146 #define O_LDO_BYPASS_CRI REG_BIT(0) 147 148 #define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy)) 149 #define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy)) 150 #define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy)) 151 #define N_SCALAR_MASK REG_GENMASK(30, 24) 152 #define N_SCALAR(x) REG_FIELD_PREP(N_SCALAR_MASK, (x)) 153 154 #define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy)) 155 #define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy)) 156 #define ICL_PORT_TX_DW8_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(8, ln, phy)) 157 #define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31) 158 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29) 159 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1) 160 161 #define _ICL_DPHY_CHKN_REG 0x194 162 #define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG) 163 #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7) 164 165 #endif /* __INTEL_COMBO_PHY_REGS__ */ 166