1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2018 Intel Corporation 4 */ 5 6 #include "intel_combo_phy.h" 7 #include "intel_display_types.h" 8 9 #define for_each_combo_phy(__dev_priv, __phy) \ 10 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 11 for_each_if(intel_phy_is_combo(__dev_priv, __phy)) 12 13 #define for_each_combo_phy_reverse(__dev_priv, __phy) \ 14 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ 15 for_each_if(intel_phy_is_combo(__dev_priv, __phy)) 16 17 enum { 18 PROCMON_0_85V_DOT_0, 19 PROCMON_0_95V_DOT_0, 20 PROCMON_0_95V_DOT_1, 21 PROCMON_1_05V_DOT_0, 22 PROCMON_1_05V_DOT_1, 23 }; 24 25 static const struct cnl_procmon { 26 u32 dw1, dw9, dw10; 27 } cnl_procmon_values[] = { 28 [PROCMON_0_85V_DOT_0] = 29 { .dw1 = 0x00000000, .dw9 = 0x62AB67BB, .dw10 = 0x51914F96, }, 30 [PROCMON_0_95V_DOT_0] = 31 { .dw1 = 0x00000000, .dw9 = 0x86E172C7, .dw10 = 0x77CA5EAB, }, 32 [PROCMON_0_95V_DOT_1] = 33 { .dw1 = 0x00000000, .dw9 = 0x93F87FE1, .dw10 = 0x8AE871C5, }, 34 [PROCMON_1_05V_DOT_0] = 35 { .dw1 = 0x00000000, .dw9 = 0x98FA82DD, .dw10 = 0x89E46DC1, }, 36 [PROCMON_1_05V_DOT_1] = 37 { .dw1 = 0x00440000, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, }, 38 }; 39 40 /* 41 * CNL has just one set of registers, while gen11 has a set for each combo PHY. 42 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we 43 * call the ICL macros even though the function has CNL on its name. 44 */ 45 static const struct cnl_procmon * 46 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) 47 { 48 const struct cnl_procmon *procmon; 49 u32 val; 50 51 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); 52 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { 53 default: 54 MISSING_CASE(val); 55 /* fall through */ 56 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0: 57 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0]; 58 break; 59 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_0: 60 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_0]; 61 break; 62 case VOLTAGE_INFO_0_95V | PROCESS_INFO_DOT_1: 63 procmon = &cnl_procmon_values[PROCMON_0_95V_DOT_1]; 64 break; 65 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_0: 66 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_0]; 67 break; 68 case VOLTAGE_INFO_1_05V | PROCESS_INFO_DOT_1: 69 procmon = &cnl_procmon_values[PROCMON_1_05V_DOT_1]; 70 break; 71 } 72 73 return procmon; 74 } 75 76 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, 77 enum phy phy) 78 { 79 const struct cnl_procmon *procmon; 80 u32 val; 81 82 procmon = cnl_get_procmon_ref_values(dev_priv, phy); 83 84 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); 85 val &= ~((0xff << 16) | 0xff); 86 val |= procmon->dw1; 87 intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); 88 89 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); 90 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); 91 } 92 93 static bool check_phy_reg(struct drm_i915_private *dev_priv, 94 enum phy phy, i915_reg_t reg, u32 mask, 95 u32 expected_val) 96 { 97 u32 val = intel_de_read(dev_priv, reg); 98 99 if ((val & mask) != expected_val) { 100 drm_dbg(&dev_priv->drm, 101 "Combo PHY %c reg %08x state mismatch: " 102 "current %08x mask %08x expected %08x\n", 103 phy_name(phy), 104 reg.reg, val, mask, expected_val); 105 return false; 106 } 107 108 return true; 109 } 110 111 static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, 112 enum phy phy) 113 { 114 const struct cnl_procmon *procmon; 115 bool ret; 116 117 procmon = cnl_get_procmon_ref_values(dev_priv, phy); 118 119 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), 120 (0xff << 16) | 0xff, procmon->dw1); 121 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), 122 -1U, procmon->dw9); 123 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), 124 -1U, procmon->dw10); 125 126 return ret; 127 } 128 129 static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) 130 { 131 return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && 132 (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT); 133 } 134 135 static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) 136 { 137 enum phy phy = PHY_A; 138 bool ret; 139 140 if (!cnl_combo_phy_enabled(dev_priv)) 141 return false; 142 143 ret = cnl_verify_procmon_ref_values(dev_priv, phy); 144 145 ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5, 146 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); 147 148 return ret; 149 } 150 151 static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) 152 { 153 u32 val; 154 155 val = intel_de_read(dev_priv, CHICKEN_MISC_2); 156 val &= ~CNL_COMP_PWR_DOWN; 157 intel_de_write(dev_priv, CHICKEN_MISC_2, val); 158 159 /* Dummy PORT_A to get the correct CNL register from the ICL macro */ 160 cnl_set_procmon_ref_values(dev_priv, PHY_A); 161 162 val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0); 163 val |= COMP_INIT; 164 intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val); 165 166 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); 167 val |= CL_POWER_DOWN_ENABLE; 168 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); 169 } 170 171 static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) 172 { 173 u32 val; 174 175 if (!cnl_combo_phy_verify_state(dev_priv)) 176 drm_warn(&dev_priv->drm, 177 "Combo PHY HW state changed unexpectedly.\n"); 178 179 val = intel_de_read(dev_priv, CHICKEN_MISC_2); 180 val |= CNL_COMP_PWR_DOWN; 181 intel_de_write(dev_priv, CHICKEN_MISC_2, val); 182 } 183 184 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, 185 enum phy phy) 186 { 187 /* The PHY C added by EHL has no PHY_MISC register */ 188 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) 189 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; 190 else 191 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & 192 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && 193 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); 194 } 195 196 static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) 197 { 198 bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A); 199 bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D); 200 bool dsi_present = intel_bios_is_dsi_present(i915, NULL); 201 202 /* 203 * VBT's 'dvo port' field for child devices references the DDI, not 204 * the PHY. So if combo PHY A is wired up to drive an external 205 * display, we should see a child device present on PORT_D and 206 * nothing on PORT_A and no DSI. 207 */ 208 if (ddi_d_present && !ddi_a_present && !dsi_present) 209 return true; 210 211 /* 212 * If we encounter a VBT that claims to have an external display on 213 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message 214 * in the log and let the internal display win. 215 */ 216 if (ddi_d_present) 217 drm_err(&i915->drm, 218 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); 219 220 return false; 221 } 222 223 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, 224 enum phy phy) 225 { 226 bool ret; 227 u32 expected_val = 0; 228 229 if (!icl_combo_phy_enabled(dev_priv, phy)) 230 return false; 231 232 ret = cnl_verify_procmon_ref_values(dev_priv, phy); 233 234 if (phy == PHY_A) { 235 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), 236 IREFGEN, IREFGEN); 237 238 if (IS_ELKHARTLAKE(dev_priv)) { 239 if (ehl_vbt_ddi_d_present(dev_priv)) 240 expected_val = ICL_PHY_MISC_MUX_DDID; 241 242 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), 243 ICL_PHY_MISC_MUX_DDID, 244 expected_val); 245 } 246 } 247 248 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), 249 CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); 250 251 return ret; 252 } 253 254 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, 255 enum phy phy, bool is_dsi, 256 int lane_count, bool lane_reversal) 257 { 258 u8 lane_mask; 259 u32 val; 260 261 if (is_dsi) { 262 drm_WARN_ON(&dev_priv->drm, lane_reversal); 263 264 switch (lane_count) { 265 case 1: 266 lane_mask = PWR_DOWN_LN_3_1_0; 267 break; 268 case 2: 269 lane_mask = PWR_DOWN_LN_3_1; 270 break; 271 case 3: 272 lane_mask = PWR_DOWN_LN_3; 273 break; 274 default: 275 MISSING_CASE(lane_count); 276 /* fall-through */ 277 case 4: 278 lane_mask = PWR_UP_ALL_LANES; 279 break; 280 } 281 } else { 282 switch (lane_count) { 283 case 1: 284 lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 : 285 PWR_DOWN_LN_3_2_1; 286 break; 287 case 2: 288 lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 : 289 PWR_DOWN_LN_3_2; 290 break; 291 default: 292 MISSING_CASE(lane_count); 293 /* fall-through */ 294 case 4: 295 lane_mask = PWR_UP_ALL_LANES; 296 break; 297 } 298 } 299 300 val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); 301 val &= ~PWR_DOWN_LN_MASK; 302 val |= lane_mask << PWR_DOWN_LN_SHIFT; 303 intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); 304 } 305 306 static void icl_combo_phys_init(struct drm_i915_private *dev_priv) 307 { 308 enum phy phy; 309 310 for_each_combo_phy(dev_priv, phy) { 311 u32 val; 312 313 if (icl_combo_phy_verify_state(dev_priv, phy)) { 314 drm_dbg(&dev_priv->drm, 315 "Combo PHY %c already enabled, won't reprogram it.\n", 316 phy_name(phy)); 317 continue; 318 } 319 320 /* 321 * Although EHL adds a combo PHY C, there's no PHY_MISC 322 * register for it and no need to program the 323 * DE_IO_COMP_PWR_DOWN setting on PHY C. 324 */ 325 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) 326 goto skip_phy_misc; 327 328 /* 329 * EHL's combo PHY A can be hooked up to either an external 330 * display (via DDI-D) or an internal display (via DDI-A or 331 * the DSI DPHY). This is a motherboard design decision that 332 * can't be changed on the fly, so initialize the PHY's mux 333 * based on whether our VBT indicates the presence of any 334 * "internal" child devices. 335 */ 336 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); 337 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) { 338 val &= ~ICL_PHY_MISC_MUX_DDID; 339 340 if (ehl_vbt_ddi_d_present(dev_priv)) 341 val |= ICL_PHY_MISC_MUX_DDID; 342 } 343 344 val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 345 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); 346 347 skip_phy_misc: 348 cnl_set_procmon_ref_values(dev_priv, phy); 349 350 if (phy == PHY_A) { 351 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); 352 val |= IREFGEN; 353 intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); 354 } 355 356 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); 357 val |= COMP_INIT; 358 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); 359 360 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 361 val |= CL_POWER_DOWN_ENABLE; 362 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); 363 } 364 } 365 366 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) 367 { 368 enum phy phy; 369 370 for_each_combo_phy_reverse(dev_priv, phy) { 371 u32 val; 372 373 if (phy == PHY_A && 374 !icl_combo_phy_verify_state(dev_priv, phy)) 375 drm_warn(&dev_priv->drm, 376 "Combo PHY %c HW state changed unexpectedly\n", 377 phy_name(phy)); 378 379 /* 380 * Although EHL adds a combo PHY C, there's no PHY_MISC 381 * register for it and no need to program the 382 * DE_IO_COMP_PWR_DOWN setting on PHY C. 383 */ 384 if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) 385 goto skip_phy_misc; 386 387 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); 388 val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; 389 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); 390 391 skip_phy_misc: 392 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); 393 val &= ~COMP_INIT; 394 intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); 395 } 396 } 397 398 void intel_combo_phy_init(struct drm_i915_private *i915) 399 { 400 if (INTEL_GEN(i915) >= 11) 401 icl_combo_phys_init(i915); 402 else if (IS_CANNONLAKE(i915)) 403 cnl_combo_phys_init(i915); 404 } 405 406 void intel_combo_phy_uninit(struct drm_i915_private *i915) 407 { 408 if (INTEL_GEN(i915) >= 11) 409 icl_combo_phys_uninit(i915); 410 else if (IS_CANNONLAKE(i915)) 411 cnl_combo_phys_uninit(i915); 412 } 413