1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2025 Intel Corporation 4 */ 5 6 #ifndef __INTEL_CMTG_REGS_H__ 7 #define __INTEL_CMTG_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 #define CMTG_CLK_SEL _MMIO(0x46160) 12 #define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29) 13 #define CMTG_CLK_SELECT_PHYA_ENABLE REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4) 14 #define CMTG_CLK_SEL_A_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0) 15 #define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13) 16 #define CMTG_CLK_SELECT_PHYB_ENABLE REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6) 17 #define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0) 18 19 #define _TRANS_CMTG_CTL_A 0x6fa88 20 #define _TRANS_CMTG_CTL_B 0x6fb88 21 #define TRANS_CMTG_CTL(trans) _MMIO_TRANS((trans), \ 22 _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B) 23 #define CMTG_ENABLE REG_BIT(31) 24 #define CMTG_SYNC_TO_PORT REG_BIT(29) 25 #define CMTG_STATE REG_BIT(23) 26 27 #define _CMTG_HW_GB_A 0x6fa8c 28 #define _CMTG_HW_GB_B 0x6fb8c 29 #define CMTG_HW_GB(trans) _MMIO_TRANS((trans), \ 30 _CMTG_HW_GB_A, _CMTG_HW_GB_B) 31 #define CMTG_HW_GB_BREAKEVEN_MASK REG_GENMASK(11, 0) 32 #define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK REG_GENMASK(27, 16) 33 #define CMTG_HW_GB_UP_LW_BG_DIFF_MASK REG_GENMASK(31, 28) 34 35 #define _CMTG_SCANLINE_GB1_A 0x456A0 36 #define _CMTG_SCANLINE_GB1_B 0x456C0 37 #define CMTG_SCANLINE_GB1(trans) _MMIO_TRANS((trans), \ 38 _CMTG_SCANLINE_GB1_A, _CMTG_SCANLINE_GB1_B) 39 #define CMTG_HW_GB_ENABLE REG_BIT(31) 40 41 #endif /* __INTEL_CMTG_REGS_H__ */ 42