1*f14d81b7SGustavo Sousa /* SPDX-License-Identifier: MIT */ 2*f14d81b7SGustavo Sousa /* 3*f14d81b7SGustavo Sousa * Copyright (C) 2025 Intel Corporation 4*f14d81b7SGustavo Sousa */ 5*f14d81b7SGustavo Sousa 6*f14d81b7SGustavo Sousa #ifndef __INTEL_CMTG_REGS_H__ 7*f14d81b7SGustavo Sousa #define __INTEL_CMTG_REGS_H__ 8*f14d81b7SGustavo Sousa 9*f14d81b7SGustavo Sousa #include "i915_reg_defs.h" 10*f14d81b7SGustavo Sousa 11*f14d81b7SGustavo Sousa #define CMTG_CLK_SEL _MMIO(0x46160) 12*f14d81b7SGustavo Sousa #define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29) 13*f14d81b7SGustavo Sousa #define CMTG_CLK_SEL_A_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0) 14*f14d81b7SGustavo Sousa #define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13) 15*f14d81b7SGustavo Sousa #define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0) 16*f14d81b7SGustavo Sousa 17*f14d81b7SGustavo Sousa #define TRANS_CMTG_CTL_A _MMIO(0x6fa88) 18*f14d81b7SGustavo Sousa #define TRANS_CMTG_CTL_B _MMIO(0x6fb88) 19*f14d81b7SGustavo Sousa #define CMTG_ENABLE REG_BIT(31) 20*f14d81b7SGustavo Sousa 21*f14d81b7SGustavo Sousa #endif /* __INTEL_CMTG_REGS_H__ */ 22