1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/time.h> 26 27 #include <drm/drm_fixed.h> 28 29 #include "soc/intel_dram.h" 30 31 #include "hsw_ips.h" 32 #include "i915_drv.h" 33 #include "i915_reg.h" 34 #include "intel_atomic.h" 35 #include "intel_atomic_plane.h" 36 #include "intel_audio.h" 37 #include "intel_bw.h" 38 #include "intel_cdclk.h" 39 #include "intel_crtc.h" 40 #include "intel_de.h" 41 #include "intel_display_regs.h" 42 #include "intel_display_types.h" 43 #include "intel_mchbar_regs.h" 44 #include "intel_pci_config.h" 45 #include "intel_pcode.h" 46 #include "intel_psr.h" 47 #include "intel_vdsc.h" 48 #include "skl_watermark.h" 49 #include "skl_watermark_regs.h" 50 #include "vlv_dsi.h" 51 #include "vlv_sideband.h" 52 53 /** 54 * DOC: CDCLK / RAWCLK 55 * 56 * The display engine uses several different clocks to do its work. There 57 * are two main clocks involved that aren't directly related to the actual 58 * pixel clock or any symbol/bit clock of the actual output port. These 59 * are the core display clock (CDCLK) and RAWCLK. 60 * 61 * CDCLK clocks most of the display pipe logic, and thus its frequency 62 * must be high enough to support the rate at which pixels are flowing 63 * through the pipes. Downscaling must also be accounted as that increases 64 * the effective pixel rate. 65 * 66 * On several platforms the CDCLK frequency can be changed dynamically 67 * to minimize power consumption for a given display configuration. 68 * Typically changes to the CDCLK frequency require all the display pipes 69 * to be shut down while the frequency is being changed. 70 * 71 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 72 * DMC will not change the active CDCLK frequency however, so that part 73 * will still be performed by the driver directly. 74 * 75 * There are multiple components involved in the generation of the CDCLK 76 * frequency: 77 * 78 * - We have the CDCLK PLL, which generates an output clock based on a 79 * reference clock and a ratio parameter. 80 * - The CD2X Divider, which divides the output of the PLL based on a 81 * divisor selected from a set of pre-defined choices. 82 * - The CD2X Squasher, which further divides the output based on a 83 * waveform represented as a sequence of bits where each zero 84 * "squashes out" a clock cycle. 85 * - And, finally, a fixed divider that divides the output frequency by 2. 86 * 87 * As such, the resulting CDCLK frequency can be calculated with the 88 * following formula: 89 * 90 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 91 * 92 * , where vco is the frequency generated by the PLL; cd2x_div 93 * represents the CD2X Divider; sq_len and sq_div are the bit length 94 * and the number of high bits for the CD2X Squasher waveform, respectively; 95 * and 2 represents the fixed divider. 96 * 97 * Note that some older platforms do not contain the CD2X Divider 98 * and/or CD2X Squasher, in which case we can ignore their respective 99 * factors in the formula above. 100 * 101 * Several methods exist to change the CDCLK frequency, which ones are 102 * supported depends on the platform: 103 * 104 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 105 * - CD2X divider update. Single pipe can be active as the divider update 106 * can be synchronized with the pipe's start of vblank. 107 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 108 * - Squash waveform update. Pipes can be active. 109 * - Crawl and squash can also be done back to back. Pipes can be active. 110 * 111 * RAWCLK is a fixed frequency clock, often used by various auxiliary 112 * blocks such as AUX CH or backlight PWM. Hence the only thing we 113 * really need to know about RAWCLK is its frequency so that various 114 * dividers can be programmed correctly. 115 */ 116 117 struct intel_cdclk_funcs { 118 void (*get_cdclk)(struct intel_display *display, 119 struct intel_cdclk_config *cdclk_config); 120 void (*set_cdclk)(struct intel_display *display, 121 const struct intel_cdclk_config *cdclk_config, 122 enum pipe pipe); 123 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 124 u8 (*calc_voltage_level)(int cdclk); 125 }; 126 127 void intel_cdclk_get_cdclk(struct intel_display *display, 128 struct intel_cdclk_config *cdclk_config) 129 { 130 display->funcs.cdclk->get_cdclk(display, cdclk_config); 131 } 132 133 static void intel_cdclk_set_cdclk(struct intel_display *display, 134 const struct intel_cdclk_config *cdclk_config, 135 enum pipe pipe) 136 { 137 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); 138 } 139 140 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 141 { 142 struct intel_display *display = to_intel_display(state); 143 144 return display->funcs.cdclk->modeset_calc_cdclk(state); 145 } 146 147 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, 148 int cdclk) 149 { 150 return display->funcs.cdclk->calc_voltage_level(cdclk); 151 } 152 153 static void fixed_133mhz_get_cdclk(struct intel_display *display, 154 struct intel_cdclk_config *cdclk_config) 155 { 156 cdclk_config->cdclk = 133333; 157 } 158 159 static void fixed_200mhz_get_cdclk(struct intel_display *display, 160 struct intel_cdclk_config *cdclk_config) 161 { 162 cdclk_config->cdclk = 200000; 163 } 164 165 static void fixed_266mhz_get_cdclk(struct intel_display *display, 166 struct intel_cdclk_config *cdclk_config) 167 { 168 cdclk_config->cdclk = 266667; 169 } 170 171 static void fixed_333mhz_get_cdclk(struct intel_display *display, 172 struct intel_cdclk_config *cdclk_config) 173 { 174 cdclk_config->cdclk = 333333; 175 } 176 177 static void fixed_400mhz_get_cdclk(struct intel_display *display, 178 struct intel_cdclk_config *cdclk_config) 179 { 180 cdclk_config->cdclk = 400000; 181 } 182 183 static void fixed_450mhz_get_cdclk(struct intel_display *display, 184 struct intel_cdclk_config *cdclk_config) 185 { 186 cdclk_config->cdclk = 450000; 187 } 188 189 static void i85x_get_cdclk(struct intel_display *display, 190 struct intel_cdclk_config *cdclk_config) 191 { 192 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 193 u16 hpllcc = 0; 194 195 /* 196 * 852GM/852GMV only supports 133 MHz and the HPLLCC 197 * encoding is different :( 198 * FIXME is this the right way to detect 852GM/852GMV? 199 */ 200 if (pdev->revision == 0x1) { 201 cdclk_config->cdclk = 133333; 202 return; 203 } 204 205 pci_bus_read_config_word(pdev->bus, 206 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 207 208 /* Assume that the hardware is in the high speed state. This 209 * should be the default. 210 */ 211 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 212 case GC_CLOCK_133_200: 213 case GC_CLOCK_133_200_2: 214 case GC_CLOCK_100_200: 215 cdclk_config->cdclk = 200000; 216 break; 217 case GC_CLOCK_166_250: 218 cdclk_config->cdclk = 250000; 219 break; 220 case GC_CLOCK_100_133: 221 cdclk_config->cdclk = 133333; 222 break; 223 case GC_CLOCK_133_266: 224 case GC_CLOCK_133_266_2: 225 case GC_CLOCK_166_266: 226 cdclk_config->cdclk = 266667; 227 break; 228 } 229 } 230 231 static void i915gm_get_cdclk(struct intel_display *display, 232 struct intel_cdclk_config *cdclk_config) 233 { 234 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 235 u16 gcfgc = 0; 236 237 pci_read_config_word(pdev, GCFGC, &gcfgc); 238 239 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 240 cdclk_config->cdclk = 133333; 241 return; 242 } 243 244 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 245 case GC_DISPLAY_CLOCK_333_320_MHZ: 246 cdclk_config->cdclk = 333333; 247 break; 248 default: 249 case GC_DISPLAY_CLOCK_190_200_MHZ: 250 cdclk_config->cdclk = 190000; 251 break; 252 } 253 } 254 255 static void i945gm_get_cdclk(struct intel_display *display, 256 struct intel_cdclk_config *cdclk_config) 257 { 258 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 259 u16 gcfgc = 0; 260 261 pci_read_config_word(pdev, GCFGC, &gcfgc); 262 263 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 264 cdclk_config->cdclk = 133333; 265 return; 266 } 267 268 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 269 case GC_DISPLAY_CLOCK_333_320_MHZ: 270 cdclk_config->cdclk = 320000; 271 break; 272 default: 273 case GC_DISPLAY_CLOCK_190_200_MHZ: 274 cdclk_config->cdclk = 200000; 275 break; 276 } 277 } 278 279 static unsigned int intel_hpll_vco(struct intel_display *display) 280 { 281 static const unsigned int blb_vco[8] = { 282 [0] = 3200000, 283 [1] = 4000000, 284 [2] = 5333333, 285 [3] = 4800000, 286 [4] = 6400000, 287 }; 288 static const unsigned int pnv_vco[8] = { 289 [0] = 3200000, 290 [1] = 4000000, 291 [2] = 5333333, 292 [3] = 4800000, 293 [4] = 2666667, 294 }; 295 static const unsigned int cl_vco[8] = { 296 [0] = 3200000, 297 [1] = 4000000, 298 [2] = 5333333, 299 [3] = 6400000, 300 [4] = 3333333, 301 [5] = 3566667, 302 [6] = 4266667, 303 }; 304 static const unsigned int elk_vco[8] = { 305 [0] = 3200000, 306 [1] = 4000000, 307 [2] = 5333333, 308 [3] = 4800000, 309 }; 310 static const unsigned int ctg_vco[8] = { 311 [0] = 3200000, 312 [1] = 4000000, 313 [2] = 5333333, 314 [3] = 6400000, 315 [4] = 2666667, 316 [5] = 4266667, 317 }; 318 const unsigned int *vco_table; 319 unsigned int vco; 320 u8 tmp = 0; 321 322 /* FIXME other chipsets? */ 323 if (display->platform.gm45) 324 vco_table = ctg_vco; 325 else if (display->platform.g45) 326 vco_table = elk_vco; 327 else if (display->platform.i965gm) 328 vco_table = cl_vco; 329 else if (display->platform.pineview) 330 vco_table = pnv_vco; 331 else if (display->platform.g33) 332 vco_table = blb_vco; 333 else 334 return 0; 335 336 tmp = intel_de_read(display, display->platform.pineview || 337 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); 338 339 vco = vco_table[tmp & 0x7]; 340 if (vco == 0) 341 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 342 tmp); 343 else 344 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); 345 346 return vco; 347 } 348 349 static void g33_get_cdclk(struct intel_display *display, 350 struct intel_cdclk_config *cdclk_config) 351 { 352 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 353 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 354 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 355 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 356 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 357 const u8 *div_table; 358 unsigned int cdclk_sel; 359 u16 tmp = 0; 360 361 cdclk_config->vco = intel_hpll_vco(display); 362 363 pci_read_config_word(pdev, GCFGC, &tmp); 364 365 cdclk_sel = (tmp >> 4) & 0x7; 366 367 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 368 goto fail; 369 370 switch (cdclk_config->vco) { 371 case 3200000: 372 div_table = div_3200; 373 break; 374 case 4000000: 375 div_table = div_4000; 376 break; 377 case 4800000: 378 div_table = div_4800; 379 break; 380 case 5333333: 381 div_table = div_5333; 382 break; 383 default: 384 goto fail; 385 } 386 387 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 388 div_table[cdclk_sel]); 389 return; 390 391 fail: 392 drm_err(display->drm, 393 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 394 cdclk_config->vco, tmp); 395 cdclk_config->cdclk = 190476; 396 } 397 398 static void pnv_get_cdclk(struct intel_display *display, 399 struct intel_cdclk_config *cdclk_config) 400 { 401 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 402 u16 gcfgc = 0; 403 404 pci_read_config_word(pdev, GCFGC, &gcfgc); 405 406 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 407 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 408 cdclk_config->cdclk = 266667; 409 break; 410 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 411 cdclk_config->cdclk = 333333; 412 break; 413 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 414 cdclk_config->cdclk = 444444; 415 break; 416 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 417 cdclk_config->cdclk = 200000; 418 break; 419 default: 420 drm_err(display->drm, 421 "Unknown pnv display core clock 0x%04x\n", gcfgc); 422 fallthrough; 423 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 424 cdclk_config->cdclk = 133333; 425 break; 426 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 427 cdclk_config->cdclk = 166667; 428 break; 429 } 430 } 431 432 static void i965gm_get_cdclk(struct intel_display *display, 433 struct intel_cdclk_config *cdclk_config) 434 { 435 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 436 static const u8 div_3200[] = { 16, 10, 8 }; 437 static const u8 div_4000[] = { 20, 12, 10 }; 438 static const u8 div_5333[] = { 24, 16, 14 }; 439 const u8 *div_table; 440 unsigned int cdclk_sel; 441 u16 tmp = 0; 442 443 cdclk_config->vco = intel_hpll_vco(display); 444 445 pci_read_config_word(pdev, GCFGC, &tmp); 446 447 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 448 449 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 450 goto fail; 451 452 switch (cdclk_config->vco) { 453 case 3200000: 454 div_table = div_3200; 455 break; 456 case 4000000: 457 div_table = div_4000; 458 break; 459 case 5333333: 460 div_table = div_5333; 461 break; 462 default: 463 goto fail; 464 } 465 466 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 467 div_table[cdclk_sel]); 468 return; 469 470 fail: 471 drm_err(display->drm, 472 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 473 cdclk_config->vco, tmp); 474 cdclk_config->cdclk = 200000; 475 } 476 477 static void gm45_get_cdclk(struct intel_display *display, 478 struct intel_cdclk_config *cdclk_config) 479 { 480 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 481 unsigned int cdclk_sel; 482 u16 tmp = 0; 483 484 cdclk_config->vco = intel_hpll_vco(display); 485 486 pci_read_config_word(pdev, GCFGC, &tmp); 487 488 cdclk_sel = (tmp >> 12) & 0x1; 489 490 switch (cdclk_config->vco) { 491 case 2666667: 492 case 4000000: 493 case 5333333: 494 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 495 break; 496 case 3200000: 497 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 498 break; 499 default: 500 drm_err(display->drm, 501 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 502 cdclk_config->vco, tmp); 503 cdclk_config->cdclk = 222222; 504 break; 505 } 506 } 507 508 static void hsw_get_cdclk(struct intel_display *display, 509 struct intel_cdclk_config *cdclk_config) 510 { 511 u32 lcpll = intel_de_read(display, LCPLL_CTL); 512 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 513 514 if (lcpll & LCPLL_CD_SOURCE_FCLK) 515 cdclk_config->cdclk = 800000; 516 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 517 cdclk_config->cdclk = 450000; 518 else if (freq == LCPLL_CLK_FREQ_450) 519 cdclk_config->cdclk = 450000; 520 else if (display->platform.haswell_ult) 521 cdclk_config->cdclk = 337500; 522 else 523 cdclk_config->cdclk = 540000; 524 } 525 526 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) 527 { 528 struct drm_i915_private *dev_priv = to_i915(display->drm); 529 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 530 333333 : 320000; 531 532 /* 533 * We seem to get an unstable or solid color picture at 200MHz. 534 * Not sure what's wrong. For now use 200MHz only when all pipes 535 * are off. 536 */ 537 if (display->platform.valleyview && min_cdclk > freq_320) 538 return 400000; 539 else if (min_cdclk > 266667) 540 return freq_320; 541 else if (min_cdclk > 0) 542 return 266667; 543 else 544 return 200000; 545 } 546 547 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 548 { 549 struct drm_i915_private *dev_priv = to_i915(display->drm); 550 551 if (display->platform.valleyview) { 552 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 553 return 2; 554 else if (cdclk >= 266667) 555 return 1; 556 else 557 return 0; 558 } else { 559 /* 560 * Specs are full of misinformation, but testing on actual 561 * hardware has shown that we just need to write the desired 562 * CCK divider into the Punit register. 563 */ 564 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 565 } 566 } 567 568 static void vlv_get_cdclk(struct intel_display *display, 569 struct intel_cdclk_config *cdclk_config) 570 { 571 u32 val; 572 573 vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 574 575 cdclk_config->vco = vlv_get_hpll_vco(display->drm); 576 cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk", 577 CCK_DISPLAY_CLOCK_CONTROL, 578 cdclk_config->vco); 579 580 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 581 582 vlv_iosf_sb_put(display->drm, 583 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 584 585 if (display->platform.valleyview) 586 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 587 DSPFREQGUAR_SHIFT; 588 else 589 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 590 DSPFREQGUAR_SHIFT_CHV; 591 } 592 593 static void vlv_program_pfi_credits(struct intel_display *display) 594 { 595 struct drm_i915_private *dev_priv = to_i915(display->drm); 596 unsigned int credits, default_credits; 597 598 if (display->platform.cherryview) 599 default_credits = PFI_CREDIT(12); 600 else 601 default_credits = PFI_CREDIT(8); 602 603 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 604 /* CHV suggested value is 31 or 63 */ 605 if (display->platform.cherryview) 606 credits = PFI_CREDIT_63; 607 else 608 credits = PFI_CREDIT(15); 609 } else { 610 credits = default_credits; 611 } 612 613 /* 614 * WA - write default credits before re-programming 615 * FIXME: should we also set the resend bit here? 616 */ 617 intel_de_write(display, GCI_CONTROL, 618 VGA_FAST_MODE_DISABLE | default_credits); 619 620 intel_de_write(display, GCI_CONTROL, 621 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 622 623 /* 624 * FIXME is this guaranteed to clear 625 * immediately or should we poll for it? 626 */ 627 drm_WARN_ON(display->drm, 628 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); 629 } 630 631 static void vlv_set_cdclk(struct intel_display *display, 632 const struct intel_cdclk_config *cdclk_config, 633 enum pipe pipe) 634 { 635 struct drm_i915_private *dev_priv = to_i915(display->drm); 636 int cdclk = cdclk_config->cdclk; 637 u32 val, cmd = cdclk_config->voltage_level; 638 intel_wakeref_t wakeref; 639 640 switch (cdclk) { 641 case 400000: 642 case 333333: 643 case 320000: 644 case 266667: 645 case 200000: 646 break; 647 default: 648 MISSING_CASE(cdclk); 649 return; 650 } 651 652 /* There are cases where we can end up here with power domains 653 * off and a CDCLK frequency other than the minimum, like when 654 * issuing a modeset without actually changing any display after 655 * a system suspend. So grab the display core domain, which covers 656 * the HW blocks needed for the following programming. 657 */ 658 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 659 660 vlv_iosf_sb_get(display->drm, 661 BIT(VLV_IOSF_SB_CCK) | 662 BIT(VLV_IOSF_SB_BUNIT) | 663 BIT(VLV_IOSF_SB_PUNIT)); 664 665 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 666 val &= ~DSPFREQGUAR_MASK; 667 val |= (cmd << DSPFREQGUAR_SHIFT); 668 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); 669 if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & 670 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 671 50)) { 672 drm_err(display->drm, 673 "timed out waiting for CDclk change\n"); 674 } 675 676 if (cdclk == 400000) { 677 u32 divider; 678 679 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 680 cdclk) - 1; 681 682 /* adjust cdclk divider */ 683 val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL); 684 val &= ~CCK_FREQUENCY_VALUES; 685 val |= divider; 686 vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val); 687 688 if (wait_for((vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL) & 689 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 690 50)) 691 drm_err(display->drm, 692 "timed out waiting for CDclk change\n"); 693 } 694 695 /* adjust self-refresh exit latency value */ 696 val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC); 697 val &= ~0x7f; 698 699 /* 700 * For high bandwidth configs, we set a higher latency in the bunit 701 * so that the core display fetch happens in time to avoid underruns. 702 */ 703 if (cdclk == 400000) 704 val |= 4500 / 250; /* 4.5 usec */ 705 else 706 val |= 3000 / 250; /* 3.0 usec */ 707 vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val); 708 709 vlv_iosf_sb_put(display->drm, 710 BIT(VLV_IOSF_SB_CCK) | 711 BIT(VLV_IOSF_SB_BUNIT) | 712 BIT(VLV_IOSF_SB_PUNIT)); 713 714 intel_update_cdclk(display); 715 716 vlv_program_pfi_credits(display); 717 718 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 719 } 720 721 static void chv_set_cdclk(struct intel_display *display, 722 const struct intel_cdclk_config *cdclk_config, 723 enum pipe pipe) 724 { 725 int cdclk = cdclk_config->cdclk; 726 u32 val, cmd = cdclk_config->voltage_level; 727 intel_wakeref_t wakeref; 728 729 switch (cdclk) { 730 case 333333: 731 case 320000: 732 case 266667: 733 case 200000: 734 break; 735 default: 736 MISSING_CASE(cdclk); 737 return; 738 } 739 740 /* There are cases where we can end up here with power domains 741 * off and a CDCLK frequency other than the minimum, like when 742 * issuing a modeset without actually changing any display after 743 * a system suspend. So grab the display core domain, which covers 744 * the HW blocks needed for the following programming. 745 */ 746 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 747 748 vlv_punit_get(display->drm); 749 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 750 val &= ~DSPFREQGUAR_MASK_CHV; 751 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 752 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); 753 if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & 754 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 755 50)) { 756 drm_err(display->drm, 757 "timed out waiting for CDclk change\n"); 758 } 759 760 vlv_punit_put(display->drm); 761 762 intel_update_cdclk(display); 763 764 vlv_program_pfi_credits(display); 765 766 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 767 } 768 769 static int bdw_calc_cdclk(int min_cdclk) 770 { 771 if (min_cdclk > 540000) 772 return 675000; 773 else if (min_cdclk > 450000) 774 return 540000; 775 else if (min_cdclk > 337500) 776 return 450000; 777 else 778 return 337500; 779 } 780 781 static u8 bdw_calc_voltage_level(int cdclk) 782 { 783 switch (cdclk) { 784 default: 785 case 337500: 786 return 2; 787 case 450000: 788 return 0; 789 case 540000: 790 return 1; 791 case 675000: 792 return 3; 793 } 794 } 795 796 static void bdw_get_cdclk(struct intel_display *display, 797 struct intel_cdclk_config *cdclk_config) 798 { 799 u32 lcpll = intel_de_read(display, LCPLL_CTL); 800 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 801 802 if (lcpll & LCPLL_CD_SOURCE_FCLK) 803 cdclk_config->cdclk = 800000; 804 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 805 cdclk_config->cdclk = 450000; 806 else if (freq == LCPLL_CLK_FREQ_450) 807 cdclk_config->cdclk = 450000; 808 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 809 cdclk_config->cdclk = 540000; 810 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 811 cdclk_config->cdclk = 337500; 812 else 813 cdclk_config->cdclk = 675000; 814 815 /* 816 * Can't read this out :( Let's assume it's 817 * at least what the CDCLK frequency requires. 818 */ 819 cdclk_config->voltage_level = 820 bdw_calc_voltage_level(cdclk_config->cdclk); 821 } 822 823 static u32 bdw_cdclk_freq_sel(int cdclk) 824 { 825 switch (cdclk) { 826 default: 827 MISSING_CASE(cdclk); 828 fallthrough; 829 case 337500: 830 return LCPLL_CLK_FREQ_337_5_BDW; 831 case 450000: 832 return LCPLL_CLK_FREQ_450; 833 case 540000: 834 return LCPLL_CLK_FREQ_54O_BDW; 835 case 675000: 836 return LCPLL_CLK_FREQ_675_BDW; 837 } 838 } 839 840 static void bdw_set_cdclk(struct intel_display *display, 841 const struct intel_cdclk_config *cdclk_config, 842 enum pipe pipe) 843 { 844 struct drm_i915_private *dev_priv = to_i915(display->drm); 845 int cdclk = cdclk_config->cdclk; 846 int ret; 847 848 if (drm_WARN(display->drm, 849 (intel_de_read(display, LCPLL_CTL) & 850 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 851 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 852 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 853 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 854 "trying to change cdclk frequency with cdclk not enabled\n")) 855 return; 856 857 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 858 if (ret) { 859 drm_err(display->drm, 860 "failed to inform pcode about cdclk change\n"); 861 return; 862 } 863 864 intel_de_rmw(display, LCPLL_CTL, 865 0, LCPLL_CD_SOURCE_FCLK); 866 867 /* 868 * According to the spec, it should be enough to poll for this 1 us. 869 * However, extensive testing shows that this can take longer. 870 */ 871 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & 872 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 873 drm_err(display->drm, "Switching to FCLK failed\n"); 874 875 intel_de_rmw(display, LCPLL_CTL, 876 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 877 878 intel_de_rmw(display, LCPLL_CTL, 879 LCPLL_CD_SOURCE_FCLK, 0); 880 881 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & 882 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 883 drm_err(display->drm, "Switching back to LCPLL failed\n"); 884 885 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, 886 cdclk_config->voltage_level); 887 888 intel_de_write(display, CDCLK_FREQ, 889 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 890 891 intel_update_cdclk(display); 892 } 893 894 static int skl_calc_cdclk(int min_cdclk, int vco) 895 { 896 if (vco == 8640000) { 897 if (min_cdclk > 540000) 898 return 617143; 899 else if (min_cdclk > 432000) 900 return 540000; 901 else if (min_cdclk > 308571) 902 return 432000; 903 else 904 return 308571; 905 } else { 906 if (min_cdclk > 540000) 907 return 675000; 908 else if (min_cdclk > 450000) 909 return 540000; 910 else if (min_cdclk > 337500) 911 return 450000; 912 else 913 return 337500; 914 } 915 } 916 917 static u8 skl_calc_voltage_level(int cdclk) 918 { 919 if (cdclk > 540000) 920 return 3; 921 else if (cdclk > 450000) 922 return 2; 923 else if (cdclk > 337500) 924 return 1; 925 else 926 return 0; 927 } 928 929 static void skl_dpll0_update(struct intel_display *display, 930 struct intel_cdclk_config *cdclk_config) 931 { 932 u32 val; 933 934 cdclk_config->ref = 24000; 935 cdclk_config->vco = 0; 936 937 val = intel_de_read(display, LCPLL1_CTL); 938 if ((val & LCPLL_PLL_ENABLE) == 0) 939 return; 940 941 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) 942 return; 943 944 val = intel_de_read(display, DPLL_CTRL1); 945 946 if (drm_WARN_ON(display->drm, 947 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 948 DPLL_CTRL1_SSC(SKL_DPLL0) | 949 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 950 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 951 return; 952 953 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 954 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 955 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 956 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 957 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 958 cdclk_config->vco = 8100000; 959 break; 960 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 961 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 962 cdclk_config->vco = 8640000; 963 break; 964 default: 965 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 966 break; 967 } 968 } 969 970 static void skl_get_cdclk(struct intel_display *display, 971 struct intel_cdclk_config *cdclk_config) 972 { 973 u32 cdctl; 974 975 skl_dpll0_update(display, cdclk_config); 976 977 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 978 979 if (cdclk_config->vco == 0) 980 goto out; 981 982 cdctl = intel_de_read(display, CDCLK_CTL); 983 984 if (cdclk_config->vco == 8640000) { 985 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 986 case CDCLK_FREQ_450_432: 987 cdclk_config->cdclk = 432000; 988 break; 989 case CDCLK_FREQ_337_308: 990 cdclk_config->cdclk = 308571; 991 break; 992 case CDCLK_FREQ_540: 993 cdclk_config->cdclk = 540000; 994 break; 995 case CDCLK_FREQ_675_617: 996 cdclk_config->cdclk = 617143; 997 break; 998 default: 999 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1000 break; 1001 } 1002 } else { 1003 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1004 case CDCLK_FREQ_450_432: 1005 cdclk_config->cdclk = 450000; 1006 break; 1007 case CDCLK_FREQ_337_308: 1008 cdclk_config->cdclk = 337500; 1009 break; 1010 case CDCLK_FREQ_540: 1011 cdclk_config->cdclk = 540000; 1012 break; 1013 case CDCLK_FREQ_675_617: 1014 cdclk_config->cdclk = 675000; 1015 break; 1016 default: 1017 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1018 break; 1019 } 1020 } 1021 1022 out: 1023 /* 1024 * Can't read this out :( Let's assume it's 1025 * at least what the CDCLK frequency requires. 1026 */ 1027 cdclk_config->voltage_level = 1028 skl_calc_voltage_level(cdclk_config->cdclk); 1029 } 1030 1031 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1032 static int skl_cdclk_decimal(int cdclk) 1033 { 1034 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1035 } 1036 1037 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) 1038 { 1039 bool changed = display->cdclk.skl_preferred_vco_freq != vco; 1040 1041 display->cdclk.skl_preferred_vco_freq = vco; 1042 1043 if (changed) 1044 intel_update_max_cdclk(display); 1045 } 1046 1047 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) 1048 { 1049 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 1050 1051 /* 1052 * We always enable DPLL0 with the lowest link rate possible, but still 1053 * taking into account the VCO required to operate the eDP panel at the 1054 * desired frequency. The usual DP link rates operate with a VCO of 1055 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1056 * The modeset code is responsible for the selection of the exact link 1057 * rate later on, with the constraint of choosing a frequency that 1058 * works with vco. 1059 */ 1060 if (vco == 8640000) 1061 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1062 else 1063 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1064 } 1065 1066 static void skl_dpll0_enable(struct intel_display *display, int vco) 1067 { 1068 intel_de_rmw(display, DPLL_CTRL1, 1069 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1070 DPLL_CTRL1_SSC(SKL_DPLL0) | 1071 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1072 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1073 skl_dpll0_link_rate(display, vco)); 1074 intel_de_posting_read(display, DPLL_CTRL1); 1075 1076 intel_de_rmw(display, LCPLL1_CTL, 1077 0, LCPLL_PLL_ENABLE); 1078 1079 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1080 drm_err(display->drm, "DPLL0 not locked\n"); 1081 1082 display->cdclk.hw.vco = vco; 1083 1084 /* We'll want to keep using the current vco from now on. */ 1085 skl_set_preferred_cdclk_vco(display, vco); 1086 } 1087 1088 static void skl_dpll0_disable(struct intel_display *display) 1089 { 1090 intel_de_rmw(display, LCPLL1_CTL, 1091 LCPLL_PLL_ENABLE, 0); 1092 1093 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1094 drm_err(display->drm, "Couldn't disable DPLL0\n"); 1095 1096 display->cdclk.hw.vco = 0; 1097 } 1098 1099 static u32 skl_cdclk_freq_sel(struct intel_display *display, 1100 int cdclk, int vco) 1101 { 1102 switch (cdclk) { 1103 default: 1104 drm_WARN_ON(display->drm, 1105 cdclk != display->cdclk.hw.bypass); 1106 drm_WARN_ON(display->drm, vco != 0); 1107 fallthrough; 1108 case 308571: 1109 case 337500: 1110 return CDCLK_FREQ_337_308; 1111 case 450000: 1112 case 432000: 1113 return CDCLK_FREQ_450_432; 1114 case 540000: 1115 return CDCLK_FREQ_540; 1116 case 617143: 1117 case 675000: 1118 return CDCLK_FREQ_675_617; 1119 } 1120 } 1121 1122 static void skl_set_cdclk(struct intel_display *display, 1123 const struct intel_cdclk_config *cdclk_config, 1124 enum pipe pipe) 1125 { 1126 struct drm_i915_private *dev_priv = to_i915(display->drm); 1127 int cdclk = cdclk_config->cdclk; 1128 int vco = cdclk_config->vco; 1129 u32 freq_select, cdclk_ctl; 1130 int ret; 1131 1132 /* 1133 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1134 * unsupported on SKL. In theory this should never happen since only 1135 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1136 * supported on SKL either, see the above WA. WARN whenever trying to 1137 * use the corresponding VCO freq as that always leads to using the 1138 * minimum 308MHz CDCLK. 1139 */ 1140 drm_WARN_ON_ONCE(display->drm, 1141 display->platform.skylake && vco == 8640000); 1142 1143 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1144 SKL_CDCLK_PREPARE_FOR_CHANGE, 1145 SKL_CDCLK_READY_FOR_CHANGE, 1146 SKL_CDCLK_READY_FOR_CHANGE, 3); 1147 if (ret) { 1148 drm_err(display->drm, 1149 "Failed to inform PCU about cdclk change (%d)\n", ret); 1150 return; 1151 } 1152 1153 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); 1154 1155 if (display->cdclk.hw.vco != 0 && 1156 display->cdclk.hw.vco != vco) 1157 skl_dpll0_disable(display); 1158 1159 cdclk_ctl = intel_de_read(display, CDCLK_CTL); 1160 1161 if (display->cdclk.hw.vco != vco) { 1162 /* Wa Display #1183: skl,kbl,cfl */ 1163 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1164 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1165 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1166 } 1167 1168 /* Wa Display #1183: skl,kbl,cfl */ 1169 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1170 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1171 intel_de_posting_read(display, CDCLK_CTL); 1172 1173 if (display->cdclk.hw.vco != vco) 1174 skl_dpll0_enable(display, vco); 1175 1176 /* Wa Display #1183: skl,kbl,cfl */ 1177 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1178 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1179 1180 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1181 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1182 1183 /* Wa Display #1183: skl,kbl,cfl */ 1184 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1185 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1186 intel_de_posting_read(display, CDCLK_CTL); 1187 1188 /* inform PCU of the change */ 1189 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1190 cdclk_config->voltage_level); 1191 1192 intel_update_cdclk(display); 1193 } 1194 1195 static void skl_sanitize_cdclk(struct intel_display *display) 1196 { 1197 u32 cdctl, expected; 1198 1199 /* 1200 * check if the pre-os initialized the display 1201 * There is SWF18 scratchpad register defined which is set by the 1202 * pre-os which can be used by the OS drivers to check the status 1203 */ 1204 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1205 goto sanitize; 1206 1207 intel_update_cdclk(display); 1208 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1209 1210 /* Is PLL enabled and locked ? */ 1211 if (display->cdclk.hw.vco == 0 || 1212 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 1213 goto sanitize; 1214 1215 /* DPLL okay; verify the cdclock 1216 * 1217 * Noticed in some instances that the freq selection is correct but 1218 * decimal part is programmed wrong from BIOS where pre-os does not 1219 * enable display. Verify the same as well. 1220 */ 1221 cdctl = intel_de_read(display, CDCLK_CTL); 1222 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1223 skl_cdclk_decimal(display->cdclk.hw.cdclk); 1224 if (cdctl == expected) 1225 /* All well; nothing to sanitize */ 1226 return; 1227 1228 sanitize: 1229 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 1230 1231 /* force cdclk programming */ 1232 display->cdclk.hw.cdclk = 0; 1233 /* force full PLL disable + enable */ 1234 display->cdclk.hw.vco = ~0; 1235 } 1236 1237 static void skl_cdclk_init_hw(struct intel_display *display) 1238 { 1239 struct intel_cdclk_config cdclk_config; 1240 1241 skl_sanitize_cdclk(display); 1242 1243 if (display->cdclk.hw.cdclk != 0 && 1244 display->cdclk.hw.vco != 0) { 1245 /* 1246 * Use the current vco as our initial 1247 * guess as to what the preferred vco is. 1248 */ 1249 if (display->cdclk.skl_preferred_vco_freq == 0) 1250 skl_set_preferred_cdclk_vco(display, 1251 display->cdclk.hw.vco); 1252 return; 1253 } 1254 1255 cdclk_config = display->cdclk.hw; 1256 1257 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; 1258 if (cdclk_config.vco == 0) 1259 cdclk_config.vco = 8100000; 1260 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1261 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1262 1263 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1264 } 1265 1266 static void skl_cdclk_uninit_hw(struct intel_display *display) 1267 { 1268 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 1269 1270 cdclk_config.cdclk = cdclk_config.bypass; 1271 cdclk_config.vco = 0; 1272 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1273 1274 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1275 } 1276 1277 struct intel_cdclk_vals { 1278 u32 cdclk; 1279 u16 refclk; 1280 u16 waveform; 1281 u8 ratio; 1282 }; 1283 1284 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1285 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1286 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1287 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1288 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1289 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1290 {} 1291 }; 1292 1293 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1294 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1295 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1296 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1297 {} 1298 }; 1299 1300 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1301 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1302 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1303 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1304 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1305 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1306 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1307 1308 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1309 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1310 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1311 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1312 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1313 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1314 1315 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1316 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1317 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1318 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1319 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1320 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1321 {} 1322 }; 1323 1324 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1325 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1326 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1327 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1328 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1329 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1330 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1331 1332 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1333 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1334 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1335 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1336 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1337 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1338 1339 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1340 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1341 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1342 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1343 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1344 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1345 {} 1346 }; 1347 1348 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1349 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1350 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1351 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1352 1353 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1354 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1355 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1356 1357 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1358 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1359 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1360 {} 1361 }; 1362 1363 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1364 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1365 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1366 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1367 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1368 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1369 1370 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1371 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1372 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1373 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1374 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1375 1376 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1377 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1378 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1379 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1380 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1381 {} 1382 }; 1383 1384 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1385 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1386 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1387 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1388 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1389 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1390 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1391 1392 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1393 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1394 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1395 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1396 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1397 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1398 1399 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1400 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1401 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1402 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1403 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1404 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1405 {} 1406 }; 1407 1408 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1409 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1410 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1411 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1412 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1413 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1414 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1415 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1416 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1417 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1418 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1419 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1420 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1421 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1422 {} 1423 }; 1424 1425 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1426 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1427 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1428 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1429 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1430 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1431 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1432 {} 1433 }; 1434 1435 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1436 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1437 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1438 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1439 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1440 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1441 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1442 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1443 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1444 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1445 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1446 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1447 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1448 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1449 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1450 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1451 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1452 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1453 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1454 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1455 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1456 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1457 {} 1458 }; 1459 1460 /* 1461 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1462 */ 1463 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1464 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1465 {} 1466 }; 1467 1468 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { 1469 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1470 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1471 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1472 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1473 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1474 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1475 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1476 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1477 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1478 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff }, 1479 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff }, 1480 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff }, 1481 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff }, 1482 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1483 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1484 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1485 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1486 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1487 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1488 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1489 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1490 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1491 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1492 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1493 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1494 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1495 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1496 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1497 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1498 {} 1499 }; 1500 1501 static const int cdclk_squash_len = 16; 1502 1503 static int cdclk_squash_divider(u16 waveform) 1504 { 1505 return hweight16(waveform ?: 0xffff); 1506 } 1507 1508 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1509 { 1510 /* 2 * cd2x divider */ 1511 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1512 cdclk * cdclk_squash_len); 1513 } 1514 1515 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 1516 { 1517 const struct intel_cdclk_vals *table = display->cdclk.table; 1518 int i; 1519 1520 for (i = 0; table[i].refclk; i++) 1521 if (table[i].refclk == display->cdclk.hw.ref && 1522 table[i].cdclk >= min_cdclk) 1523 return table[i].cdclk; 1524 1525 drm_WARN(display->drm, 1, 1526 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1527 min_cdclk, display->cdclk.hw.ref); 1528 return 0; 1529 } 1530 1531 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) 1532 { 1533 const struct intel_cdclk_vals *table = display->cdclk.table; 1534 int i; 1535 1536 if (cdclk == display->cdclk.hw.bypass) 1537 return 0; 1538 1539 for (i = 0; table[i].refclk; i++) 1540 if (table[i].refclk == display->cdclk.hw.ref && 1541 table[i].cdclk == cdclk) 1542 return display->cdclk.hw.ref * table[i].ratio; 1543 1544 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1545 cdclk, display->cdclk.hw.ref); 1546 return 0; 1547 } 1548 1549 static u8 bxt_calc_voltage_level(int cdclk) 1550 { 1551 return DIV_ROUND_UP(cdclk, 25000); 1552 } 1553 1554 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1555 const int voltage_level_max_cdclk[]) 1556 { 1557 int voltage_level; 1558 1559 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1560 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1561 return voltage_level; 1562 } 1563 1564 MISSING_CASE(cdclk); 1565 return num_voltage_levels - 1; 1566 } 1567 1568 static u8 icl_calc_voltage_level(int cdclk) 1569 { 1570 static const int icl_voltage_level_max_cdclk[] = { 1571 [0] = 312000, 1572 [1] = 556800, 1573 [2] = 652800, 1574 }; 1575 1576 return calc_voltage_level(cdclk, 1577 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1578 icl_voltage_level_max_cdclk); 1579 } 1580 1581 static u8 ehl_calc_voltage_level(int cdclk) 1582 { 1583 static const int ehl_voltage_level_max_cdclk[] = { 1584 [0] = 180000, 1585 [1] = 312000, 1586 [2] = 326400, 1587 /* 1588 * Bspec lists the limit as 556.8 MHz, but some JSL 1589 * development boards (at least) boot with 652.8 MHz 1590 */ 1591 [3] = 652800, 1592 }; 1593 1594 return calc_voltage_level(cdclk, 1595 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1596 ehl_voltage_level_max_cdclk); 1597 } 1598 1599 static u8 tgl_calc_voltage_level(int cdclk) 1600 { 1601 static const int tgl_voltage_level_max_cdclk[] = { 1602 [0] = 312000, 1603 [1] = 326400, 1604 [2] = 556800, 1605 [3] = 652800, 1606 }; 1607 1608 return calc_voltage_level(cdclk, 1609 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1610 tgl_voltage_level_max_cdclk); 1611 } 1612 1613 static u8 rplu_calc_voltage_level(int cdclk) 1614 { 1615 static const int rplu_voltage_level_max_cdclk[] = { 1616 [0] = 312000, 1617 [1] = 480000, 1618 [2] = 556800, 1619 [3] = 652800, 1620 }; 1621 1622 return calc_voltage_level(cdclk, 1623 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1624 rplu_voltage_level_max_cdclk); 1625 } 1626 1627 static u8 xe3lpd_calc_voltage_level(int cdclk) 1628 { 1629 /* 1630 * Starting with xe3lpd power controller does not need the voltage 1631 * index when doing the modeset update. This function is best left 1632 * defined but returning 0 to the mask. 1633 */ 1634 return 0; 1635 } 1636 1637 static void icl_readout_refclk(struct intel_display *display, 1638 struct intel_cdclk_config *cdclk_config) 1639 { 1640 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1641 1642 switch (dssm) { 1643 default: 1644 MISSING_CASE(dssm); 1645 fallthrough; 1646 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1647 cdclk_config->ref = 24000; 1648 break; 1649 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1650 cdclk_config->ref = 19200; 1651 break; 1652 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1653 cdclk_config->ref = 38400; 1654 break; 1655 } 1656 } 1657 1658 static void bxt_de_pll_readout(struct intel_display *display, 1659 struct intel_cdclk_config *cdclk_config) 1660 { 1661 u32 val, ratio; 1662 1663 if (display->platform.dg2) 1664 cdclk_config->ref = 38400; 1665 else if (DISPLAY_VER(display) >= 11) 1666 icl_readout_refclk(display, cdclk_config); 1667 else 1668 cdclk_config->ref = 19200; 1669 1670 val = intel_de_read(display, BXT_DE_PLL_ENABLE); 1671 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1672 (val & BXT_DE_PLL_LOCK) == 0) { 1673 /* 1674 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1675 * setting it to zero is a way to signal that. 1676 */ 1677 cdclk_config->vco = 0; 1678 return; 1679 } 1680 1681 /* 1682 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1683 * gen9lp had it in a separate PLL control register. 1684 */ 1685 if (DISPLAY_VER(display) >= 11) 1686 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1687 else 1688 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1689 1690 cdclk_config->vco = ratio * cdclk_config->ref; 1691 } 1692 1693 static void bxt_get_cdclk(struct intel_display *display, 1694 struct intel_cdclk_config *cdclk_config) 1695 { 1696 u32 squash_ctl = 0; 1697 u32 divider; 1698 int div; 1699 1700 bxt_de_pll_readout(display, cdclk_config); 1701 1702 if (DISPLAY_VER(display) >= 12) 1703 cdclk_config->bypass = cdclk_config->ref / 2; 1704 else if (DISPLAY_VER(display) >= 11) 1705 cdclk_config->bypass = 50000; 1706 else 1707 cdclk_config->bypass = cdclk_config->ref; 1708 1709 if (cdclk_config->vco == 0) { 1710 cdclk_config->cdclk = cdclk_config->bypass; 1711 goto out; 1712 } 1713 1714 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1715 1716 switch (divider) { 1717 case BXT_CDCLK_CD2X_DIV_SEL_1: 1718 div = 2; 1719 break; 1720 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1721 div = 3; 1722 break; 1723 case BXT_CDCLK_CD2X_DIV_SEL_2: 1724 div = 4; 1725 break; 1726 case BXT_CDCLK_CD2X_DIV_SEL_4: 1727 div = 8; 1728 break; 1729 default: 1730 MISSING_CASE(divider); 1731 return; 1732 } 1733 1734 if (HAS_CDCLK_SQUASH(display)) 1735 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); 1736 1737 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1738 u16 waveform; 1739 int size; 1740 1741 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1742 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1743 1744 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1745 cdclk_config->vco, size * div); 1746 } else { 1747 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1748 } 1749 1750 out: 1751 if (DISPLAY_VER(display) >= 20) 1752 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 1753 /* 1754 * Can't read this out :( Let's assume it's 1755 * at least what the CDCLK frequency requires. 1756 */ 1757 cdclk_config->voltage_level = 1758 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); 1759 } 1760 1761 static void bxt_de_pll_disable(struct intel_display *display) 1762 { 1763 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); 1764 1765 /* Timeout 200us */ 1766 if (intel_de_wait_for_clear(display, 1767 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1768 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); 1769 1770 display->cdclk.hw.vco = 0; 1771 } 1772 1773 static void bxt_de_pll_enable(struct intel_display *display, int vco) 1774 { 1775 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1776 1777 intel_de_rmw(display, BXT_DE_PLL_CTL, 1778 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1779 1780 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1781 1782 /* Timeout 200us */ 1783 if (intel_de_wait_for_set(display, 1784 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1785 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); 1786 1787 display->cdclk.hw.vco = vco; 1788 } 1789 1790 static void icl_cdclk_pll_disable(struct intel_display *display) 1791 { 1792 intel_de_rmw(display, BXT_DE_PLL_ENABLE, 1793 BXT_DE_PLL_PLL_ENABLE, 0); 1794 1795 /* Timeout 200us */ 1796 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1797 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); 1798 1799 display->cdclk.hw.vco = 0; 1800 } 1801 1802 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) 1803 { 1804 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1805 u32 val; 1806 1807 val = ICL_CDCLK_PLL_RATIO(ratio); 1808 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1809 1810 val |= BXT_DE_PLL_PLL_ENABLE; 1811 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1812 1813 /* Timeout 200us */ 1814 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1815 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); 1816 1817 display->cdclk.hw.vco = vco; 1818 } 1819 1820 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) 1821 { 1822 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1823 u32 val; 1824 1825 /* Write PLL ratio without disabling */ 1826 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1827 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1828 1829 /* Submit freq change request */ 1830 val |= BXT_DE_PLL_FREQ_REQ; 1831 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1832 1833 /* Timeout 200us */ 1834 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, 1835 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1836 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); 1837 1838 val &= ~BXT_DE_PLL_FREQ_REQ; 1839 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1840 1841 display->cdclk.hw.vco = vco; 1842 } 1843 1844 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 1845 { 1846 if (DISPLAY_VER(display) >= 12) { 1847 if (pipe == INVALID_PIPE) 1848 return TGL_CDCLK_CD2X_PIPE_NONE; 1849 else 1850 return TGL_CDCLK_CD2X_PIPE(pipe); 1851 } else if (DISPLAY_VER(display) >= 11) { 1852 if (pipe == INVALID_PIPE) 1853 return ICL_CDCLK_CD2X_PIPE_NONE; 1854 else 1855 return ICL_CDCLK_CD2X_PIPE(pipe); 1856 } else { 1857 if (pipe == INVALID_PIPE) 1858 return BXT_CDCLK_CD2X_PIPE_NONE; 1859 else 1860 return BXT_CDCLK_CD2X_PIPE(pipe); 1861 } 1862 } 1863 1864 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 1865 int cdclk, int vco, u16 waveform) 1866 { 1867 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1868 switch (cdclk_divider(cdclk, vco, waveform)) { 1869 default: 1870 drm_WARN_ON(display->drm, 1871 cdclk != display->cdclk.hw.bypass); 1872 drm_WARN_ON(display->drm, vco != 0); 1873 fallthrough; 1874 case 2: 1875 return BXT_CDCLK_CD2X_DIV_SEL_1; 1876 case 3: 1877 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1878 case 4: 1879 return BXT_CDCLK_CD2X_DIV_SEL_2; 1880 case 8: 1881 return BXT_CDCLK_CD2X_DIV_SEL_4; 1882 } 1883 } 1884 1885 static u16 cdclk_squash_waveform(struct intel_display *display, 1886 int cdclk) 1887 { 1888 const struct intel_cdclk_vals *table = display->cdclk.table; 1889 int i; 1890 1891 if (cdclk == display->cdclk.hw.bypass) 1892 return 0; 1893 1894 for (i = 0; table[i].refclk; i++) 1895 if (table[i].refclk == display->cdclk.hw.ref && 1896 table[i].cdclk == cdclk) 1897 return table[i].waveform; 1898 1899 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1900 cdclk, display->cdclk.hw.ref); 1901 1902 return 0xffff; 1903 } 1904 1905 static void icl_cdclk_pll_update(struct intel_display *display, int vco) 1906 { 1907 if (display->cdclk.hw.vco != 0 && 1908 display->cdclk.hw.vco != vco) 1909 icl_cdclk_pll_disable(display); 1910 1911 if (display->cdclk.hw.vco != vco) 1912 icl_cdclk_pll_enable(display, vco); 1913 } 1914 1915 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) 1916 { 1917 if (display->cdclk.hw.vco != 0 && 1918 display->cdclk.hw.vco != vco) 1919 bxt_de_pll_disable(display); 1920 1921 if (display->cdclk.hw.vco != vco) 1922 bxt_de_pll_enable(display, vco); 1923 } 1924 1925 static void dg2_cdclk_squash_program(struct intel_display *display, 1926 u16 waveform) 1927 { 1928 u32 squash_ctl = 0; 1929 1930 if (waveform) 1931 squash_ctl = CDCLK_SQUASH_ENABLE | 1932 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1933 1934 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); 1935 } 1936 1937 static bool cdclk_pll_is_unknown(unsigned int vco) 1938 { 1939 /* 1940 * Ensure driver does not take the crawl path for the 1941 * case when the vco is set to ~0 in the 1942 * sanitize path. 1943 */ 1944 return vco == ~0; 1945 } 1946 1947 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) 1948 { 1949 return DISPLAY_VER(display) >= 20; 1950 } 1951 1952 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) 1953 { 1954 if (mdclk_source_is_cdclk_pll(display)) 1955 return MDCLK_SOURCE_SEL_CDCLK_PLL; 1956 1957 return MDCLK_SOURCE_SEL_CD2XCLK; 1958 } 1959 1960 int intel_mdclk_cdclk_ratio(struct intel_display *display, 1961 const struct intel_cdclk_config *cdclk_config) 1962 { 1963 if (mdclk_source_is_cdclk_pll(display)) 1964 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 1965 1966 /* Otherwise, source for MDCLK is CD2XCLK. */ 1967 return 2; 1968 } 1969 1970 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, 1971 const struct intel_cdclk_config *cdclk_config) 1972 { 1973 intel_dbuf_mdclk_cdclk_ratio_update(display, 1974 intel_mdclk_cdclk_ratio(display, cdclk_config), 1975 cdclk_config->joined_mbus); 1976 } 1977 1978 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, 1979 const struct intel_cdclk_config *old_cdclk_config, 1980 const struct intel_cdclk_config *new_cdclk_config, 1981 struct intel_cdclk_config *mid_cdclk_config) 1982 { 1983 u16 old_waveform, new_waveform, mid_waveform; 1984 int old_div, new_div, mid_div; 1985 1986 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 1987 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 1988 return false; 1989 1990 /* Return if both Squash and Crawl are not present */ 1991 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 1992 return false; 1993 1994 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); 1995 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); 1996 1997 /* Return if Squash only or Crawl only is the desired action */ 1998 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 1999 old_cdclk_config->vco == new_cdclk_config->vco || 2000 old_waveform == new_waveform) 2001 return false; 2002 2003 old_div = cdclk_divider(old_cdclk_config->cdclk, 2004 old_cdclk_config->vco, old_waveform); 2005 new_div = cdclk_divider(new_cdclk_config->cdclk, 2006 new_cdclk_config->vco, new_waveform); 2007 2008 /* 2009 * Should not happen currently. We might need more midpoint 2010 * transitions if we need to also change the cd2x divider. 2011 */ 2012 if (drm_WARN_ON(display->drm, old_div != new_div)) 2013 return false; 2014 2015 *mid_cdclk_config = *new_cdclk_config; 2016 2017 /* 2018 * Populate the mid_cdclk_config accordingly. 2019 * - If moving to a higher cdclk, the desired action is squashing. 2020 * The mid cdclk config should have the new (squash) waveform. 2021 * - If moving to a lower cdclk, the desired action is crawling. 2022 * The mid cdclk config should have the new vco. 2023 */ 2024 2025 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 2026 mid_cdclk_config->vco = old_cdclk_config->vco; 2027 mid_div = old_div; 2028 mid_waveform = new_waveform; 2029 } else { 2030 mid_cdclk_config->vco = new_cdclk_config->vco; 2031 mid_div = new_div; 2032 mid_waveform = old_waveform; 2033 } 2034 2035 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 2036 mid_cdclk_config->vco, 2037 cdclk_squash_len * mid_div); 2038 2039 /* make sure the mid clock came out sane */ 2040 2041 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < 2042 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 2043 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > 2044 display->cdclk.max_cdclk_freq); 2045 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != 2046 mid_waveform); 2047 2048 return true; 2049 } 2050 2051 static bool pll_enable_wa_needed(struct intel_display *display) 2052 { 2053 return (DISPLAY_VERx100(display) == 2000 || 2054 DISPLAY_VERx100(display) == 1400 || 2055 display->platform.dg2) && 2056 display->cdclk.hw.vco > 0; 2057 } 2058 2059 static u32 bxt_cdclk_ctl(struct intel_display *display, 2060 const struct intel_cdclk_config *cdclk_config, 2061 enum pipe pipe) 2062 { 2063 int cdclk = cdclk_config->cdclk; 2064 int vco = cdclk_config->vco; 2065 u16 waveform; 2066 u32 val; 2067 2068 waveform = cdclk_squash_waveform(display, cdclk); 2069 2070 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | 2071 bxt_cdclk_cd2x_pipe(display, pipe); 2072 2073 /* 2074 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2075 * enable otherwise. 2076 */ 2077 if ((display->platform.geminilake || display->platform.broxton) && 2078 cdclk >= 500000) 2079 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2080 2081 if (DISPLAY_VER(display) >= 20) 2082 val |= xe2lpd_mdclk_source_sel(display); 2083 else 2084 val |= skl_cdclk_decimal(cdclk); 2085 2086 return val; 2087 } 2088 2089 static void _bxt_set_cdclk(struct intel_display *display, 2090 const struct intel_cdclk_config *cdclk_config, 2091 enum pipe pipe) 2092 { 2093 int cdclk = cdclk_config->cdclk; 2094 int vco = cdclk_config->vco; 2095 2096 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && 2097 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { 2098 if (display->cdclk.hw.vco != vco) 2099 adlp_cdclk_pll_crawl(display, vco); 2100 } else if (DISPLAY_VER(display) >= 11) { 2101 /* wa_15010685871: dg2, mtl */ 2102 if (pll_enable_wa_needed(display)) 2103 dg2_cdclk_squash_program(display, 0); 2104 2105 icl_cdclk_pll_update(display, vco); 2106 } else { 2107 bxt_cdclk_pll_update(display, vco); 2108 } 2109 2110 if (HAS_CDCLK_SQUASH(display)) { 2111 u16 waveform = cdclk_squash_waveform(display, cdclk); 2112 2113 dg2_cdclk_squash_program(display, waveform); 2114 } 2115 2116 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); 2117 2118 if (pipe != INVALID_PIPE) 2119 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 2120 } 2121 2122 static void bxt_set_cdclk(struct intel_display *display, 2123 const struct intel_cdclk_config *cdclk_config, 2124 enum pipe pipe) 2125 { 2126 struct drm_i915_private *dev_priv = to_i915(display->drm); 2127 struct intel_cdclk_config mid_cdclk_config; 2128 int cdclk = cdclk_config->cdclk; 2129 int ret = 0; 2130 2131 /* 2132 * Inform power controller of upcoming frequency change. 2133 * Display versions 14 and beyond do not follow the PUnit 2134 * mailbox communication, skip 2135 * this step. 2136 */ 2137 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) 2138 ; /* NOOP */ 2139 else if (DISPLAY_VER(display) >= 11) 2140 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 2141 SKL_CDCLK_PREPARE_FOR_CHANGE, 2142 SKL_CDCLK_READY_FOR_CHANGE, 2143 SKL_CDCLK_READY_FOR_CHANGE, 3); 2144 else 2145 /* 2146 * BSpec requires us to wait up to 150usec, but that leads to 2147 * timeouts; the 2ms used here is based on experiment. 2148 */ 2149 ret = snb_pcode_write_timeout(&dev_priv->uncore, 2150 HSW_PCODE_DE_WRITE_FREQ_REQ, 2151 0x80000000, 150, 2); 2152 2153 if (ret) { 2154 drm_err(display->drm, 2155 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2156 ret, cdclk); 2157 return; 2158 } 2159 2160 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) 2161 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2162 2163 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, 2164 cdclk_config, &mid_cdclk_config)) { 2165 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); 2166 _bxt_set_cdclk(display, cdclk_config, pipe); 2167 } else { 2168 _bxt_set_cdclk(display, cdclk_config, pipe); 2169 } 2170 2171 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) 2172 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2173 2174 if (DISPLAY_VER(display) >= 14) 2175 /* 2176 * NOOP - No Pcode communication needed for 2177 * Display versions 14 and beyond 2178 */; 2179 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) 2180 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 2181 cdclk_config->voltage_level); 2182 if (DISPLAY_VER(display) < 11) { 2183 /* 2184 * The timeout isn't specified, the 2ms used here is based on 2185 * experiment. 2186 * FIXME: Waiting for the request completion could be delayed 2187 * until the next PCODE request based on BSpec. 2188 */ 2189 ret = snb_pcode_write_timeout(&dev_priv->uncore, 2190 HSW_PCODE_DE_WRITE_FREQ_REQ, 2191 cdclk_config->voltage_level, 2192 150, 2); 2193 } 2194 if (ret) { 2195 drm_err(display->drm, 2196 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2197 ret, cdclk); 2198 return; 2199 } 2200 2201 intel_update_cdclk(display); 2202 2203 if (DISPLAY_VER(display) >= 11) 2204 /* 2205 * Can't read out the voltage level :( 2206 * Let's just assume everything is as expected. 2207 */ 2208 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; 2209 } 2210 2211 static void bxt_sanitize_cdclk(struct intel_display *display) 2212 { 2213 u32 cdctl, expected; 2214 int cdclk, vco; 2215 2216 intel_update_cdclk(display); 2217 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 2218 2219 if (display->cdclk.hw.vco == 0 || 2220 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 2221 goto sanitize; 2222 2223 /* Make sure this is a legal cdclk value for the platform */ 2224 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); 2225 if (cdclk != display->cdclk.hw.cdclk) 2226 goto sanitize; 2227 2228 /* Make sure the VCO is correct for the cdclk */ 2229 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 2230 if (vco != display->cdclk.hw.vco) 2231 goto sanitize; 2232 2233 /* 2234 * Some BIOS versions leave an incorrect decimal frequency value and 2235 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2236 * so sanitize this register. 2237 */ 2238 cdctl = intel_de_read(display, CDCLK_CTL); 2239 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); 2240 2241 /* 2242 * Let's ignore the pipe field, since BIOS could have configured the 2243 * dividers both syncing to an active pipe, or asynchronously 2244 * (PIPE_NONE). 2245 */ 2246 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2247 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2248 2249 if (cdctl == expected) 2250 /* All well; nothing to sanitize */ 2251 return; 2252 2253 sanitize: 2254 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 2255 2256 /* force cdclk programming */ 2257 display->cdclk.hw.cdclk = 0; 2258 2259 /* force full PLL disable + enable */ 2260 display->cdclk.hw.vco = ~0; 2261 } 2262 2263 static void bxt_cdclk_init_hw(struct intel_display *display) 2264 { 2265 struct intel_cdclk_config cdclk_config; 2266 2267 bxt_sanitize_cdclk(display); 2268 2269 if (display->cdclk.hw.cdclk != 0 && 2270 display->cdclk.hw.vco != 0) 2271 return; 2272 2273 cdclk_config = display->cdclk.hw; 2274 2275 /* 2276 * FIXME: 2277 * - The initial CDCLK needs to be read from VBT. 2278 * Need to make this change after VBT has changes for BXT. 2279 */ 2280 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); 2281 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); 2282 cdclk_config.voltage_level = 2283 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2284 2285 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2286 } 2287 2288 static void bxt_cdclk_uninit_hw(struct intel_display *display) 2289 { 2290 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 2291 2292 cdclk_config.cdclk = cdclk_config.bypass; 2293 cdclk_config.vco = 0; 2294 cdclk_config.voltage_level = 2295 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2296 2297 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2298 } 2299 2300 /** 2301 * intel_cdclk_init_hw - Initialize CDCLK hardware 2302 * @display: display instance 2303 * 2304 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and 2305 * sanitizing the state of the hardware if needed. This is generally done only 2306 * during the display core initialization sequence, after which the DMC will 2307 * take care of turning CDCLK off/on as needed. 2308 */ 2309 void intel_cdclk_init_hw(struct intel_display *display) 2310 { 2311 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2312 bxt_cdclk_init_hw(display); 2313 else if (DISPLAY_VER(display) == 9) 2314 skl_cdclk_init_hw(display); 2315 } 2316 2317 /** 2318 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2319 * @display: display instance 2320 * 2321 * Uninitialize CDCLK. This is done only during the display core 2322 * uninitialization sequence. 2323 */ 2324 void intel_cdclk_uninit_hw(struct intel_display *display) 2325 { 2326 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2327 bxt_cdclk_uninit_hw(display); 2328 else if (DISPLAY_VER(display) == 9) 2329 skl_cdclk_uninit_hw(display); 2330 } 2331 2332 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, 2333 const struct intel_cdclk_config *a, 2334 const struct intel_cdclk_config *b) 2335 { 2336 u16 old_waveform; 2337 u16 new_waveform; 2338 2339 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); 2340 2341 if (a->vco == 0 || b->vco == 0) 2342 return false; 2343 2344 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2345 return false; 2346 2347 old_waveform = cdclk_squash_waveform(display, a->cdclk); 2348 new_waveform = cdclk_squash_waveform(display, b->cdclk); 2349 2350 return a->vco != b->vco && 2351 old_waveform != new_waveform; 2352 } 2353 2354 static bool intel_cdclk_can_crawl(struct intel_display *display, 2355 const struct intel_cdclk_config *a, 2356 const struct intel_cdclk_config *b) 2357 { 2358 int a_div, b_div; 2359 2360 if (!HAS_CDCLK_CRAWL(display)) 2361 return false; 2362 2363 /* 2364 * The vco and cd2x divider will change independently 2365 * from each, so we disallow cd2x change when crawling. 2366 */ 2367 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2368 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2369 2370 return a->vco != 0 && b->vco != 0 && 2371 a->vco != b->vco && 2372 a_div == b_div && 2373 a->ref == b->ref; 2374 } 2375 2376 static bool intel_cdclk_can_squash(struct intel_display *display, 2377 const struct intel_cdclk_config *a, 2378 const struct intel_cdclk_config *b) 2379 { 2380 /* 2381 * FIXME should store a bit more state in intel_cdclk_config 2382 * to differentiate squasher vs. cd2x divider properly. For 2383 * the moment all platforms with squasher use a fixed cd2x 2384 * divider. 2385 */ 2386 if (!HAS_CDCLK_SQUASH(display)) 2387 return false; 2388 2389 return a->cdclk != b->cdclk && 2390 a->vco != 0 && 2391 a->vco == b->vco && 2392 a->ref == b->ref; 2393 } 2394 2395 /** 2396 * intel_cdclk_clock_changed - Check whether the clock changed 2397 * @a: first CDCLK configuration 2398 * @b: second CDCLK configuration 2399 * 2400 * Returns: 2401 * True if CDCLK changed in a way that requires re-programming and 2402 * False otherwise. 2403 */ 2404 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2405 const struct intel_cdclk_config *b) 2406 { 2407 return a->cdclk != b->cdclk || 2408 a->vco != b->vco || 2409 a->ref != b->ref; 2410 } 2411 2412 /** 2413 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2414 * configurations requires only a cd2x divider update 2415 * @display: display instance 2416 * @a: first CDCLK configuration 2417 * @b: second CDCLK configuration 2418 * 2419 * Returns: 2420 * True if changing between the two CDCLK configurations 2421 * can be done with just a cd2x divider update, false if not. 2422 */ 2423 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, 2424 const struct intel_cdclk_config *a, 2425 const struct intel_cdclk_config *b) 2426 { 2427 /* Older hw doesn't have the capability */ 2428 if (DISPLAY_VER(display) < 10 && !display->platform.broxton) 2429 return false; 2430 2431 /* 2432 * FIXME should store a bit more state in intel_cdclk_config 2433 * to differentiate squasher vs. cd2x divider properly. For 2434 * the moment all platforms with squasher use a fixed cd2x 2435 * divider. 2436 */ 2437 if (HAS_CDCLK_SQUASH(display)) 2438 return false; 2439 2440 return a->cdclk != b->cdclk && 2441 a->vco != 0 && 2442 a->vco == b->vco && 2443 a->ref == b->ref; 2444 } 2445 2446 /** 2447 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2448 * @a: first CDCLK configuration 2449 * @b: second CDCLK configuration 2450 * 2451 * Returns: 2452 * True if the CDCLK configurations don't match, false if they do. 2453 */ 2454 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2455 const struct intel_cdclk_config *b) 2456 { 2457 return intel_cdclk_clock_changed(a, b) || 2458 a->voltage_level != b->voltage_level; 2459 } 2460 2461 void intel_cdclk_dump_config(struct intel_display *display, 2462 const struct intel_cdclk_config *cdclk_config, 2463 const char *context) 2464 { 2465 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2466 context, cdclk_config->cdclk, cdclk_config->vco, 2467 cdclk_config->ref, cdclk_config->bypass, 2468 cdclk_config->voltage_level); 2469 } 2470 2471 static void intel_pcode_notify(struct intel_display *display, 2472 u8 voltage_level, 2473 u8 active_pipe_count, 2474 u16 cdclk, 2475 bool cdclk_update_valid, 2476 bool pipe_count_update_valid) 2477 { 2478 struct drm_i915_private *i915 = to_i915(display->drm); 2479 int ret; 2480 u32 update_mask = 0; 2481 2482 if (!display->platform.dg2) 2483 return; 2484 2485 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2486 2487 if (cdclk_update_valid) 2488 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2489 2490 if (pipe_count_update_valid) 2491 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2492 2493 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL, 2494 SKL_CDCLK_PREPARE_FOR_CHANGE | 2495 update_mask, 2496 SKL_CDCLK_READY_FOR_CHANGE, 2497 SKL_CDCLK_READY_FOR_CHANGE, 3); 2498 if (ret) 2499 drm_err(display->drm, 2500 "Failed to inform PCU about display config (err %d)\n", 2501 ret); 2502 } 2503 2504 static void intel_set_cdclk(struct intel_display *display, 2505 const struct intel_cdclk_config *cdclk_config, 2506 enum pipe pipe, const char *context) 2507 { 2508 struct intel_encoder *encoder; 2509 2510 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) 2511 return; 2512 2513 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) 2514 return; 2515 2516 intel_cdclk_dump_config(display, cdclk_config, context); 2517 2518 for_each_intel_encoder_with_psr(display->drm, encoder) { 2519 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2520 2521 intel_psr_pause(intel_dp); 2522 } 2523 2524 intel_audio_cdclk_change_pre(display); 2525 2526 /* 2527 * Lock aux/gmbus while we change cdclk in case those 2528 * functions use cdclk. Not all platforms/ports do, 2529 * but we'll lock them all for simplicity. 2530 */ 2531 mutex_lock(&display->gmbus.mutex); 2532 for_each_intel_dp(display->drm, encoder) { 2533 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2534 2535 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2536 &display->gmbus.mutex); 2537 } 2538 2539 intel_cdclk_set_cdclk(display, cdclk_config, pipe); 2540 2541 for_each_intel_dp(display->drm, encoder) { 2542 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2543 2544 mutex_unlock(&intel_dp->aux.hw_mutex); 2545 } 2546 mutex_unlock(&display->gmbus.mutex); 2547 2548 for_each_intel_encoder_with_psr(display->drm, encoder) { 2549 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2550 2551 intel_psr_resume(intel_dp); 2552 } 2553 2554 intel_audio_cdclk_change_post(display); 2555 2556 if (drm_WARN(display->drm, 2557 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), 2558 "cdclk state doesn't match!\n")) { 2559 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); 2560 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); 2561 } 2562 } 2563 2564 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2565 { 2566 struct intel_display *display = to_intel_display(state); 2567 const struct intel_cdclk_state *old_cdclk_state = 2568 intel_atomic_get_old_cdclk_state(state); 2569 const struct intel_cdclk_state *new_cdclk_state = 2570 intel_atomic_get_new_cdclk_state(state); 2571 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2572 bool change_cdclk, update_pipe_count; 2573 2574 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2575 &new_cdclk_state->actual) && 2576 new_cdclk_state->active_pipes == 2577 old_cdclk_state->active_pipes) 2578 return; 2579 2580 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2581 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2582 2583 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2584 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > 2585 hweight8(old_cdclk_state->active_pipes); 2586 2587 /* 2588 * According to "Sequence Before Frequency Change", 2589 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2590 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2591 * which basically means we choose the maximum of old and new CDCLK, if we know both 2592 */ 2593 if (change_cdclk) 2594 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2595 2596 /* 2597 * According to "Sequence For Pipe Count Change", 2598 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2599 * (power well is enabled) 2600 * no action if it is decreasing, before the change 2601 */ 2602 if (update_pipe_count) 2603 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2604 2605 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2606 change_cdclk, update_pipe_count); 2607 } 2608 2609 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2610 { 2611 struct intel_display *display = to_intel_display(state); 2612 const struct intel_cdclk_state *new_cdclk_state = 2613 intel_atomic_get_new_cdclk_state(state); 2614 const struct intel_cdclk_state *old_cdclk_state = 2615 intel_atomic_get_old_cdclk_state(state); 2616 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2617 bool update_cdclk, update_pipe_count; 2618 2619 /* According to "Sequence After Frequency Change", set voltage to used level */ 2620 voltage_level = new_cdclk_state->actual.voltage_level; 2621 2622 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2623 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < 2624 hweight8(old_cdclk_state->active_pipes); 2625 2626 /* 2627 * According to "Sequence After Frequency Change", 2628 * set bits 25:16 to current CDCLK 2629 */ 2630 if (update_cdclk) 2631 cdclk = new_cdclk_state->actual.cdclk; 2632 2633 /* 2634 * According to "Sequence For Pipe Count Change", 2635 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2636 * after the change(power well is disabled) 2637 * no action if it is increasing, after the change 2638 */ 2639 if (update_pipe_count) 2640 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2641 2642 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2643 update_cdclk, update_pipe_count); 2644 } 2645 2646 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2647 { 2648 const struct intel_cdclk_state *old_cdclk_state = 2649 intel_atomic_get_old_cdclk_state(state); 2650 const struct intel_cdclk_state *new_cdclk_state = 2651 intel_atomic_get_new_cdclk_state(state); 2652 2653 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2654 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2655 } 2656 2657 /** 2658 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2659 * @state: intel atomic state 2660 * 2661 * Program the hardware before updating the HW plane state based on the 2662 * new CDCLK state, if necessary. 2663 */ 2664 void 2665 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2666 { 2667 struct intel_display *display = to_intel_display(state); 2668 const struct intel_cdclk_state *old_cdclk_state = 2669 intel_atomic_get_old_cdclk_state(state); 2670 const struct intel_cdclk_state *new_cdclk_state = 2671 intel_atomic_get_new_cdclk_state(state); 2672 struct intel_cdclk_config cdclk_config; 2673 enum pipe pipe; 2674 2675 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2676 &new_cdclk_state->actual)) 2677 return; 2678 2679 if (display->platform.dg2) 2680 intel_cdclk_pcode_pre_notify(state); 2681 2682 if (new_cdclk_state->disable_pipes) { 2683 cdclk_config = new_cdclk_state->actual; 2684 pipe = INVALID_PIPE; 2685 } else { 2686 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2687 cdclk_config = new_cdclk_state->actual; 2688 pipe = new_cdclk_state->pipe; 2689 } else { 2690 cdclk_config = old_cdclk_state->actual; 2691 pipe = INVALID_PIPE; 2692 } 2693 2694 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2695 old_cdclk_state->actual.voltage_level); 2696 } 2697 2698 /* 2699 * mbus joining will be changed later by 2700 * intel_dbuf_mbus_{pre,post}_ddb_update() 2701 */ 2702 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2703 2704 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2705 2706 intel_set_cdclk(display, &cdclk_config, pipe, 2707 "Pre changing CDCLK to"); 2708 } 2709 2710 /** 2711 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2712 * @state: intel atomic state 2713 * 2714 * Program the hardware after updating the HW plane state based on the 2715 * new CDCLK state, if necessary. 2716 */ 2717 void 2718 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2719 { 2720 struct intel_display *display = to_intel_display(state); 2721 const struct intel_cdclk_state *old_cdclk_state = 2722 intel_atomic_get_old_cdclk_state(state); 2723 const struct intel_cdclk_state *new_cdclk_state = 2724 intel_atomic_get_new_cdclk_state(state); 2725 enum pipe pipe; 2726 2727 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2728 &new_cdclk_state->actual)) 2729 return; 2730 2731 if (display->platform.dg2) 2732 intel_cdclk_pcode_post_notify(state); 2733 2734 if (!new_cdclk_state->disable_pipes && 2735 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2736 pipe = new_cdclk_state->pipe; 2737 else 2738 pipe = INVALID_PIPE; 2739 2740 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2741 2742 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, 2743 "Post changing CDCLK to"); 2744 } 2745 2746 /* pixels per CDCLK */ 2747 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) 2748 { 2749 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; 2750 } 2751 2752 /* max pixel rate as % of CDCLK (not accounting for PPC) */ 2753 static int intel_cdclk_guardband(struct intel_display *display) 2754 { 2755 if (DISPLAY_VER(display) >= 9 || 2756 display->platform.broadwell || display->platform.haswell) 2757 return 100; 2758 else if (display->platform.cherryview) 2759 return 95; 2760 else 2761 return 90; 2762 } 2763 2764 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2765 { 2766 struct intel_display *display = to_intel_display(crtc_state); 2767 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 2768 int guardband = intel_cdclk_guardband(display); 2769 int pixel_rate = crtc_state->pixel_rate; 2770 2771 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); 2772 } 2773 2774 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2775 { 2776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2777 struct intel_display *display = to_intel_display(crtc); 2778 struct intel_plane *plane; 2779 int min_cdclk = 0; 2780 2781 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2782 min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]); 2783 2784 return min_cdclk; 2785 } 2786 2787 static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2788 { 2789 int min_cdclk; 2790 2791 if (!crtc_state->hw.enable) 2792 return 0; 2793 2794 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2795 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state)); 2796 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state)); 2797 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); 2798 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state)); 2799 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2800 2801 return min_cdclk; 2802 } 2803 2804 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 2805 { 2806 struct intel_display *display = to_intel_display(state); 2807 struct intel_cdclk_state *cdclk_state = 2808 intel_atomic_get_new_cdclk_state(state); 2809 const struct intel_bw_state *bw_state; 2810 struct intel_crtc *crtc; 2811 struct intel_crtc_state *crtc_state; 2812 int min_cdclk, i; 2813 enum pipe pipe; 2814 2815 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2816 int ret; 2817 2818 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2819 if (min_cdclk < 0) 2820 return min_cdclk; 2821 2822 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2823 continue; 2824 2825 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2826 2827 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2828 if (ret) 2829 return ret; 2830 } 2831 2832 bw_state = intel_atomic_get_new_bw_state(state); 2833 if (bw_state) { 2834 min_cdclk = intel_bw_min_cdclk(display, bw_state); 2835 2836 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2837 int ret; 2838 2839 cdclk_state->bw_min_cdclk = min_cdclk; 2840 2841 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2842 if (ret) 2843 return ret; 2844 } 2845 } 2846 2847 min_cdclk = max(cdclk_state->force_min_cdclk, 2848 cdclk_state->bw_min_cdclk); 2849 for_each_pipe(display, pipe) 2850 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); 2851 2852 /* 2853 * Avoid glk_force_audio_cdclk() causing excessive screen 2854 * blinking when multiple pipes are active by making sure 2855 * CDCLK frequency is always high enough for audio. With a 2856 * single active pipe we can always change CDCLK frequency 2857 * by changing the cd2x divider (see glk_cdclk_table[]) and 2858 * thus a full modeset won't be needed then. 2859 */ 2860 if (display->platform.geminilake && cdclk_state->active_pipes && 2861 !is_power_of_2(cdclk_state->active_pipes)) 2862 min_cdclk = max(min_cdclk, 2 * 96000); 2863 2864 if (min_cdclk > display->cdclk.max_cdclk_freq) { 2865 drm_dbg_kms(display->drm, 2866 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2867 min_cdclk, display->cdclk.max_cdclk_freq); 2868 return -EINVAL; 2869 } 2870 2871 return min_cdclk; 2872 } 2873 2874 /* 2875 * Account for port clock min voltage level requirements. 2876 * This only really does something on DISPLA_VER >= 11 but can be 2877 * called on earlier platforms as well. 2878 * 2879 * Note that this functions assumes that 0 is 2880 * the lowest voltage value, and higher values 2881 * correspond to increasingly higher voltages. 2882 * 2883 * Should that relationship no longer hold on 2884 * future platforms this code will need to be 2885 * adjusted. 2886 */ 2887 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 2888 { 2889 struct intel_display *display = to_intel_display(state); 2890 struct intel_cdclk_state *cdclk_state = 2891 intel_atomic_get_new_cdclk_state(state); 2892 struct intel_crtc *crtc; 2893 struct intel_crtc_state *crtc_state; 2894 u8 min_voltage_level; 2895 int i; 2896 enum pipe pipe; 2897 2898 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2899 int ret; 2900 2901 if (crtc_state->hw.enable) 2902 min_voltage_level = crtc_state->min_voltage_level; 2903 else 2904 min_voltage_level = 0; 2905 2906 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2907 continue; 2908 2909 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2910 2911 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2912 if (ret) 2913 return ret; 2914 } 2915 2916 min_voltage_level = 0; 2917 for_each_pipe(display, pipe) 2918 min_voltage_level = max(min_voltage_level, 2919 cdclk_state->min_voltage_level[pipe]); 2920 2921 return min_voltage_level; 2922 } 2923 2924 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 2925 { 2926 struct intel_display *display = to_intel_display(state); 2927 struct intel_cdclk_state *cdclk_state = 2928 intel_atomic_get_new_cdclk_state(state); 2929 int min_cdclk, cdclk; 2930 2931 min_cdclk = intel_compute_min_cdclk(state); 2932 if (min_cdclk < 0) 2933 return min_cdclk; 2934 2935 cdclk = vlv_calc_cdclk(display, min_cdclk); 2936 2937 cdclk_state->logical.cdclk = cdclk; 2938 cdclk_state->logical.voltage_level = 2939 vlv_calc_voltage_level(display, cdclk); 2940 2941 if (!cdclk_state->active_pipes) { 2942 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); 2943 2944 cdclk_state->actual.cdclk = cdclk; 2945 cdclk_state->actual.voltage_level = 2946 vlv_calc_voltage_level(display, cdclk); 2947 } else { 2948 cdclk_state->actual = cdclk_state->logical; 2949 } 2950 2951 return 0; 2952 } 2953 2954 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 2955 { 2956 struct intel_cdclk_state *cdclk_state = 2957 intel_atomic_get_new_cdclk_state(state); 2958 int min_cdclk, cdclk; 2959 2960 min_cdclk = intel_compute_min_cdclk(state); 2961 if (min_cdclk < 0) 2962 return min_cdclk; 2963 2964 cdclk = bdw_calc_cdclk(min_cdclk); 2965 2966 cdclk_state->logical.cdclk = cdclk; 2967 cdclk_state->logical.voltage_level = 2968 bdw_calc_voltage_level(cdclk); 2969 2970 if (!cdclk_state->active_pipes) { 2971 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2972 2973 cdclk_state->actual.cdclk = cdclk; 2974 cdclk_state->actual.voltage_level = 2975 bdw_calc_voltage_level(cdclk); 2976 } else { 2977 cdclk_state->actual = cdclk_state->logical; 2978 } 2979 2980 return 0; 2981 } 2982 2983 static int skl_dpll0_vco(struct intel_atomic_state *state) 2984 { 2985 struct intel_display *display = to_intel_display(state); 2986 struct intel_cdclk_state *cdclk_state = 2987 intel_atomic_get_new_cdclk_state(state); 2988 struct intel_crtc *crtc; 2989 struct intel_crtc_state *crtc_state; 2990 int vco, i; 2991 2992 vco = cdclk_state->logical.vco; 2993 if (!vco) 2994 vco = display->cdclk.skl_preferred_vco_freq; 2995 2996 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2997 if (!crtc_state->hw.enable) 2998 continue; 2999 3000 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3001 continue; 3002 3003 /* 3004 * DPLL0 VCO may need to be adjusted to get the correct 3005 * clock for eDP. This will affect cdclk as well. 3006 */ 3007 switch (crtc_state->port_clock / 2) { 3008 case 108000: 3009 case 216000: 3010 vco = 8640000; 3011 break; 3012 default: 3013 vco = 8100000; 3014 break; 3015 } 3016 } 3017 3018 return vco; 3019 } 3020 3021 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3022 { 3023 struct intel_cdclk_state *cdclk_state = 3024 intel_atomic_get_new_cdclk_state(state); 3025 int min_cdclk, cdclk, vco; 3026 3027 min_cdclk = intel_compute_min_cdclk(state); 3028 if (min_cdclk < 0) 3029 return min_cdclk; 3030 3031 vco = skl_dpll0_vco(state); 3032 3033 cdclk = skl_calc_cdclk(min_cdclk, vco); 3034 3035 cdclk_state->logical.vco = vco; 3036 cdclk_state->logical.cdclk = cdclk; 3037 cdclk_state->logical.voltage_level = 3038 skl_calc_voltage_level(cdclk); 3039 3040 if (!cdclk_state->active_pipes) { 3041 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3042 3043 cdclk_state->actual.vco = vco; 3044 cdclk_state->actual.cdclk = cdclk; 3045 cdclk_state->actual.voltage_level = 3046 skl_calc_voltage_level(cdclk); 3047 } else { 3048 cdclk_state->actual = cdclk_state->logical; 3049 } 3050 3051 return 0; 3052 } 3053 3054 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3055 { 3056 struct intel_display *display = to_intel_display(state); 3057 struct intel_cdclk_state *cdclk_state = 3058 intel_atomic_get_new_cdclk_state(state); 3059 int min_cdclk, min_voltage_level, cdclk, vco; 3060 3061 min_cdclk = intel_compute_min_cdclk(state); 3062 if (min_cdclk < 0) 3063 return min_cdclk; 3064 3065 min_voltage_level = bxt_compute_min_voltage_level(state); 3066 if (min_voltage_level < 0) 3067 return min_voltage_level; 3068 3069 cdclk = bxt_calc_cdclk(display, min_cdclk); 3070 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3071 3072 cdclk_state->logical.vco = vco; 3073 cdclk_state->logical.cdclk = cdclk; 3074 cdclk_state->logical.voltage_level = 3075 max_t(int, min_voltage_level, 3076 intel_cdclk_calc_voltage_level(display, cdclk)); 3077 3078 if (!cdclk_state->active_pipes) { 3079 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); 3080 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3081 3082 cdclk_state->actual.vco = vco; 3083 cdclk_state->actual.cdclk = cdclk; 3084 cdclk_state->actual.voltage_level = 3085 intel_cdclk_calc_voltage_level(display, cdclk); 3086 } else { 3087 cdclk_state->actual = cdclk_state->logical; 3088 } 3089 3090 return 0; 3091 } 3092 3093 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3094 { 3095 int min_cdclk; 3096 3097 /* 3098 * We can't change the cdclk frequency, but we still want to 3099 * check that the required minimum frequency doesn't exceed 3100 * the actual cdclk frequency. 3101 */ 3102 min_cdclk = intel_compute_min_cdclk(state); 3103 if (min_cdclk < 0) 3104 return min_cdclk; 3105 3106 return 0; 3107 } 3108 3109 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3110 { 3111 struct intel_cdclk_state *cdclk_state; 3112 3113 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3114 if (!cdclk_state) 3115 return NULL; 3116 3117 cdclk_state->pipe = INVALID_PIPE; 3118 cdclk_state->disable_pipes = false; 3119 3120 return &cdclk_state->base; 3121 } 3122 3123 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3124 struct intel_global_state *state) 3125 { 3126 kfree(state); 3127 } 3128 3129 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3130 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3131 .atomic_destroy_state = intel_cdclk_destroy_state, 3132 }; 3133 3134 struct intel_cdclk_state * 3135 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3136 { 3137 struct intel_display *display = to_intel_display(state); 3138 struct intel_global_state *cdclk_state; 3139 3140 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); 3141 if (IS_ERR(cdclk_state)) 3142 return ERR_CAST(cdclk_state); 3143 3144 return to_intel_cdclk_state(cdclk_state); 3145 } 3146 3147 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 3148 bool *need_cdclk_calc) 3149 { 3150 const struct intel_cdclk_state *old_cdclk_state; 3151 const struct intel_cdclk_state *new_cdclk_state; 3152 struct intel_plane_state __maybe_unused *plane_state; 3153 struct intel_plane *plane; 3154 int ret; 3155 int i; 3156 3157 /* 3158 * active_planes bitmask has been updated, and potentially affected 3159 * planes are part of the state. We can now compute the minimum cdclk 3160 * for each plane. 3161 */ 3162 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 3163 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 3164 if (ret) 3165 return ret; 3166 } 3167 3168 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 3169 if (ret) 3170 return ret; 3171 3172 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3173 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3174 3175 if (new_cdclk_state && 3176 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 3177 *need_cdclk_calc = true; 3178 3179 return 0; 3180 } 3181 3182 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3183 { 3184 struct intel_cdclk_state *cdclk_state; 3185 3186 cdclk_state = intel_atomic_get_cdclk_state(state); 3187 if (IS_ERR(cdclk_state)) 3188 return PTR_ERR(cdclk_state); 3189 3190 cdclk_state->actual.joined_mbus = joined_mbus; 3191 cdclk_state->logical.joined_mbus = joined_mbus; 3192 3193 return intel_atomic_lock_global_state(&cdclk_state->base); 3194 } 3195 3196 int intel_cdclk_init(struct intel_display *display) 3197 { 3198 struct intel_cdclk_state *cdclk_state; 3199 3200 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 3201 if (!cdclk_state) 3202 return -ENOMEM; 3203 3204 intel_atomic_global_obj_init(display, &display->cdclk.obj, 3205 &cdclk_state->base, &intel_cdclk_funcs); 3206 3207 return 0; 3208 } 3209 3210 static bool intel_cdclk_need_serialize(struct intel_display *display, 3211 const struct intel_cdclk_state *old_cdclk_state, 3212 const struct intel_cdclk_state *new_cdclk_state) 3213 { 3214 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != 3215 hweight8(new_cdclk_state->active_pipes); 3216 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, 3217 &new_cdclk_state->actual); 3218 /* 3219 * We need to poke hw for gen >= 12, because we notify PCode if 3220 * pipe power well count changes. 3221 */ 3222 return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed); 3223 } 3224 3225 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3226 { 3227 struct intel_display *display = to_intel_display(state); 3228 const struct intel_cdclk_state *old_cdclk_state; 3229 struct intel_cdclk_state *new_cdclk_state; 3230 enum pipe pipe = INVALID_PIPE; 3231 int ret; 3232 3233 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3234 if (IS_ERR(new_cdclk_state)) 3235 return PTR_ERR(new_cdclk_state); 3236 3237 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3238 3239 new_cdclk_state->active_pipes = 3240 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3241 3242 ret = intel_cdclk_modeset_calc_cdclk(state); 3243 if (ret) 3244 return ret; 3245 3246 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { 3247 /* 3248 * Also serialize commits across all crtcs 3249 * if the actual hw needs to be poked. 3250 */ 3251 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3252 if (ret) 3253 return ret; 3254 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 3255 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 3256 intel_cdclk_changed(&old_cdclk_state->logical, 3257 &new_cdclk_state->logical)) { 3258 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3259 if (ret) 3260 return ret; 3261 } else { 3262 return 0; 3263 } 3264 3265 if (is_power_of_2(new_cdclk_state->active_pipes) && 3266 intel_cdclk_can_cd2x_update(display, 3267 &old_cdclk_state->actual, 3268 &new_cdclk_state->actual)) { 3269 struct intel_crtc *crtc; 3270 struct intel_crtc_state *crtc_state; 3271 3272 pipe = ilog2(new_cdclk_state->active_pipes); 3273 crtc = intel_crtc_for_pipe(display, pipe); 3274 3275 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3276 if (IS_ERR(crtc_state)) 3277 return PTR_ERR(crtc_state); 3278 3279 if (intel_crtc_needs_modeset(crtc_state)) 3280 pipe = INVALID_PIPE; 3281 } 3282 3283 if (intel_cdclk_can_crawl_and_squash(display, 3284 &old_cdclk_state->actual, 3285 &new_cdclk_state->actual)) { 3286 drm_dbg_kms(display->drm, 3287 "Can change cdclk via crawling and squashing\n"); 3288 } else if (intel_cdclk_can_squash(display, 3289 &old_cdclk_state->actual, 3290 &new_cdclk_state->actual)) { 3291 drm_dbg_kms(display->drm, 3292 "Can change cdclk via squashing\n"); 3293 } else if (intel_cdclk_can_crawl(display, 3294 &old_cdclk_state->actual, 3295 &new_cdclk_state->actual)) { 3296 drm_dbg_kms(display->drm, 3297 "Can change cdclk via crawling\n"); 3298 } else if (pipe != INVALID_PIPE) { 3299 new_cdclk_state->pipe = pipe; 3300 3301 drm_dbg_kms(display->drm, 3302 "Can change cdclk cd2x divider with pipe %c active\n", 3303 pipe_name(pipe)); 3304 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3305 &new_cdclk_state->actual)) { 3306 /* All pipes must be switched off while we change the cdclk. */ 3307 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3308 if (ret) 3309 return ret; 3310 3311 new_cdclk_state->disable_pipes = true; 3312 3313 drm_dbg_kms(display->drm, 3314 "Modeset required for cdclk change\n"); 3315 } 3316 3317 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != 3318 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { 3319 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); 3320 3321 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3322 if (ret) 3323 return ret; 3324 } 3325 3326 drm_dbg_kms(display->drm, 3327 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3328 new_cdclk_state->logical.cdclk, 3329 new_cdclk_state->actual.cdclk); 3330 drm_dbg_kms(display->drm, 3331 "New voltage level calculated to be logical %u, actual %u\n", 3332 new_cdclk_state->logical.voltage_level, 3333 new_cdclk_state->actual.voltage_level); 3334 3335 return 0; 3336 } 3337 3338 void intel_cdclk_update_hw_state(struct intel_display *display) 3339 { 3340 const struct intel_bw_state *bw_state = 3341 to_intel_bw_state(display->bw.obj.state); 3342 struct intel_cdclk_state *cdclk_state = 3343 to_intel_cdclk_state(display->cdclk.obj.state); 3344 struct intel_crtc *crtc; 3345 3346 cdclk_state->active_pipes = 0; 3347 3348 for_each_intel_crtc(display->drm, crtc) { 3349 const struct intel_crtc_state *crtc_state = 3350 to_intel_crtc_state(crtc->base.state); 3351 enum pipe pipe = crtc->pipe; 3352 3353 if (crtc_state->hw.active) 3354 cdclk_state->active_pipes |= BIT(pipe); 3355 3356 cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state); 3357 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level; 3358 } 3359 3360 cdclk_state->bw_min_cdclk = intel_bw_min_cdclk(display, bw_state); 3361 } 3362 3363 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc) 3364 { 3365 struct intel_display *display = to_intel_display(crtc); 3366 3367 intel_cdclk_update_hw_state(display); 3368 } 3369 3370 static int intel_compute_max_dotclk(struct intel_display *display) 3371 { 3372 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); 3373 int guardband = intel_cdclk_guardband(display); 3374 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3375 3376 return ppc * max_cdclk_freq * guardband / 100; 3377 } 3378 3379 /** 3380 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3381 * @display: display instance 3382 * 3383 * Determine the maximum CDCLK frequency the platform supports, and also 3384 * derive the maximum dot clock frequency the maximum CDCLK frequency 3385 * allows. 3386 */ 3387 void intel_update_max_cdclk(struct intel_display *display) 3388 { 3389 if (DISPLAY_VER(display) >= 30) { 3390 display->cdclk.max_cdclk_freq = 691200; 3391 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3392 if (display->cdclk.hw.ref == 24000) 3393 display->cdclk.max_cdclk_freq = 552000; 3394 else 3395 display->cdclk.max_cdclk_freq = 556800; 3396 } else if (DISPLAY_VER(display) >= 11) { 3397 if (display->cdclk.hw.ref == 24000) 3398 display->cdclk.max_cdclk_freq = 648000; 3399 else 3400 display->cdclk.max_cdclk_freq = 652800; 3401 } else if (display->platform.geminilake) { 3402 display->cdclk.max_cdclk_freq = 316800; 3403 } else if (display->platform.broxton) { 3404 display->cdclk.max_cdclk_freq = 624000; 3405 } else if (DISPLAY_VER(display) == 9) { 3406 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3407 int max_cdclk, vco; 3408 3409 vco = display->cdclk.skl_preferred_vco_freq; 3410 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 3411 3412 /* 3413 * Use the lower (vco 8640) cdclk values as a 3414 * first guess. skl_calc_cdclk() will correct it 3415 * if the preferred vco is 8100 instead. 3416 */ 3417 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3418 max_cdclk = 617143; 3419 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3420 max_cdclk = 540000; 3421 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3422 max_cdclk = 432000; 3423 else 3424 max_cdclk = 308571; 3425 3426 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3427 } else if (display->platform.broadwell) { 3428 /* 3429 * FIXME with extra cooling we can allow 3430 * 540 MHz for ULX and 675 Mhz for ULT. 3431 * How can we know if extra cooling is 3432 * available? PCI ID, VTB, something else? 3433 */ 3434 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3435 display->cdclk.max_cdclk_freq = 450000; 3436 else if (display->platform.broadwell_ulx) 3437 display->cdclk.max_cdclk_freq = 450000; 3438 else if (display->platform.broadwell_ult) 3439 display->cdclk.max_cdclk_freq = 540000; 3440 else 3441 display->cdclk.max_cdclk_freq = 675000; 3442 } else if (display->platform.cherryview) { 3443 display->cdclk.max_cdclk_freq = 320000; 3444 } else if (display->platform.valleyview) { 3445 display->cdclk.max_cdclk_freq = 400000; 3446 } else { 3447 /* otherwise assume cdclk is fixed */ 3448 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; 3449 } 3450 3451 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); 3452 3453 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", 3454 display->cdclk.max_cdclk_freq); 3455 3456 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", 3457 display->cdclk.max_dotclk_freq); 3458 } 3459 3460 /** 3461 * intel_update_cdclk - Determine the current CDCLK frequency 3462 * @display: display instance 3463 * 3464 * Determine the current CDCLK frequency. 3465 */ 3466 void intel_update_cdclk(struct intel_display *display) 3467 { 3468 intel_cdclk_get_cdclk(display, &display->cdclk.hw); 3469 3470 /* 3471 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3472 * Programmng [sic] note: bit[9:2] should be programmed to the number 3473 * of cdclk that generates 4MHz reference clock freq which is used to 3474 * generate GMBus clock. This will vary with the cdclk freq. 3475 */ 3476 if (display->platform.valleyview || display->platform.cherryview) 3477 intel_de_write(display, GMBUSFREQ_VLV, 3478 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); 3479 } 3480 3481 static int dg1_rawclk(struct intel_display *display) 3482 { 3483 /* 3484 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3485 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3486 */ 3487 intel_de_write(display, PCH_RAWCLK_FREQ, 3488 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3489 3490 return 38400; 3491 } 3492 3493 static int cnp_rawclk(struct intel_display *display) 3494 { 3495 int divider, fraction; 3496 u32 rawclk; 3497 3498 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3499 /* 24 MHz */ 3500 divider = 24000; 3501 fraction = 0; 3502 } else { 3503 /* 19.2 MHz */ 3504 divider = 19000; 3505 fraction = 200; 3506 } 3507 3508 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3509 if (fraction) { 3510 int numerator = 1; 3511 3512 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3513 fraction) - 1); 3514 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 3515 rawclk |= ICP_RAWCLK_NUM(numerator); 3516 } 3517 3518 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); 3519 return divider + fraction; 3520 } 3521 3522 static int pch_rawclk(struct intel_display *display) 3523 { 3524 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3525 } 3526 3527 static int vlv_hrawclk(struct intel_display *display) 3528 { 3529 /* RAWCLK_FREQ_VLV register updated from power well code */ 3530 return vlv_get_cck_clock_hpll(display->drm, "hrawclk", 3531 CCK_DISPLAY_REF_CLOCK_CONTROL); 3532 } 3533 3534 static int i9xx_hrawclk(struct intel_display *display) 3535 { 3536 struct drm_i915_private *i915 = to_i915(display->drm); 3537 3538 /* hrawclock is 1/4 the FSB frequency */ 3539 return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); 3540 } 3541 3542 /** 3543 * intel_read_rawclk - Determine the current RAWCLK frequency 3544 * @display: display instance 3545 * 3546 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3547 * frequency clock so this needs to done only once. 3548 */ 3549 u32 intel_read_rawclk(struct intel_display *display) 3550 { 3551 u32 freq; 3552 3553 if (INTEL_PCH_TYPE(display) >= PCH_MTL) 3554 /* 3555 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3556 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3557 * not need to be programmed." 3558 */ 3559 freq = 38400; 3560 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 3561 freq = dg1_rawclk(display); 3562 else if (INTEL_PCH_TYPE(display) >= PCH_CNP) 3563 freq = cnp_rawclk(display); 3564 else if (HAS_PCH_SPLIT(display)) 3565 freq = pch_rawclk(display); 3566 else if (display->platform.valleyview || display->platform.cherryview) 3567 freq = vlv_hrawclk(display); 3568 else if (DISPLAY_VER(display) >= 3) 3569 freq = i9xx_hrawclk(display); 3570 else 3571 /* no rawclk on other platforms, or no need to know it */ 3572 return 0; 3573 3574 return freq; 3575 } 3576 3577 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3578 { 3579 struct intel_display *display = m->private; 3580 3581 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); 3582 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); 3583 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); 3584 3585 return 0; 3586 } 3587 3588 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3589 3590 void intel_cdclk_debugfs_register(struct intel_display *display) 3591 { 3592 struct drm_minor *minor = display->drm->primary; 3593 3594 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, 3595 display, &i915_cdclk_info_fops); 3596 } 3597 3598 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { 3599 .get_cdclk = bxt_get_cdclk, 3600 .set_cdclk = bxt_set_cdclk, 3601 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3602 .calc_voltage_level = xe3lpd_calc_voltage_level, 3603 }; 3604 3605 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3606 .get_cdclk = bxt_get_cdclk, 3607 .set_cdclk = bxt_set_cdclk, 3608 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3609 .calc_voltage_level = rplu_calc_voltage_level, 3610 }; 3611 3612 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3613 .get_cdclk = bxt_get_cdclk, 3614 .set_cdclk = bxt_set_cdclk, 3615 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3616 .calc_voltage_level = tgl_calc_voltage_level, 3617 }; 3618 3619 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3620 .get_cdclk = bxt_get_cdclk, 3621 .set_cdclk = bxt_set_cdclk, 3622 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3623 .calc_voltage_level = ehl_calc_voltage_level, 3624 }; 3625 3626 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3627 .get_cdclk = bxt_get_cdclk, 3628 .set_cdclk = bxt_set_cdclk, 3629 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3630 .calc_voltage_level = icl_calc_voltage_level, 3631 }; 3632 3633 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3634 .get_cdclk = bxt_get_cdclk, 3635 .set_cdclk = bxt_set_cdclk, 3636 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3637 .calc_voltage_level = bxt_calc_voltage_level, 3638 }; 3639 3640 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3641 .get_cdclk = skl_get_cdclk, 3642 .set_cdclk = skl_set_cdclk, 3643 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3644 }; 3645 3646 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3647 .get_cdclk = bdw_get_cdclk, 3648 .set_cdclk = bdw_set_cdclk, 3649 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3650 }; 3651 3652 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3653 .get_cdclk = vlv_get_cdclk, 3654 .set_cdclk = chv_set_cdclk, 3655 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3656 }; 3657 3658 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3659 .get_cdclk = vlv_get_cdclk, 3660 .set_cdclk = vlv_set_cdclk, 3661 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3662 }; 3663 3664 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3665 .get_cdclk = hsw_get_cdclk, 3666 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3667 }; 3668 3669 /* SNB, IVB, 965G, 945G */ 3670 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3671 .get_cdclk = fixed_400mhz_get_cdclk, 3672 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3673 }; 3674 3675 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3676 .get_cdclk = fixed_450mhz_get_cdclk, 3677 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3678 }; 3679 3680 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3681 .get_cdclk = gm45_get_cdclk, 3682 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3683 }; 3684 3685 /* G45 uses G33 */ 3686 3687 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3688 .get_cdclk = i965gm_get_cdclk, 3689 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3690 }; 3691 3692 /* i965G uses fixed 400 */ 3693 3694 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3695 .get_cdclk = pnv_get_cdclk, 3696 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3697 }; 3698 3699 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3700 .get_cdclk = g33_get_cdclk, 3701 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3702 }; 3703 3704 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3705 .get_cdclk = i945gm_get_cdclk, 3706 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3707 }; 3708 3709 /* i945G uses fixed 400 */ 3710 3711 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3712 .get_cdclk = i915gm_get_cdclk, 3713 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3714 }; 3715 3716 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3717 .get_cdclk = fixed_333mhz_get_cdclk, 3718 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3719 }; 3720 3721 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3722 .get_cdclk = fixed_266mhz_get_cdclk, 3723 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3724 }; 3725 3726 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3727 .get_cdclk = i85x_get_cdclk, 3728 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3729 }; 3730 3731 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3732 .get_cdclk = fixed_200mhz_get_cdclk, 3733 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3734 }; 3735 3736 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3737 .get_cdclk = fixed_133mhz_get_cdclk, 3738 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3739 }; 3740 3741 /** 3742 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3743 * @display: display instance 3744 */ 3745 void intel_init_cdclk_hooks(struct intel_display *display) 3746 { 3747 if (DISPLAY_VER(display) >= 30) { 3748 display->funcs.cdclk = &xe3lpd_cdclk_funcs; 3749 display->cdclk.table = xe3lpd_cdclk_table; 3750 } else if (DISPLAY_VER(display) >= 20) { 3751 display->funcs.cdclk = &rplu_cdclk_funcs; 3752 display->cdclk.table = xe2lpd_cdclk_table; 3753 } else if (DISPLAY_VERx100(display) >= 1401) { 3754 display->funcs.cdclk = &rplu_cdclk_funcs; 3755 display->cdclk.table = xe2hpd_cdclk_table; 3756 } else if (DISPLAY_VER(display) >= 14) { 3757 display->funcs.cdclk = &rplu_cdclk_funcs; 3758 display->cdclk.table = mtl_cdclk_table; 3759 } else if (display->platform.dg2) { 3760 display->funcs.cdclk = &tgl_cdclk_funcs; 3761 display->cdclk.table = dg2_cdclk_table; 3762 } else if (display->platform.alderlake_p) { 3763 /* Wa_22011320316:adl-p[a0] */ 3764 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 3765 display->cdclk.table = adlp_a_step_cdclk_table; 3766 display->funcs.cdclk = &tgl_cdclk_funcs; 3767 } else if (display->platform.alderlake_p_raptorlake_u) { 3768 display->cdclk.table = rplu_cdclk_table; 3769 display->funcs.cdclk = &rplu_cdclk_funcs; 3770 } else { 3771 display->cdclk.table = adlp_cdclk_table; 3772 display->funcs.cdclk = &tgl_cdclk_funcs; 3773 } 3774 } else if (display->platform.rocketlake) { 3775 display->funcs.cdclk = &tgl_cdclk_funcs; 3776 display->cdclk.table = rkl_cdclk_table; 3777 } else if (DISPLAY_VER(display) >= 12) { 3778 display->funcs.cdclk = &tgl_cdclk_funcs; 3779 display->cdclk.table = icl_cdclk_table; 3780 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3781 display->funcs.cdclk = &ehl_cdclk_funcs; 3782 display->cdclk.table = icl_cdclk_table; 3783 } else if (DISPLAY_VER(display) >= 11) { 3784 display->funcs.cdclk = &icl_cdclk_funcs; 3785 display->cdclk.table = icl_cdclk_table; 3786 } else if (display->platform.geminilake || display->platform.broxton) { 3787 display->funcs.cdclk = &bxt_cdclk_funcs; 3788 if (display->platform.geminilake) 3789 display->cdclk.table = glk_cdclk_table; 3790 else 3791 display->cdclk.table = bxt_cdclk_table; 3792 } else if (DISPLAY_VER(display) == 9) { 3793 display->funcs.cdclk = &skl_cdclk_funcs; 3794 } else if (display->platform.broadwell) { 3795 display->funcs.cdclk = &bdw_cdclk_funcs; 3796 } else if (display->platform.haswell) { 3797 display->funcs.cdclk = &hsw_cdclk_funcs; 3798 } else if (display->platform.cherryview) { 3799 display->funcs.cdclk = &chv_cdclk_funcs; 3800 } else if (display->platform.valleyview) { 3801 display->funcs.cdclk = &vlv_cdclk_funcs; 3802 } else if (display->platform.sandybridge || display->platform.ivybridge) { 3803 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3804 } else if (display->platform.ironlake) { 3805 display->funcs.cdclk = &ilk_cdclk_funcs; 3806 } else if (display->platform.gm45) { 3807 display->funcs.cdclk = &gm45_cdclk_funcs; 3808 } else if (display->platform.g45) { 3809 display->funcs.cdclk = &g33_cdclk_funcs; 3810 } else if (display->platform.i965gm) { 3811 display->funcs.cdclk = &i965gm_cdclk_funcs; 3812 } else if (display->platform.i965g) { 3813 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3814 } else if (display->platform.pineview) { 3815 display->funcs.cdclk = &pnv_cdclk_funcs; 3816 } else if (display->platform.g33) { 3817 display->funcs.cdclk = &g33_cdclk_funcs; 3818 } else if (display->platform.i945gm) { 3819 display->funcs.cdclk = &i945gm_cdclk_funcs; 3820 } else if (display->platform.i945g) { 3821 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3822 } else if (display->platform.i915gm) { 3823 display->funcs.cdclk = &i915gm_cdclk_funcs; 3824 } else if (display->platform.i915g) { 3825 display->funcs.cdclk = &i915g_cdclk_funcs; 3826 } else if (display->platform.i865g) { 3827 display->funcs.cdclk = &i865g_cdclk_funcs; 3828 } else if (display->platform.i85x) { 3829 display->funcs.cdclk = &i85x_cdclk_funcs; 3830 } else if (display->platform.i845g) { 3831 display->funcs.cdclk = &i845g_cdclk_funcs; 3832 } else if (display->platform.i830) { 3833 display->funcs.cdclk = &i830_cdclk_funcs; 3834 } 3835 3836 if (drm_WARN(display->drm, !display->funcs.cdclk, 3837 "Unknown platform. Assuming i830\n")) 3838 display->funcs.cdclk = &i830_cdclk_funcs; 3839 } 3840