1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/iopoll.h> 26 #include <linux/time.h> 27 28 #include <drm/drm_fixed.h> 29 #include <drm/drm_print.h> 30 31 #include "soc/intel_dram.h" 32 33 #include "hsw_ips.h" 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "i915_utils.h" 37 #include "intel_atomic.h" 38 #include "intel_audio.h" 39 #include "intel_bw.h" 40 #include "intel_cdclk.h" 41 #include "intel_crtc.h" 42 #include "intel_de.h" 43 #include "intel_display_regs.h" 44 #include "intel_display_types.h" 45 #include "intel_mchbar_regs.h" 46 #include "intel_pci_config.h" 47 #include "intel_pcode.h" 48 #include "intel_plane.h" 49 #include "intel_psr.h" 50 #include "intel_vdsc.h" 51 #include "skl_watermark.h" 52 #include "skl_watermark_regs.h" 53 #include "vlv_dsi.h" 54 #include "vlv_sideband.h" 55 56 /** 57 * DOC: CDCLK / RAWCLK 58 * 59 * The display engine uses several different clocks to do its work. There 60 * are two main clocks involved that aren't directly related to the actual 61 * pixel clock or any symbol/bit clock of the actual output port. These 62 * are the core display clock (CDCLK) and RAWCLK. 63 * 64 * CDCLK clocks most of the display pipe logic, and thus its frequency 65 * must be high enough to support the rate at which pixels are flowing 66 * through the pipes. Downscaling must also be accounted as that increases 67 * the effective pixel rate. 68 * 69 * On several platforms the CDCLK frequency can be changed dynamically 70 * to minimize power consumption for a given display configuration. 71 * Typically changes to the CDCLK frequency require all the display pipes 72 * to be shut down while the frequency is being changed. 73 * 74 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 75 * DMC will not change the active CDCLK frequency however, so that part 76 * will still be performed by the driver directly. 77 * 78 * There are multiple components involved in the generation of the CDCLK 79 * frequency: 80 * 81 * - We have the CDCLK PLL, which generates an output clock based on a 82 * reference clock and a ratio parameter. 83 * - The CD2X Divider, which divides the output of the PLL based on a 84 * divisor selected from a set of pre-defined choices. 85 * - The CD2X Squasher, which further divides the output based on a 86 * waveform represented as a sequence of bits where each zero 87 * "squashes out" a clock cycle. 88 * - And, finally, a fixed divider that divides the output frequency by 2. 89 * 90 * As such, the resulting CDCLK frequency can be calculated with the 91 * following formula: 92 * 93 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 94 * 95 * , where vco is the frequency generated by the PLL; cd2x_div 96 * represents the CD2X Divider; sq_len and sq_div are the bit length 97 * and the number of high bits for the CD2X Squasher waveform, respectively; 98 * and 2 represents the fixed divider. 99 * 100 * Note that some older platforms do not contain the CD2X Divider 101 * and/or CD2X Squasher, in which case we can ignore their respective 102 * factors in the formula above. 103 * 104 * Several methods exist to change the CDCLK frequency, which ones are 105 * supported depends on the platform: 106 * 107 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 108 * - CD2X divider update. Single pipe can be active as the divider update 109 * can be synchronized with the pipe's start of vblank. 110 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 111 * - Squash waveform update. Pipes can be active. 112 * - Crawl and squash can also be done back to back. Pipes can be active. 113 * 114 * RAWCLK is a fixed frequency clock, often used by various auxiliary 115 * blocks such as AUX CH or backlight PWM. Hence the only thing we 116 * really need to know about RAWCLK is its frequency so that various 117 * dividers can be programmed correctly. 118 */ 119 120 struct intel_cdclk_state { 121 struct intel_global_state base; 122 123 /* 124 * Logical configuration of cdclk (used for all scaling, 125 * watermark, etc. calculations and checks). This is 126 * computed as if all enabled crtcs were active. 127 */ 128 struct intel_cdclk_config logical; 129 130 /* 131 * Actual configuration of cdclk, can be different from the 132 * logical configuration only when all crtc's are DPMS off. 133 */ 134 struct intel_cdclk_config actual; 135 136 /* minimum acceptable cdclk to satisfy bandwidth requirements */ 137 int bw_min_cdclk; 138 /* minimum acceptable cdclk for each pipe */ 139 int min_cdclk[I915_MAX_PIPES]; 140 /* minimum acceptable voltage level for each pipe */ 141 u8 min_voltage_level[I915_MAX_PIPES]; 142 143 /* pipe to which cd2x update is synchronized */ 144 enum pipe pipe; 145 146 /* forced minimum cdclk for glk+ audio w/a */ 147 int force_min_cdclk; 148 149 /* bitmask of active pipes */ 150 u8 active_pipes; 151 152 /* update cdclk with pipes disabled */ 153 bool disable_pipes; 154 }; 155 156 struct intel_cdclk_funcs { 157 void (*get_cdclk)(struct intel_display *display, 158 struct intel_cdclk_config *cdclk_config); 159 void (*set_cdclk)(struct intel_display *display, 160 const struct intel_cdclk_config *cdclk_config, 161 enum pipe pipe); 162 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 163 u8 (*calc_voltage_level)(int cdclk); 164 }; 165 166 void intel_cdclk_get_cdclk(struct intel_display *display, 167 struct intel_cdclk_config *cdclk_config) 168 { 169 display->funcs.cdclk->get_cdclk(display, cdclk_config); 170 } 171 172 static void intel_cdclk_set_cdclk(struct intel_display *display, 173 const struct intel_cdclk_config *cdclk_config, 174 enum pipe pipe) 175 { 176 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); 177 } 178 179 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 180 { 181 struct intel_display *display = to_intel_display(state); 182 183 return display->funcs.cdclk->modeset_calc_cdclk(state); 184 } 185 186 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, 187 int cdclk) 188 { 189 return display->funcs.cdclk->calc_voltage_level(cdclk); 190 } 191 192 static void fixed_133mhz_get_cdclk(struct intel_display *display, 193 struct intel_cdclk_config *cdclk_config) 194 { 195 cdclk_config->cdclk = 133333; 196 } 197 198 static void fixed_200mhz_get_cdclk(struct intel_display *display, 199 struct intel_cdclk_config *cdclk_config) 200 { 201 cdclk_config->cdclk = 200000; 202 } 203 204 static void fixed_266mhz_get_cdclk(struct intel_display *display, 205 struct intel_cdclk_config *cdclk_config) 206 { 207 cdclk_config->cdclk = 266667; 208 } 209 210 static void fixed_333mhz_get_cdclk(struct intel_display *display, 211 struct intel_cdclk_config *cdclk_config) 212 { 213 cdclk_config->cdclk = 333333; 214 } 215 216 static void fixed_400mhz_get_cdclk(struct intel_display *display, 217 struct intel_cdclk_config *cdclk_config) 218 { 219 cdclk_config->cdclk = 400000; 220 } 221 222 static void fixed_450mhz_get_cdclk(struct intel_display *display, 223 struct intel_cdclk_config *cdclk_config) 224 { 225 cdclk_config->cdclk = 450000; 226 } 227 228 static void i85x_get_cdclk(struct intel_display *display, 229 struct intel_cdclk_config *cdclk_config) 230 { 231 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 232 u16 hpllcc = 0; 233 234 /* 235 * 852GM/852GMV only supports 133 MHz and the HPLLCC 236 * encoding is different :( 237 * FIXME is this the right way to detect 852GM/852GMV? 238 */ 239 if (pdev->revision == 0x1) { 240 cdclk_config->cdclk = 133333; 241 return; 242 } 243 244 pci_bus_read_config_word(pdev->bus, 245 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 246 247 /* Assume that the hardware is in the high speed state. This 248 * should be the default. 249 */ 250 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 251 case GC_CLOCK_133_200: 252 case GC_CLOCK_133_200_2: 253 case GC_CLOCK_100_200: 254 cdclk_config->cdclk = 200000; 255 break; 256 case GC_CLOCK_166_250: 257 cdclk_config->cdclk = 250000; 258 break; 259 case GC_CLOCK_100_133: 260 cdclk_config->cdclk = 133333; 261 break; 262 case GC_CLOCK_133_266: 263 case GC_CLOCK_133_266_2: 264 case GC_CLOCK_166_266: 265 cdclk_config->cdclk = 266667; 266 break; 267 } 268 } 269 270 static void i915gm_get_cdclk(struct intel_display *display, 271 struct intel_cdclk_config *cdclk_config) 272 { 273 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 274 u16 gcfgc = 0; 275 276 pci_read_config_word(pdev, GCFGC, &gcfgc); 277 278 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 279 cdclk_config->cdclk = 133333; 280 return; 281 } 282 283 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 284 case GC_DISPLAY_CLOCK_333_320_MHZ: 285 cdclk_config->cdclk = 333333; 286 break; 287 default: 288 case GC_DISPLAY_CLOCK_190_200_MHZ: 289 cdclk_config->cdclk = 190000; 290 break; 291 } 292 } 293 294 static void i945gm_get_cdclk(struct intel_display *display, 295 struct intel_cdclk_config *cdclk_config) 296 { 297 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 298 u16 gcfgc = 0; 299 300 pci_read_config_word(pdev, GCFGC, &gcfgc); 301 302 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 303 cdclk_config->cdclk = 133333; 304 return; 305 } 306 307 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 308 case GC_DISPLAY_CLOCK_333_320_MHZ: 309 cdclk_config->cdclk = 320000; 310 break; 311 default: 312 case GC_DISPLAY_CLOCK_190_200_MHZ: 313 cdclk_config->cdclk = 200000; 314 break; 315 } 316 } 317 318 static unsigned int intel_hpll_vco(struct intel_display *display) 319 { 320 static const unsigned int blb_vco[8] = { 321 [0] = 3200000, 322 [1] = 4000000, 323 [2] = 5333333, 324 [3] = 4800000, 325 [4] = 6400000, 326 }; 327 static const unsigned int pnv_vco[8] = { 328 [0] = 3200000, 329 [1] = 4000000, 330 [2] = 5333333, 331 [3] = 4800000, 332 [4] = 2666667, 333 }; 334 static const unsigned int cl_vco[8] = { 335 [0] = 3200000, 336 [1] = 4000000, 337 [2] = 5333333, 338 [3] = 6400000, 339 [4] = 3333333, 340 [5] = 3566667, 341 [6] = 4266667, 342 }; 343 static const unsigned int elk_vco[8] = { 344 [0] = 3200000, 345 [1] = 4000000, 346 [2] = 5333333, 347 [3] = 4800000, 348 }; 349 static const unsigned int ctg_vco[8] = { 350 [0] = 3200000, 351 [1] = 4000000, 352 [2] = 5333333, 353 [3] = 6400000, 354 [4] = 2666667, 355 [5] = 4266667, 356 }; 357 const unsigned int *vco_table; 358 unsigned int vco; 359 u8 tmp = 0; 360 361 /* FIXME other chipsets? */ 362 if (display->platform.gm45) 363 vco_table = ctg_vco; 364 else if (display->platform.g45) 365 vco_table = elk_vco; 366 else if (display->platform.i965gm) 367 vco_table = cl_vco; 368 else if (display->platform.pineview) 369 vco_table = pnv_vco; 370 else if (display->platform.g33) 371 vco_table = blb_vco; 372 else 373 return 0; 374 375 tmp = intel_de_read(display, display->platform.pineview || 376 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); 377 378 vco = vco_table[tmp & 0x7]; 379 if (vco == 0) 380 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 381 tmp); 382 else 383 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); 384 385 return vco; 386 } 387 388 static void g33_get_cdclk(struct intel_display *display, 389 struct intel_cdclk_config *cdclk_config) 390 { 391 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 392 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 393 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 394 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 395 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 396 const u8 *div_table; 397 unsigned int cdclk_sel; 398 u16 tmp = 0; 399 400 cdclk_config->vco = intel_hpll_vco(display); 401 402 pci_read_config_word(pdev, GCFGC, &tmp); 403 404 cdclk_sel = (tmp >> 4) & 0x7; 405 406 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 407 goto fail; 408 409 switch (cdclk_config->vco) { 410 case 3200000: 411 div_table = div_3200; 412 break; 413 case 4000000: 414 div_table = div_4000; 415 break; 416 case 4800000: 417 div_table = div_4800; 418 break; 419 case 5333333: 420 div_table = div_5333; 421 break; 422 default: 423 goto fail; 424 } 425 426 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 427 div_table[cdclk_sel]); 428 return; 429 430 fail: 431 drm_err(display->drm, 432 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 433 cdclk_config->vco, tmp); 434 cdclk_config->cdclk = 190476; 435 } 436 437 static void pnv_get_cdclk(struct intel_display *display, 438 struct intel_cdclk_config *cdclk_config) 439 { 440 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 441 u16 gcfgc = 0; 442 443 pci_read_config_word(pdev, GCFGC, &gcfgc); 444 445 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 446 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 447 cdclk_config->cdclk = 266667; 448 break; 449 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 450 cdclk_config->cdclk = 333333; 451 break; 452 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 453 cdclk_config->cdclk = 444444; 454 break; 455 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 456 cdclk_config->cdclk = 200000; 457 break; 458 default: 459 drm_err(display->drm, 460 "Unknown pnv display core clock 0x%04x\n", gcfgc); 461 fallthrough; 462 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 463 cdclk_config->cdclk = 133333; 464 break; 465 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 466 cdclk_config->cdclk = 166667; 467 break; 468 } 469 } 470 471 static void i965gm_get_cdclk(struct intel_display *display, 472 struct intel_cdclk_config *cdclk_config) 473 { 474 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 475 static const u8 div_3200[] = { 16, 10, 8 }; 476 static const u8 div_4000[] = { 20, 12, 10 }; 477 static const u8 div_5333[] = { 24, 16, 14 }; 478 const u8 *div_table; 479 unsigned int cdclk_sel; 480 u16 tmp = 0; 481 482 cdclk_config->vco = intel_hpll_vco(display); 483 484 pci_read_config_word(pdev, GCFGC, &tmp); 485 486 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 487 488 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 489 goto fail; 490 491 switch (cdclk_config->vco) { 492 case 3200000: 493 div_table = div_3200; 494 break; 495 case 4000000: 496 div_table = div_4000; 497 break; 498 case 5333333: 499 div_table = div_5333; 500 break; 501 default: 502 goto fail; 503 } 504 505 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 506 div_table[cdclk_sel]); 507 return; 508 509 fail: 510 drm_err(display->drm, 511 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 512 cdclk_config->vco, tmp); 513 cdclk_config->cdclk = 200000; 514 } 515 516 static void gm45_get_cdclk(struct intel_display *display, 517 struct intel_cdclk_config *cdclk_config) 518 { 519 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 520 unsigned int cdclk_sel; 521 u16 tmp = 0; 522 523 cdclk_config->vco = intel_hpll_vco(display); 524 525 pci_read_config_word(pdev, GCFGC, &tmp); 526 527 cdclk_sel = (tmp >> 12) & 0x1; 528 529 switch (cdclk_config->vco) { 530 case 2666667: 531 case 4000000: 532 case 5333333: 533 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 534 break; 535 case 3200000: 536 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 537 break; 538 default: 539 drm_err(display->drm, 540 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 541 cdclk_config->vco, tmp); 542 cdclk_config->cdclk = 222222; 543 break; 544 } 545 } 546 547 static void hsw_get_cdclk(struct intel_display *display, 548 struct intel_cdclk_config *cdclk_config) 549 { 550 u32 lcpll = intel_de_read(display, LCPLL_CTL); 551 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 552 553 if (lcpll & LCPLL_CD_SOURCE_FCLK) 554 cdclk_config->cdclk = 800000; 555 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 556 cdclk_config->cdclk = 450000; 557 else if (freq == LCPLL_CLK_FREQ_450) 558 cdclk_config->cdclk = 450000; 559 else if (display->platform.haswell_ult) 560 cdclk_config->cdclk = 337500; 561 else 562 cdclk_config->cdclk = 540000; 563 } 564 565 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) 566 { 567 struct drm_i915_private *dev_priv = to_i915(display->drm); 568 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 569 333333 : 320000; 570 571 /* 572 * We seem to get an unstable or solid color picture at 200MHz. 573 * Not sure what's wrong. For now use 200MHz only when all pipes 574 * are off. 575 */ 576 if (display->platform.valleyview && min_cdclk > freq_320) 577 return 400000; 578 else if (min_cdclk > 266667) 579 return freq_320; 580 else if (min_cdclk > 0) 581 return 266667; 582 else 583 return 200000; 584 } 585 586 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 587 { 588 struct drm_i915_private *dev_priv = to_i915(display->drm); 589 590 if (display->platform.valleyview) { 591 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 592 return 2; 593 else if (cdclk >= 266667) 594 return 1; 595 else 596 return 0; 597 } else { 598 /* 599 * Specs are full of misinformation, but testing on actual 600 * hardware has shown that we just need to write the desired 601 * CCK divider into the Punit register. 602 */ 603 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 604 } 605 } 606 607 static void vlv_get_cdclk(struct intel_display *display, 608 struct intel_cdclk_config *cdclk_config) 609 { 610 u32 val; 611 612 vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 613 614 cdclk_config->vco = vlv_get_hpll_vco(display->drm); 615 cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk", 616 CCK_DISPLAY_CLOCK_CONTROL, 617 cdclk_config->vco); 618 619 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 620 621 vlv_iosf_sb_put(display->drm, 622 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 623 624 if (display->platform.valleyview) 625 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 626 DSPFREQGUAR_SHIFT; 627 else 628 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 629 DSPFREQGUAR_SHIFT_CHV; 630 } 631 632 static void vlv_program_pfi_credits(struct intel_display *display) 633 { 634 struct drm_i915_private *dev_priv = to_i915(display->drm); 635 unsigned int credits, default_credits; 636 637 if (display->platform.cherryview) 638 default_credits = PFI_CREDIT(12); 639 else 640 default_credits = PFI_CREDIT(8); 641 642 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 643 /* CHV suggested value is 31 or 63 */ 644 if (display->platform.cherryview) 645 credits = PFI_CREDIT_63; 646 else 647 credits = PFI_CREDIT(15); 648 } else { 649 credits = default_credits; 650 } 651 652 /* 653 * WA - write default credits before re-programming 654 * FIXME: should we also set the resend bit here? 655 */ 656 intel_de_write(display, GCI_CONTROL, 657 VGA_FAST_MODE_DISABLE | default_credits); 658 659 intel_de_write(display, GCI_CONTROL, 660 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 661 662 /* 663 * FIXME is this guaranteed to clear 664 * immediately or should we poll for it? 665 */ 666 drm_WARN_ON(display->drm, 667 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); 668 } 669 670 static void vlv_set_cdclk(struct intel_display *display, 671 const struct intel_cdclk_config *cdclk_config, 672 enum pipe pipe) 673 { 674 struct drm_i915_private *dev_priv = to_i915(display->drm); 675 int cdclk = cdclk_config->cdclk; 676 u32 val, cmd = cdclk_config->voltage_level; 677 intel_wakeref_t wakeref; 678 int ret; 679 680 switch (cdclk) { 681 case 400000: 682 case 333333: 683 case 320000: 684 case 266667: 685 case 200000: 686 break; 687 default: 688 MISSING_CASE(cdclk); 689 return; 690 } 691 692 /* There are cases where we can end up here with power domains 693 * off and a CDCLK frequency other than the minimum, like when 694 * issuing a modeset without actually changing any display after 695 * a system suspend. So grab the display core domain, which covers 696 * the HW blocks needed for the following programming. 697 */ 698 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 699 700 vlv_iosf_sb_get(display->drm, 701 BIT(VLV_IOSF_SB_CCK) | 702 BIT(VLV_IOSF_SB_BUNIT) | 703 BIT(VLV_IOSF_SB_PUNIT)); 704 705 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 706 val &= ~DSPFREQGUAR_MASK; 707 val |= (cmd << DSPFREQGUAR_SHIFT); 708 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); 709 710 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), 711 (val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 712 500, 50 * 1000, false); 713 if (ret) 714 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 715 716 if (cdclk == 400000) { 717 u32 divider; 718 719 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 720 cdclk) - 1; 721 722 /* adjust cdclk divider */ 723 val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL); 724 val &= ~CCK_FREQUENCY_VALUES; 725 val |= divider; 726 vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val); 727 728 ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL), 729 (val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 730 500, 50 * 1000, false); 731 if (ret) 732 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 733 } 734 735 /* adjust self-refresh exit latency value */ 736 val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC); 737 val &= ~0x7f; 738 739 /* 740 * For high bandwidth configs, we set a higher latency in the bunit 741 * so that the core display fetch happens in time to avoid underruns. 742 */ 743 if (cdclk == 400000) 744 val |= 4500 / 250; /* 4.5 usec */ 745 else 746 val |= 3000 / 250; /* 3.0 usec */ 747 vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val); 748 749 vlv_iosf_sb_put(display->drm, 750 BIT(VLV_IOSF_SB_CCK) | 751 BIT(VLV_IOSF_SB_BUNIT) | 752 BIT(VLV_IOSF_SB_PUNIT)); 753 754 intel_update_cdclk(display); 755 756 vlv_program_pfi_credits(display); 757 758 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 759 } 760 761 static void chv_set_cdclk(struct intel_display *display, 762 const struct intel_cdclk_config *cdclk_config, 763 enum pipe pipe) 764 { 765 int cdclk = cdclk_config->cdclk; 766 u32 val, cmd = cdclk_config->voltage_level; 767 intel_wakeref_t wakeref; 768 int ret; 769 770 switch (cdclk) { 771 case 333333: 772 case 320000: 773 case 266667: 774 case 200000: 775 break; 776 default: 777 MISSING_CASE(cdclk); 778 return; 779 } 780 781 /* There are cases where we can end up here with power domains 782 * off and a CDCLK frequency other than the minimum, like when 783 * issuing a modeset without actually changing any display after 784 * a system suspend. So grab the display core domain, which covers 785 * the HW blocks needed for the following programming. 786 */ 787 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 788 789 vlv_punit_get(display->drm); 790 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 791 val &= ~DSPFREQGUAR_MASK_CHV; 792 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 793 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); 794 795 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), 796 (val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 797 500, 50 * 1000, false); 798 if (ret) 799 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 800 801 vlv_punit_put(display->drm); 802 803 intel_update_cdclk(display); 804 805 vlv_program_pfi_credits(display); 806 807 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 808 } 809 810 static int bdw_calc_cdclk(int min_cdclk) 811 { 812 if (min_cdclk > 540000) 813 return 675000; 814 else if (min_cdclk > 450000) 815 return 540000; 816 else if (min_cdclk > 337500) 817 return 450000; 818 else 819 return 337500; 820 } 821 822 static u8 bdw_calc_voltage_level(int cdclk) 823 { 824 switch (cdclk) { 825 default: 826 case 337500: 827 return 2; 828 case 450000: 829 return 0; 830 case 540000: 831 return 1; 832 case 675000: 833 return 3; 834 } 835 } 836 837 static void bdw_get_cdclk(struct intel_display *display, 838 struct intel_cdclk_config *cdclk_config) 839 { 840 u32 lcpll = intel_de_read(display, LCPLL_CTL); 841 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 842 843 if (lcpll & LCPLL_CD_SOURCE_FCLK) 844 cdclk_config->cdclk = 800000; 845 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 846 cdclk_config->cdclk = 450000; 847 else if (freq == LCPLL_CLK_FREQ_450) 848 cdclk_config->cdclk = 450000; 849 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 850 cdclk_config->cdclk = 540000; 851 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 852 cdclk_config->cdclk = 337500; 853 else 854 cdclk_config->cdclk = 675000; 855 856 /* 857 * Can't read this out :( Let's assume it's 858 * at least what the CDCLK frequency requires. 859 */ 860 cdclk_config->voltage_level = 861 bdw_calc_voltage_level(cdclk_config->cdclk); 862 } 863 864 static u32 bdw_cdclk_freq_sel(int cdclk) 865 { 866 switch (cdclk) { 867 default: 868 MISSING_CASE(cdclk); 869 fallthrough; 870 case 337500: 871 return LCPLL_CLK_FREQ_337_5_BDW; 872 case 450000: 873 return LCPLL_CLK_FREQ_450; 874 case 540000: 875 return LCPLL_CLK_FREQ_54O_BDW; 876 case 675000: 877 return LCPLL_CLK_FREQ_675_BDW; 878 } 879 } 880 881 static void bdw_set_cdclk(struct intel_display *display, 882 const struct intel_cdclk_config *cdclk_config, 883 enum pipe pipe) 884 { 885 int cdclk = cdclk_config->cdclk; 886 int ret; 887 888 if (drm_WARN(display->drm, 889 (intel_de_read(display, LCPLL_CTL) & 890 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 891 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 892 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 893 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 894 "trying to change cdclk frequency with cdclk not enabled\n")) 895 return; 896 897 ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 898 if (ret) { 899 drm_err(display->drm, 900 "failed to inform pcode about cdclk change\n"); 901 return; 902 } 903 904 intel_de_rmw(display, LCPLL_CTL, 905 0, LCPLL_CD_SOURCE_FCLK); 906 907 /* 908 * According to the spec, it should be enough to poll for this 1 us. 909 * However, extensive testing shows that this can take longer. 910 */ 911 ret = intel_de_wait_custom(display, LCPLL_CTL, 912 LCPLL_CD_SOURCE_FCLK_DONE, LCPLL_CD_SOURCE_FCLK_DONE, 913 100, 0, NULL); 914 if (ret) 915 drm_err(display->drm, "Switching to FCLK failed\n"); 916 917 intel_de_rmw(display, LCPLL_CTL, 918 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 919 920 intel_de_rmw(display, LCPLL_CTL, 921 LCPLL_CD_SOURCE_FCLK, 0); 922 923 ret = intel_de_wait_custom(display, LCPLL_CTL, 924 LCPLL_CD_SOURCE_FCLK_DONE, 0, 925 1, 0, NULL); 926 if (ret) 927 drm_err(display->drm, "Switching back to LCPLL failed\n"); 928 929 intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ, 930 cdclk_config->voltage_level); 931 932 intel_de_write(display, CDCLK_FREQ, 933 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 934 935 intel_update_cdclk(display); 936 } 937 938 static int skl_calc_cdclk(int min_cdclk, int vco) 939 { 940 if (vco == 8640000) { 941 if (min_cdclk > 540000) 942 return 617143; 943 else if (min_cdclk > 432000) 944 return 540000; 945 else if (min_cdclk > 308571) 946 return 432000; 947 else 948 return 308571; 949 } else { 950 if (min_cdclk > 540000) 951 return 675000; 952 else if (min_cdclk > 450000) 953 return 540000; 954 else if (min_cdclk > 337500) 955 return 450000; 956 else 957 return 337500; 958 } 959 } 960 961 static u8 skl_calc_voltage_level(int cdclk) 962 { 963 if (cdclk > 540000) 964 return 3; 965 else if (cdclk > 450000) 966 return 2; 967 else if (cdclk > 337500) 968 return 1; 969 else 970 return 0; 971 } 972 973 static void skl_dpll0_update(struct intel_display *display, 974 struct intel_cdclk_config *cdclk_config) 975 { 976 u32 val; 977 978 cdclk_config->ref = 24000; 979 cdclk_config->vco = 0; 980 981 val = intel_de_read(display, LCPLL1_CTL); 982 if ((val & LCPLL_PLL_ENABLE) == 0) 983 return; 984 985 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) 986 return; 987 988 val = intel_de_read(display, DPLL_CTRL1); 989 990 if (drm_WARN_ON(display->drm, 991 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 992 DPLL_CTRL1_SSC(SKL_DPLL0) | 993 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 994 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 995 return; 996 997 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 998 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 999 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 1000 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 1001 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 1002 cdclk_config->vco = 8100000; 1003 break; 1004 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 1005 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 1006 cdclk_config->vco = 8640000; 1007 break; 1008 default: 1009 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 1010 break; 1011 } 1012 } 1013 1014 static void skl_get_cdclk(struct intel_display *display, 1015 struct intel_cdclk_config *cdclk_config) 1016 { 1017 u32 cdctl; 1018 1019 skl_dpll0_update(display, cdclk_config); 1020 1021 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 1022 1023 if (cdclk_config->vco == 0) 1024 goto out; 1025 1026 cdctl = intel_de_read(display, CDCLK_CTL); 1027 1028 if (cdclk_config->vco == 8640000) { 1029 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1030 case CDCLK_FREQ_450_432: 1031 cdclk_config->cdclk = 432000; 1032 break; 1033 case CDCLK_FREQ_337_308: 1034 cdclk_config->cdclk = 308571; 1035 break; 1036 case CDCLK_FREQ_540: 1037 cdclk_config->cdclk = 540000; 1038 break; 1039 case CDCLK_FREQ_675_617: 1040 cdclk_config->cdclk = 617143; 1041 break; 1042 default: 1043 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1044 break; 1045 } 1046 } else { 1047 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1048 case CDCLK_FREQ_450_432: 1049 cdclk_config->cdclk = 450000; 1050 break; 1051 case CDCLK_FREQ_337_308: 1052 cdclk_config->cdclk = 337500; 1053 break; 1054 case CDCLK_FREQ_540: 1055 cdclk_config->cdclk = 540000; 1056 break; 1057 case CDCLK_FREQ_675_617: 1058 cdclk_config->cdclk = 675000; 1059 break; 1060 default: 1061 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1062 break; 1063 } 1064 } 1065 1066 out: 1067 /* 1068 * Can't read this out :( Let's assume it's 1069 * at least what the CDCLK frequency requires. 1070 */ 1071 cdclk_config->voltage_level = 1072 skl_calc_voltage_level(cdclk_config->cdclk); 1073 } 1074 1075 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1076 static int skl_cdclk_decimal(int cdclk) 1077 { 1078 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1079 } 1080 1081 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) 1082 { 1083 bool changed = display->cdclk.skl_preferred_vco_freq != vco; 1084 1085 display->cdclk.skl_preferred_vco_freq = vco; 1086 1087 if (changed) 1088 intel_update_max_cdclk(display); 1089 } 1090 1091 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) 1092 { 1093 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 1094 1095 /* 1096 * We always enable DPLL0 with the lowest link rate possible, but still 1097 * taking into account the VCO required to operate the eDP panel at the 1098 * desired frequency. The usual DP link rates operate with a VCO of 1099 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1100 * The modeset code is responsible for the selection of the exact link 1101 * rate later on, with the constraint of choosing a frequency that 1102 * works with vco. 1103 */ 1104 if (vco == 8640000) 1105 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1106 else 1107 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1108 } 1109 1110 static void skl_dpll0_enable(struct intel_display *display, int vco) 1111 { 1112 intel_de_rmw(display, DPLL_CTRL1, 1113 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1114 DPLL_CTRL1_SSC(SKL_DPLL0) | 1115 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1116 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1117 skl_dpll0_link_rate(display, vco)); 1118 intel_de_posting_read(display, DPLL_CTRL1); 1119 1120 intel_de_rmw(display, LCPLL1_CTL, 1121 0, LCPLL_PLL_ENABLE); 1122 1123 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1124 drm_err(display->drm, "DPLL0 not locked\n"); 1125 1126 display->cdclk.hw.vco = vco; 1127 1128 /* We'll want to keep using the current vco from now on. */ 1129 skl_set_preferred_cdclk_vco(display, vco); 1130 } 1131 1132 static void skl_dpll0_disable(struct intel_display *display) 1133 { 1134 intel_de_rmw(display, LCPLL1_CTL, 1135 LCPLL_PLL_ENABLE, 0); 1136 1137 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1138 drm_err(display->drm, "Couldn't disable DPLL0\n"); 1139 1140 display->cdclk.hw.vco = 0; 1141 } 1142 1143 static u32 skl_cdclk_freq_sel(struct intel_display *display, 1144 int cdclk, int vco) 1145 { 1146 switch (cdclk) { 1147 default: 1148 drm_WARN_ON(display->drm, 1149 cdclk != display->cdclk.hw.bypass); 1150 drm_WARN_ON(display->drm, vco != 0); 1151 fallthrough; 1152 case 308571: 1153 case 337500: 1154 return CDCLK_FREQ_337_308; 1155 case 450000: 1156 case 432000: 1157 return CDCLK_FREQ_450_432; 1158 case 540000: 1159 return CDCLK_FREQ_540; 1160 case 617143: 1161 case 675000: 1162 return CDCLK_FREQ_675_617; 1163 } 1164 } 1165 1166 static void skl_set_cdclk(struct intel_display *display, 1167 const struct intel_cdclk_config *cdclk_config, 1168 enum pipe pipe) 1169 { 1170 int cdclk = cdclk_config->cdclk; 1171 int vco = cdclk_config->vco; 1172 u32 freq_select, cdclk_ctl; 1173 int ret; 1174 1175 /* 1176 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1177 * unsupported on SKL. In theory this should never happen since only 1178 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1179 * supported on SKL either, see the above WA. WARN whenever trying to 1180 * use the corresponding VCO freq as that always leads to using the 1181 * minimum 308MHz CDCLK. 1182 */ 1183 drm_WARN_ON_ONCE(display->drm, 1184 display->platform.skylake && vco == 8640000); 1185 1186 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 1187 SKL_CDCLK_PREPARE_FOR_CHANGE, 1188 SKL_CDCLK_READY_FOR_CHANGE, 1189 SKL_CDCLK_READY_FOR_CHANGE, 3); 1190 if (ret) { 1191 drm_err(display->drm, 1192 "Failed to inform PCU about cdclk change (%d)\n", ret); 1193 return; 1194 } 1195 1196 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); 1197 1198 if (display->cdclk.hw.vco != 0 && 1199 display->cdclk.hw.vco != vco) 1200 skl_dpll0_disable(display); 1201 1202 cdclk_ctl = intel_de_read(display, CDCLK_CTL); 1203 1204 if (display->cdclk.hw.vco != vco) { 1205 /* Wa Display #1183: skl,kbl,cfl */ 1206 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1207 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1208 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1209 } 1210 1211 /* Wa Display #1183: skl,kbl,cfl */ 1212 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1213 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1214 intel_de_posting_read(display, CDCLK_CTL); 1215 1216 if (display->cdclk.hw.vco != vco) 1217 skl_dpll0_enable(display, vco); 1218 1219 /* Wa Display #1183: skl,kbl,cfl */ 1220 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1221 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1222 1223 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1224 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1225 1226 /* Wa Display #1183: skl,kbl,cfl */ 1227 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1228 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1229 intel_de_posting_read(display, CDCLK_CTL); 1230 1231 /* inform PCU of the change */ 1232 intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, 1233 cdclk_config->voltage_level); 1234 1235 intel_update_cdclk(display); 1236 } 1237 1238 static void skl_sanitize_cdclk(struct intel_display *display) 1239 { 1240 u32 cdctl, expected; 1241 1242 /* 1243 * check if the pre-os initialized the display 1244 * There is SWF18 scratchpad register defined which is set by the 1245 * pre-os which can be used by the OS drivers to check the status 1246 */ 1247 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1248 goto sanitize; 1249 1250 intel_update_cdclk(display); 1251 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1252 1253 /* Is PLL enabled and locked ? */ 1254 if (display->cdclk.hw.vco == 0 || 1255 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 1256 goto sanitize; 1257 1258 /* DPLL okay; verify the cdclock 1259 * 1260 * Noticed in some instances that the freq selection is correct but 1261 * decimal part is programmed wrong from BIOS where pre-os does not 1262 * enable display. Verify the same as well. 1263 */ 1264 cdctl = intel_de_read(display, CDCLK_CTL); 1265 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1266 skl_cdclk_decimal(display->cdclk.hw.cdclk); 1267 if (cdctl == expected) 1268 /* All well; nothing to sanitize */ 1269 return; 1270 1271 sanitize: 1272 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 1273 1274 /* force cdclk programming */ 1275 display->cdclk.hw.cdclk = 0; 1276 /* force full PLL disable + enable */ 1277 display->cdclk.hw.vco = ~0; 1278 } 1279 1280 static void skl_cdclk_init_hw(struct intel_display *display) 1281 { 1282 struct intel_cdclk_config cdclk_config; 1283 1284 skl_sanitize_cdclk(display); 1285 1286 if (display->cdclk.hw.cdclk != 0 && 1287 display->cdclk.hw.vco != 0) { 1288 /* 1289 * Use the current vco as our initial 1290 * guess as to what the preferred vco is. 1291 */ 1292 if (display->cdclk.skl_preferred_vco_freq == 0) 1293 skl_set_preferred_cdclk_vco(display, 1294 display->cdclk.hw.vco); 1295 return; 1296 } 1297 1298 cdclk_config = display->cdclk.hw; 1299 1300 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; 1301 if (cdclk_config.vco == 0) 1302 cdclk_config.vco = 8100000; 1303 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1304 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1305 1306 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1307 } 1308 1309 static void skl_cdclk_uninit_hw(struct intel_display *display) 1310 { 1311 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 1312 1313 cdclk_config.cdclk = cdclk_config.bypass; 1314 cdclk_config.vco = 0; 1315 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1316 1317 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1318 } 1319 1320 struct intel_cdclk_vals { 1321 u32 cdclk; 1322 u16 refclk; 1323 u16 waveform; 1324 u8 ratio; 1325 }; 1326 1327 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1328 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1329 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1330 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1331 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1332 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1333 {} 1334 }; 1335 1336 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1337 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1338 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1339 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1340 {} 1341 }; 1342 1343 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1344 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1345 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1346 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1347 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1348 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1349 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1350 1351 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1352 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1353 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1354 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1355 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1356 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1357 1358 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1359 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1360 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1361 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1362 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1363 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1364 {} 1365 }; 1366 1367 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1368 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1369 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1370 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1371 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1372 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1373 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1374 1375 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1376 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1377 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1378 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1379 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1380 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1381 1382 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1383 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1384 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1385 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1386 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1387 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1388 {} 1389 }; 1390 1391 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1392 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1393 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1394 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1395 1396 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1397 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1398 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1399 1400 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1401 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1402 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1403 {} 1404 }; 1405 1406 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1407 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1408 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1409 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1410 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1411 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1412 1413 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1414 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1415 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1416 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1417 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1418 1419 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1420 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1421 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1422 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1423 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1424 {} 1425 }; 1426 1427 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1428 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1429 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1430 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1431 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1432 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1433 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1434 1435 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1436 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1437 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1438 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1439 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1440 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1441 1442 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1443 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1444 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1445 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1446 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1447 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1448 {} 1449 }; 1450 1451 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1452 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1453 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1454 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1455 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1456 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1457 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1458 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1459 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1460 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1461 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1462 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1463 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1464 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1465 {} 1466 }; 1467 1468 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1469 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1470 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1471 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1472 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1473 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1474 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1475 {} 1476 }; 1477 1478 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1479 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1480 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1481 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1482 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1483 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1484 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1485 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1486 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1487 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1488 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1489 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1490 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1491 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1492 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1493 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1494 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1495 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1496 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1497 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1498 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1499 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1500 {} 1501 }; 1502 1503 /* 1504 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1505 */ 1506 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1507 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1508 {} 1509 }; 1510 1511 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { 1512 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1513 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1514 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1515 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1516 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1517 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1518 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1519 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1520 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1521 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff }, 1522 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff }, 1523 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff }, 1524 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff }, 1525 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1526 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1527 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1528 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1529 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1530 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1531 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1532 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1533 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1534 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1535 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1536 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1537 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1538 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1539 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1540 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1541 {} 1542 }; 1543 1544 static const int cdclk_squash_len = 16; 1545 1546 static int cdclk_squash_divider(u16 waveform) 1547 { 1548 return hweight16(waveform ?: 0xffff); 1549 } 1550 1551 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1552 { 1553 /* 2 * cd2x divider */ 1554 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1555 cdclk * cdclk_squash_len); 1556 } 1557 1558 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 1559 { 1560 const struct intel_cdclk_vals *table = display->cdclk.table; 1561 int i; 1562 1563 for (i = 0; table[i].refclk; i++) 1564 if (table[i].refclk == display->cdclk.hw.ref && 1565 table[i].cdclk >= min_cdclk) 1566 return table[i].cdclk; 1567 1568 drm_WARN(display->drm, 1, 1569 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1570 min_cdclk, display->cdclk.hw.ref); 1571 return 0; 1572 } 1573 1574 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) 1575 { 1576 const struct intel_cdclk_vals *table = display->cdclk.table; 1577 int i; 1578 1579 if (cdclk == display->cdclk.hw.bypass) 1580 return 0; 1581 1582 for (i = 0; table[i].refclk; i++) 1583 if (table[i].refclk == display->cdclk.hw.ref && 1584 table[i].cdclk == cdclk) 1585 return display->cdclk.hw.ref * table[i].ratio; 1586 1587 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1588 cdclk, display->cdclk.hw.ref); 1589 return 0; 1590 } 1591 1592 static u8 bxt_calc_voltage_level(int cdclk) 1593 { 1594 return DIV_ROUND_UP(cdclk, 25000); 1595 } 1596 1597 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1598 const int voltage_level_max_cdclk[]) 1599 { 1600 int voltage_level; 1601 1602 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1603 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1604 return voltage_level; 1605 } 1606 1607 MISSING_CASE(cdclk); 1608 return num_voltage_levels - 1; 1609 } 1610 1611 static u8 icl_calc_voltage_level(int cdclk) 1612 { 1613 static const int icl_voltage_level_max_cdclk[] = { 1614 [0] = 312000, 1615 [1] = 556800, 1616 [2] = 652800, 1617 }; 1618 1619 return calc_voltage_level(cdclk, 1620 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1621 icl_voltage_level_max_cdclk); 1622 } 1623 1624 static u8 ehl_calc_voltage_level(int cdclk) 1625 { 1626 static const int ehl_voltage_level_max_cdclk[] = { 1627 [0] = 180000, 1628 [1] = 312000, 1629 [2] = 326400, 1630 /* 1631 * Bspec lists the limit as 556.8 MHz, but some JSL 1632 * development boards (at least) boot with 652.8 MHz 1633 */ 1634 [3] = 652800, 1635 }; 1636 1637 return calc_voltage_level(cdclk, 1638 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1639 ehl_voltage_level_max_cdclk); 1640 } 1641 1642 static u8 tgl_calc_voltage_level(int cdclk) 1643 { 1644 static const int tgl_voltage_level_max_cdclk[] = { 1645 [0] = 312000, 1646 [1] = 326400, 1647 [2] = 556800, 1648 [3] = 652800, 1649 }; 1650 1651 return calc_voltage_level(cdclk, 1652 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1653 tgl_voltage_level_max_cdclk); 1654 } 1655 1656 static u8 rplu_calc_voltage_level(int cdclk) 1657 { 1658 static const int rplu_voltage_level_max_cdclk[] = { 1659 [0] = 312000, 1660 [1] = 480000, 1661 [2] = 556800, 1662 [3] = 652800, 1663 }; 1664 1665 return calc_voltage_level(cdclk, 1666 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1667 rplu_voltage_level_max_cdclk); 1668 } 1669 1670 static u8 xe3lpd_calc_voltage_level(int cdclk) 1671 { 1672 /* 1673 * Starting with xe3lpd power controller does not need the voltage 1674 * index when doing the modeset update. This function is best left 1675 * defined but returning 0 to the mask. 1676 */ 1677 return 0; 1678 } 1679 1680 static void icl_readout_refclk(struct intel_display *display, 1681 struct intel_cdclk_config *cdclk_config) 1682 { 1683 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1684 1685 switch (dssm) { 1686 default: 1687 MISSING_CASE(dssm); 1688 fallthrough; 1689 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1690 cdclk_config->ref = 24000; 1691 break; 1692 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1693 cdclk_config->ref = 19200; 1694 break; 1695 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1696 cdclk_config->ref = 38400; 1697 break; 1698 } 1699 } 1700 1701 static void bxt_de_pll_readout(struct intel_display *display, 1702 struct intel_cdclk_config *cdclk_config) 1703 { 1704 u32 val, ratio; 1705 1706 if (display->platform.dg2) 1707 cdclk_config->ref = 38400; 1708 else if (DISPLAY_VER(display) >= 11) 1709 icl_readout_refclk(display, cdclk_config); 1710 else 1711 cdclk_config->ref = 19200; 1712 1713 val = intel_de_read(display, BXT_DE_PLL_ENABLE); 1714 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1715 (val & BXT_DE_PLL_LOCK) == 0) { 1716 /* 1717 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1718 * setting it to zero is a way to signal that. 1719 */ 1720 cdclk_config->vco = 0; 1721 return; 1722 } 1723 1724 /* 1725 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1726 * gen9lp had it in a separate PLL control register. 1727 */ 1728 if (DISPLAY_VER(display) >= 11) 1729 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1730 else 1731 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1732 1733 cdclk_config->vco = ratio * cdclk_config->ref; 1734 } 1735 1736 static void bxt_get_cdclk(struct intel_display *display, 1737 struct intel_cdclk_config *cdclk_config) 1738 { 1739 u32 squash_ctl = 0; 1740 u32 divider; 1741 int div; 1742 1743 bxt_de_pll_readout(display, cdclk_config); 1744 1745 if (DISPLAY_VER(display) >= 12) 1746 cdclk_config->bypass = cdclk_config->ref / 2; 1747 else if (DISPLAY_VER(display) >= 11) 1748 cdclk_config->bypass = 50000; 1749 else 1750 cdclk_config->bypass = cdclk_config->ref; 1751 1752 if (cdclk_config->vco == 0) { 1753 cdclk_config->cdclk = cdclk_config->bypass; 1754 goto out; 1755 } 1756 1757 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1758 1759 switch (divider) { 1760 case BXT_CDCLK_CD2X_DIV_SEL_1: 1761 div = 2; 1762 break; 1763 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1764 div = 3; 1765 break; 1766 case BXT_CDCLK_CD2X_DIV_SEL_2: 1767 div = 4; 1768 break; 1769 case BXT_CDCLK_CD2X_DIV_SEL_4: 1770 div = 8; 1771 break; 1772 default: 1773 MISSING_CASE(divider); 1774 return; 1775 } 1776 1777 if (HAS_CDCLK_SQUASH(display)) 1778 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); 1779 1780 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1781 u16 waveform; 1782 int size; 1783 1784 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1785 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1786 1787 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1788 cdclk_config->vco, size * div); 1789 } else { 1790 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1791 } 1792 1793 out: 1794 if (DISPLAY_VER(display) >= 20) 1795 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 1796 /* 1797 * Can't read this out :( Let's assume it's 1798 * at least what the CDCLK frequency requires. 1799 */ 1800 cdclk_config->voltage_level = 1801 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); 1802 } 1803 1804 static void bxt_de_pll_disable(struct intel_display *display) 1805 { 1806 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); 1807 1808 /* Timeout 200us */ 1809 if (intel_de_wait_for_clear(display, 1810 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1811 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); 1812 1813 display->cdclk.hw.vco = 0; 1814 } 1815 1816 static void bxt_de_pll_enable(struct intel_display *display, int vco) 1817 { 1818 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1819 1820 intel_de_rmw(display, BXT_DE_PLL_CTL, 1821 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1822 1823 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1824 1825 /* Timeout 200us */ 1826 if (intel_de_wait_for_set(display, 1827 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1828 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); 1829 1830 display->cdclk.hw.vco = vco; 1831 } 1832 1833 static void icl_cdclk_pll_disable(struct intel_display *display) 1834 { 1835 intel_de_rmw(display, BXT_DE_PLL_ENABLE, 1836 BXT_DE_PLL_PLL_ENABLE, 0); 1837 1838 /* Timeout 200us */ 1839 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1840 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); 1841 1842 display->cdclk.hw.vco = 0; 1843 } 1844 1845 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) 1846 { 1847 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1848 u32 val; 1849 1850 val = ICL_CDCLK_PLL_RATIO(ratio); 1851 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1852 1853 val |= BXT_DE_PLL_PLL_ENABLE; 1854 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1855 1856 /* Timeout 200us */ 1857 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1858 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); 1859 1860 display->cdclk.hw.vco = vco; 1861 } 1862 1863 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) 1864 { 1865 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1866 u32 val; 1867 1868 /* Write PLL ratio without disabling */ 1869 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1870 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1871 1872 /* Submit freq change request */ 1873 val |= BXT_DE_PLL_FREQ_REQ; 1874 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1875 1876 /* Timeout 200us */ 1877 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, 1878 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1879 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); 1880 1881 val &= ~BXT_DE_PLL_FREQ_REQ; 1882 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1883 1884 display->cdclk.hw.vco = vco; 1885 } 1886 1887 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 1888 { 1889 if (DISPLAY_VER(display) >= 12) { 1890 if (pipe == INVALID_PIPE) 1891 return TGL_CDCLK_CD2X_PIPE_NONE; 1892 else 1893 return TGL_CDCLK_CD2X_PIPE(pipe); 1894 } else if (DISPLAY_VER(display) >= 11) { 1895 if (pipe == INVALID_PIPE) 1896 return ICL_CDCLK_CD2X_PIPE_NONE; 1897 else 1898 return ICL_CDCLK_CD2X_PIPE(pipe); 1899 } else { 1900 if (pipe == INVALID_PIPE) 1901 return BXT_CDCLK_CD2X_PIPE_NONE; 1902 else 1903 return BXT_CDCLK_CD2X_PIPE(pipe); 1904 } 1905 } 1906 1907 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 1908 int cdclk, int vco, u16 waveform) 1909 { 1910 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1911 switch (cdclk_divider(cdclk, vco, waveform)) { 1912 default: 1913 drm_WARN_ON(display->drm, 1914 cdclk != display->cdclk.hw.bypass); 1915 drm_WARN_ON(display->drm, vco != 0); 1916 fallthrough; 1917 case 2: 1918 return BXT_CDCLK_CD2X_DIV_SEL_1; 1919 case 3: 1920 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1921 case 4: 1922 return BXT_CDCLK_CD2X_DIV_SEL_2; 1923 case 8: 1924 return BXT_CDCLK_CD2X_DIV_SEL_4; 1925 } 1926 } 1927 1928 static u16 cdclk_squash_waveform(struct intel_display *display, 1929 int cdclk) 1930 { 1931 const struct intel_cdclk_vals *table = display->cdclk.table; 1932 int i; 1933 1934 if (cdclk == display->cdclk.hw.bypass) 1935 return 0; 1936 1937 for (i = 0; table[i].refclk; i++) 1938 if (table[i].refclk == display->cdclk.hw.ref && 1939 table[i].cdclk == cdclk) 1940 return table[i].waveform; 1941 1942 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1943 cdclk, display->cdclk.hw.ref); 1944 1945 return 0xffff; 1946 } 1947 1948 static void icl_cdclk_pll_update(struct intel_display *display, int vco) 1949 { 1950 if (display->cdclk.hw.vco != 0 && 1951 display->cdclk.hw.vco != vco) 1952 icl_cdclk_pll_disable(display); 1953 1954 if (display->cdclk.hw.vco != vco) 1955 icl_cdclk_pll_enable(display, vco); 1956 } 1957 1958 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) 1959 { 1960 if (display->cdclk.hw.vco != 0 && 1961 display->cdclk.hw.vco != vco) 1962 bxt_de_pll_disable(display); 1963 1964 if (display->cdclk.hw.vco != vco) 1965 bxt_de_pll_enable(display, vco); 1966 } 1967 1968 static void dg2_cdclk_squash_program(struct intel_display *display, 1969 u16 waveform) 1970 { 1971 u32 squash_ctl = 0; 1972 1973 if (waveform) 1974 squash_ctl = CDCLK_SQUASH_ENABLE | 1975 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1976 1977 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); 1978 } 1979 1980 static bool cdclk_pll_is_unknown(unsigned int vco) 1981 { 1982 /* 1983 * Ensure driver does not take the crawl path for the 1984 * case when the vco is set to ~0 in the 1985 * sanitize path. 1986 */ 1987 return vco == ~0; 1988 } 1989 1990 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) 1991 { 1992 return DISPLAY_VER(display) >= 20; 1993 } 1994 1995 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) 1996 { 1997 if (mdclk_source_is_cdclk_pll(display)) 1998 return MDCLK_SOURCE_SEL_CDCLK_PLL; 1999 2000 return MDCLK_SOURCE_SEL_CD2XCLK; 2001 } 2002 2003 int intel_mdclk_cdclk_ratio(struct intel_display *display, 2004 const struct intel_cdclk_config *cdclk_config) 2005 { 2006 if (mdclk_source_is_cdclk_pll(display)) 2007 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 2008 2009 /* Otherwise, source for MDCLK is CD2XCLK. */ 2010 return 2; 2011 } 2012 2013 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, 2014 const struct intel_cdclk_config *cdclk_config) 2015 { 2016 intel_dbuf_mdclk_cdclk_ratio_update(display, 2017 intel_mdclk_cdclk_ratio(display, cdclk_config), 2018 cdclk_config->joined_mbus); 2019 } 2020 2021 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, 2022 const struct intel_cdclk_config *old_cdclk_config, 2023 const struct intel_cdclk_config *new_cdclk_config, 2024 struct intel_cdclk_config *mid_cdclk_config) 2025 { 2026 u16 old_waveform, new_waveform, mid_waveform; 2027 int old_div, new_div, mid_div; 2028 2029 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 2030 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 2031 return false; 2032 2033 /* Return if both Squash and Crawl are not present */ 2034 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2035 return false; 2036 2037 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); 2038 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); 2039 2040 /* Return if Squash only or Crawl only is the desired action */ 2041 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 2042 old_cdclk_config->vco == new_cdclk_config->vco || 2043 old_waveform == new_waveform) 2044 return false; 2045 2046 old_div = cdclk_divider(old_cdclk_config->cdclk, 2047 old_cdclk_config->vco, old_waveform); 2048 new_div = cdclk_divider(new_cdclk_config->cdclk, 2049 new_cdclk_config->vco, new_waveform); 2050 2051 /* 2052 * Should not happen currently. We might need more midpoint 2053 * transitions if we need to also change the cd2x divider. 2054 */ 2055 if (drm_WARN_ON(display->drm, old_div != new_div)) 2056 return false; 2057 2058 *mid_cdclk_config = *new_cdclk_config; 2059 2060 /* 2061 * Populate the mid_cdclk_config accordingly. 2062 * - If moving to a higher cdclk, the desired action is squashing. 2063 * The mid cdclk config should have the new (squash) waveform. 2064 * - If moving to a lower cdclk, the desired action is crawling. 2065 * The mid cdclk config should have the new vco. 2066 */ 2067 2068 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 2069 mid_cdclk_config->vco = old_cdclk_config->vco; 2070 mid_div = old_div; 2071 mid_waveform = new_waveform; 2072 } else { 2073 mid_cdclk_config->vco = new_cdclk_config->vco; 2074 mid_div = new_div; 2075 mid_waveform = old_waveform; 2076 } 2077 2078 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 2079 mid_cdclk_config->vco, 2080 cdclk_squash_len * mid_div); 2081 2082 /* make sure the mid clock came out sane */ 2083 2084 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < 2085 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 2086 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > 2087 display->cdclk.max_cdclk_freq); 2088 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != 2089 mid_waveform); 2090 2091 return true; 2092 } 2093 2094 static bool pll_enable_wa_needed(struct intel_display *display) 2095 { 2096 return (DISPLAY_VERx100(display) == 2000 || 2097 DISPLAY_VERx100(display) == 1400 || 2098 display->platform.dg2) && 2099 display->cdclk.hw.vco > 0; 2100 } 2101 2102 static u32 bxt_cdclk_ctl(struct intel_display *display, 2103 const struct intel_cdclk_config *cdclk_config, 2104 enum pipe pipe) 2105 { 2106 int cdclk = cdclk_config->cdclk; 2107 int vco = cdclk_config->vco; 2108 u16 waveform; 2109 u32 val; 2110 2111 waveform = cdclk_squash_waveform(display, cdclk); 2112 2113 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | 2114 bxt_cdclk_cd2x_pipe(display, pipe); 2115 2116 /* 2117 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2118 * enable otherwise. 2119 */ 2120 if ((display->platform.geminilake || display->platform.broxton) && 2121 cdclk >= 500000) 2122 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2123 2124 if (DISPLAY_VER(display) >= 20) 2125 val |= xe2lpd_mdclk_source_sel(display); 2126 else 2127 val |= skl_cdclk_decimal(cdclk); 2128 2129 return val; 2130 } 2131 2132 static void _bxt_set_cdclk(struct intel_display *display, 2133 const struct intel_cdclk_config *cdclk_config, 2134 enum pipe pipe) 2135 { 2136 int cdclk = cdclk_config->cdclk; 2137 int vco = cdclk_config->vco; 2138 2139 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && 2140 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { 2141 if (display->cdclk.hw.vco != vco) 2142 adlp_cdclk_pll_crawl(display, vco); 2143 } else if (DISPLAY_VER(display) >= 11) { 2144 /* wa_15010685871: dg2, mtl */ 2145 if (pll_enable_wa_needed(display)) 2146 dg2_cdclk_squash_program(display, 0); 2147 2148 icl_cdclk_pll_update(display, vco); 2149 } else { 2150 bxt_cdclk_pll_update(display, vco); 2151 } 2152 2153 if (HAS_CDCLK_SQUASH(display)) { 2154 u16 waveform = cdclk_squash_waveform(display, cdclk); 2155 2156 dg2_cdclk_squash_program(display, waveform); 2157 } 2158 2159 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); 2160 2161 if (pipe != INVALID_PIPE) 2162 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 2163 } 2164 2165 static void bxt_set_cdclk(struct intel_display *display, 2166 const struct intel_cdclk_config *cdclk_config, 2167 enum pipe pipe) 2168 { 2169 struct intel_cdclk_config mid_cdclk_config; 2170 int cdclk = cdclk_config->cdclk; 2171 int ret = 0; 2172 2173 /* 2174 * Inform power controller of upcoming frequency change. 2175 * Display versions 14 and beyond do not follow the PUnit 2176 * mailbox communication, skip 2177 * this step. 2178 */ 2179 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) 2180 ; /* NOOP */ 2181 else if (DISPLAY_VER(display) >= 11) 2182 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 2183 SKL_CDCLK_PREPARE_FOR_CHANGE, 2184 SKL_CDCLK_READY_FOR_CHANGE, 2185 SKL_CDCLK_READY_FOR_CHANGE, 3); 2186 else 2187 /* 2188 * BSpec requires us to wait up to 150usec, but that leads to 2189 * timeouts; the 2ms used here is based on experiment. 2190 */ 2191 ret = intel_pcode_write_timeout(display->drm, 2192 HSW_PCODE_DE_WRITE_FREQ_REQ, 2193 0x80000000, 2); 2194 2195 if (ret) { 2196 drm_err(display->drm, 2197 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2198 ret, cdclk); 2199 return; 2200 } 2201 2202 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) 2203 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2204 2205 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, 2206 cdclk_config, &mid_cdclk_config)) { 2207 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); 2208 _bxt_set_cdclk(display, cdclk_config, pipe); 2209 } else { 2210 _bxt_set_cdclk(display, cdclk_config, pipe); 2211 } 2212 2213 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) 2214 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2215 2216 if (DISPLAY_VER(display) >= 14) 2217 /* 2218 * NOOP - No Pcode communication needed for 2219 * Display versions 14 and beyond 2220 */; 2221 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) 2222 ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, 2223 cdclk_config->voltage_level); 2224 if (DISPLAY_VER(display) < 11) { 2225 /* 2226 * The timeout isn't specified, the 2ms used here is based on 2227 * experiment. 2228 * FIXME: Waiting for the request completion could be delayed 2229 * until the next PCODE request based on BSpec. 2230 */ 2231 ret = intel_pcode_write_timeout(display->drm, 2232 HSW_PCODE_DE_WRITE_FREQ_REQ, 2233 cdclk_config->voltage_level, 2); 2234 } 2235 if (ret) { 2236 drm_err(display->drm, 2237 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2238 ret, cdclk); 2239 return; 2240 } 2241 2242 intel_update_cdclk(display); 2243 2244 if (DISPLAY_VER(display) >= 11) 2245 /* 2246 * Can't read out the voltage level :( 2247 * Let's just assume everything is as expected. 2248 */ 2249 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; 2250 } 2251 2252 static void bxt_sanitize_cdclk(struct intel_display *display) 2253 { 2254 u32 cdctl, expected; 2255 int cdclk, vco; 2256 2257 intel_update_cdclk(display); 2258 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 2259 2260 if (display->cdclk.hw.vco == 0 || 2261 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 2262 goto sanitize; 2263 2264 /* Make sure this is a legal cdclk value for the platform */ 2265 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); 2266 if (cdclk != display->cdclk.hw.cdclk) 2267 goto sanitize; 2268 2269 /* Make sure the VCO is correct for the cdclk */ 2270 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 2271 if (vco != display->cdclk.hw.vco) 2272 goto sanitize; 2273 2274 /* 2275 * Some BIOS versions leave an incorrect decimal frequency value and 2276 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2277 * so sanitize this register. 2278 */ 2279 cdctl = intel_de_read(display, CDCLK_CTL); 2280 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); 2281 2282 /* 2283 * Let's ignore the pipe field, since BIOS could have configured the 2284 * dividers both syncing to an active pipe, or asynchronously 2285 * (PIPE_NONE). 2286 */ 2287 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2288 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2289 2290 if (cdctl == expected) 2291 /* All well; nothing to sanitize */ 2292 return; 2293 2294 sanitize: 2295 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 2296 2297 /* force cdclk programming */ 2298 display->cdclk.hw.cdclk = 0; 2299 2300 /* force full PLL disable + enable */ 2301 display->cdclk.hw.vco = ~0; 2302 } 2303 2304 static void bxt_cdclk_init_hw(struct intel_display *display) 2305 { 2306 struct intel_cdclk_config cdclk_config; 2307 2308 bxt_sanitize_cdclk(display); 2309 2310 if (display->cdclk.hw.cdclk != 0 && 2311 display->cdclk.hw.vco != 0) 2312 return; 2313 2314 cdclk_config = display->cdclk.hw; 2315 2316 /* 2317 * FIXME: 2318 * - The initial CDCLK needs to be read from VBT. 2319 * Need to make this change after VBT has changes for BXT. 2320 */ 2321 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); 2322 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); 2323 cdclk_config.voltage_level = 2324 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2325 2326 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2327 } 2328 2329 static void bxt_cdclk_uninit_hw(struct intel_display *display) 2330 { 2331 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 2332 2333 cdclk_config.cdclk = cdclk_config.bypass; 2334 cdclk_config.vco = 0; 2335 cdclk_config.voltage_level = 2336 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2337 2338 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2339 } 2340 2341 /** 2342 * intel_cdclk_init_hw - Initialize CDCLK hardware 2343 * @display: display instance 2344 * 2345 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and 2346 * sanitizing the state of the hardware if needed. This is generally done only 2347 * during the display core initialization sequence, after which the DMC will 2348 * take care of turning CDCLK off/on as needed. 2349 */ 2350 void intel_cdclk_init_hw(struct intel_display *display) 2351 { 2352 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2353 bxt_cdclk_init_hw(display); 2354 else if (DISPLAY_VER(display) == 9) 2355 skl_cdclk_init_hw(display); 2356 } 2357 2358 /** 2359 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2360 * @display: display instance 2361 * 2362 * Uninitialize CDCLK. This is done only during the display core 2363 * uninitialization sequence. 2364 */ 2365 void intel_cdclk_uninit_hw(struct intel_display *display) 2366 { 2367 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2368 bxt_cdclk_uninit_hw(display); 2369 else if (DISPLAY_VER(display) == 9) 2370 skl_cdclk_uninit_hw(display); 2371 } 2372 2373 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, 2374 const struct intel_cdclk_config *a, 2375 const struct intel_cdclk_config *b) 2376 { 2377 u16 old_waveform; 2378 u16 new_waveform; 2379 2380 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); 2381 2382 if (a->vco == 0 || b->vco == 0) 2383 return false; 2384 2385 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2386 return false; 2387 2388 old_waveform = cdclk_squash_waveform(display, a->cdclk); 2389 new_waveform = cdclk_squash_waveform(display, b->cdclk); 2390 2391 return a->vco != b->vco && 2392 old_waveform != new_waveform; 2393 } 2394 2395 static bool intel_cdclk_can_crawl(struct intel_display *display, 2396 const struct intel_cdclk_config *a, 2397 const struct intel_cdclk_config *b) 2398 { 2399 int a_div, b_div; 2400 2401 if (!HAS_CDCLK_CRAWL(display)) 2402 return false; 2403 2404 /* 2405 * The vco and cd2x divider will change independently 2406 * from each, so we disallow cd2x change when crawling. 2407 */ 2408 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2409 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2410 2411 return a->vco != 0 && b->vco != 0 && 2412 a->vco != b->vco && 2413 a_div == b_div && 2414 a->ref == b->ref; 2415 } 2416 2417 static bool intel_cdclk_can_squash(struct intel_display *display, 2418 const struct intel_cdclk_config *a, 2419 const struct intel_cdclk_config *b) 2420 { 2421 /* 2422 * FIXME should store a bit more state in intel_cdclk_config 2423 * to differentiate squasher vs. cd2x divider properly. For 2424 * the moment all platforms with squasher use a fixed cd2x 2425 * divider. 2426 */ 2427 if (!HAS_CDCLK_SQUASH(display)) 2428 return false; 2429 2430 return a->cdclk != b->cdclk && 2431 a->vco != 0 && 2432 a->vco == b->vco && 2433 a->ref == b->ref; 2434 } 2435 2436 /** 2437 * intel_cdclk_clock_changed - Check whether the clock changed 2438 * @a: first CDCLK configuration 2439 * @b: second CDCLK configuration 2440 * 2441 * Returns: 2442 * True if CDCLK changed in a way that requires re-programming and 2443 * False otherwise. 2444 */ 2445 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2446 const struct intel_cdclk_config *b) 2447 { 2448 return a->cdclk != b->cdclk || 2449 a->vco != b->vco || 2450 a->ref != b->ref; 2451 } 2452 2453 /** 2454 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2455 * configurations requires only a cd2x divider update 2456 * @display: display instance 2457 * @a: first CDCLK configuration 2458 * @b: second CDCLK configuration 2459 * 2460 * Returns: 2461 * True if changing between the two CDCLK configurations 2462 * can be done with just a cd2x divider update, false if not. 2463 */ 2464 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, 2465 const struct intel_cdclk_config *a, 2466 const struct intel_cdclk_config *b) 2467 { 2468 /* Older hw doesn't have the capability */ 2469 if (DISPLAY_VER(display) < 10 && !display->platform.broxton) 2470 return false; 2471 2472 /* 2473 * FIXME should store a bit more state in intel_cdclk_config 2474 * to differentiate squasher vs. cd2x divider properly. For 2475 * the moment all platforms with squasher use a fixed cd2x 2476 * divider. 2477 */ 2478 if (HAS_CDCLK_SQUASH(display)) 2479 return false; 2480 2481 return a->cdclk != b->cdclk && 2482 a->vco != 0 && 2483 a->vco == b->vco && 2484 a->ref == b->ref; 2485 } 2486 2487 /** 2488 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2489 * @a: first CDCLK configuration 2490 * @b: second CDCLK configuration 2491 * 2492 * Returns: 2493 * True if the CDCLK configurations don't match, false if they do. 2494 */ 2495 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2496 const struct intel_cdclk_config *b) 2497 { 2498 return intel_cdclk_clock_changed(a, b) || 2499 a->voltage_level != b->voltage_level; 2500 } 2501 2502 void intel_cdclk_dump_config(struct intel_display *display, 2503 const struct intel_cdclk_config *cdclk_config, 2504 const char *context) 2505 { 2506 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2507 context, cdclk_config->cdclk, cdclk_config->vco, 2508 cdclk_config->ref, cdclk_config->bypass, 2509 cdclk_config->voltage_level); 2510 } 2511 2512 static void intel_pcode_notify(struct intel_display *display, 2513 u8 voltage_level, 2514 u8 active_pipe_count, 2515 u16 cdclk, 2516 bool cdclk_update_valid, 2517 bool pipe_count_update_valid) 2518 { 2519 int ret; 2520 u32 update_mask = 0; 2521 2522 if (!display->platform.dg2) 2523 return; 2524 2525 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2526 2527 if (cdclk_update_valid) 2528 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2529 2530 if (pipe_count_update_valid) 2531 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2532 2533 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 2534 SKL_CDCLK_PREPARE_FOR_CHANGE | 2535 update_mask, 2536 SKL_CDCLK_READY_FOR_CHANGE, 2537 SKL_CDCLK_READY_FOR_CHANGE, 3); 2538 if (ret) 2539 drm_err(display->drm, 2540 "Failed to inform PCU about display config (err %d)\n", 2541 ret); 2542 } 2543 2544 static void intel_set_cdclk(struct intel_display *display, 2545 const struct intel_cdclk_config *cdclk_config, 2546 enum pipe pipe, const char *context) 2547 { 2548 struct intel_encoder *encoder; 2549 2550 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) 2551 return; 2552 2553 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) 2554 return; 2555 2556 intel_cdclk_dump_config(display, cdclk_config, context); 2557 2558 for_each_intel_encoder_with_psr(display->drm, encoder) { 2559 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2560 2561 intel_psr_pause(intel_dp); 2562 } 2563 2564 intel_audio_cdclk_change_pre(display); 2565 2566 /* 2567 * Lock aux/gmbus while we change cdclk in case those 2568 * functions use cdclk. Not all platforms/ports do, 2569 * but we'll lock them all for simplicity. 2570 */ 2571 mutex_lock(&display->gmbus.mutex); 2572 for_each_intel_dp(display->drm, encoder) { 2573 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2574 2575 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2576 &display->gmbus.mutex); 2577 } 2578 2579 intel_cdclk_set_cdclk(display, cdclk_config, pipe); 2580 2581 for_each_intel_dp(display->drm, encoder) { 2582 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2583 2584 mutex_unlock(&intel_dp->aux.hw_mutex); 2585 } 2586 mutex_unlock(&display->gmbus.mutex); 2587 2588 for_each_intel_encoder_with_psr(display->drm, encoder) { 2589 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2590 2591 intel_psr_resume(intel_dp); 2592 } 2593 2594 intel_audio_cdclk_change_post(display); 2595 2596 if (drm_WARN(display->drm, 2597 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), 2598 "cdclk state doesn't match!\n")) { 2599 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); 2600 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); 2601 } 2602 } 2603 2604 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2605 { 2606 struct intel_display *display = to_intel_display(state); 2607 const struct intel_cdclk_state *old_cdclk_state = 2608 intel_atomic_get_old_cdclk_state(state); 2609 const struct intel_cdclk_state *new_cdclk_state = 2610 intel_atomic_get_new_cdclk_state(state); 2611 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2612 bool change_cdclk, update_pipe_count; 2613 2614 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2615 &new_cdclk_state->actual) && 2616 new_cdclk_state->active_pipes == 2617 old_cdclk_state->active_pipes) 2618 return; 2619 2620 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2621 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2622 2623 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2624 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > 2625 hweight8(old_cdclk_state->active_pipes); 2626 2627 /* 2628 * According to "Sequence Before Frequency Change", 2629 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2630 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2631 * which basically means we choose the maximum of old and new CDCLK, if we know both 2632 */ 2633 if (change_cdclk) 2634 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2635 2636 /* 2637 * According to "Sequence For Pipe Count Change", 2638 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2639 * (power well is enabled) 2640 * no action if it is decreasing, before the change 2641 */ 2642 if (update_pipe_count) 2643 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2644 2645 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2646 change_cdclk, update_pipe_count); 2647 } 2648 2649 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2650 { 2651 struct intel_display *display = to_intel_display(state); 2652 const struct intel_cdclk_state *new_cdclk_state = 2653 intel_atomic_get_new_cdclk_state(state); 2654 const struct intel_cdclk_state *old_cdclk_state = 2655 intel_atomic_get_old_cdclk_state(state); 2656 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2657 bool update_cdclk, update_pipe_count; 2658 2659 /* According to "Sequence After Frequency Change", set voltage to used level */ 2660 voltage_level = new_cdclk_state->actual.voltage_level; 2661 2662 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2663 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < 2664 hweight8(old_cdclk_state->active_pipes); 2665 2666 /* 2667 * According to "Sequence After Frequency Change", 2668 * set bits 25:16 to current CDCLK 2669 */ 2670 if (update_cdclk) 2671 cdclk = new_cdclk_state->actual.cdclk; 2672 2673 /* 2674 * According to "Sequence For Pipe Count Change", 2675 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2676 * after the change(power well is disabled) 2677 * no action if it is increasing, after the change 2678 */ 2679 if (update_pipe_count) 2680 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2681 2682 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2683 update_cdclk, update_pipe_count); 2684 } 2685 2686 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2687 { 2688 const struct intel_cdclk_state *old_cdclk_state = 2689 intel_atomic_get_old_cdclk_state(state); 2690 const struct intel_cdclk_state *new_cdclk_state = 2691 intel_atomic_get_new_cdclk_state(state); 2692 2693 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2694 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2695 } 2696 2697 /** 2698 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2699 * @state: intel atomic state 2700 * 2701 * Program the hardware before updating the HW plane state based on the 2702 * new CDCLK state, if necessary. 2703 */ 2704 void 2705 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2706 { 2707 struct intel_display *display = to_intel_display(state); 2708 const struct intel_cdclk_state *old_cdclk_state = 2709 intel_atomic_get_old_cdclk_state(state); 2710 const struct intel_cdclk_state *new_cdclk_state = 2711 intel_atomic_get_new_cdclk_state(state); 2712 struct intel_cdclk_config cdclk_config; 2713 enum pipe pipe; 2714 2715 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2716 &new_cdclk_state->actual)) 2717 return; 2718 2719 if (display->platform.dg2) 2720 intel_cdclk_pcode_pre_notify(state); 2721 2722 if (new_cdclk_state->disable_pipes) { 2723 cdclk_config = new_cdclk_state->actual; 2724 pipe = INVALID_PIPE; 2725 } else { 2726 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2727 cdclk_config = new_cdclk_state->actual; 2728 pipe = new_cdclk_state->pipe; 2729 } else { 2730 cdclk_config = old_cdclk_state->actual; 2731 pipe = INVALID_PIPE; 2732 } 2733 2734 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2735 old_cdclk_state->actual.voltage_level); 2736 } 2737 2738 /* 2739 * mbus joining will be changed later by 2740 * intel_dbuf_mbus_{pre,post}_ddb_update() 2741 */ 2742 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2743 2744 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2745 2746 intel_set_cdclk(display, &cdclk_config, pipe, 2747 "Pre changing CDCLK to"); 2748 } 2749 2750 /** 2751 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2752 * @state: intel atomic state 2753 * 2754 * Program the hardware after updating the HW plane state based on the 2755 * new CDCLK state, if necessary. 2756 */ 2757 void 2758 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2759 { 2760 struct intel_display *display = to_intel_display(state); 2761 const struct intel_cdclk_state *old_cdclk_state = 2762 intel_atomic_get_old_cdclk_state(state); 2763 const struct intel_cdclk_state *new_cdclk_state = 2764 intel_atomic_get_new_cdclk_state(state); 2765 enum pipe pipe; 2766 2767 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2768 &new_cdclk_state->actual)) 2769 return; 2770 2771 if (display->platform.dg2) 2772 intel_cdclk_pcode_post_notify(state); 2773 2774 if (!new_cdclk_state->disable_pipes && 2775 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2776 pipe = new_cdclk_state->pipe; 2777 else 2778 pipe = INVALID_PIPE; 2779 2780 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2781 2782 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, 2783 "Post changing CDCLK to"); 2784 } 2785 2786 /* pixels per CDCLK */ 2787 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) 2788 { 2789 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; 2790 } 2791 2792 /* max pixel rate as % of CDCLK (not accounting for PPC) */ 2793 static int intel_cdclk_guardband(struct intel_display *display) 2794 { 2795 if (DISPLAY_VER(display) >= 9 || 2796 display->platform.broadwell || display->platform.haswell) 2797 return 100; 2798 else if (display->platform.cherryview) 2799 return 95; 2800 else 2801 return 90; 2802 } 2803 2804 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2805 { 2806 struct intel_display *display = to_intel_display(crtc_state); 2807 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 2808 int guardband = intel_cdclk_guardband(display); 2809 int pixel_rate = crtc_state->pixel_rate; 2810 2811 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); 2812 } 2813 2814 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2815 { 2816 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2817 struct intel_display *display = to_intel_display(crtc); 2818 struct intel_plane *plane; 2819 int min_cdclk = 0; 2820 2821 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2822 min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]); 2823 2824 return min_cdclk; 2825 } 2826 2827 static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2828 { 2829 int min_cdclk; 2830 2831 if (!crtc_state->hw.enable) 2832 return 0; 2833 2834 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2835 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state)); 2836 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state)); 2837 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); 2838 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state)); 2839 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2840 2841 return min_cdclk; 2842 } 2843 2844 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 2845 { 2846 struct intel_display *display = to_intel_display(state); 2847 struct intel_cdclk_state *cdclk_state = 2848 intel_atomic_get_new_cdclk_state(state); 2849 const struct intel_bw_state *bw_state; 2850 struct intel_crtc *crtc; 2851 struct intel_crtc_state *crtc_state; 2852 int min_cdclk, i; 2853 enum pipe pipe; 2854 2855 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2856 int ret; 2857 2858 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2859 if (min_cdclk < 0) 2860 return min_cdclk; 2861 2862 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2863 continue; 2864 2865 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2866 2867 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2868 if (ret) 2869 return ret; 2870 } 2871 2872 bw_state = intel_atomic_get_new_bw_state(state); 2873 if (bw_state) { 2874 min_cdclk = intel_bw_min_cdclk(display, bw_state); 2875 2876 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2877 int ret; 2878 2879 cdclk_state->bw_min_cdclk = min_cdclk; 2880 2881 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2882 if (ret) 2883 return ret; 2884 } 2885 } 2886 2887 min_cdclk = max(cdclk_state->force_min_cdclk, 2888 cdclk_state->bw_min_cdclk); 2889 for_each_pipe(display, pipe) 2890 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); 2891 2892 /* 2893 * Avoid glk_force_audio_cdclk() causing excessive screen 2894 * blinking when multiple pipes are active by making sure 2895 * CDCLK frequency is always high enough for audio. With a 2896 * single active pipe we can always change CDCLK frequency 2897 * by changing the cd2x divider (see glk_cdclk_table[]) and 2898 * thus a full modeset won't be needed then. 2899 */ 2900 if (display->platform.geminilake && cdclk_state->active_pipes && 2901 !is_power_of_2(cdclk_state->active_pipes)) 2902 min_cdclk = max(min_cdclk, 2 * 96000); 2903 2904 if (min_cdclk > display->cdclk.max_cdclk_freq) { 2905 drm_dbg_kms(display->drm, 2906 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2907 min_cdclk, display->cdclk.max_cdclk_freq); 2908 return -EINVAL; 2909 } 2910 2911 return min_cdclk; 2912 } 2913 2914 /* 2915 * Account for port clock min voltage level requirements. 2916 * This only really does something on DISPLA_VER >= 11 but can be 2917 * called on earlier platforms as well. 2918 * 2919 * Note that this functions assumes that 0 is 2920 * the lowest voltage value, and higher values 2921 * correspond to increasingly higher voltages. 2922 * 2923 * Should that relationship no longer hold on 2924 * future platforms this code will need to be 2925 * adjusted. 2926 */ 2927 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 2928 { 2929 struct intel_display *display = to_intel_display(state); 2930 struct intel_cdclk_state *cdclk_state = 2931 intel_atomic_get_new_cdclk_state(state); 2932 struct intel_crtc *crtc; 2933 struct intel_crtc_state *crtc_state; 2934 u8 min_voltage_level; 2935 int i; 2936 enum pipe pipe; 2937 2938 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2939 int ret; 2940 2941 if (crtc_state->hw.enable) 2942 min_voltage_level = crtc_state->min_voltage_level; 2943 else 2944 min_voltage_level = 0; 2945 2946 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2947 continue; 2948 2949 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2950 2951 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2952 if (ret) 2953 return ret; 2954 } 2955 2956 min_voltage_level = 0; 2957 for_each_pipe(display, pipe) 2958 min_voltage_level = max(min_voltage_level, 2959 cdclk_state->min_voltage_level[pipe]); 2960 2961 return min_voltage_level; 2962 } 2963 2964 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 2965 { 2966 struct intel_display *display = to_intel_display(state); 2967 struct intel_cdclk_state *cdclk_state = 2968 intel_atomic_get_new_cdclk_state(state); 2969 int min_cdclk, cdclk; 2970 2971 min_cdclk = intel_compute_min_cdclk(state); 2972 if (min_cdclk < 0) 2973 return min_cdclk; 2974 2975 cdclk = vlv_calc_cdclk(display, min_cdclk); 2976 2977 cdclk_state->logical.cdclk = cdclk; 2978 cdclk_state->logical.voltage_level = 2979 vlv_calc_voltage_level(display, cdclk); 2980 2981 if (!cdclk_state->active_pipes) { 2982 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); 2983 2984 cdclk_state->actual.cdclk = cdclk; 2985 cdclk_state->actual.voltage_level = 2986 vlv_calc_voltage_level(display, cdclk); 2987 } else { 2988 cdclk_state->actual = cdclk_state->logical; 2989 } 2990 2991 return 0; 2992 } 2993 2994 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 2995 { 2996 struct intel_cdclk_state *cdclk_state = 2997 intel_atomic_get_new_cdclk_state(state); 2998 int min_cdclk, cdclk; 2999 3000 min_cdclk = intel_compute_min_cdclk(state); 3001 if (min_cdclk < 0) 3002 return min_cdclk; 3003 3004 cdclk = bdw_calc_cdclk(min_cdclk); 3005 3006 cdclk_state->logical.cdclk = cdclk; 3007 cdclk_state->logical.voltage_level = 3008 bdw_calc_voltage_level(cdclk); 3009 3010 if (!cdclk_state->active_pipes) { 3011 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 3012 3013 cdclk_state->actual.cdclk = cdclk; 3014 cdclk_state->actual.voltage_level = 3015 bdw_calc_voltage_level(cdclk); 3016 } else { 3017 cdclk_state->actual = cdclk_state->logical; 3018 } 3019 3020 return 0; 3021 } 3022 3023 static int skl_dpll0_vco(struct intel_atomic_state *state) 3024 { 3025 struct intel_display *display = to_intel_display(state); 3026 struct intel_cdclk_state *cdclk_state = 3027 intel_atomic_get_new_cdclk_state(state); 3028 struct intel_crtc *crtc; 3029 struct intel_crtc_state *crtc_state; 3030 int vco, i; 3031 3032 vco = cdclk_state->logical.vco; 3033 if (!vco) 3034 vco = display->cdclk.skl_preferred_vco_freq; 3035 3036 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 3037 if (!crtc_state->hw.enable) 3038 continue; 3039 3040 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3041 continue; 3042 3043 /* 3044 * DPLL0 VCO may need to be adjusted to get the correct 3045 * clock for eDP. This will affect cdclk as well. 3046 */ 3047 switch (crtc_state->port_clock / 2) { 3048 case 108000: 3049 case 216000: 3050 vco = 8640000; 3051 break; 3052 default: 3053 vco = 8100000; 3054 break; 3055 } 3056 } 3057 3058 return vco; 3059 } 3060 3061 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3062 { 3063 struct intel_cdclk_state *cdclk_state = 3064 intel_atomic_get_new_cdclk_state(state); 3065 int min_cdclk, cdclk, vco; 3066 3067 min_cdclk = intel_compute_min_cdclk(state); 3068 if (min_cdclk < 0) 3069 return min_cdclk; 3070 3071 vco = skl_dpll0_vco(state); 3072 3073 cdclk = skl_calc_cdclk(min_cdclk, vco); 3074 3075 cdclk_state->logical.vco = vco; 3076 cdclk_state->logical.cdclk = cdclk; 3077 cdclk_state->logical.voltage_level = 3078 skl_calc_voltage_level(cdclk); 3079 3080 if (!cdclk_state->active_pipes) { 3081 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3082 3083 cdclk_state->actual.vco = vco; 3084 cdclk_state->actual.cdclk = cdclk; 3085 cdclk_state->actual.voltage_level = 3086 skl_calc_voltage_level(cdclk); 3087 } else { 3088 cdclk_state->actual = cdclk_state->logical; 3089 } 3090 3091 return 0; 3092 } 3093 3094 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3095 { 3096 struct intel_display *display = to_intel_display(state); 3097 struct intel_cdclk_state *cdclk_state = 3098 intel_atomic_get_new_cdclk_state(state); 3099 int min_cdclk, min_voltage_level, cdclk, vco; 3100 3101 min_cdclk = intel_compute_min_cdclk(state); 3102 if (min_cdclk < 0) 3103 return min_cdclk; 3104 3105 min_voltage_level = bxt_compute_min_voltage_level(state); 3106 if (min_voltage_level < 0) 3107 return min_voltage_level; 3108 3109 cdclk = bxt_calc_cdclk(display, min_cdclk); 3110 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3111 3112 cdclk_state->logical.vco = vco; 3113 cdclk_state->logical.cdclk = cdclk; 3114 cdclk_state->logical.voltage_level = 3115 max_t(int, min_voltage_level, 3116 intel_cdclk_calc_voltage_level(display, cdclk)); 3117 3118 if (!cdclk_state->active_pipes) { 3119 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); 3120 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3121 3122 cdclk_state->actual.vco = vco; 3123 cdclk_state->actual.cdclk = cdclk; 3124 cdclk_state->actual.voltage_level = 3125 intel_cdclk_calc_voltage_level(display, cdclk); 3126 } else { 3127 cdclk_state->actual = cdclk_state->logical; 3128 } 3129 3130 return 0; 3131 } 3132 3133 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3134 { 3135 int min_cdclk; 3136 3137 /* 3138 * We can't change the cdclk frequency, but we still want to 3139 * check that the required minimum frequency doesn't exceed 3140 * the actual cdclk frequency. 3141 */ 3142 min_cdclk = intel_compute_min_cdclk(state); 3143 if (min_cdclk < 0) 3144 return min_cdclk; 3145 3146 return 0; 3147 } 3148 3149 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3150 { 3151 struct intel_cdclk_state *cdclk_state; 3152 3153 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3154 if (!cdclk_state) 3155 return NULL; 3156 3157 cdclk_state->pipe = INVALID_PIPE; 3158 cdclk_state->disable_pipes = false; 3159 3160 return &cdclk_state->base; 3161 } 3162 3163 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3164 struct intel_global_state *state) 3165 { 3166 kfree(state); 3167 } 3168 3169 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3170 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3171 .atomic_destroy_state = intel_cdclk_destroy_state, 3172 }; 3173 3174 struct intel_cdclk_state * 3175 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3176 { 3177 struct intel_display *display = to_intel_display(state); 3178 struct intel_global_state *cdclk_state; 3179 3180 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); 3181 if (IS_ERR(cdclk_state)) 3182 return ERR_CAST(cdclk_state); 3183 3184 return to_intel_cdclk_state(cdclk_state); 3185 } 3186 3187 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 3188 bool *need_cdclk_calc) 3189 { 3190 const struct intel_cdclk_state *old_cdclk_state; 3191 const struct intel_cdclk_state *new_cdclk_state; 3192 struct intel_plane_state __maybe_unused *plane_state; 3193 struct intel_plane *plane; 3194 int ret; 3195 int i; 3196 3197 /* 3198 * active_planes bitmask has been updated, and potentially affected 3199 * planes are part of the state. We can now compute the minimum cdclk 3200 * for each plane. 3201 */ 3202 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 3203 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 3204 if (ret) 3205 return ret; 3206 } 3207 3208 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 3209 if (ret) 3210 return ret; 3211 3212 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3213 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3214 3215 if (new_cdclk_state && 3216 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 3217 *need_cdclk_calc = true; 3218 3219 return 0; 3220 } 3221 3222 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3223 { 3224 struct intel_cdclk_state *cdclk_state; 3225 3226 cdclk_state = intel_atomic_get_cdclk_state(state); 3227 if (IS_ERR(cdclk_state)) 3228 return PTR_ERR(cdclk_state); 3229 3230 cdclk_state->actual.joined_mbus = joined_mbus; 3231 cdclk_state->logical.joined_mbus = joined_mbus; 3232 3233 return intel_atomic_lock_global_state(&cdclk_state->base); 3234 } 3235 3236 int intel_cdclk_init(struct intel_display *display) 3237 { 3238 struct intel_cdclk_state *cdclk_state; 3239 3240 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 3241 if (!cdclk_state) 3242 return -ENOMEM; 3243 3244 intel_atomic_global_obj_init(display, &display->cdclk.obj, 3245 &cdclk_state->base, &intel_cdclk_funcs); 3246 3247 return 0; 3248 } 3249 3250 static bool intel_cdclk_need_serialize(struct intel_display *display, 3251 const struct intel_cdclk_state *old_cdclk_state, 3252 const struct intel_cdclk_state *new_cdclk_state) 3253 { 3254 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != 3255 hweight8(new_cdclk_state->active_pipes); 3256 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, 3257 &new_cdclk_state->actual); 3258 /* 3259 * We need to poke hw for gen >= 12, because we notify PCode if 3260 * pipe power well count changes. 3261 */ 3262 return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed); 3263 } 3264 3265 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3266 { 3267 struct intel_display *display = to_intel_display(state); 3268 const struct intel_cdclk_state *old_cdclk_state; 3269 struct intel_cdclk_state *new_cdclk_state; 3270 enum pipe pipe = INVALID_PIPE; 3271 int ret; 3272 3273 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3274 if (IS_ERR(new_cdclk_state)) 3275 return PTR_ERR(new_cdclk_state); 3276 3277 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3278 3279 new_cdclk_state->active_pipes = 3280 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3281 3282 ret = intel_cdclk_modeset_calc_cdclk(state); 3283 if (ret) 3284 return ret; 3285 3286 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { 3287 /* 3288 * Also serialize commits across all crtcs 3289 * if the actual hw needs to be poked. 3290 */ 3291 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3292 if (ret) 3293 return ret; 3294 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 3295 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 3296 intel_cdclk_changed(&old_cdclk_state->logical, 3297 &new_cdclk_state->logical)) { 3298 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3299 if (ret) 3300 return ret; 3301 } else { 3302 return 0; 3303 } 3304 3305 if (is_power_of_2(new_cdclk_state->active_pipes) && 3306 intel_cdclk_can_cd2x_update(display, 3307 &old_cdclk_state->actual, 3308 &new_cdclk_state->actual)) { 3309 struct intel_crtc *crtc; 3310 struct intel_crtc_state *crtc_state; 3311 3312 pipe = ilog2(new_cdclk_state->active_pipes); 3313 crtc = intel_crtc_for_pipe(display, pipe); 3314 3315 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3316 if (IS_ERR(crtc_state)) 3317 return PTR_ERR(crtc_state); 3318 3319 if (intel_crtc_needs_modeset(crtc_state)) 3320 pipe = INVALID_PIPE; 3321 } 3322 3323 if (intel_cdclk_can_crawl_and_squash(display, 3324 &old_cdclk_state->actual, 3325 &new_cdclk_state->actual)) { 3326 drm_dbg_kms(display->drm, 3327 "Can change cdclk via crawling and squashing\n"); 3328 } else if (intel_cdclk_can_squash(display, 3329 &old_cdclk_state->actual, 3330 &new_cdclk_state->actual)) { 3331 drm_dbg_kms(display->drm, 3332 "Can change cdclk via squashing\n"); 3333 } else if (intel_cdclk_can_crawl(display, 3334 &old_cdclk_state->actual, 3335 &new_cdclk_state->actual)) { 3336 drm_dbg_kms(display->drm, 3337 "Can change cdclk via crawling\n"); 3338 } else if (pipe != INVALID_PIPE) { 3339 new_cdclk_state->pipe = pipe; 3340 3341 drm_dbg_kms(display->drm, 3342 "Can change cdclk cd2x divider with pipe %c active\n", 3343 pipe_name(pipe)); 3344 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3345 &new_cdclk_state->actual)) { 3346 /* All pipes must be switched off while we change the cdclk. */ 3347 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3348 if (ret) 3349 return ret; 3350 3351 new_cdclk_state->disable_pipes = true; 3352 3353 drm_dbg_kms(display->drm, 3354 "Modeset required for cdclk change\n"); 3355 } 3356 3357 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != 3358 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { 3359 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); 3360 3361 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3362 if (ret) 3363 return ret; 3364 } 3365 3366 drm_dbg_kms(display->drm, 3367 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3368 new_cdclk_state->logical.cdclk, 3369 new_cdclk_state->actual.cdclk); 3370 drm_dbg_kms(display->drm, 3371 "New voltage level calculated to be logical %u, actual %u\n", 3372 new_cdclk_state->logical.voltage_level, 3373 new_cdclk_state->actual.voltage_level); 3374 3375 return 0; 3376 } 3377 3378 void intel_cdclk_update_hw_state(struct intel_display *display) 3379 { 3380 const struct intel_bw_state *bw_state = 3381 to_intel_bw_state(display->bw.obj.state); 3382 struct intel_cdclk_state *cdclk_state = 3383 to_intel_cdclk_state(display->cdclk.obj.state); 3384 struct intel_crtc *crtc; 3385 3386 cdclk_state->active_pipes = 0; 3387 3388 for_each_intel_crtc(display->drm, crtc) { 3389 const struct intel_crtc_state *crtc_state = 3390 to_intel_crtc_state(crtc->base.state); 3391 enum pipe pipe = crtc->pipe; 3392 3393 if (crtc_state->hw.active) 3394 cdclk_state->active_pipes |= BIT(pipe); 3395 3396 cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state); 3397 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level; 3398 } 3399 3400 cdclk_state->bw_min_cdclk = intel_bw_min_cdclk(display, bw_state); 3401 } 3402 3403 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc) 3404 { 3405 struct intel_display *display = to_intel_display(crtc); 3406 3407 intel_cdclk_update_hw_state(display); 3408 } 3409 3410 static int intel_compute_max_dotclk(struct intel_display *display) 3411 { 3412 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); 3413 int guardband = intel_cdclk_guardband(display); 3414 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3415 3416 return ppc * max_cdclk_freq * guardband / 100; 3417 } 3418 3419 /** 3420 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3421 * @display: display instance 3422 * 3423 * Determine the maximum CDCLK frequency the platform supports, and also 3424 * derive the maximum dot clock frequency the maximum CDCLK frequency 3425 * allows. 3426 */ 3427 void intel_update_max_cdclk(struct intel_display *display) 3428 { 3429 if (DISPLAY_VERx100(display) >= 3002) { 3430 display->cdclk.max_cdclk_freq = 480000; 3431 } else if (DISPLAY_VER(display) >= 30) { 3432 display->cdclk.max_cdclk_freq = 691200; 3433 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3434 if (display->cdclk.hw.ref == 24000) 3435 display->cdclk.max_cdclk_freq = 552000; 3436 else 3437 display->cdclk.max_cdclk_freq = 556800; 3438 } else if (DISPLAY_VER(display) >= 11) { 3439 if (display->cdclk.hw.ref == 24000) 3440 display->cdclk.max_cdclk_freq = 648000; 3441 else 3442 display->cdclk.max_cdclk_freq = 652800; 3443 } else if (display->platform.geminilake) { 3444 display->cdclk.max_cdclk_freq = 316800; 3445 } else if (display->platform.broxton) { 3446 display->cdclk.max_cdclk_freq = 624000; 3447 } else if (DISPLAY_VER(display) == 9) { 3448 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3449 int max_cdclk, vco; 3450 3451 vco = display->cdclk.skl_preferred_vco_freq; 3452 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 3453 3454 /* 3455 * Use the lower (vco 8640) cdclk values as a 3456 * first guess. skl_calc_cdclk() will correct it 3457 * if the preferred vco is 8100 instead. 3458 */ 3459 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3460 max_cdclk = 617143; 3461 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3462 max_cdclk = 540000; 3463 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3464 max_cdclk = 432000; 3465 else 3466 max_cdclk = 308571; 3467 3468 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3469 } else if (display->platform.broadwell) { 3470 /* 3471 * FIXME with extra cooling we can allow 3472 * 540 MHz for ULX and 675 Mhz for ULT. 3473 * How can we know if extra cooling is 3474 * available? PCI ID, VTB, something else? 3475 */ 3476 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3477 display->cdclk.max_cdclk_freq = 450000; 3478 else if (display->platform.broadwell_ulx) 3479 display->cdclk.max_cdclk_freq = 450000; 3480 else if (display->platform.broadwell_ult) 3481 display->cdclk.max_cdclk_freq = 540000; 3482 else 3483 display->cdclk.max_cdclk_freq = 675000; 3484 } else if (display->platform.cherryview) { 3485 display->cdclk.max_cdclk_freq = 320000; 3486 } else if (display->platform.valleyview) { 3487 display->cdclk.max_cdclk_freq = 400000; 3488 } else { 3489 /* otherwise assume cdclk is fixed */ 3490 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; 3491 } 3492 3493 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); 3494 3495 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", 3496 display->cdclk.max_cdclk_freq); 3497 3498 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", 3499 display->cdclk.max_dotclk_freq); 3500 } 3501 3502 /** 3503 * intel_update_cdclk - Determine the current CDCLK frequency 3504 * @display: display instance 3505 * 3506 * Determine the current CDCLK frequency. 3507 */ 3508 void intel_update_cdclk(struct intel_display *display) 3509 { 3510 intel_cdclk_get_cdclk(display, &display->cdclk.hw); 3511 3512 /* 3513 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3514 * Programmng [sic] note: bit[9:2] should be programmed to the number 3515 * of cdclk that generates 4MHz reference clock freq which is used to 3516 * generate GMBus clock. This will vary with the cdclk freq. 3517 */ 3518 if (display->platform.valleyview || display->platform.cherryview) 3519 intel_de_write(display, GMBUSFREQ_VLV, 3520 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); 3521 } 3522 3523 static int dg1_rawclk(struct intel_display *display) 3524 { 3525 /* 3526 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3527 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3528 */ 3529 intel_de_write(display, PCH_RAWCLK_FREQ, 3530 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3531 3532 return 38400; 3533 } 3534 3535 static int cnp_rawclk(struct intel_display *display) 3536 { 3537 int divider, fraction; 3538 u32 rawclk; 3539 3540 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3541 /* 24 MHz */ 3542 divider = 24000; 3543 fraction = 0; 3544 } else { 3545 /* 19.2 MHz */ 3546 divider = 19000; 3547 fraction = 200; 3548 } 3549 3550 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3551 if (fraction) { 3552 int numerator = 1; 3553 3554 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3555 fraction) - 1); 3556 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 3557 rawclk |= ICP_RAWCLK_NUM(numerator); 3558 } 3559 3560 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); 3561 return divider + fraction; 3562 } 3563 3564 static int pch_rawclk(struct intel_display *display) 3565 { 3566 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3567 } 3568 3569 static int vlv_hrawclk(struct intel_display *display) 3570 { 3571 /* RAWCLK_FREQ_VLV register updated from power well code */ 3572 return vlv_get_cck_clock_hpll(display->drm, "hrawclk", 3573 CCK_DISPLAY_REF_CLOCK_CONTROL); 3574 } 3575 3576 static int i9xx_hrawclk(struct intel_display *display) 3577 { 3578 struct drm_i915_private *i915 = to_i915(display->drm); 3579 3580 /* hrawclock is 1/4 the FSB frequency */ 3581 return DIV_ROUND_CLOSEST(intel_fsb_freq(i915), 4); 3582 } 3583 3584 /** 3585 * intel_read_rawclk - Determine the current RAWCLK frequency 3586 * @display: display instance 3587 * 3588 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3589 * frequency clock so this needs to done only once. 3590 */ 3591 u32 intel_read_rawclk(struct intel_display *display) 3592 { 3593 u32 freq; 3594 3595 if (INTEL_PCH_TYPE(display) >= PCH_MTL) 3596 /* 3597 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3598 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3599 * not need to be programmed." 3600 */ 3601 freq = 38400; 3602 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 3603 freq = dg1_rawclk(display); 3604 else if (INTEL_PCH_TYPE(display) >= PCH_CNP) 3605 freq = cnp_rawclk(display); 3606 else if (HAS_PCH_SPLIT(display)) 3607 freq = pch_rawclk(display); 3608 else if (display->platform.valleyview || display->platform.cherryview) 3609 freq = vlv_hrawclk(display); 3610 else if (DISPLAY_VER(display) >= 3) 3611 freq = i9xx_hrawclk(display); 3612 else 3613 /* no rawclk on other platforms, or no need to know it */ 3614 return 0; 3615 3616 return freq; 3617 } 3618 3619 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3620 { 3621 struct intel_display *display = m->private; 3622 3623 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); 3624 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); 3625 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); 3626 3627 return 0; 3628 } 3629 3630 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3631 3632 void intel_cdclk_debugfs_register(struct intel_display *display) 3633 { 3634 debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root, 3635 display, &i915_cdclk_info_fops); 3636 } 3637 3638 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { 3639 .get_cdclk = bxt_get_cdclk, 3640 .set_cdclk = bxt_set_cdclk, 3641 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3642 .calc_voltage_level = xe3lpd_calc_voltage_level, 3643 }; 3644 3645 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3646 .get_cdclk = bxt_get_cdclk, 3647 .set_cdclk = bxt_set_cdclk, 3648 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3649 .calc_voltage_level = rplu_calc_voltage_level, 3650 }; 3651 3652 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3653 .get_cdclk = bxt_get_cdclk, 3654 .set_cdclk = bxt_set_cdclk, 3655 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3656 .calc_voltage_level = tgl_calc_voltage_level, 3657 }; 3658 3659 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3660 .get_cdclk = bxt_get_cdclk, 3661 .set_cdclk = bxt_set_cdclk, 3662 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3663 .calc_voltage_level = ehl_calc_voltage_level, 3664 }; 3665 3666 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3667 .get_cdclk = bxt_get_cdclk, 3668 .set_cdclk = bxt_set_cdclk, 3669 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3670 .calc_voltage_level = icl_calc_voltage_level, 3671 }; 3672 3673 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3674 .get_cdclk = bxt_get_cdclk, 3675 .set_cdclk = bxt_set_cdclk, 3676 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3677 .calc_voltage_level = bxt_calc_voltage_level, 3678 }; 3679 3680 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3681 .get_cdclk = skl_get_cdclk, 3682 .set_cdclk = skl_set_cdclk, 3683 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3684 }; 3685 3686 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3687 .get_cdclk = bdw_get_cdclk, 3688 .set_cdclk = bdw_set_cdclk, 3689 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3690 }; 3691 3692 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3693 .get_cdclk = vlv_get_cdclk, 3694 .set_cdclk = chv_set_cdclk, 3695 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3696 }; 3697 3698 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3699 .get_cdclk = vlv_get_cdclk, 3700 .set_cdclk = vlv_set_cdclk, 3701 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3702 }; 3703 3704 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3705 .get_cdclk = hsw_get_cdclk, 3706 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3707 }; 3708 3709 /* SNB, IVB, 965G, 945G */ 3710 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3711 .get_cdclk = fixed_400mhz_get_cdclk, 3712 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3713 }; 3714 3715 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3716 .get_cdclk = fixed_450mhz_get_cdclk, 3717 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3718 }; 3719 3720 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3721 .get_cdclk = gm45_get_cdclk, 3722 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3723 }; 3724 3725 /* G45 uses G33 */ 3726 3727 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3728 .get_cdclk = i965gm_get_cdclk, 3729 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3730 }; 3731 3732 /* i965G uses fixed 400 */ 3733 3734 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3735 .get_cdclk = pnv_get_cdclk, 3736 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3737 }; 3738 3739 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3740 .get_cdclk = g33_get_cdclk, 3741 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3742 }; 3743 3744 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3745 .get_cdclk = i945gm_get_cdclk, 3746 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3747 }; 3748 3749 /* i945G uses fixed 400 */ 3750 3751 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3752 .get_cdclk = i915gm_get_cdclk, 3753 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3754 }; 3755 3756 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3757 .get_cdclk = fixed_333mhz_get_cdclk, 3758 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3759 }; 3760 3761 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3762 .get_cdclk = fixed_266mhz_get_cdclk, 3763 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3764 }; 3765 3766 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3767 .get_cdclk = i85x_get_cdclk, 3768 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3769 }; 3770 3771 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3772 .get_cdclk = fixed_200mhz_get_cdclk, 3773 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3774 }; 3775 3776 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3777 .get_cdclk = fixed_133mhz_get_cdclk, 3778 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3779 }; 3780 3781 /** 3782 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3783 * @display: display instance 3784 */ 3785 void intel_init_cdclk_hooks(struct intel_display *display) 3786 { 3787 if (DISPLAY_VER(display) >= 30) { 3788 display->funcs.cdclk = &xe3lpd_cdclk_funcs; 3789 display->cdclk.table = xe3lpd_cdclk_table; 3790 } else if (DISPLAY_VER(display) >= 20) { 3791 display->funcs.cdclk = &rplu_cdclk_funcs; 3792 display->cdclk.table = xe2lpd_cdclk_table; 3793 } else if (DISPLAY_VERx100(display) >= 1401) { 3794 display->funcs.cdclk = &rplu_cdclk_funcs; 3795 display->cdclk.table = xe2hpd_cdclk_table; 3796 } else if (DISPLAY_VER(display) >= 14) { 3797 display->funcs.cdclk = &rplu_cdclk_funcs; 3798 display->cdclk.table = mtl_cdclk_table; 3799 } else if (display->platform.dg2) { 3800 display->funcs.cdclk = &tgl_cdclk_funcs; 3801 display->cdclk.table = dg2_cdclk_table; 3802 } else if (display->platform.alderlake_p) { 3803 /* Wa_22011320316:adl-p[a0] */ 3804 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 3805 display->cdclk.table = adlp_a_step_cdclk_table; 3806 display->funcs.cdclk = &tgl_cdclk_funcs; 3807 } else if (display->platform.alderlake_p_raptorlake_u) { 3808 display->cdclk.table = rplu_cdclk_table; 3809 display->funcs.cdclk = &rplu_cdclk_funcs; 3810 } else { 3811 display->cdclk.table = adlp_cdclk_table; 3812 display->funcs.cdclk = &tgl_cdclk_funcs; 3813 } 3814 } else if (display->platform.rocketlake) { 3815 display->funcs.cdclk = &tgl_cdclk_funcs; 3816 display->cdclk.table = rkl_cdclk_table; 3817 } else if (DISPLAY_VER(display) >= 12) { 3818 display->funcs.cdclk = &tgl_cdclk_funcs; 3819 display->cdclk.table = icl_cdclk_table; 3820 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3821 display->funcs.cdclk = &ehl_cdclk_funcs; 3822 display->cdclk.table = icl_cdclk_table; 3823 } else if (DISPLAY_VER(display) >= 11) { 3824 display->funcs.cdclk = &icl_cdclk_funcs; 3825 display->cdclk.table = icl_cdclk_table; 3826 } else if (display->platform.geminilake || display->platform.broxton) { 3827 display->funcs.cdclk = &bxt_cdclk_funcs; 3828 if (display->platform.geminilake) 3829 display->cdclk.table = glk_cdclk_table; 3830 else 3831 display->cdclk.table = bxt_cdclk_table; 3832 } else if (DISPLAY_VER(display) == 9) { 3833 display->funcs.cdclk = &skl_cdclk_funcs; 3834 } else if (display->platform.broadwell) { 3835 display->funcs.cdclk = &bdw_cdclk_funcs; 3836 } else if (display->platform.haswell) { 3837 display->funcs.cdclk = &hsw_cdclk_funcs; 3838 } else if (display->platform.cherryview) { 3839 display->funcs.cdclk = &chv_cdclk_funcs; 3840 } else if (display->platform.valleyview) { 3841 display->funcs.cdclk = &vlv_cdclk_funcs; 3842 } else if (display->platform.sandybridge || display->platform.ivybridge) { 3843 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3844 } else if (display->platform.ironlake) { 3845 display->funcs.cdclk = &ilk_cdclk_funcs; 3846 } else if (display->platform.gm45) { 3847 display->funcs.cdclk = &gm45_cdclk_funcs; 3848 } else if (display->platform.g45) { 3849 display->funcs.cdclk = &g33_cdclk_funcs; 3850 } else if (display->platform.i965gm) { 3851 display->funcs.cdclk = &i965gm_cdclk_funcs; 3852 } else if (display->platform.i965g) { 3853 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3854 } else if (display->platform.pineview) { 3855 display->funcs.cdclk = &pnv_cdclk_funcs; 3856 } else if (display->platform.g33) { 3857 display->funcs.cdclk = &g33_cdclk_funcs; 3858 } else if (display->platform.i945gm) { 3859 display->funcs.cdclk = &i945gm_cdclk_funcs; 3860 } else if (display->platform.i945g) { 3861 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3862 } else if (display->platform.i915gm) { 3863 display->funcs.cdclk = &i915gm_cdclk_funcs; 3864 } else if (display->platform.i915g) { 3865 display->funcs.cdclk = &i915g_cdclk_funcs; 3866 } else if (display->platform.i865g) { 3867 display->funcs.cdclk = &i865g_cdclk_funcs; 3868 } else if (display->platform.i85x) { 3869 display->funcs.cdclk = &i85x_cdclk_funcs; 3870 } else if (display->platform.i845g) { 3871 display->funcs.cdclk = &i845g_cdclk_funcs; 3872 } else if (display->platform.i830) { 3873 display->funcs.cdclk = &i830_cdclk_funcs; 3874 } 3875 3876 if (drm_WARN(display->drm, !display->funcs.cdclk, 3877 "Unknown platform. Assuming i830\n")) 3878 display->funcs.cdclk = &i830_cdclk_funcs; 3879 } 3880 3881 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state) 3882 { 3883 return cdclk_state->logical.cdclk; 3884 } 3885 3886 int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state) 3887 { 3888 return cdclk_state->actual.cdclk; 3889 } 3890 3891 int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state) 3892 { 3893 return cdclk_state->actual.voltage_level; 3894 } 3895 3896 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe) 3897 { 3898 return cdclk_state->min_cdclk[pipe]; 3899 } 3900 3901 int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state) 3902 { 3903 return cdclk_state->bw_min_cdclk; 3904 } 3905 3906 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state) 3907 { 3908 const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state; 3909 3910 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3911 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3912 3913 if (new_cdclk_state && 3914 (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk || 3915 new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level)) 3916 return true; 3917 3918 return false; 3919 } 3920 3921 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk) 3922 { 3923 cdclk_state->force_min_cdclk = force_min_cdclk; 3924 } 3925 3926 void intel_cdclk_read_hw(struct intel_display *display) 3927 { 3928 struct intel_cdclk_state *cdclk_state; 3929 3930 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); 3931 3932 intel_update_cdclk(display); 3933 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 3934 cdclk_state->actual = display->cdclk.hw; 3935 cdclk_state->logical = display->cdclk.hw; 3936 } 3937