1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/iopoll.h> 26 #include <linux/time.h> 27 28 #include <drm/drm_fixed.h> 29 #include <drm/drm_print.h> 30 #include <drm/intel/intel_pcode_regs.h> 31 #include <drm/intel/pci_config.h> 32 #include <drm/intel/step.h> 33 34 #include "hsw_ips.h" 35 #include "intel_atomic.h" 36 #include "intel_audio.h" 37 #include "intel_cdclk.h" 38 #include "intel_crtc.h" 39 #include "intel_dbuf_bw.h" 40 #include "intel_de.h" 41 #include "intel_display_regs.h" 42 #include "intel_display_types.h" 43 #include "intel_display_utils.h" 44 #include "intel_display_wa.h" 45 #include "intel_dram.h" 46 #include "intel_mchbar.h" 47 #include "intel_parent.h" 48 #include "intel_plane.h" 49 #include "intel_psr.h" 50 #include "intel_vdsc.h" 51 #include "skl_watermark.h" 52 #include "skl_watermark_regs.h" 53 #include "vlv_clock.h" 54 #include "vlv_dsi.h" 55 #include "vlv_sideband.h" 56 57 /** 58 * DOC: CDCLK / RAWCLK 59 * 60 * The display engine uses several different clocks to do its work. There 61 * are two main clocks involved that aren't directly related to the actual 62 * pixel clock or any symbol/bit clock of the actual output port. These 63 * are the core display clock (CDCLK) and RAWCLK. 64 * 65 * CDCLK clocks most of the display pipe logic, and thus its frequency 66 * must be high enough to support the rate at which pixels are flowing 67 * through the pipes. Downscaling must also be accounted as that increases 68 * the effective pixel rate. 69 * 70 * On several platforms the CDCLK frequency can be changed dynamically 71 * to minimize power consumption for a given display configuration. 72 * Typically changes to the CDCLK frequency require all the display pipes 73 * to be shut down while the frequency is being changed. 74 * 75 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 76 * DMC will not change the active CDCLK frequency however, so that part 77 * will still be performed by the driver directly. 78 * 79 * There are multiple components involved in the generation of the CDCLK 80 * frequency: 81 * 82 * - We have the CDCLK PLL, which generates an output clock based on a 83 * reference clock and a ratio parameter. 84 * - The CD2X Divider, which divides the output of the PLL based on a 85 * divisor selected from a set of pre-defined choices. 86 * - The CD2X Squasher, which further divides the output based on a 87 * waveform represented as a sequence of bits where each zero 88 * "squashes out" a clock cycle. 89 * - And, finally, a fixed divider that divides the output frequency by 2. 90 * 91 * As such, the resulting CDCLK frequency can be calculated with the 92 * following formula: 93 * 94 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 95 * 96 * , where vco is the frequency generated by the PLL; cd2x_div 97 * represents the CD2X Divider; sq_len and sq_div are the bit length 98 * and the number of high bits for the CD2X Squasher waveform, respectively; 99 * and 2 represents the fixed divider. 100 * 101 * Note that some older platforms do not contain the CD2X Divider 102 * and/or CD2X Squasher, in which case we can ignore their respective 103 * factors in the formula above. 104 * 105 * Several methods exist to change the CDCLK frequency, which ones are 106 * supported depends on the platform: 107 * 108 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 109 * - CD2X divider update. Single pipe can be active as the divider update 110 * can be synchronized with the pipe's start of vblank. 111 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 112 * - Squash waveform update. Pipes can be active. 113 * - Crawl and squash can also be done back to back. Pipes can be active. 114 * 115 * RAWCLK is a fixed frequency clock, often used by various auxiliary 116 * blocks such as AUX CH or backlight PWM. Hence the only thing we 117 * really need to know about RAWCLK is its frequency so that various 118 * dividers can be programmed correctly. 119 */ 120 121 struct intel_cdclk_state { 122 struct intel_global_state base; 123 124 /* 125 * Logical configuration of cdclk (used for all scaling, 126 * watermark, etc. calculations and checks). This is 127 * computed as if all enabled crtcs were active. 128 */ 129 struct intel_cdclk_config logical; 130 131 /* 132 * Actual configuration of cdclk, can be different from the 133 * logical configuration only when all crtc's are DPMS off. 134 */ 135 struct intel_cdclk_config actual; 136 137 /* minimum acceptable cdclk to satisfy DBUF bandwidth requirements */ 138 int dbuf_bw_min_cdclk; 139 /* minimum acceptable cdclk for each pipe */ 140 int min_cdclk[I915_MAX_PIPES]; 141 /* minimum acceptable voltage level for each pipe */ 142 u8 min_voltage_level[I915_MAX_PIPES]; 143 144 /* pipe to which cd2x update is synchronized */ 145 enum pipe pipe; 146 147 /* forced minimum cdclk for glk+ audio w/a */ 148 int force_min_cdclk; 149 150 /* bitmask of enabled pipes */ 151 u8 enabled_pipes; 152 153 /* bitmask of active pipes */ 154 u8 active_pipes; 155 156 /* update cdclk with pipes disabled */ 157 bool disable_pipes; 158 }; 159 160 struct intel_cdclk_funcs { 161 void (*get_cdclk)(struct intel_display *display, 162 struct intel_cdclk_config *cdclk_config); 163 void (*set_cdclk)(struct intel_display *display, 164 const struct intel_cdclk_config *cdclk_config, 165 enum pipe pipe); 166 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 167 u8 (*calc_voltage_level)(int cdclk); 168 }; 169 170 void intel_cdclk_get_cdclk(struct intel_display *display, 171 struct intel_cdclk_config *cdclk_config) 172 { 173 display->cdclk.funcs->get_cdclk(display, cdclk_config); 174 } 175 176 static void intel_cdclk_set_cdclk(struct intel_display *display, 177 const struct intel_cdclk_config *cdclk_config, 178 enum pipe pipe) 179 { 180 display->cdclk.funcs->set_cdclk(display, cdclk_config, pipe); 181 } 182 183 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 184 { 185 struct intel_display *display = to_intel_display(state); 186 187 return display->cdclk.funcs->modeset_calc_cdclk(state); 188 } 189 190 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, 191 int cdclk) 192 { 193 return display->cdclk.funcs->calc_voltage_level(cdclk); 194 } 195 196 static void fixed_133mhz_get_cdclk(struct intel_display *display, 197 struct intel_cdclk_config *cdclk_config) 198 { 199 cdclk_config->cdclk = 133333; 200 } 201 202 static void fixed_200mhz_get_cdclk(struct intel_display *display, 203 struct intel_cdclk_config *cdclk_config) 204 { 205 cdclk_config->cdclk = 200000; 206 } 207 208 static void fixed_266mhz_get_cdclk(struct intel_display *display, 209 struct intel_cdclk_config *cdclk_config) 210 { 211 cdclk_config->cdclk = 266667; 212 } 213 214 static void fixed_333mhz_get_cdclk(struct intel_display *display, 215 struct intel_cdclk_config *cdclk_config) 216 { 217 cdclk_config->cdclk = 333333; 218 } 219 220 static void fixed_400mhz_get_cdclk(struct intel_display *display, 221 struct intel_cdclk_config *cdclk_config) 222 { 223 cdclk_config->cdclk = 400000; 224 } 225 226 static void fixed_450mhz_get_cdclk(struct intel_display *display, 227 struct intel_cdclk_config *cdclk_config) 228 { 229 cdclk_config->cdclk = 450000; 230 } 231 232 static void i85x_get_cdclk(struct intel_display *display, 233 struct intel_cdclk_config *cdclk_config) 234 { 235 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 236 u16 hpllcc = 0; 237 238 /* 239 * 852GM/852GMV only supports 133 MHz and the HPLLCC 240 * encoding is different :( 241 * FIXME is this the right way to detect 852GM/852GMV? 242 */ 243 if (pdev->revision == 0x1) { 244 cdclk_config->cdclk = 133333; 245 return; 246 } 247 248 pci_bus_read_config_word(pdev->bus, 249 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 250 251 /* Assume that the hardware is in the high speed state. This 252 * should be the default. 253 */ 254 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 255 case GC_CLOCK_133_200: 256 case GC_CLOCK_133_200_2: 257 case GC_CLOCK_100_200: 258 cdclk_config->cdclk = 200000; 259 break; 260 case GC_CLOCK_166_250: 261 cdclk_config->cdclk = 250000; 262 break; 263 case GC_CLOCK_100_133: 264 cdclk_config->cdclk = 133333; 265 break; 266 case GC_CLOCK_133_266: 267 case GC_CLOCK_133_266_2: 268 case GC_CLOCK_166_266: 269 cdclk_config->cdclk = 266667; 270 break; 271 } 272 } 273 274 static void i915gm_get_cdclk(struct intel_display *display, 275 struct intel_cdclk_config *cdclk_config) 276 { 277 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 278 u16 gcfgc = 0; 279 280 pci_read_config_word(pdev, GCFGC, &gcfgc); 281 282 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 283 cdclk_config->cdclk = 133333; 284 return; 285 } 286 287 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 288 case GC_DISPLAY_CLOCK_333_320_MHZ: 289 cdclk_config->cdclk = 333333; 290 break; 291 default: 292 case GC_DISPLAY_CLOCK_190_200_MHZ: 293 cdclk_config->cdclk = 190000; 294 break; 295 } 296 } 297 298 static void i945gm_get_cdclk(struct intel_display *display, 299 struct intel_cdclk_config *cdclk_config) 300 { 301 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 302 u16 gcfgc = 0; 303 304 pci_read_config_word(pdev, GCFGC, &gcfgc); 305 306 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 307 cdclk_config->cdclk = 133333; 308 return; 309 } 310 311 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 312 case GC_DISPLAY_CLOCK_333_320_MHZ: 313 cdclk_config->cdclk = 320000; 314 break; 315 default: 316 case GC_DISPLAY_CLOCK_190_200_MHZ: 317 cdclk_config->cdclk = 200000; 318 break; 319 } 320 } 321 322 static unsigned int intel_hpll_vco(struct intel_display *display) 323 { 324 static const unsigned int blb_vco[8] = { 325 [0] = 3200000, 326 [1] = 4000000, 327 [2] = 5333333, 328 [3] = 4800000, 329 [4] = 6400000, 330 }; 331 static const unsigned int pnv_vco[8] = { 332 [0] = 3200000, 333 [1] = 4000000, 334 [2] = 5333333, 335 [3] = 4800000, 336 [4] = 2666667, 337 }; 338 static const unsigned int cl_vco[8] = { 339 [0] = 3200000, 340 [1] = 4000000, 341 [2] = 5333333, 342 [3] = 6400000, 343 [4] = 3333333, 344 [5] = 3566667, 345 [6] = 4266667, 346 }; 347 static const unsigned int elk_vco[8] = { 348 [0] = 3200000, 349 [1] = 4000000, 350 [2] = 5333333, 351 [3] = 4800000, 352 }; 353 static const unsigned int ctg_vco[8] = { 354 [0] = 3200000, 355 [1] = 4000000, 356 [2] = 5333333, 357 [3] = 6400000, 358 [4] = 2666667, 359 [5] = 4266667, 360 }; 361 const unsigned int *vco_table; 362 unsigned int vco; 363 u8 tmp = 0; 364 365 /* FIXME other chipsets? */ 366 if (display->platform.gm45) 367 vco_table = ctg_vco; 368 else if (display->platform.g45) 369 vco_table = elk_vco; 370 else if (display->platform.i965gm) 371 vco_table = cl_vco; 372 else if (display->platform.pineview) 373 vco_table = pnv_vco; 374 else if (display->platform.g33) 375 vco_table = blb_vco; 376 else 377 return 0; 378 379 tmp = intel_mchbar_read(display, display->platform.pineview || 380 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); 381 382 vco = vco_table[tmp & 0x7]; 383 if (vco == 0) 384 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 385 tmp); 386 else 387 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); 388 389 return vco; 390 } 391 392 static void g33_get_cdclk(struct intel_display *display, 393 struct intel_cdclk_config *cdclk_config) 394 { 395 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 396 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 397 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 398 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 399 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 400 const u8 *div_table; 401 unsigned int cdclk_sel; 402 u16 tmp = 0; 403 404 cdclk_config->vco = intel_hpll_vco(display); 405 406 pci_read_config_word(pdev, GCFGC, &tmp); 407 408 cdclk_sel = (tmp >> 4) & 0x7; 409 410 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 411 goto fail; 412 413 switch (cdclk_config->vco) { 414 case 3200000: 415 div_table = div_3200; 416 break; 417 case 4000000: 418 div_table = div_4000; 419 break; 420 case 4800000: 421 div_table = div_4800; 422 break; 423 case 5333333: 424 div_table = div_5333; 425 break; 426 default: 427 goto fail; 428 } 429 430 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 431 div_table[cdclk_sel]); 432 return; 433 434 fail: 435 drm_err(display->drm, 436 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 437 cdclk_config->vco, tmp); 438 cdclk_config->cdclk = 190476; 439 } 440 441 static void pnv_get_cdclk(struct intel_display *display, 442 struct intel_cdclk_config *cdclk_config) 443 { 444 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 445 u16 gcfgc = 0; 446 447 pci_read_config_word(pdev, GCFGC, &gcfgc); 448 449 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 450 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 451 cdclk_config->cdclk = 266667; 452 break; 453 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 454 cdclk_config->cdclk = 333333; 455 break; 456 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 457 cdclk_config->cdclk = 444444; 458 break; 459 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 460 cdclk_config->cdclk = 200000; 461 break; 462 default: 463 drm_err(display->drm, 464 "Unknown pnv display core clock 0x%04x\n", gcfgc); 465 fallthrough; 466 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 467 cdclk_config->cdclk = 133333; 468 break; 469 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 470 cdclk_config->cdclk = 166667; 471 break; 472 } 473 } 474 475 static void i965gm_get_cdclk(struct intel_display *display, 476 struct intel_cdclk_config *cdclk_config) 477 { 478 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 479 static const u8 div_3200[] = { 16, 10, 8 }; 480 static const u8 div_4000[] = { 20, 12, 10 }; 481 static const u8 div_5333[] = { 24, 16, 14 }; 482 const u8 *div_table; 483 unsigned int cdclk_sel; 484 u16 tmp = 0; 485 486 cdclk_config->vco = intel_hpll_vco(display); 487 488 pci_read_config_word(pdev, GCFGC, &tmp); 489 490 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 491 492 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 493 goto fail; 494 495 switch (cdclk_config->vco) { 496 case 3200000: 497 div_table = div_3200; 498 break; 499 case 4000000: 500 div_table = div_4000; 501 break; 502 case 5333333: 503 div_table = div_5333; 504 break; 505 default: 506 goto fail; 507 } 508 509 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 510 div_table[cdclk_sel]); 511 return; 512 513 fail: 514 drm_err(display->drm, 515 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 516 cdclk_config->vco, tmp); 517 cdclk_config->cdclk = 200000; 518 } 519 520 static void gm45_get_cdclk(struct intel_display *display, 521 struct intel_cdclk_config *cdclk_config) 522 { 523 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 524 unsigned int cdclk_sel; 525 u16 tmp = 0; 526 527 cdclk_config->vco = intel_hpll_vco(display); 528 529 pci_read_config_word(pdev, GCFGC, &tmp); 530 531 cdclk_sel = (tmp >> 12) & 0x1; 532 533 switch (cdclk_config->vco) { 534 case 2666667: 535 case 4000000: 536 case 5333333: 537 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 538 break; 539 case 3200000: 540 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 541 break; 542 default: 543 drm_err(display->drm, 544 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 545 cdclk_config->vco, tmp); 546 cdclk_config->cdclk = 222222; 547 break; 548 } 549 } 550 551 static void hsw_get_cdclk(struct intel_display *display, 552 struct intel_cdclk_config *cdclk_config) 553 { 554 u32 lcpll = intel_de_read(display, LCPLL_CTL); 555 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 556 557 if (lcpll & LCPLL_CD_SOURCE_FCLK) 558 cdclk_config->cdclk = 800000; 559 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 560 cdclk_config->cdclk = 450000; 561 else if (freq == LCPLL_CLK_FREQ_450) 562 cdclk_config->cdclk = 450000; 563 else if (display->platform.haswell_ult) 564 cdclk_config->cdclk = 337500; 565 else 566 cdclk_config->cdclk = 540000; 567 } 568 569 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) 570 { 571 int freq_320 = (vlv_clock_get_hpll_vco(display->drm) << 1) % 320000 != 0 ? 572 333333 : 320000; 573 574 /* 575 * We seem to get an unstable or solid color picture at 200MHz. 576 * Not sure what's wrong. For now use 200MHz only when all pipes 577 * are off. 578 */ 579 if (display->platform.valleyview && min_cdclk > freq_320) 580 return 400000; 581 else if (min_cdclk > 266667) 582 return freq_320; 583 else if (min_cdclk > 0) 584 return 266667; 585 else 586 return 200000; 587 } 588 589 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 590 { 591 if (display->platform.valleyview) { 592 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 593 return 2; 594 else if (cdclk >= 266667) 595 return 1; 596 else 597 return 0; 598 } else { 599 /* 600 * Specs are full of misinformation, but testing on actual 601 * hardware has shown that we just need to write the desired 602 * CCK divider into the Punit register. 603 */ 604 return DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, cdclk) - 1; 605 } 606 } 607 608 static void vlv_get_cdclk(struct intel_display *display, 609 struct intel_cdclk_config *cdclk_config) 610 { 611 u32 val; 612 613 cdclk_config->vco = vlv_clock_get_hpll_vco(display->drm); 614 cdclk_config->cdclk = vlv_clock_get_cdclk(display->drm); 615 616 vlv_punit_get(display); 617 val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 618 vlv_punit_put(display); 619 620 if (display->platform.valleyview) 621 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 622 DSPFREQGUAR_SHIFT; 623 else 624 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 625 DSPFREQGUAR_SHIFT_CHV; 626 } 627 628 static void vlv_program_pfi_credits(struct intel_display *display) 629 { 630 unsigned int credits, default_credits; 631 632 if (display->platform.cherryview) 633 default_credits = PFI_CREDIT(12); 634 else 635 default_credits = PFI_CREDIT(8); 636 637 if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(display->drm)) { 638 /* CHV suggested value is 31 or 63 */ 639 if (display->platform.cherryview) 640 credits = PFI_CREDIT_63; 641 else 642 credits = PFI_CREDIT(15); 643 } else { 644 credits = default_credits; 645 } 646 647 /* 648 * WA - write default credits before re-programming 649 * FIXME: should we also set the resend bit here? 650 */ 651 intel_de_write(display, GCI_CONTROL, 652 VGA_FAST_MODE_DISABLE | default_credits); 653 654 intel_de_write(display, GCI_CONTROL, 655 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 656 657 /* 658 * FIXME is this guaranteed to clear 659 * immediately or should we poll for it? 660 */ 661 drm_WARN_ON(display->drm, 662 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); 663 } 664 665 static void vlv_set_cdclk(struct intel_display *display, 666 const struct intel_cdclk_config *cdclk_config, 667 enum pipe pipe) 668 { 669 int cdclk = cdclk_config->cdclk; 670 u32 val, cmd = cdclk_config->voltage_level; 671 struct ref_tracker *wakeref; 672 int ret; 673 674 switch (cdclk) { 675 case 400000: 676 case 333333: 677 case 320000: 678 case 266667: 679 case 200000: 680 break; 681 default: 682 MISSING_CASE(cdclk); 683 return; 684 } 685 686 /* There are cases where we can end up here with power domains 687 * off and a CDCLK frequency other than the minimum, like when 688 * issuing a modeset without actually changing any display after 689 * a system suspend. So grab the display core domain, which covers 690 * the HW blocks needed for the following programming. 691 */ 692 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 693 694 intel_parent_vlv_iosf_get(display, 695 BIT(VLV_IOSF_SB_CCK) | 696 BIT(VLV_IOSF_SB_BUNIT) | 697 BIT(VLV_IOSF_SB_PUNIT)); 698 699 val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 700 val &= ~DSPFREQGUAR_MASK; 701 val |= (cmd << DSPFREQGUAR_SHIFT); 702 vlv_punit_write(display, PUNIT_REG_DSPSSPM, val); 703 704 ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM), 705 (val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 706 500, 50 * 1000, false); 707 if (ret) 708 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 709 710 if (cdclk == 400000) { 711 u32 divider; 712 713 divider = DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, 714 cdclk) - 1; 715 716 /* adjust cdclk divider */ 717 val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL); 718 val &= ~CCK_FREQUENCY_VALUES; 719 val |= divider; 720 vlv_cck_write(display, CCK_DISPLAY_CLOCK_CONTROL, val); 721 722 ret = poll_timeout_us(val = vlv_cck_read(display, CCK_DISPLAY_CLOCK_CONTROL), 723 (val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 724 500, 50 * 1000, false); 725 if (ret) 726 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 727 } 728 729 /* adjust self-refresh exit latency value */ 730 val = vlv_bunit_read(display, BUNIT_REG_BISOC); 731 val &= ~0x7f; 732 733 /* 734 * For high bandwidth configs, we set a higher latency in the bunit 735 * so that the core display fetch happens in time to avoid underruns. 736 */ 737 if (cdclk == 400000) 738 val |= 4500 / 250; /* 4.5 usec */ 739 else 740 val |= 3000 / 250; /* 3.0 usec */ 741 vlv_bunit_write(display, BUNIT_REG_BISOC, val); 742 743 intel_parent_vlv_iosf_put(display, 744 BIT(VLV_IOSF_SB_CCK) | 745 BIT(VLV_IOSF_SB_BUNIT) | 746 BIT(VLV_IOSF_SB_PUNIT)); 747 748 intel_update_cdclk(display); 749 750 vlv_program_pfi_credits(display); 751 752 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 753 } 754 755 static void chv_set_cdclk(struct intel_display *display, 756 const struct intel_cdclk_config *cdclk_config, 757 enum pipe pipe) 758 { 759 int cdclk = cdclk_config->cdclk; 760 u32 val, cmd = cdclk_config->voltage_level; 761 struct ref_tracker *wakeref; 762 int ret; 763 764 switch (cdclk) { 765 case 333333: 766 case 320000: 767 case 266667: 768 case 200000: 769 break; 770 default: 771 MISSING_CASE(cdclk); 772 return; 773 } 774 775 /* There are cases where we can end up here with power domains 776 * off and a CDCLK frequency other than the minimum, like when 777 * issuing a modeset without actually changing any display after 778 * a system suspend. So grab the display core domain, which covers 779 * the HW blocks needed for the following programming. 780 */ 781 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 782 783 vlv_punit_get(display); 784 val = vlv_punit_read(display, PUNIT_REG_DSPSSPM); 785 val &= ~DSPFREQGUAR_MASK_CHV; 786 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 787 vlv_punit_write(display, PUNIT_REG_DSPSSPM, val); 788 789 ret = poll_timeout_us(val = vlv_punit_read(display, PUNIT_REG_DSPSSPM), 790 (val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 791 500, 50 * 1000, false); 792 if (ret) 793 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 794 795 vlv_punit_put(display); 796 797 intel_update_cdclk(display); 798 799 vlv_program_pfi_credits(display); 800 801 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 802 } 803 804 static int bdw_calc_cdclk(int min_cdclk) 805 { 806 if (min_cdclk > 540000) 807 return 675000; 808 else if (min_cdclk > 450000) 809 return 540000; 810 else if (min_cdclk > 337500) 811 return 450000; 812 else 813 return 337500; 814 } 815 816 static u8 bdw_calc_voltage_level(int cdclk) 817 { 818 switch (cdclk) { 819 default: 820 case 337500: 821 return 2; 822 case 450000: 823 return 0; 824 case 540000: 825 return 1; 826 case 675000: 827 return 3; 828 } 829 } 830 831 static void bdw_get_cdclk(struct intel_display *display, 832 struct intel_cdclk_config *cdclk_config) 833 { 834 u32 lcpll = intel_de_read(display, LCPLL_CTL); 835 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 836 837 if (lcpll & LCPLL_CD_SOURCE_FCLK) 838 cdclk_config->cdclk = 800000; 839 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 840 cdclk_config->cdclk = 450000; 841 else if (freq == LCPLL_CLK_FREQ_450) 842 cdclk_config->cdclk = 450000; 843 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 844 cdclk_config->cdclk = 540000; 845 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 846 cdclk_config->cdclk = 337500; 847 else 848 cdclk_config->cdclk = 675000; 849 850 /* 851 * Can't read this out :( Let's assume it's 852 * at least what the CDCLK frequency requires. 853 */ 854 cdclk_config->voltage_level = 855 bdw_calc_voltage_level(cdclk_config->cdclk); 856 } 857 858 static u32 bdw_cdclk_freq_sel(int cdclk) 859 { 860 switch (cdclk) { 861 default: 862 MISSING_CASE(cdclk); 863 fallthrough; 864 case 337500: 865 return LCPLL_CLK_FREQ_337_5_BDW; 866 case 450000: 867 return LCPLL_CLK_FREQ_450; 868 case 540000: 869 return LCPLL_CLK_FREQ_54O_BDW; 870 case 675000: 871 return LCPLL_CLK_FREQ_675_BDW; 872 } 873 } 874 875 static void bdw_set_cdclk(struct intel_display *display, 876 const struct intel_cdclk_config *cdclk_config, 877 enum pipe pipe) 878 { 879 int cdclk = cdclk_config->cdclk; 880 int ret; 881 882 if (drm_WARN(display->drm, 883 (intel_de_read(display, LCPLL_CTL) & 884 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 885 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 886 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 887 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 888 "trying to change cdclk frequency with cdclk not enabled\n")) 889 return; 890 891 ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 892 if (ret) { 893 drm_err(display->drm, 894 "failed to inform pcode about cdclk change\n"); 895 return; 896 } 897 898 intel_de_rmw(display, LCPLL_CTL, 899 0, LCPLL_CD_SOURCE_FCLK); 900 901 /* 902 * According to the spec, it should be enough to poll for this 1 us. 903 * However, extensive testing shows that this can take longer. 904 */ 905 ret = intel_de_wait_for_set_us(display, LCPLL_CTL, 906 LCPLL_CD_SOURCE_FCLK_DONE, 100); 907 if (ret) 908 drm_err(display->drm, "Switching to FCLK failed\n"); 909 910 intel_de_rmw(display, LCPLL_CTL, 911 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 912 913 intel_de_rmw(display, LCPLL_CTL, 914 LCPLL_CD_SOURCE_FCLK, 0); 915 916 ret = intel_de_wait_for_clear_us(display, LCPLL_CTL, 917 LCPLL_CD_SOURCE_FCLK_DONE, 1); 918 if (ret) 919 drm_err(display->drm, "Switching back to LCPLL failed\n"); 920 921 intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ, 922 cdclk_config->voltage_level); 923 924 intel_de_write(display, CDCLK_FREQ, 925 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 926 927 intel_update_cdclk(display); 928 } 929 930 static int skl_calc_cdclk(int min_cdclk, int vco) 931 { 932 if (vco == 8640000) { 933 if (min_cdclk > 540000) 934 return 617143; 935 else if (min_cdclk > 432000) 936 return 540000; 937 else if (min_cdclk > 308571) 938 return 432000; 939 else 940 return 308571; 941 } else { 942 if (min_cdclk > 540000) 943 return 675000; 944 else if (min_cdclk > 450000) 945 return 540000; 946 else if (min_cdclk > 337500) 947 return 450000; 948 else 949 return 337500; 950 } 951 } 952 953 static u8 skl_calc_voltage_level(int cdclk) 954 { 955 if (cdclk > 540000) 956 return 3; 957 else if (cdclk > 450000) 958 return 2; 959 else if (cdclk > 337500) 960 return 1; 961 else 962 return 0; 963 } 964 965 static void skl_dpll0_update(struct intel_display *display, 966 struct intel_cdclk_config *cdclk_config) 967 { 968 u32 val; 969 970 cdclk_config->ref = 24000; 971 cdclk_config->vco = 0; 972 973 val = intel_de_read(display, LCPLL1_CTL); 974 if ((val & LCPLL_PLL_ENABLE) == 0) 975 return; 976 977 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) 978 return; 979 980 val = intel_de_read(display, DPLL_CTRL1); 981 982 if (drm_WARN_ON(display->drm, 983 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 984 DPLL_CTRL1_SSC(SKL_DPLL0) | 985 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 986 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 987 return; 988 989 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 990 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 991 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 992 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 993 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 994 cdclk_config->vco = 8100000; 995 break; 996 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 997 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 998 cdclk_config->vco = 8640000; 999 break; 1000 default: 1001 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 1002 break; 1003 } 1004 } 1005 1006 static void skl_get_cdclk(struct intel_display *display, 1007 struct intel_cdclk_config *cdclk_config) 1008 { 1009 u32 cdctl; 1010 1011 skl_dpll0_update(display, cdclk_config); 1012 1013 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 1014 1015 if (cdclk_config->vco == 0) 1016 goto out; 1017 1018 cdctl = intel_de_read(display, CDCLK_CTL); 1019 1020 if (cdclk_config->vco == 8640000) { 1021 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1022 case CDCLK_FREQ_450_432: 1023 cdclk_config->cdclk = 432000; 1024 break; 1025 case CDCLK_FREQ_337_308: 1026 cdclk_config->cdclk = 308571; 1027 break; 1028 case CDCLK_FREQ_540: 1029 cdclk_config->cdclk = 540000; 1030 break; 1031 case CDCLK_FREQ_675_617: 1032 cdclk_config->cdclk = 617143; 1033 break; 1034 default: 1035 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1036 break; 1037 } 1038 } else { 1039 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1040 case CDCLK_FREQ_450_432: 1041 cdclk_config->cdclk = 450000; 1042 break; 1043 case CDCLK_FREQ_337_308: 1044 cdclk_config->cdclk = 337500; 1045 break; 1046 case CDCLK_FREQ_540: 1047 cdclk_config->cdclk = 540000; 1048 break; 1049 case CDCLK_FREQ_675_617: 1050 cdclk_config->cdclk = 675000; 1051 break; 1052 default: 1053 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1054 break; 1055 } 1056 } 1057 1058 out: 1059 /* 1060 * Can't read this out :( Let's assume it's 1061 * at least what the CDCLK frequency requires. 1062 */ 1063 cdclk_config->voltage_level = 1064 skl_calc_voltage_level(cdclk_config->cdclk); 1065 } 1066 1067 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1068 static int skl_cdclk_decimal(int cdclk) 1069 { 1070 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1071 } 1072 1073 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) 1074 { 1075 bool changed = display->cdclk.skl_preferred_vco_freq != vco; 1076 1077 display->cdclk.skl_preferred_vco_freq = vco; 1078 1079 if (changed) 1080 intel_update_max_cdclk(display); 1081 } 1082 1083 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) 1084 { 1085 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 1086 1087 /* 1088 * We always enable DPLL0 with the lowest link rate possible, but still 1089 * taking into account the VCO required to operate the eDP panel at the 1090 * desired frequency. The usual DP link rates operate with a VCO of 1091 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1092 * The modeset code is responsible for the selection of the exact link 1093 * rate later on, with the constraint of choosing a frequency that 1094 * works with vco. 1095 */ 1096 if (vco == 8640000) 1097 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1098 else 1099 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1100 } 1101 1102 static void skl_dpll0_enable(struct intel_display *display, int vco) 1103 { 1104 intel_de_rmw(display, DPLL_CTRL1, 1105 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1106 DPLL_CTRL1_SSC(SKL_DPLL0) | 1107 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1108 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1109 skl_dpll0_link_rate(display, vco)); 1110 intel_de_posting_read(display, DPLL_CTRL1); 1111 1112 intel_de_rmw(display, LCPLL1_CTL, 1113 0, LCPLL_PLL_ENABLE); 1114 1115 if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1116 drm_err(display->drm, "DPLL0 not locked\n"); 1117 1118 display->cdclk.hw.vco = vco; 1119 1120 /* We'll want to keep using the current vco from now on. */ 1121 skl_set_preferred_cdclk_vco(display, vco); 1122 } 1123 1124 static void skl_dpll0_disable(struct intel_display *display) 1125 { 1126 intel_de_rmw(display, LCPLL1_CTL, 1127 LCPLL_PLL_ENABLE, 0); 1128 1129 if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1130 drm_err(display->drm, "Couldn't disable DPLL0\n"); 1131 1132 display->cdclk.hw.vco = 0; 1133 } 1134 1135 static u32 skl_cdclk_freq_sel(struct intel_display *display, 1136 int cdclk, int vco) 1137 { 1138 switch (cdclk) { 1139 default: 1140 drm_WARN_ON(display->drm, 1141 cdclk != display->cdclk.hw.bypass); 1142 drm_WARN_ON(display->drm, vco != 0); 1143 fallthrough; 1144 case 308571: 1145 case 337500: 1146 return CDCLK_FREQ_337_308; 1147 case 450000: 1148 case 432000: 1149 return CDCLK_FREQ_450_432; 1150 case 540000: 1151 return CDCLK_FREQ_540; 1152 case 617143: 1153 case 675000: 1154 return CDCLK_FREQ_675_617; 1155 } 1156 } 1157 1158 static void skl_set_cdclk(struct intel_display *display, 1159 const struct intel_cdclk_config *cdclk_config, 1160 enum pipe pipe) 1161 { 1162 int cdclk = cdclk_config->cdclk; 1163 int vco = cdclk_config->vco; 1164 u32 freq_select, cdclk_ctl; 1165 int ret; 1166 1167 /* 1168 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1169 * unsupported on SKL. In theory this should never happen since only 1170 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1171 * supported on SKL either, see the above WA. WARN whenever trying to 1172 * use the corresponding VCO freq as that always leads to using the 1173 * minimum 308MHz CDCLK. 1174 */ 1175 drm_WARN_ON_ONCE(display->drm, 1176 display->platform.skylake && vco == 8640000); 1177 1178 ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL, 1179 SKL_CDCLK_PREPARE_FOR_CHANGE, 1180 SKL_CDCLK_READY_FOR_CHANGE, 1181 SKL_CDCLK_READY_FOR_CHANGE, 3); 1182 if (ret) { 1183 drm_err(display->drm, 1184 "Failed to inform PCU about cdclk change (%d)\n", ret); 1185 return; 1186 } 1187 1188 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); 1189 1190 if (display->cdclk.hw.vco != 0 && 1191 display->cdclk.hw.vco != vco) 1192 skl_dpll0_disable(display); 1193 1194 cdclk_ctl = intel_de_read(display, CDCLK_CTL); 1195 1196 if (display->cdclk.hw.vco != vco) { 1197 /* Wa Display #1183: skl,kbl,cfl */ 1198 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1199 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1200 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1201 } 1202 1203 /* Wa Display #1183: skl,kbl,cfl */ 1204 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1205 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1206 intel_de_posting_read(display, CDCLK_CTL); 1207 1208 if (display->cdclk.hw.vco != vco) 1209 skl_dpll0_enable(display, vco); 1210 1211 /* Wa Display #1183: skl,kbl,cfl */ 1212 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1213 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1214 1215 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1216 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1217 1218 /* Wa Display #1183: skl,kbl,cfl */ 1219 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1220 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1221 intel_de_posting_read(display, CDCLK_CTL); 1222 1223 /* inform PCU of the change */ 1224 intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL, 1225 cdclk_config->voltage_level); 1226 1227 intel_update_cdclk(display); 1228 } 1229 1230 static void skl_sanitize_cdclk(struct intel_display *display) 1231 { 1232 u32 cdctl, expected, swf18; 1233 1234 /* 1235 * check if the pre-os initialized the display 1236 * There is SWF18 scratchpad register defined which is set by the 1237 * pre-os which can be used by the OS drivers to check the status 1238 */ 1239 swf18 = intel_de_read(display, SWF_ILK(0x18)); 1240 if ((swf18 & 0x00FFFFFF) == 0) { 1241 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to SWF18 0x%x\n", swf18); 1242 goto sanitize; 1243 } 1244 1245 intel_update_cdclk(display); 1246 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1247 1248 /* Is PLL enabled and locked ? */ 1249 if (display->cdclk.hw.vco == 0 || 1250 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) { 1251 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to PLL not enabled/locked\n"); 1252 goto sanitize; 1253 } 1254 1255 /* DPLL okay; verify the cdclock 1256 * 1257 * Noticed in some instances that the freq selection is correct but 1258 * decimal part is programmed wrong from BIOS where pre-os does not 1259 * enable display. Verify the same as well. 1260 */ 1261 cdctl = intel_de_read(display, CDCLK_CTL); 1262 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1263 skl_cdclk_decimal(display->cdclk.hw.cdclk); 1264 1265 if (cdctl != expected) { 1266 cdctl &= ~CDCLK_FREQ_DECIMAL_MASK; 1267 cdctl |= expected & CDCLK_FREQ_DECIMAL_MASK; 1268 1269 if (cdctl != expected) { 1270 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to CDCLK_CTL 0x%x, expected 0x%x)\n", 1271 intel_de_read(display, CDCLK_CTL), expected); 1272 goto sanitize; 1273 } 1274 1275 drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n", 1276 intel_de_read(display, CDCLK_CTL), expected); 1277 1278 intel_de_write(display, CDCLK_CTL, expected); 1279 } 1280 1281 /* All well; nothing to sanitize */ 1282 return; 1283 1284 sanitize: 1285 /* force cdclk programming */ 1286 display->cdclk.hw.cdclk = 0; 1287 /* force full PLL disable + enable */ 1288 display->cdclk.hw.vco = ~0; 1289 } 1290 1291 static void skl_cdclk_init_hw(struct intel_display *display) 1292 { 1293 struct intel_cdclk_config cdclk_config; 1294 1295 skl_sanitize_cdclk(display); 1296 1297 if (display->cdclk.hw.cdclk != 0 && 1298 display->cdclk.hw.vco != 0) { 1299 /* 1300 * Use the current vco as our initial 1301 * guess as to what the preferred vco is. 1302 */ 1303 if (display->cdclk.skl_preferred_vco_freq == 0) 1304 skl_set_preferred_cdclk_vco(display, 1305 display->cdclk.hw.vco); 1306 return; 1307 } 1308 1309 cdclk_config = display->cdclk.hw; 1310 1311 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; 1312 if (cdclk_config.vco == 0) 1313 cdclk_config.vco = 8100000; 1314 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1315 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1316 1317 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1318 } 1319 1320 static void skl_cdclk_uninit_hw(struct intel_display *display) 1321 { 1322 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 1323 1324 cdclk_config.cdclk = cdclk_config.bypass; 1325 cdclk_config.vco = 0; 1326 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1327 1328 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1329 } 1330 1331 struct intel_cdclk_vals { 1332 u32 cdclk; 1333 u16 refclk; 1334 u16 waveform; 1335 u8 ratio; 1336 }; 1337 1338 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1339 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1340 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1341 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1342 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1343 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1344 {} 1345 }; 1346 1347 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1348 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1349 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1350 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1351 {} 1352 }; 1353 1354 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1355 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1356 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1357 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1358 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1359 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1360 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1361 1362 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1363 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1364 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1365 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1366 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1367 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1368 1369 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1370 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1371 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1372 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1373 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1374 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1375 {} 1376 }; 1377 1378 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1379 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1380 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1381 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1382 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1383 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1384 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1385 1386 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1387 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1388 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1389 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1390 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1391 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1392 1393 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1394 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1395 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1396 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1397 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1398 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1399 {} 1400 }; 1401 1402 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1403 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1404 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1405 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1406 1407 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1408 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1409 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1410 1411 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1412 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1413 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1414 {} 1415 }; 1416 1417 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1418 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1419 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1420 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1421 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1422 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1423 1424 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1425 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1426 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1427 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1428 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1429 1430 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1431 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1432 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1433 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1434 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1435 {} 1436 }; 1437 1438 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1439 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1440 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1441 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1442 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1443 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1444 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1445 1446 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1447 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1448 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1449 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1450 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1451 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1452 1453 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1454 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1455 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1456 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1457 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1458 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1459 {} 1460 }; 1461 1462 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1463 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1464 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1465 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1466 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1467 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1468 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1469 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1470 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1471 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1472 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1473 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1474 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1475 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1476 {} 1477 }; 1478 1479 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1480 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1481 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1482 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1483 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1484 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1485 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1486 {} 1487 }; 1488 1489 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1490 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1491 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1492 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1493 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1494 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1495 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1496 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1497 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1498 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1499 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1500 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1501 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1502 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1503 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1504 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1505 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1506 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1507 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1508 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1509 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1510 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1511 {} 1512 }; 1513 1514 /* 1515 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1516 */ 1517 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1518 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1519 {} 1520 }; 1521 1522 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { 1523 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1524 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1525 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1526 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1527 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1528 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1529 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1530 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1531 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1532 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff }, 1533 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff }, 1534 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff }, 1535 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff }, 1536 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1537 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1538 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1539 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1540 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1541 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1542 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1543 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1544 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1545 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1546 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1547 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1548 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1549 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1550 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1551 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1552 {} 1553 }; 1554 1555 static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = { 1556 { .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 }, 1557 { .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 }, 1558 { .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa }, 1559 { .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a }, 1560 { .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 }, 1561 { .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 }, 1562 { .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee }, 1563 { .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de }, 1564 { .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe }, 1565 { .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe }, 1566 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1567 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1568 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1569 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1570 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1571 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1572 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1573 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1574 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1575 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1576 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1577 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1578 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1579 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1580 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1581 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1582 { .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff }, 1583 { .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff }, 1584 { .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff }, 1585 { .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff }, 1586 { .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff }, 1587 {} 1588 }; 1589 1590 static const int cdclk_squash_len = 16; 1591 1592 static int cdclk_squash_divider(u16 waveform) 1593 { 1594 return hweight16(waveform ?: 0xffff); 1595 } 1596 1597 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1598 { 1599 /* 2 * cd2x divider */ 1600 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1601 cdclk * cdclk_squash_len); 1602 } 1603 1604 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 1605 { 1606 const struct intel_cdclk_vals *table = display->cdclk.table; 1607 int i; 1608 1609 for (i = 0; table[i].refclk; i++) 1610 if (table[i].refclk == display->cdclk.hw.ref && 1611 table[i].cdclk >= min_cdclk) 1612 return table[i].cdclk; 1613 1614 drm_WARN(display->drm, 1, 1615 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1616 min_cdclk, display->cdclk.hw.ref); 1617 return display->cdclk.max_cdclk_freq; 1618 } 1619 1620 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) 1621 { 1622 const struct intel_cdclk_vals *table = display->cdclk.table; 1623 int i; 1624 1625 if (cdclk == display->cdclk.hw.bypass) 1626 return 0; 1627 1628 for (i = 0; table[i].refclk; i++) 1629 if (table[i].refclk == display->cdclk.hw.ref && 1630 table[i].cdclk == cdclk) 1631 return display->cdclk.hw.ref * table[i].ratio; 1632 1633 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1634 cdclk, display->cdclk.hw.ref); 1635 return 0; 1636 } 1637 1638 static u8 bxt_calc_voltage_level(int cdclk) 1639 { 1640 return DIV_ROUND_UP(cdclk, 25000); 1641 } 1642 1643 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1644 const int voltage_level_max_cdclk[]) 1645 { 1646 int voltage_level; 1647 1648 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1649 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1650 return voltage_level; 1651 } 1652 1653 MISSING_CASE(cdclk); 1654 return num_voltage_levels - 1; 1655 } 1656 1657 static u8 icl_calc_voltage_level(int cdclk) 1658 { 1659 static const int icl_voltage_level_max_cdclk[] = { 1660 [0] = 312000, 1661 [1] = 556800, 1662 [2] = 652800, 1663 }; 1664 1665 return calc_voltage_level(cdclk, 1666 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1667 icl_voltage_level_max_cdclk); 1668 } 1669 1670 static u8 ehl_calc_voltage_level(int cdclk) 1671 { 1672 static const int ehl_voltage_level_max_cdclk[] = { 1673 [0] = 180000, 1674 [1] = 312000, 1675 [2] = 326400, 1676 /* 1677 * Bspec lists the limit as 556.8 MHz, but some JSL 1678 * development boards (at least) boot with 652.8 MHz 1679 */ 1680 [3] = 652800, 1681 }; 1682 1683 return calc_voltage_level(cdclk, 1684 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1685 ehl_voltage_level_max_cdclk); 1686 } 1687 1688 static u8 tgl_calc_voltage_level(int cdclk) 1689 { 1690 static const int tgl_voltage_level_max_cdclk[] = { 1691 [0] = 312000, 1692 [1] = 326400, 1693 [2] = 556800, 1694 [3] = 652800, 1695 }; 1696 1697 return calc_voltage_level(cdclk, 1698 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1699 tgl_voltage_level_max_cdclk); 1700 } 1701 1702 static u8 rplu_calc_voltage_level(int cdclk) 1703 { 1704 static const int rplu_voltage_level_max_cdclk[] = { 1705 [0] = 312000, 1706 [1] = 480000, 1707 [2] = 556800, 1708 [3] = 652800, 1709 }; 1710 1711 return calc_voltage_level(cdclk, 1712 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1713 rplu_voltage_level_max_cdclk); 1714 } 1715 1716 static u8 xe3lpd_calc_voltage_level(int cdclk) 1717 { 1718 /* 1719 * Starting with xe3lpd power controller does not need the voltage 1720 * index when doing the modeset update. This function is best left 1721 * defined but returning 0 to the mask. 1722 */ 1723 return 0; 1724 } 1725 1726 static void icl_readout_refclk(struct intel_display *display, 1727 struct intel_cdclk_config *cdclk_config) 1728 { 1729 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1730 1731 switch (dssm) { 1732 default: 1733 MISSING_CASE(dssm); 1734 fallthrough; 1735 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1736 cdclk_config->ref = 24000; 1737 break; 1738 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1739 cdclk_config->ref = 19200; 1740 break; 1741 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1742 cdclk_config->ref = 38400; 1743 break; 1744 } 1745 } 1746 1747 static void bxt_de_pll_readout(struct intel_display *display, 1748 struct intel_cdclk_config *cdclk_config) 1749 { 1750 u32 val, ratio; 1751 1752 if (display->platform.dg2) 1753 cdclk_config->ref = 38400; 1754 else if (DISPLAY_VER(display) >= 11) 1755 icl_readout_refclk(display, cdclk_config); 1756 else 1757 cdclk_config->ref = 19200; 1758 1759 val = intel_de_read(display, BXT_DE_PLL_ENABLE); 1760 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1761 (val & BXT_DE_PLL_LOCK) == 0) { 1762 /* 1763 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1764 * setting it to zero is a way to signal that. 1765 */ 1766 cdclk_config->vco = 0; 1767 return; 1768 } 1769 1770 /* 1771 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1772 * gen9lp had it in a separate PLL control register. 1773 */ 1774 if (DISPLAY_VER(display) >= 11) 1775 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1776 else 1777 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1778 1779 cdclk_config->vco = ratio * cdclk_config->ref; 1780 } 1781 1782 static void bxt_get_cdclk(struct intel_display *display, 1783 struct intel_cdclk_config *cdclk_config) 1784 { 1785 u32 squash_ctl = 0; 1786 u32 divider; 1787 int div; 1788 1789 bxt_de_pll_readout(display, cdclk_config); 1790 1791 if (DISPLAY_VER(display) >= 12) 1792 cdclk_config->bypass = cdclk_config->ref / 2; 1793 else if (DISPLAY_VER(display) >= 11) 1794 cdclk_config->bypass = 50000; 1795 else 1796 cdclk_config->bypass = cdclk_config->ref; 1797 1798 if (cdclk_config->vco == 0) { 1799 cdclk_config->cdclk = cdclk_config->bypass; 1800 goto out; 1801 } 1802 1803 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1804 1805 switch (divider) { 1806 case BXT_CDCLK_CD2X_DIV_SEL_1: 1807 div = 2; 1808 break; 1809 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1810 div = 3; 1811 break; 1812 case BXT_CDCLK_CD2X_DIV_SEL_2: 1813 div = 4; 1814 break; 1815 case BXT_CDCLK_CD2X_DIV_SEL_4: 1816 div = 8; 1817 break; 1818 default: 1819 MISSING_CASE(divider); 1820 return; 1821 } 1822 1823 if (HAS_CDCLK_SQUASH(display)) 1824 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); 1825 1826 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1827 u16 waveform; 1828 int size; 1829 1830 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1831 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1832 1833 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1834 cdclk_config->vco, size * div); 1835 } else { 1836 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1837 } 1838 1839 out: 1840 if (DISPLAY_VER(display) >= 20) 1841 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 1842 /* 1843 * Can't read this out :( Let's assume it's 1844 * at least what the CDCLK frequency requires. 1845 */ 1846 cdclk_config->voltage_level = 1847 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); 1848 } 1849 1850 static void bxt_de_pll_disable(struct intel_display *display) 1851 { 1852 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); 1853 1854 /* Timeout 200us */ 1855 if (intel_de_wait_for_clear_ms(display, 1856 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1857 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); 1858 1859 display->cdclk.hw.vco = 0; 1860 } 1861 1862 static void bxt_de_pll_enable(struct intel_display *display, int vco) 1863 { 1864 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1865 1866 intel_de_rmw(display, BXT_DE_PLL_CTL, 1867 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1868 1869 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1870 1871 /* Timeout 200us */ 1872 if (intel_de_wait_for_set_ms(display, 1873 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1874 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); 1875 1876 display->cdclk.hw.vco = vco; 1877 } 1878 1879 static void icl_cdclk_pll_disable(struct intel_display *display) 1880 { 1881 /* 1882 * Wa_13012396614: 1883 * Fixes: A sporadic race condition between MDCLK selection and PLL 1884 * enabling. 1885 * Workaround: 1886 * Change programming of MDCLK source selection in CDCLK_CTL: 1887 * - When disabling the CDCLK PLL, first set MDCLK source to be CD2XCLK. 1888 * - When enabling the CDCLK PLL, update MDCLK source selection only 1889 * after the PLL is enabled (which is already done as part of the 1890 * normal flow of _bxt_set_cdclk()). 1891 */ 1892 if (intel_display_wa(display, INTEL_DISPLAY_WA_13012396614)) 1893 intel_de_rmw(display, CDCLK_CTL, MDCLK_SOURCE_SEL_MASK, MDCLK_SOURCE_SEL_CD2XCLK); 1894 1895 intel_de_rmw(display, BXT_DE_PLL_ENABLE, 1896 BXT_DE_PLL_PLL_ENABLE, 0); 1897 1898 /* Timeout 200us */ 1899 if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1900 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); 1901 1902 display->cdclk.hw.vco = 0; 1903 } 1904 1905 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) 1906 { 1907 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1908 u32 val; 1909 1910 val = ICL_CDCLK_PLL_RATIO(ratio); 1911 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1912 1913 val |= BXT_DE_PLL_PLL_ENABLE; 1914 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1915 1916 /* Timeout 200us */ 1917 if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1918 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); 1919 1920 display->cdclk.hw.vco = vco; 1921 } 1922 1923 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) 1924 { 1925 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1926 u32 val; 1927 1928 /* Write PLL ratio without disabling */ 1929 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1930 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1931 1932 /* Submit freq change request */ 1933 val |= BXT_DE_PLL_FREQ_REQ; 1934 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1935 1936 /* Timeout 200us */ 1937 if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, 1938 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1939 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); 1940 1941 val &= ~BXT_DE_PLL_FREQ_REQ; 1942 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1943 1944 display->cdclk.hw.vco = vco; 1945 } 1946 1947 static u32 bxt_cdclk_cd2x_pipe_mask(struct intel_display *display) 1948 { 1949 if (DISPLAY_VER(display) >= 11) 1950 return ICL_CDCLK_CD2X_PIPE_MASK; 1951 else 1952 return BXT_CDCLK_CD2X_PIPE_MASK; 1953 } 1954 1955 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 1956 { 1957 if (DISPLAY_VER(display) >= 11) { 1958 if (pipe == INVALID_PIPE) 1959 return ICL_CDCLK_CD2X_PIPE_NONE; 1960 else 1961 return ICL_CDCLK_CD2X_PIPE(pipe); 1962 } else { 1963 if (pipe == INVALID_PIPE) 1964 return BXT_CDCLK_CD2X_PIPE_NONE; 1965 else 1966 return BXT_CDCLK_CD2X_PIPE(pipe); 1967 } 1968 } 1969 1970 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 1971 int cdclk, int vco, u16 waveform) 1972 { 1973 u32 ret; 1974 1975 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1976 switch (cdclk_divider(cdclk, vco, waveform)) { 1977 default: 1978 drm_WARN_ON(display->drm, 1979 cdclk != display->cdclk.hw.bypass); 1980 drm_WARN_ON(display->drm, vco != 0); 1981 fallthrough; 1982 case 2: 1983 ret = BXT_CDCLK_CD2X_DIV_SEL_1; 1984 break; 1985 case 3: 1986 ret = BXT_CDCLK_CD2X_DIV_SEL_1_5; 1987 break; 1988 case 4: 1989 ret = BXT_CDCLK_CD2X_DIV_SEL_2; 1990 break; 1991 case 8: 1992 ret = BXT_CDCLK_CD2X_DIV_SEL_4; 1993 break; 1994 } 1995 1996 /* 1997 * On Xe3_LPD onward, the expectation is to always have 1998 * BXT_CDCLK_CD2X_DIV_SEL_1 as the default. 1999 */ 2000 if (DISPLAY_VER(display) >= 30) 2001 drm_WARN_ON(display->drm, ret != BXT_CDCLK_CD2X_DIV_SEL_1); 2002 2003 return ret; 2004 } 2005 2006 static u16 cdclk_squash_waveform(struct intel_display *display, 2007 int cdclk) 2008 { 2009 const struct intel_cdclk_vals *table = display->cdclk.table; 2010 int i; 2011 2012 if (cdclk == display->cdclk.hw.bypass) 2013 return 0; 2014 2015 for (i = 0; table[i].refclk; i++) 2016 if (table[i].refclk == display->cdclk.hw.ref && 2017 table[i].cdclk == cdclk) 2018 return table[i].waveform; 2019 2020 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 2021 cdclk, display->cdclk.hw.ref); 2022 2023 return 0xffff; 2024 } 2025 2026 static void icl_cdclk_pll_update(struct intel_display *display, int vco) 2027 { 2028 if (display->cdclk.hw.vco != 0 && 2029 display->cdclk.hw.vco != vco) 2030 icl_cdclk_pll_disable(display); 2031 2032 if (display->cdclk.hw.vco != vco) 2033 icl_cdclk_pll_enable(display, vco); 2034 } 2035 2036 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) 2037 { 2038 if (display->cdclk.hw.vco != 0 && 2039 display->cdclk.hw.vco != vco) 2040 bxt_de_pll_disable(display); 2041 2042 if (display->cdclk.hw.vco != vco) 2043 bxt_de_pll_enable(display, vco); 2044 } 2045 2046 static void dg2_cdclk_squash_program(struct intel_display *display, 2047 u16 waveform) 2048 { 2049 u32 squash_ctl = 0; 2050 2051 if (waveform) 2052 squash_ctl = CDCLK_SQUASH_ENABLE | 2053 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 2054 2055 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); 2056 } 2057 2058 static bool cdclk_pll_is_unknown(unsigned int vco) 2059 { 2060 /* 2061 * Ensure driver does not take the crawl path for the 2062 * case when the vco is set to ~0 in the 2063 * sanitize path. 2064 */ 2065 return vco == ~0; 2066 } 2067 2068 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) 2069 { 2070 return DISPLAY_VER(display) >= 20; 2071 } 2072 2073 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) 2074 { 2075 if (mdclk_source_is_cdclk_pll(display)) 2076 return MDCLK_SOURCE_SEL_CDCLK_PLL; 2077 2078 return MDCLK_SOURCE_SEL_CD2XCLK; 2079 } 2080 2081 int intel_mdclk_cdclk_ratio(struct intel_display *display, 2082 const struct intel_cdclk_config *cdclk_config) 2083 { 2084 if (mdclk_source_is_cdclk_pll(display)) 2085 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 2086 2087 /* Otherwise, source for MDCLK is CD2XCLK. */ 2088 return 2; 2089 } 2090 2091 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, 2092 const struct intel_cdclk_config *cdclk_config) 2093 { 2094 intel_dbuf_mdclk_cdclk_ratio_update(display, 2095 intel_mdclk_cdclk_ratio(display, cdclk_config), 2096 cdclk_config->joined_mbus); 2097 } 2098 2099 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, 2100 const struct intel_cdclk_config *old_cdclk_config, 2101 const struct intel_cdclk_config *new_cdclk_config, 2102 struct intel_cdclk_config *mid_cdclk_config) 2103 { 2104 u16 old_waveform, new_waveform, mid_waveform; 2105 int old_div, new_div, mid_div; 2106 2107 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 2108 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 2109 return false; 2110 2111 /* Return if both Squash and Crawl are not present */ 2112 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2113 return false; 2114 2115 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); 2116 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); 2117 2118 /* Return if Squash only or Crawl only is the desired action */ 2119 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 2120 old_cdclk_config->vco == new_cdclk_config->vco || 2121 old_waveform == new_waveform) 2122 return false; 2123 2124 old_div = cdclk_divider(old_cdclk_config->cdclk, 2125 old_cdclk_config->vco, old_waveform); 2126 new_div = cdclk_divider(new_cdclk_config->cdclk, 2127 new_cdclk_config->vco, new_waveform); 2128 2129 /* 2130 * Should not happen currently. We might need more midpoint 2131 * transitions if we need to also change the cd2x divider. 2132 */ 2133 if (drm_WARN_ON(display->drm, old_div != new_div)) 2134 return false; 2135 2136 *mid_cdclk_config = *new_cdclk_config; 2137 2138 /* 2139 * Populate the mid_cdclk_config accordingly. 2140 * - If moving to a higher cdclk, the desired action is squashing. 2141 * The mid cdclk config should have the new (squash) waveform. 2142 * - If moving to a lower cdclk, the desired action is crawling. 2143 * The mid cdclk config should have the new vco. 2144 */ 2145 2146 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 2147 mid_cdclk_config->vco = old_cdclk_config->vco; 2148 mid_div = old_div; 2149 mid_waveform = new_waveform; 2150 } else { 2151 mid_cdclk_config->vco = new_cdclk_config->vco; 2152 mid_div = new_div; 2153 mid_waveform = old_waveform; 2154 } 2155 2156 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 2157 mid_cdclk_config->vco, 2158 cdclk_squash_len * mid_div); 2159 2160 /* make sure the mid clock came out sane */ 2161 2162 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < 2163 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 2164 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > 2165 display->cdclk.max_cdclk_freq); 2166 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != 2167 mid_waveform); 2168 2169 return true; 2170 } 2171 2172 static bool pll_enable_wa_needed(struct intel_display *display) 2173 { 2174 return (DISPLAY_VERx100(display) == 2000 || 2175 DISPLAY_VERx100(display) == 1400 || 2176 display->platform.dg2) && 2177 display->cdclk.hw.vco > 0; 2178 } 2179 2180 static u32 bxt_cdclk_ctl(struct intel_display *display, 2181 const struct intel_cdclk_config *cdclk_config, 2182 enum pipe pipe) 2183 { 2184 int cdclk = cdclk_config->cdclk; 2185 int vco = cdclk_config->vco; 2186 u16 waveform; 2187 u32 val; 2188 2189 waveform = cdclk_squash_waveform(display, cdclk); 2190 2191 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform); 2192 2193 if (DISPLAY_VER(display) < 30) 2194 val |= bxt_cdclk_cd2x_pipe(display, pipe); 2195 2196 /* 2197 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2198 * enable otherwise. 2199 */ 2200 if ((display->platform.geminilake || display->platform.broxton) && 2201 cdclk >= 500000) 2202 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2203 2204 if (DISPLAY_VER(display) >= 20) { 2205 /* 2206 * Wa_13012396614 requires selecting CD2XCLK as MDCLK source 2207 * prior to disabling the PLL, which is already handled by 2208 * icl_cdclk_pll_disable(). Here we are just making sure 2209 * we keep the expected value. 2210 */ 2211 if (intel_display_wa(display, INTEL_DISPLAY_WA_13012396614) && 2212 vco == 0) 2213 val |= MDCLK_SOURCE_SEL_CD2XCLK; 2214 else 2215 val |= xe2lpd_mdclk_source_sel(display); 2216 } else { 2217 val |= skl_cdclk_decimal(cdclk); 2218 } 2219 2220 return val; 2221 } 2222 2223 static void _bxt_set_cdclk(struct intel_display *display, 2224 const struct intel_cdclk_config *cdclk_config, 2225 enum pipe pipe) 2226 { 2227 int cdclk = cdclk_config->cdclk; 2228 int vco = cdclk_config->vco; 2229 2230 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && 2231 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { 2232 if (display->cdclk.hw.vco != vco) 2233 adlp_cdclk_pll_crawl(display, vco); 2234 } else if (DISPLAY_VER(display) >= 11) { 2235 /* wa_15010685871: dg2, mtl */ 2236 if (pll_enable_wa_needed(display)) 2237 dg2_cdclk_squash_program(display, 0); 2238 2239 icl_cdclk_pll_update(display, vco); 2240 } else { 2241 bxt_cdclk_pll_update(display, vco); 2242 } 2243 2244 if (HAS_CDCLK_SQUASH(display)) { 2245 u16 waveform = cdclk_squash_waveform(display, cdclk); 2246 2247 dg2_cdclk_squash_program(display, waveform); 2248 } 2249 2250 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); 2251 2252 if (pipe != INVALID_PIPE) 2253 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 2254 } 2255 2256 static void bxt_set_cdclk(struct intel_display *display, 2257 const struct intel_cdclk_config *cdclk_config, 2258 enum pipe pipe) 2259 { 2260 struct intel_cdclk_config mid_cdclk_config; 2261 int cdclk = cdclk_config->cdclk; 2262 int ret = 0; 2263 2264 /* 2265 * Inform power controller of upcoming frequency change. 2266 * Display versions 14 and beyond do not follow the PUnit 2267 * mailbox communication, skip 2268 * this step. 2269 */ 2270 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) 2271 ; /* NOOP */ 2272 else if (DISPLAY_VER(display) >= 11) 2273 ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL, 2274 SKL_CDCLK_PREPARE_FOR_CHANGE, 2275 SKL_CDCLK_READY_FOR_CHANGE, 2276 SKL_CDCLK_READY_FOR_CHANGE, 3); 2277 else 2278 /* 2279 * BSpec requires us to wait up to 150usec, but that leads to 2280 * timeouts; the 2ms used here is based on experiment. 2281 */ 2282 ret = intel_parent_pcode_write_timeout(display, 2283 HSW_PCODE_DE_WRITE_FREQ_REQ, 2284 0x80000000, 2); 2285 2286 if (ret) { 2287 drm_err(display->drm, 2288 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2289 ret, cdclk); 2290 return; 2291 } 2292 2293 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) 2294 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2295 2296 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, 2297 cdclk_config, &mid_cdclk_config)) { 2298 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); 2299 _bxt_set_cdclk(display, cdclk_config, pipe); 2300 } else { 2301 _bxt_set_cdclk(display, cdclk_config, pipe); 2302 } 2303 2304 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) 2305 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2306 2307 if (DISPLAY_VER(display) >= 14) 2308 /* 2309 * NOOP - No Pcode communication needed for 2310 * Display versions 14 and beyond 2311 */; 2312 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) 2313 ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL, 2314 cdclk_config->voltage_level); 2315 if (DISPLAY_VER(display) < 11) { 2316 /* 2317 * The timeout isn't specified, the 2ms used here is based on 2318 * experiment. 2319 * FIXME: Waiting for the request completion could be delayed 2320 * until the next PCODE request based on BSpec. 2321 */ 2322 ret = intel_parent_pcode_write_timeout(display, 2323 HSW_PCODE_DE_WRITE_FREQ_REQ, 2324 cdclk_config->voltage_level, 2); 2325 } 2326 if (ret) { 2327 drm_err(display->drm, 2328 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2329 ret, cdclk); 2330 return; 2331 } 2332 2333 intel_update_cdclk(display); 2334 2335 if (DISPLAY_VER(display) >= 11) 2336 /* 2337 * Can't read out the voltage level :( 2338 * Let's just assume everything is as expected. 2339 */ 2340 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; 2341 } 2342 2343 static void bxt_sanitize_cdclk(struct intel_display *display) 2344 { 2345 u32 cdctl, expected; 2346 int cdclk, vco; 2347 2348 intel_update_cdclk(display); 2349 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 2350 2351 if (display->cdclk.hw.vco == 0 || 2352 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) { 2353 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to PLL not enabled/locked\n"); 2354 goto sanitize; 2355 } 2356 2357 /* Make sure this is a legal cdclk value for the platform */ 2358 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); 2359 if (cdclk != display->cdclk.hw.cdclk) { 2360 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to bad CDCLK frequency\n"); 2361 goto sanitize; 2362 } 2363 2364 /* Make sure the VCO is correct for the cdclk */ 2365 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 2366 if (vco != display->cdclk.hw.vco) { 2367 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to bad VCO frequency\n"); 2368 goto sanitize; 2369 } 2370 2371 /* 2372 * Some BIOS versions leave an incorrect decimal frequency value and 2373 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2374 * so sanitize this register. 2375 */ 2376 cdctl = intel_de_read(display, CDCLK_CTL); 2377 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); 2378 2379 /* 2380 * Let's ignore the pipe field, since BIOS could have configured the 2381 * dividers both syncing to an active pipe, or asynchronously 2382 * (PIPE_NONE). 2383 */ 2384 if (DISPLAY_VER(display) < 30) { 2385 cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display); 2386 cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2387 } 2388 2389 if (cdctl != expected) { 2390 if (DISPLAY_VER(display) < 20) { 2391 cdctl &= ~CDCLK_FREQ_DECIMAL_MASK; 2392 cdctl |= expected & CDCLK_FREQ_DECIMAL_MASK; 2393 } 2394 2395 if (cdctl != expected) { 2396 drm_dbg_kms(display->drm, "Sanitizing CDCLK due to CDCLK_CTL 0x%x, expected 0x%x\n", 2397 intel_de_read(display, CDCLK_CTL), expected); 2398 goto sanitize; 2399 } 2400 2401 drm_dbg_kms(display->drm, "Sanitizing CDCLK decimal divider (CDCLK_CTL 0x%x, expected 0x%x)\n", 2402 intel_de_read(display, CDCLK_CTL), expected); 2403 2404 intel_de_write(display, CDCLK_CTL, expected); 2405 } 2406 2407 /* All well; nothing to sanitize */ 2408 return; 2409 2410 sanitize: 2411 /* force cdclk programming */ 2412 display->cdclk.hw.cdclk = 0; 2413 2414 /* force full PLL disable + enable */ 2415 display->cdclk.hw.vco = ~0; 2416 } 2417 2418 static void bxt_cdclk_init_hw(struct intel_display *display) 2419 { 2420 struct intel_cdclk_config cdclk_config; 2421 2422 bxt_sanitize_cdclk(display); 2423 2424 if (display->cdclk.hw.cdclk != 0 && 2425 display->cdclk.hw.vco != 0) 2426 return; 2427 2428 cdclk_config = display->cdclk.hw; 2429 2430 /* 2431 * FIXME: 2432 * - The initial CDCLK needs to be read from VBT. 2433 * Need to make this change after VBT has changes for BXT. 2434 */ 2435 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); 2436 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); 2437 cdclk_config.voltage_level = 2438 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2439 2440 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2441 } 2442 2443 static void bxt_cdclk_uninit_hw(struct intel_display *display) 2444 { 2445 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 2446 2447 cdclk_config.cdclk = cdclk_config.bypass; 2448 cdclk_config.vco = 0; 2449 cdclk_config.voltage_level = 2450 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2451 2452 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2453 } 2454 2455 /** 2456 * intel_cdclk_init_hw - Initialize CDCLK hardware 2457 * @display: display instance 2458 * 2459 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and 2460 * sanitizing the state of the hardware if needed. This is generally done only 2461 * during the display core initialization sequence, after which the DMC will 2462 * take care of turning CDCLK off/on as needed. 2463 */ 2464 void intel_cdclk_init_hw(struct intel_display *display) 2465 { 2466 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2467 bxt_cdclk_init_hw(display); 2468 else if (DISPLAY_VER(display) == 9) 2469 skl_cdclk_init_hw(display); 2470 } 2471 2472 /** 2473 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2474 * @display: display instance 2475 * 2476 * Uninitialize CDCLK. This is done only during the display core 2477 * uninitialization sequence. 2478 */ 2479 void intel_cdclk_uninit_hw(struct intel_display *display) 2480 { 2481 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2482 bxt_cdclk_uninit_hw(display); 2483 else if (DISPLAY_VER(display) == 9) 2484 skl_cdclk_uninit_hw(display); 2485 } 2486 2487 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, 2488 const struct intel_cdclk_config *a, 2489 const struct intel_cdclk_config *b) 2490 { 2491 u16 old_waveform; 2492 u16 new_waveform; 2493 2494 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); 2495 2496 if (a->vco == 0 || b->vco == 0) 2497 return false; 2498 2499 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2500 return false; 2501 2502 old_waveform = cdclk_squash_waveform(display, a->cdclk); 2503 new_waveform = cdclk_squash_waveform(display, b->cdclk); 2504 2505 return a->vco != b->vco && 2506 old_waveform != new_waveform; 2507 } 2508 2509 static bool intel_cdclk_can_crawl(struct intel_display *display, 2510 const struct intel_cdclk_config *a, 2511 const struct intel_cdclk_config *b) 2512 { 2513 int a_div, b_div; 2514 2515 if (!HAS_CDCLK_CRAWL(display)) 2516 return false; 2517 2518 /* 2519 * The vco and cd2x divider will change independently 2520 * from each, so we disallow cd2x change when crawling. 2521 */ 2522 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2523 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2524 2525 return a->vco != 0 && b->vco != 0 && 2526 a->vco != b->vco && 2527 a_div == b_div && 2528 a->ref == b->ref; 2529 } 2530 2531 static bool intel_cdclk_can_squash(struct intel_display *display, 2532 const struct intel_cdclk_config *a, 2533 const struct intel_cdclk_config *b) 2534 { 2535 /* 2536 * FIXME should store a bit more state in intel_cdclk_config 2537 * to differentiate squasher vs. cd2x divider properly. For 2538 * the moment all platforms with squasher use a fixed cd2x 2539 * divider. 2540 */ 2541 if (!HAS_CDCLK_SQUASH(display)) 2542 return false; 2543 2544 return a->cdclk != b->cdclk && 2545 a->vco != 0 && 2546 a->vco == b->vco && 2547 a->ref == b->ref; 2548 } 2549 2550 /** 2551 * intel_cdclk_clock_changed - Check whether the clock changed 2552 * @a: first CDCLK configuration 2553 * @b: second CDCLK configuration 2554 * 2555 * Returns: 2556 * True if CDCLK changed in a way that requires re-programming and 2557 * False otherwise. 2558 */ 2559 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2560 const struct intel_cdclk_config *b) 2561 { 2562 return a->cdclk != b->cdclk || 2563 a->vco != b->vco || 2564 a->ref != b->ref; 2565 } 2566 2567 /** 2568 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2569 * configurations requires only a cd2x divider update 2570 * @display: display instance 2571 * @a: first CDCLK configuration 2572 * @b: second CDCLK configuration 2573 * 2574 * Returns: 2575 * True if changing between the two CDCLK configurations 2576 * can be done with just a cd2x divider update, false if not. 2577 */ 2578 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, 2579 const struct intel_cdclk_config *a, 2580 const struct intel_cdclk_config *b) 2581 { 2582 /* Older hw doesn't have the capability */ 2583 if (DISPLAY_VER(display) < 10 && !display->platform.broxton) 2584 return false; 2585 2586 /* 2587 * FIXME should store a bit more state in intel_cdclk_config 2588 * to differentiate squasher vs. cd2x divider properly. For 2589 * the moment all platforms with squasher use a fixed cd2x 2590 * divider. 2591 */ 2592 if (HAS_CDCLK_SQUASH(display)) 2593 return false; 2594 2595 return a->cdclk != b->cdclk && 2596 a->vco != 0 && 2597 a->vco == b->vco && 2598 a->ref == b->ref; 2599 } 2600 2601 /** 2602 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2603 * @a: first CDCLK configuration 2604 * @b: second CDCLK configuration 2605 * 2606 * Returns: 2607 * True if the CDCLK configurations don't match, false if they do. 2608 */ 2609 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2610 const struct intel_cdclk_config *b) 2611 { 2612 return intel_cdclk_clock_changed(a, b) || 2613 a->voltage_level != b->voltage_level; 2614 } 2615 2616 void intel_cdclk_dump_config(struct intel_display *display, 2617 const struct intel_cdclk_config *cdclk_config, 2618 const char *context) 2619 { 2620 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2621 context, cdclk_config->cdclk, cdclk_config->vco, 2622 cdclk_config->ref, cdclk_config->bypass, 2623 cdclk_config->voltage_level); 2624 } 2625 2626 static void intel_pcode_notify(struct intel_display *display, 2627 u8 voltage_level, 2628 u8 active_pipe_count, 2629 u16 cdclk, 2630 bool cdclk_update_valid, 2631 bool pipe_count_update_valid) 2632 { 2633 int ret; 2634 u32 update_mask = 0; 2635 2636 if (!display->platform.dg2) 2637 return; 2638 2639 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2640 2641 if (cdclk_update_valid) 2642 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2643 2644 if (pipe_count_update_valid) 2645 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2646 2647 ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL, 2648 SKL_CDCLK_PREPARE_FOR_CHANGE | 2649 update_mask, 2650 SKL_CDCLK_READY_FOR_CHANGE, 2651 SKL_CDCLK_READY_FOR_CHANGE, 3); 2652 if (ret) 2653 drm_err(display->drm, 2654 "Failed to inform PCU about display config (err %d)\n", 2655 ret); 2656 } 2657 2658 static void intel_set_cdclk(struct intel_display *display, 2659 const struct intel_cdclk_config *cdclk_config, 2660 enum pipe pipe, const char *context) 2661 { 2662 struct intel_encoder *encoder; 2663 2664 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) 2665 return; 2666 2667 if (drm_WARN_ON_ONCE(display->drm, !display->cdclk.funcs->set_cdclk)) 2668 return; 2669 2670 intel_cdclk_dump_config(display, cdclk_config, context); 2671 2672 for_each_intel_encoder_with_psr(display->drm, encoder) { 2673 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2674 2675 intel_psr_pause(intel_dp); 2676 } 2677 2678 intel_audio_cdclk_change_pre(display); 2679 2680 /* 2681 * Lock aux/gmbus while we change cdclk in case those 2682 * functions use cdclk. Not all platforms/ports do, 2683 * but we'll lock them all for simplicity. 2684 */ 2685 mutex_lock(&display->gmbus.mutex); 2686 for_each_intel_dp(display->drm, encoder) { 2687 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2688 2689 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2690 &display->gmbus.mutex); 2691 } 2692 2693 intel_cdclk_set_cdclk(display, cdclk_config, pipe); 2694 2695 for_each_intel_dp(display->drm, encoder) { 2696 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2697 2698 mutex_unlock(&intel_dp->aux.hw_mutex); 2699 } 2700 mutex_unlock(&display->gmbus.mutex); 2701 2702 for_each_intel_encoder_with_psr(display->drm, encoder) { 2703 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2704 2705 intel_psr_resume(intel_dp); 2706 } 2707 2708 intel_audio_cdclk_change_post(display); 2709 2710 if (drm_WARN(display->drm, 2711 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), 2712 "cdclk state doesn't match!\n")) { 2713 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); 2714 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); 2715 } 2716 } 2717 2718 static int dg2_power_well_count(struct intel_display *display, 2719 const struct intel_cdclk_state *cdclk_state) 2720 { 2721 return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0; 2722 } 2723 2724 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2725 { 2726 struct intel_display *display = to_intel_display(state); 2727 const struct intel_cdclk_state *old_cdclk_state = 2728 intel_atomic_get_old_cdclk_state(state); 2729 const struct intel_cdclk_state *new_cdclk_state = 2730 intel_atomic_get_new_cdclk_state(state); 2731 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2732 bool change_cdclk, update_pipe_count; 2733 2734 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2735 &new_cdclk_state->actual) && 2736 dg2_power_well_count(display, old_cdclk_state) == 2737 dg2_power_well_count(display, new_cdclk_state)) 2738 return; 2739 2740 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2741 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2742 2743 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2744 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) > 2745 dg2_power_well_count(display, old_cdclk_state); 2746 2747 /* 2748 * According to "Sequence Before Frequency Change", 2749 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2750 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2751 * which basically means we choose the maximum of old and new CDCLK, if we know both 2752 */ 2753 if (change_cdclk) 2754 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2755 2756 /* 2757 * According to "Sequence For Pipe Count Change", 2758 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2759 * (power well is enabled) 2760 * no action if it is decreasing, before the change 2761 */ 2762 if (update_pipe_count) 2763 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); 2764 2765 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2766 change_cdclk, update_pipe_count); 2767 } 2768 2769 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2770 { 2771 struct intel_display *display = to_intel_display(state); 2772 const struct intel_cdclk_state *new_cdclk_state = 2773 intel_atomic_get_new_cdclk_state(state); 2774 const struct intel_cdclk_state *old_cdclk_state = 2775 intel_atomic_get_old_cdclk_state(state); 2776 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2777 bool update_cdclk, update_pipe_count; 2778 2779 /* According to "Sequence After Frequency Change", set voltage to used level */ 2780 voltage_level = new_cdclk_state->actual.voltage_level; 2781 2782 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2783 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) < 2784 dg2_power_well_count(display, old_cdclk_state); 2785 2786 /* 2787 * According to "Sequence After Frequency Change", 2788 * set bits 25:16 to current CDCLK 2789 */ 2790 if (update_cdclk) 2791 cdclk = new_cdclk_state->actual.cdclk; 2792 2793 /* 2794 * According to "Sequence For Pipe Count Change", 2795 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2796 * after the change(power well is disabled) 2797 * no action if it is increasing, after the change 2798 */ 2799 if (update_pipe_count) 2800 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); 2801 2802 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2803 update_cdclk, update_pipe_count); 2804 } 2805 2806 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2807 { 2808 const struct intel_cdclk_state *old_cdclk_state = 2809 intel_atomic_get_old_cdclk_state(state); 2810 const struct intel_cdclk_state *new_cdclk_state = 2811 intel_atomic_get_new_cdclk_state(state); 2812 2813 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2814 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2815 } 2816 2817 /** 2818 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2819 * @state: intel atomic state 2820 * 2821 * Program the hardware before updating the HW plane state based on the 2822 * new CDCLK state, if necessary. 2823 */ 2824 void 2825 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2826 { 2827 struct intel_display *display = to_intel_display(state); 2828 const struct intel_cdclk_state *old_cdclk_state = 2829 intel_atomic_get_old_cdclk_state(state); 2830 const struct intel_cdclk_state *new_cdclk_state = 2831 intel_atomic_get_new_cdclk_state(state); 2832 struct intel_cdclk_config cdclk_config; 2833 enum pipe pipe; 2834 2835 if (!new_cdclk_state) 2836 return; 2837 2838 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2839 &new_cdclk_state->actual)) 2840 return; 2841 2842 if (display->platform.dg2) 2843 intel_cdclk_pcode_pre_notify(state); 2844 2845 if (new_cdclk_state->disable_pipes) { 2846 cdclk_config = new_cdclk_state->actual; 2847 pipe = INVALID_PIPE; 2848 } else { 2849 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2850 cdclk_config = new_cdclk_state->actual; 2851 pipe = new_cdclk_state->pipe; 2852 } else { 2853 cdclk_config = old_cdclk_state->actual; 2854 pipe = INVALID_PIPE; 2855 } 2856 2857 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2858 old_cdclk_state->actual.voltage_level); 2859 } 2860 2861 /* 2862 * mbus joining will be changed later by 2863 * intel_dbuf_mbus_{pre,post}_ddb_update() 2864 */ 2865 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2866 2867 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2868 2869 intel_set_cdclk(display, &cdclk_config, pipe, 2870 "Pre changing CDCLK to"); 2871 } 2872 2873 /** 2874 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2875 * @state: intel atomic state 2876 * 2877 * Program the hardware after updating the HW plane state based on the 2878 * new CDCLK state, if necessary. 2879 */ 2880 void 2881 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2882 { 2883 struct intel_display *display = to_intel_display(state); 2884 const struct intel_cdclk_state *old_cdclk_state = 2885 intel_atomic_get_old_cdclk_state(state); 2886 const struct intel_cdclk_state *new_cdclk_state = 2887 intel_atomic_get_new_cdclk_state(state); 2888 enum pipe pipe; 2889 2890 if (!new_cdclk_state) 2891 return; 2892 2893 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2894 &new_cdclk_state->actual)) 2895 return; 2896 2897 if (display->platform.dg2) 2898 intel_cdclk_pcode_post_notify(state); 2899 2900 if (!new_cdclk_state->disable_pipes && 2901 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2902 pipe = new_cdclk_state->pipe; 2903 else 2904 pipe = INVALID_PIPE; 2905 2906 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2907 2908 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, 2909 "Post changing CDCLK to"); 2910 } 2911 2912 /* pixels per CDCLK */ 2913 int intel_cdclk_ppc(struct intel_display *display, bool double_wide) 2914 { 2915 return HAS_2PPC(display) || double_wide ? 2 : 1; 2916 } 2917 2918 /* max pixel rate as % of CDCLK (not accounting for PPC) */ 2919 static int intel_cdclk_guardband(struct intel_display *display) 2920 { 2921 if (DISPLAY_VER(display) >= 9 || 2922 display->platform.broadwell || display->platform.haswell) 2923 return 100; 2924 else if (display->platform.cherryview) 2925 return 95; 2926 else 2927 return 90; 2928 } 2929 2930 static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate) 2931 { 2932 struct intel_display *display = to_intel_display(crtc_state); 2933 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 2934 int guardband = intel_cdclk_guardband(display); 2935 2936 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); 2937 } 2938 2939 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2940 { 2941 return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate_cdclk); 2942 } 2943 2944 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2945 { 2946 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2947 struct intel_display *display = to_intel_display(crtc); 2948 struct intel_plane *plane; 2949 int min_cdclk = 0; 2950 2951 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2952 min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]); 2953 2954 return min_cdclk; 2955 } 2956 2957 int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state) 2958 { 2959 int min_cdclk; 2960 2961 if (!crtc_state->hw.enable) 2962 return 0; 2963 2964 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2965 min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state)); 2966 min_cdclk = max(min_cdclk, intel_fbc_min_cdclk(crtc_state)); 2967 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state)); 2968 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state)); 2969 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); 2970 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state)); 2971 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2972 2973 return min_cdclk; 2974 } 2975 2976 static int intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state *state, 2977 struct intel_crtc *crtc, 2978 int old_min_cdclk, int new_min_cdclk, 2979 bool *need_cdclk_calc) 2980 { 2981 struct intel_display *display = to_intel_display(state); 2982 struct intel_cdclk_state *cdclk_state; 2983 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state); 2984 int ret; 2985 2986 if (new_min_cdclk == old_min_cdclk) 2987 return 0; 2988 2989 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2990 return 0; 2991 2992 cdclk_state = intel_atomic_get_cdclk_state(state); 2993 if (IS_ERR(cdclk_state)) 2994 return PTR_ERR(cdclk_state); 2995 2996 old_min_cdclk = cdclk_state->min_cdclk[crtc->pipe]; 2997 2998 if (new_min_cdclk == old_min_cdclk) 2999 return 0; 3000 3001 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 3002 return 0; 3003 3004 cdclk_state->min_cdclk[crtc->pipe] = new_min_cdclk; 3005 3006 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3007 if (ret) 3008 return ret; 3009 3010 *need_cdclk_calc = true; 3011 3012 drm_dbg_kms(display->drm, 3013 "[CRTC:%d:%s] min cdclk: %d kHz -> %d kHz\n", 3014 crtc->base.base.id, crtc->base.name, 3015 old_min_cdclk, new_min_cdclk); 3016 3017 return 0; 3018 } 3019 3020 static int intel_cdclk_update_crtc_min_voltage_level(struct intel_atomic_state *state, 3021 struct intel_crtc *crtc, 3022 u8 old_min_voltage_level, 3023 u8 new_min_voltage_level, 3024 bool *need_cdclk_calc) 3025 { 3026 struct intel_display *display = to_intel_display(state); 3027 struct intel_cdclk_state *cdclk_state; 3028 bool allow_voltage_level_decrease = intel_any_crtc_needs_modeset(state); 3029 int ret; 3030 3031 if (new_min_voltage_level == old_min_voltage_level) 3032 return 0; 3033 3034 if (!allow_voltage_level_decrease && 3035 new_min_voltage_level < old_min_voltage_level) 3036 return 0; 3037 3038 cdclk_state = intel_atomic_get_cdclk_state(state); 3039 if (IS_ERR(cdclk_state)) 3040 return PTR_ERR(cdclk_state); 3041 3042 old_min_voltage_level = cdclk_state->min_voltage_level[crtc->pipe]; 3043 3044 if (new_min_voltage_level == old_min_voltage_level) 3045 return 0; 3046 3047 if (!allow_voltage_level_decrease && 3048 new_min_voltage_level < old_min_voltage_level) 3049 return 0; 3050 3051 cdclk_state->min_voltage_level[crtc->pipe] = new_min_voltage_level; 3052 3053 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3054 if (ret) 3055 return ret; 3056 3057 *need_cdclk_calc = true; 3058 3059 drm_dbg_kms(display->drm, 3060 "[CRTC:%d:%s] min voltage level: %d -> %d\n", 3061 crtc->base.base.id, crtc->base.name, 3062 old_min_voltage_level, new_min_voltage_level); 3063 3064 return 0; 3065 } 3066 3067 int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state, 3068 int old_min_cdclk, int new_min_cdclk, 3069 bool *need_cdclk_calc) 3070 { 3071 struct intel_display *display = to_intel_display(state); 3072 struct intel_cdclk_state *cdclk_state; 3073 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state); 3074 int ret; 3075 3076 if (new_min_cdclk == old_min_cdclk) 3077 return 0; 3078 3079 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 3080 return 0; 3081 3082 cdclk_state = intel_atomic_get_cdclk_state(state); 3083 if (IS_ERR(cdclk_state)) 3084 return PTR_ERR(cdclk_state); 3085 3086 old_min_cdclk = cdclk_state->dbuf_bw_min_cdclk; 3087 3088 if (new_min_cdclk == old_min_cdclk) 3089 return 0; 3090 3091 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 3092 return 0; 3093 3094 cdclk_state->dbuf_bw_min_cdclk = new_min_cdclk; 3095 3096 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3097 if (ret) 3098 return ret; 3099 3100 *need_cdclk_calc = true; 3101 3102 drm_dbg_kms(display->drm, 3103 "dbuf bandwidth min cdclk: %d kHz -> %d kHz\n", 3104 old_min_cdclk, new_min_cdclk); 3105 3106 return 0; 3107 } 3108 3109 static bool glk_cdclk_audio_wa_needed(struct intel_display *display, 3110 const struct intel_cdclk_state *cdclk_state) 3111 { 3112 return display->platform.geminilake && 3113 cdclk_state->enabled_pipes && 3114 !is_power_of_2(cdclk_state->enabled_pipes); 3115 } 3116 3117 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 3118 { 3119 struct intel_display *display = to_intel_display(state); 3120 struct intel_cdclk_state *cdclk_state = 3121 intel_atomic_get_new_cdclk_state(state); 3122 enum pipe pipe; 3123 int min_cdclk; 3124 3125 min_cdclk = cdclk_state->force_min_cdclk; 3126 min_cdclk = max(min_cdclk, cdclk_state->dbuf_bw_min_cdclk); 3127 for_each_pipe(display, pipe) 3128 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); 3129 3130 /* 3131 * Avoid glk_force_audio_cdclk() causing excessive screen 3132 * blinking when multiple pipes are active by making sure 3133 * CDCLK frequency is always high enough for audio. With a 3134 * single active pipe we can always change CDCLK frequency 3135 * by changing the cd2x divider (see glk_cdclk_table[]) and 3136 * thus a full modeset won't be needed then. 3137 */ 3138 if (glk_cdclk_audio_wa_needed(display, cdclk_state)) 3139 min_cdclk = max(min_cdclk, 2 * 96000); 3140 3141 if (min_cdclk > display->cdclk.max_cdclk_freq) { 3142 drm_dbg_kms(display->drm, 3143 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 3144 min_cdclk, display->cdclk.max_cdclk_freq); 3145 return -EINVAL; 3146 } 3147 3148 return min_cdclk; 3149 } 3150 3151 /* 3152 * Account for port clock min voltage level requirements. 3153 * This only really does something on DISPLA_VER >= 11 but can be 3154 * called on earlier platforms as well. 3155 * 3156 * Note that this functions assumes that 0 is 3157 * the lowest voltage value, and higher values 3158 * correspond to increasingly higher voltages. 3159 * 3160 * Should that relationship no longer hold on 3161 * future platforms this code will need to be 3162 * adjusted. 3163 */ 3164 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 3165 { 3166 struct intel_display *display = to_intel_display(state); 3167 struct intel_cdclk_state *cdclk_state = 3168 intel_atomic_get_new_cdclk_state(state); 3169 struct intel_crtc *crtc; 3170 struct intel_crtc_state *crtc_state; 3171 u8 min_voltage_level; 3172 enum pipe pipe; 3173 3174 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 3175 int ret; 3176 3177 if (crtc_state->hw.enable) 3178 min_voltage_level = crtc_state->min_voltage_level; 3179 else 3180 min_voltage_level = 0; 3181 3182 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 3183 continue; 3184 3185 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 3186 3187 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3188 if (ret) 3189 return ret; 3190 } 3191 3192 min_voltage_level = 0; 3193 for_each_pipe(display, pipe) 3194 min_voltage_level = max(min_voltage_level, 3195 cdclk_state->min_voltage_level[pipe]); 3196 3197 return min_voltage_level; 3198 } 3199 3200 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 3201 { 3202 struct intel_display *display = to_intel_display(state); 3203 struct intel_cdclk_state *cdclk_state = 3204 intel_atomic_get_new_cdclk_state(state); 3205 int min_cdclk, cdclk; 3206 3207 min_cdclk = intel_compute_min_cdclk(state); 3208 if (min_cdclk < 0) 3209 return min_cdclk; 3210 3211 cdclk = vlv_calc_cdclk(display, min_cdclk); 3212 3213 cdclk_state->logical.cdclk = cdclk; 3214 cdclk_state->logical.voltage_level = 3215 vlv_calc_voltage_level(display, cdclk); 3216 3217 if (!cdclk_state->active_pipes) { 3218 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); 3219 3220 cdclk_state->actual.cdclk = cdclk; 3221 cdclk_state->actual.voltage_level = 3222 vlv_calc_voltage_level(display, cdclk); 3223 } else { 3224 cdclk_state->actual = cdclk_state->logical; 3225 } 3226 3227 return 0; 3228 } 3229 3230 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 3231 { 3232 struct intel_cdclk_state *cdclk_state = 3233 intel_atomic_get_new_cdclk_state(state); 3234 int min_cdclk, cdclk; 3235 3236 min_cdclk = intel_compute_min_cdclk(state); 3237 if (min_cdclk < 0) 3238 return min_cdclk; 3239 3240 cdclk = bdw_calc_cdclk(min_cdclk); 3241 3242 cdclk_state->logical.cdclk = cdclk; 3243 cdclk_state->logical.voltage_level = 3244 bdw_calc_voltage_level(cdclk); 3245 3246 if (!cdclk_state->active_pipes) { 3247 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 3248 3249 cdclk_state->actual.cdclk = cdclk; 3250 cdclk_state->actual.voltage_level = 3251 bdw_calc_voltage_level(cdclk); 3252 } else { 3253 cdclk_state->actual = cdclk_state->logical; 3254 } 3255 3256 return 0; 3257 } 3258 3259 static int skl_dpll0_vco(struct intel_atomic_state *state) 3260 { 3261 struct intel_display *display = to_intel_display(state); 3262 struct intel_cdclk_state *cdclk_state = 3263 intel_atomic_get_new_cdclk_state(state); 3264 struct intel_crtc *crtc; 3265 struct intel_crtc_state *crtc_state; 3266 int vco; 3267 3268 vco = cdclk_state->logical.vco; 3269 if (!vco) 3270 vco = display->cdclk.skl_preferred_vco_freq; 3271 3272 for_each_new_intel_crtc_in_state(state, crtc, crtc_state) { 3273 if (!crtc_state->hw.enable) 3274 continue; 3275 3276 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3277 continue; 3278 3279 /* 3280 * DPLL0 VCO may need to be adjusted to get the correct 3281 * clock for eDP. This will affect cdclk as well. 3282 */ 3283 switch (crtc_state->port_clock / 2) { 3284 case 108000: 3285 case 216000: 3286 vco = 8640000; 3287 break; 3288 default: 3289 vco = 8100000; 3290 break; 3291 } 3292 } 3293 3294 return vco; 3295 } 3296 3297 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3298 { 3299 struct intel_cdclk_state *cdclk_state = 3300 intel_atomic_get_new_cdclk_state(state); 3301 int min_cdclk, cdclk, vco; 3302 3303 min_cdclk = intel_compute_min_cdclk(state); 3304 if (min_cdclk < 0) 3305 return min_cdclk; 3306 3307 vco = skl_dpll0_vco(state); 3308 3309 cdclk = skl_calc_cdclk(min_cdclk, vco); 3310 3311 cdclk_state->logical.vco = vco; 3312 cdclk_state->logical.cdclk = cdclk; 3313 cdclk_state->logical.voltage_level = 3314 skl_calc_voltage_level(cdclk); 3315 3316 if (!cdclk_state->active_pipes) { 3317 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3318 3319 cdclk_state->actual.vco = vco; 3320 cdclk_state->actual.cdclk = cdclk; 3321 cdclk_state->actual.voltage_level = 3322 skl_calc_voltage_level(cdclk); 3323 } else { 3324 cdclk_state->actual = cdclk_state->logical; 3325 } 3326 3327 return 0; 3328 } 3329 3330 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3331 { 3332 struct intel_display *display = to_intel_display(state); 3333 struct intel_cdclk_state *cdclk_state = 3334 intel_atomic_get_new_cdclk_state(state); 3335 int min_cdclk, min_voltage_level, cdclk, vco; 3336 3337 min_cdclk = intel_compute_min_cdclk(state); 3338 if (min_cdclk < 0) 3339 return min_cdclk; 3340 3341 min_voltage_level = bxt_compute_min_voltage_level(state); 3342 if (min_voltage_level < 0) 3343 return min_voltage_level; 3344 3345 cdclk = bxt_calc_cdclk(display, min_cdclk); 3346 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3347 3348 cdclk_state->logical.vco = vco; 3349 cdclk_state->logical.cdclk = cdclk; 3350 cdclk_state->logical.voltage_level = 3351 max_t(int, min_voltage_level, 3352 intel_cdclk_calc_voltage_level(display, cdclk)); 3353 3354 if (!cdclk_state->active_pipes) { 3355 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); 3356 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3357 3358 cdclk_state->actual.vco = vco; 3359 cdclk_state->actual.cdclk = cdclk; 3360 cdclk_state->actual.voltage_level = 3361 intel_cdclk_calc_voltage_level(display, cdclk); 3362 } else { 3363 cdclk_state->actual = cdclk_state->logical; 3364 } 3365 3366 return 0; 3367 } 3368 3369 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3370 { 3371 int min_cdclk; 3372 3373 /* 3374 * We can't change the cdclk frequency, but we still want to 3375 * check that the required minimum frequency doesn't exceed 3376 * the actual cdclk frequency. 3377 */ 3378 min_cdclk = intel_compute_min_cdclk(state); 3379 if (min_cdclk < 0) 3380 return min_cdclk; 3381 3382 return 0; 3383 } 3384 3385 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3386 { 3387 struct intel_cdclk_state *cdclk_state; 3388 3389 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3390 if (!cdclk_state) 3391 return NULL; 3392 3393 cdclk_state->pipe = INVALID_PIPE; 3394 cdclk_state->disable_pipes = false; 3395 3396 return &cdclk_state->base; 3397 } 3398 3399 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3400 struct intel_global_state *state) 3401 { 3402 kfree(state); 3403 } 3404 3405 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3406 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3407 .atomic_destroy_state = intel_cdclk_destroy_state, 3408 }; 3409 3410 struct intel_cdclk_state * 3411 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3412 { 3413 struct intel_display *display = to_intel_display(state); 3414 struct intel_global_state *cdclk_state; 3415 3416 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); 3417 if (IS_ERR(cdclk_state)) 3418 return ERR_CAST(cdclk_state); 3419 3420 return to_intel_cdclk_state(cdclk_state); 3421 } 3422 3423 static int intel_cdclk_modeset_checks(struct intel_atomic_state *state, 3424 bool *need_cdclk_calc) 3425 { 3426 struct intel_display *display = to_intel_display(state); 3427 const struct intel_cdclk_state *old_cdclk_state; 3428 struct intel_cdclk_state *new_cdclk_state; 3429 int ret; 3430 3431 if (!intel_any_crtc_enable_changed(state) && 3432 !intel_any_crtc_active_changed(state)) 3433 return 0; 3434 3435 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3436 if (IS_ERR(new_cdclk_state)) 3437 return PTR_ERR(new_cdclk_state); 3438 3439 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3440 3441 new_cdclk_state->enabled_pipes = 3442 intel_calc_enabled_pipes(state, old_cdclk_state->enabled_pipes); 3443 3444 new_cdclk_state->active_pipes = 3445 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3446 3447 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3448 if (ret) 3449 return ret; 3450 3451 if (!old_cdclk_state->active_pipes != !new_cdclk_state->active_pipes) 3452 *need_cdclk_calc = true; 3453 3454 if (glk_cdclk_audio_wa_needed(display, old_cdclk_state) != 3455 glk_cdclk_audio_wa_needed(display, new_cdclk_state)) 3456 *need_cdclk_calc = true; 3457 3458 if (dg2_power_well_count(display, old_cdclk_state) != 3459 dg2_power_well_count(display, new_cdclk_state)) 3460 *need_cdclk_calc = true; 3461 3462 return 0; 3463 } 3464 3465 static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state, 3466 bool *need_cdclk_calc) 3467 { 3468 const struct intel_crtc_state *old_crtc_state; 3469 const struct intel_crtc_state *new_crtc_state; 3470 struct intel_crtc *crtc; 3471 int ret; 3472 3473 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state) { 3474 ret = intel_cdclk_update_crtc_min_cdclk(state, crtc, 3475 old_crtc_state->min_cdclk, 3476 new_crtc_state->min_cdclk, 3477 need_cdclk_calc); 3478 if (ret) 3479 return ret; 3480 3481 ret = intel_cdclk_update_crtc_min_voltage_level(state, crtc, 3482 old_crtc_state->min_voltage_level, 3483 new_crtc_state->min_voltage_level, 3484 need_cdclk_calc); 3485 if (ret) 3486 return ret; 3487 } 3488 3489 return 0; 3490 } 3491 3492 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3493 { 3494 struct intel_cdclk_state *cdclk_state; 3495 3496 cdclk_state = intel_atomic_get_cdclk_state(state); 3497 if (IS_ERR(cdclk_state)) 3498 return PTR_ERR(cdclk_state); 3499 3500 cdclk_state->actual.joined_mbus = joined_mbus; 3501 cdclk_state->logical.joined_mbus = joined_mbus; 3502 3503 return intel_atomic_lock_global_state(&cdclk_state->base); 3504 } 3505 3506 int intel_cdclk_init(struct intel_display *display) 3507 { 3508 struct intel_cdclk_state *cdclk_state; 3509 3510 cdclk_state = kzalloc_obj(*cdclk_state); 3511 if (!cdclk_state) 3512 return -ENOMEM; 3513 3514 intel_atomic_global_obj_init(display, &display->cdclk.obj, 3515 &cdclk_state->base, &intel_cdclk_funcs); 3516 3517 return 0; 3518 } 3519 3520 static bool intel_cdclk_need_serialize(struct intel_display *display, 3521 const struct intel_cdclk_state *old_cdclk_state, 3522 const struct intel_cdclk_state *new_cdclk_state) 3523 { 3524 /* 3525 * We need to poke hw for DG2, because we notify PCode if 3526 * pipe power well count changes. 3527 */ 3528 return intel_cdclk_changed(&old_cdclk_state->actual, 3529 &new_cdclk_state->actual) || 3530 dg2_power_well_count(display, old_cdclk_state) != 3531 dg2_power_well_count(display, new_cdclk_state); 3532 } 3533 3534 static int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3535 { 3536 struct intel_display *display = to_intel_display(state); 3537 const struct intel_cdclk_state *old_cdclk_state; 3538 struct intel_cdclk_state *new_cdclk_state; 3539 enum pipe pipe = INVALID_PIPE; 3540 int ret; 3541 3542 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3543 if (IS_ERR(new_cdclk_state)) 3544 return PTR_ERR(new_cdclk_state); 3545 3546 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3547 3548 ret = intel_cdclk_modeset_calc_cdclk(state); 3549 if (ret) 3550 return ret; 3551 3552 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { 3553 /* 3554 * Also serialize commits across all crtcs 3555 * if the actual hw needs to be poked. 3556 */ 3557 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3558 if (ret) 3559 return ret; 3560 } else if (intel_cdclk_changed(&old_cdclk_state->logical, 3561 &new_cdclk_state->logical)) { 3562 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3563 if (ret) 3564 return ret; 3565 } else { 3566 return 0; 3567 } 3568 3569 if (is_power_of_2(new_cdclk_state->active_pipes) && 3570 intel_cdclk_can_cd2x_update(display, 3571 &old_cdclk_state->actual, 3572 &new_cdclk_state->actual)) { 3573 struct intel_crtc *crtc; 3574 struct intel_crtc_state *crtc_state; 3575 3576 pipe = ilog2(new_cdclk_state->active_pipes); 3577 crtc = intel_crtc_for_pipe(display, pipe); 3578 3579 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3580 if (IS_ERR(crtc_state)) 3581 return PTR_ERR(crtc_state); 3582 3583 if (intel_crtc_needs_modeset(crtc_state)) 3584 pipe = INVALID_PIPE; 3585 } 3586 3587 if (intel_cdclk_can_crawl_and_squash(display, 3588 &old_cdclk_state->actual, 3589 &new_cdclk_state->actual)) { 3590 drm_dbg_kms(display->drm, 3591 "Can change cdclk via crawling and squashing\n"); 3592 } else if (intel_cdclk_can_squash(display, 3593 &old_cdclk_state->actual, 3594 &new_cdclk_state->actual)) { 3595 drm_dbg_kms(display->drm, 3596 "Can change cdclk via squashing\n"); 3597 } else if (intel_cdclk_can_crawl(display, 3598 &old_cdclk_state->actual, 3599 &new_cdclk_state->actual)) { 3600 drm_dbg_kms(display->drm, 3601 "Can change cdclk via crawling\n"); 3602 } else if (pipe != INVALID_PIPE) { 3603 new_cdclk_state->pipe = pipe; 3604 3605 drm_dbg_kms(display->drm, 3606 "Can change cdclk cd2x divider with pipe %c active\n", 3607 pipe_name(pipe)); 3608 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3609 &new_cdclk_state->actual)) { 3610 /* All pipes must be switched off while we change the cdclk. */ 3611 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3612 if (ret) 3613 return ret; 3614 3615 new_cdclk_state->disable_pipes = true; 3616 3617 drm_dbg_kms(display->drm, 3618 "Modeset required for cdclk change\n"); 3619 } 3620 3621 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != 3622 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { 3623 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); 3624 3625 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3626 if (ret) 3627 return ret; 3628 } 3629 3630 drm_dbg_kms(display->drm, 3631 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3632 new_cdclk_state->logical.cdclk, 3633 new_cdclk_state->actual.cdclk); 3634 drm_dbg_kms(display->drm, 3635 "New voltage level calculated to be logical %u, actual %u\n", 3636 new_cdclk_state->logical.voltage_level, 3637 new_cdclk_state->actual.voltage_level); 3638 3639 return 0; 3640 } 3641 3642 int intel_cdclk_atomic_check(struct intel_atomic_state *state) 3643 { 3644 const struct intel_cdclk_state *old_cdclk_state; 3645 struct intel_cdclk_state *new_cdclk_state; 3646 bool need_cdclk_calc = false; 3647 int ret; 3648 3649 ret = intel_cdclk_modeset_checks(state, &need_cdclk_calc); 3650 if (ret) 3651 return ret; 3652 3653 ret = intel_crtcs_calc_min_cdclk(state, &need_cdclk_calc); 3654 if (ret) 3655 return ret; 3656 3657 ret = intel_dbuf_bw_calc_min_cdclk(state, &need_cdclk_calc); 3658 if (ret) 3659 return ret; 3660 3661 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3662 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3663 3664 if (new_cdclk_state && 3665 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) { 3666 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3667 if (ret) 3668 return ret; 3669 3670 need_cdclk_calc = true; 3671 } 3672 3673 if (need_cdclk_calc) { 3674 ret = intel_modeset_calc_cdclk(state); 3675 if (ret) 3676 return ret; 3677 } 3678 3679 return 0; 3680 } 3681 3682 void intel_cdclk_update_hw_state(struct intel_display *display) 3683 { 3684 const struct intel_dbuf_bw_state *dbuf_bw_state = 3685 to_intel_dbuf_bw_state(display->dbuf_bw.obj.state); 3686 struct intel_cdclk_state *cdclk_state = 3687 to_intel_cdclk_state(display->cdclk.obj.state); 3688 struct intel_crtc *crtc; 3689 3690 cdclk_state->enabled_pipes = 0; 3691 cdclk_state->active_pipes = 0; 3692 3693 for_each_intel_crtc(display, crtc) { 3694 const struct intel_crtc_state *crtc_state = 3695 to_intel_crtc_state(crtc->base.state); 3696 enum pipe pipe = crtc->pipe; 3697 3698 if (crtc_state->hw.enable) 3699 cdclk_state->enabled_pipes |= BIT(pipe); 3700 if (crtc_state->hw.active) 3701 cdclk_state->active_pipes |= BIT(pipe); 3702 3703 cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk; 3704 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level; 3705 } 3706 3707 cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display, dbuf_bw_state); 3708 } 3709 3710 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc) 3711 { 3712 struct intel_display *display = to_intel_display(crtc); 3713 3714 intel_cdclk_update_hw_state(display); 3715 } 3716 3717 static int intel_compute_max_dotclk(struct intel_display *display) 3718 { 3719 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); 3720 int guardband = intel_cdclk_guardband(display); 3721 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3722 3723 return ppc * max_cdclk_freq * guardband / 100; 3724 } 3725 3726 /** 3727 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3728 * @display: display instance 3729 * 3730 * Determine the maximum CDCLK frequency the platform supports, and also 3731 * derive the maximum dot clock frequency the maximum CDCLK frequency 3732 * allows. 3733 */ 3734 void intel_update_max_cdclk(struct intel_display *display) 3735 { 3736 if (DISPLAY_VER(display) >= 35) { 3737 display->cdclk.max_cdclk_freq = 787200; 3738 } else if (DISPLAY_VERx100(display) >= 3002) { 3739 display->cdclk.max_cdclk_freq = 480000; 3740 } else if (DISPLAY_VER(display) >= 30) { 3741 display->cdclk.max_cdclk_freq = 691200; 3742 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3743 if (display->cdclk.hw.ref == 24000) 3744 display->cdclk.max_cdclk_freq = 552000; 3745 else 3746 display->cdclk.max_cdclk_freq = 556800; 3747 } else if (DISPLAY_VER(display) >= 11) { 3748 if (display->cdclk.hw.ref == 24000) 3749 display->cdclk.max_cdclk_freq = 648000; 3750 else 3751 display->cdclk.max_cdclk_freq = 652800; 3752 } else if (display->platform.geminilake) { 3753 display->cdclk.max_cdclk_freq = 316800; 3754 } else if (display->platform.broxton) { 3755 display->cdclk.max_cdclk_freq = 624000; 3756 } else if (DISPLAY_VER(display) == 9) { 3757 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3758 int max_cdclk, vco; 3759 3760 vco = display->cdclk.skl_preferred_vco_freq; 3761 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 3762 3763 /* 3764 * Use the lower (vco 8640) cdclk values as a 3765 * first guess. skl_calc_cdclk() will correct it 3766 * if the preferred vco is 8100 instead. 3767 */ 3768 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3769 max_cdclk = 617143; 3770 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3771 max_cdclk = 540000; 3772 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3773 max_cdclk = 432000; 3774 else 3775 max_cdclk = 308571; 3776 3777 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3778 } else if (display->platform.broadwell) { 3779 /* 3780 * FIXME with extra cooling we can allow 3781 * 540 MHz for ULX and 675 Mhz for ULT. 3782 * How can we know if extra cooling is 3783 * available? PCI ID, VTB, something else? 3784 */ 3785 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3786 display->cdclk.max_cdclk_freq = 450000; 3787 else if (display->platform.broadwell_ulx) 3788 display->cdclk.max_cdclk_freq = 450000; 3789 else if (display->platform.broadwell_ult) 3790 display->cdclk.max_cdclk_freq = 540000; 3791 else 3792 display->cdclk.max_cdclk_freq = 675000; 3793 } else if (display->platform.cherryview) { 3794 display->cdclk.max_cdclk_freq = 320000; 3795 } else if (display->platform.valleyview) { 3796 display->cdclk.max_cdclk_freq = 400000; 3797 } else { 3798 /* otherwise assume cdclk is fixed */ 3799 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; 3800 } 3801 3802 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); 3803 3804 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", 3805 display->cdclk.max_cdclk_freq); 3806 3807 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", 3808 display->cdclk.max_dotclk_freq); 3809 } 3810 3811 /** 3812 * intel_update_cdclk - Determine the current CDCLK frequency 3813 * @display: display instance 3814 * 3815 * Determine the current CDCLK frequency. 3816 */ 3817 void intel_update_cdclk(struct intel_display *display) 3818 { 3819 intel_cdclk_get_cdclk(display, &display->cdclk.hw); 3820 3821 /* 3822 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3823 * Programmng [sic] note: bit[9:2] should be programmed to the number 3824 * of cdclk that generates 4MHz reference clock freq which is used to 3825 * generate GMBus clock. This will vary with the cdclk freq. 3826 */ 3827 if (display->platform.valleyview || display->platform.cherryview) 3828 intel_de_write(display, GMBUSFREQ_VLV, 3829 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); 3830 } 3831 3832 static int dg1_rawclk(struct intel_display *display) 3833 { 3834 /* 3835 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3836 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3837 */ 3838 intel_de_write(display, PCH_RAWCLK_FREQ, 3839 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3840 3841 return 38400; 3842 } 3843 3844 static int cnp_rawclk(struct intel_display *display) 3845 { 3846 int divider, fraction; 3847 u32 rawclk; 3848 3849 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3850 /* 24 MHz */ 3851 divider = 24000; 3852 fraction = 0; 3853 } else { 3854 /* 19.2 MHz */ 3855 divider = 19000; 3856 fraction = 200; 3857 } 3858 3859 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3860 if (fraction) { 3861 int numerator = 1; 3862 3863 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3864 fraction) - 1); 3865 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 3866 rawclk |= ICP_RAWCLK_NUM(numerator); 3867 } 3868 3869 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); 3870 return divider + fraction; 3871 } 3872 3873 static int pch_rawclk(struct intel_display *display) 3874 { 3875 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3876 } 3877 3878 static int i9xx_hrawclk(struct intel_display *display) 3879 { 3880 /* hrawclock is 1/4 the FSB frequency */ 3881 return DIV_ROUND_CLOSEST(intel_fsb_freq(display), 4); 3882 } 3883 3884 /** 3885 * intel_read_rawclk - Determine the current RAWCLK frequency 3886 * @display: display instance 3887 * 3888 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3889 * frequency clock so this needs to done only once. 3890 */ 3891 u32 intel_read_rawclk(struct intel_display *display) 3892 { 3893 u32 freq; 3894 3895 if (INTEL_PCH_TYPE(display) >= PCH_MTL) 3896 /* 3897 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3898 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3899 * not need to be programmed." 3900 */ 3901 freq = 38400; 3902 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 3903 freq = dg1_rawclk(display); 3904 else if (INTEL_PCH_TYPE(display) >= PCH_CNP) 3905 freq = cnp_rawclk(display); 3906 else if (HAS_PCH_SPLIT(display)) 3907 freq = pch_rawclk(display); 3908 else if (display->platform.valleyview || display->platform.cherryview) 3909 freq = vlv_clock_get_hrawclk(display->drm); 3910 else if (DISPLAY_VER(display) >= 3) 3911 freq = i9xx_hrawclk(display); 3912 else 3913 /* no rawclk on other platforms, or no need to know it */ 3914 return 0; 3915 3916 return freq; 3917 } 3918 3919 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3920 { 3921 struct intel_display *display = m->private; 3922 3923 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); 3924 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); 3925 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); 3926 3927 return 0; 3928 } 3929 3930 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3931 3932 void intel_cdclk_debugfs_register(struct intel_display *display) 3933 { 3934 debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root, 3935 display, &i915_cdclk_info_fops); 3936 } 3937 3938 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { 3939 .get_cdclk = bxt_get_cdclk, 3940 .set_cdclk = bxt_set_cdclk, 3941 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3942 .calc_voltage_level = xe3lpd_calc_voltage_level, 3943 }; 3944 3945 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3946 .get_cdclk = bxt_get_cdclk, 3947 .set_cdclk = bxt_set_cdclk, 3948 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3949 .calc_voltage_level = rplu_calc_voltage_level, 3950 }; 3951 3952 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3953 .get_cdclk = bxt_get_cdclk, 3954 .set_cdclk = bxt_set_cdclk, 3955 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3956 .calc_voltage_level = tgl_calc_voltage_level, 3957 }; 3958 3959 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3960 .get_cdclk = bxt_get_cdclk, 3961 .set_cdclk = bxt_set_cdclk, 3962 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3963 .calc_voltage_level = ehl_calc_voltage_level, 3964 }; 3965 3966 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3967 .get_cdclk = bxt_get_cdclk, 3968 .set_cdclk = bxt_set_cdclk, 3969 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3970 .calc_voltage_level = icl_calc_voltage_level, 3971 }; 3972 3973 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3974 .get_cdclk = bxt_get_cdclk, 3975 .set_cdclk = bxt_set_cdclk, 3976 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3977 .calc_voltage_level = bxt_calc_voltage_level, 3978 }; 3979 3980 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3981 .get_cdclk = skl_get_cdclk, 3982 .set_cdclk = skl_set_cdclk, 3983 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3984 }; 3985 3986 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3987 .get_cdclk = bdw_get_cdclk, 3988 .set_cdclk = bdw_set_cdclk, 3989 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3990 }; 3991 3992 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3993 .get_cdclk = vlv_get_cdclk, 3994 .set_cdclk = chv_set_cdclk, 3995 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3996 }; 3997 3998 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3999 .get_cdclk = vlv_get_cdclk, 4000 .set_cdclk = vlv_set_cdclk, 4001 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 4002 }; 4003 4004 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 4005 .get_cdclk = hsw_get_cdclk, 4006 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4007 }; 4008 4009 /* SNB, IVB, 965G, 945G */ 4010 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 4011 .get_cdclk = fixed_400mhz_get_cdclk, 4012 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4013 }; 4014 4015 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 4016 .get_cdclk = fixed_450mhz_get_cdclk, 4017 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4018 }; 4019 4020 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 4021 .get_cdclk = gm45_get_cdclk, 4022 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4023 }; 4024 4025 /* G45 uses G33 */ 4026 4027 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 4028 .get_cdclk = i965gm_get_cdclk, 4029 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4030 }; 4031 4032 /* i965G uses fixed 400 */ 4033 4034 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 4035 .get_cdclk = pnv_get_cdclk, 4036 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4037 }; 4038 4039 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 4040 .get_cdclk = g33_get_cdclk, 4041 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4042 }; 4043 4044 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 4045 .get_cdclk = i945gm_get_cdclk, 4046 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4047 }; 4048 4049 /* i945G uses fixed 400 */ 4050 4051 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 4052 .get_cdclk = i915gm_get_cdclk, 4053 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4054 }; 4055 4056 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 4057 .get_cdclk = fixed_333mhz_get_cdclk, 4058 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4059 }; 4060 4061 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 4062 .get_cdclk = fixed_266mhz_get_cdclk, 4063 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4064 }; 4065 4066 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 4067 .get_cdclk = i85x_get_cdclk, 4068 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4069 }; 4070 4071 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 4072 .get_cdclk = fixed_200mhz_get_cdclk, 4073 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4074 }; 4075 4076 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 4077 .get_cdclk = fixed_133mhz_get_cdclk, 4078 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 4079 }; 4080 4081 /** 4082 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 4083 * @display: display instance 4084 */ 4085 void intel_init_cdclk_hooks(struct intel_display *display) 4086 { 4087 if (DISPLAY_VER(display) >= 35) { 4088 display->cdclk.funcs = &xe3lpd_cdclk_funcs; 4089 display->cdclk.table = xe3p_lpd_cdclk_table; 4090 } else if (DISPLAY_VER(display) >= 30) { 4091 display->cdclk.funcs = &xe3lpd_cdclk_funcs; 4092 display->cdclk.table = xe3lpd_cdclk_table; 4093 } else if (DISPLAY_VER(display) >= 20) { 4094 display->cdclk.funcs = &rplu_cdclk_funcs; 4095 display->cdclk.table = xe2lpd_cdclk_table; 4096 } else if (DISPLAY_VERx100(display) >= 1401) { 4097 display->cdclk.funcs = &rplu_cdclk_funcs; 4098 display->cdclk.table = xe2hpd_cdclk_table; 4099 } else if (DISPLAY_VER(display) >= 14) { 4100 display->cdclk.funcs = &rplu_cdclk_funcs; 4101 display->cdclk.table = mtl_cdclk_table; 4102 } else if (display->platform.dg2) { 4103 display->cdclk.funcs = &tgl_cdclk_funcs; 4104 display->cdclk.table = dg2_cdclk_table; 4105 } else if (display->platform.alderlake_p) { 4106 /* Wa_22011320316:adl-p[a0] */ 4107 if (intel_display_wa(display, INTEL_DISPLAY_WA_22011320316)) { 4108 display->cdclk.table = adlp_a_step_cdclk_table; 4109 display->cdclk.funcs = &tgl_cdclk_funcs; 4110 } else if (display->platform.alderlake_p_raptorlake_u) { 4111 display->cdclk.table = rplu_cdclk_table; 4112 display->cdclk.funcs = &rplu_cdclk_funcs; 4113 } else { 4114 display->cdclk.table = adlp_cdclk_table; 4115 display->cdclk.funcs = &tgl_cdclk_funcs; 4116 } 4117 } else if (display->platform.rocketlake) { 4118 display->cdclk.funcs = &tgl_cdclk_funcs; 4119 display->cdclk.table = rkl_cdclk_table; 4120 } else if (DISPLAY_VER(display) >= 12) { 4121 display->cdclk.funcs = &tgl_cdclk_funcs; 4122 display->cdclk.table = icl_cdclk_table; 4123 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 4124 display->cdclk.funcs = &ehl_cdclk_funcs; 4125 display->cdclk.table = icl_cdclk_table; 4126 } else if (DISPLAY_VER(display) >= 11) { 4127 display->cdclk.funcs = &icl_cdclk_funcs; 4128 display->cdclk.table = icl_cdclk_table; 4129 } else if (display->platform.geminilake || display->platform.broxton) { 4130 display->cdclk.funcs = &bxt_cdclk_funcs; 4131 if (display->platform.geminilake) 4132 display->cdclk.table = glk_cdclk_table; 4133 else 4134 display->cdclk.table = bxt_cdclk_table; 4135 } else if (DISPLAY_VER(display) == 9) { 4136 display->cdclk.funcs = &skl_cdclk_funcs; 4137 } else if (display->platform.broadwell) { 4138 display->cdclk.funcs = &bdw_cdclk_funcs; 4139 } else if (display->platform.haswell) { 4140 display->cdclk.funcs = &hsw_cdclk_funcs; 4141 } else if (display->platform.cherryview) { 4142 display->cdclk.funcs = &chv_cdclk_funcs; 4143 } else if (display->platform.valleyview) { 4144 display->cdclk.funcs = &vlv_cdclk_funcs; 4145 } else if (display->platform.sandybridge || display->platform.ivybridge) { 4146 display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; 4147 } else if (display->platform.ironlake) { 4148 display->cdclk.funcs = &ilk_cdclk_funcs; 4149 } else if (display->platform.gm45) { 4150 display->cdclk.funcs = &gm45_cdclk_funcs; 4151 } else if (display->platform.g45) { 4152 display->cdclk.funcs = &g33_cdclk_funcs; 4153 } else if (display->platform.i965gm) { 4154 display->cdclk.funcs = &i965gm_cdclk_funcs; 4155 } else if (display->platform.i965g) { 4156 display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; 4157 } else if (display->platform.pineview) { 4158 display->cdclk.funcs = &pnv_cdclk_funcs; 4159 } else if (display->platform.g33) { 4160 display->cdclk.funcs = &g33_cdclk_funcs; 4161 } else if (display->platform.i945gm) { 4162 display->cdclk.funcs = &i945gm_cdclk_funcs; 4163 } else if (display->platform.i945g) { 4164 display->cdclk.funcs = &fixed_400mhz_cdclk_funcs; 4165 } else if (display->platform.i915gm) { 4166 display->cdclk.funcs = &i915gm_cdclk_funcs; 4167 } else if (display->platform.i915g) { 4168 display->cdclk.funcs = &i915g_cdclk_funcs; 4169 } else if (display->platform.i865g) { 4170 display->cdclk.funcs = &i865g_cdclk_funcs; 4171 } else if (display->platform.i85x) { 4172 display->cdclk.funcs = &i85x_cdclk_funcs; 4173 } else if (display->platform.i845g) { 4174 display->cdclk.funcs = &i845g_cdclk_funcs; 4175 } else if (display->platform.i830) { 4176 display->cdclk.funcs = &i830_cdclk_funcs; 4177 } 4178 4179 if (drm_WARN(display->drm, !display->cdclk.funcs, 4180 "Unknown platform. Assuming i830\n")) 4181 display->cdclk.funcs = &i830_cdclk_funcs; 4182 } 4183 4184 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state) 4185 { 4186 return cdclk_state->logical.cdclk; 4187 } 4188 4189 int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state) 4190 { 4191 return cdclk_state->actual.cdclk; 4192 } 4193 4194 int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state) 4195 { 4196 return cdclk_state->actual.voltage_level; 4197 } 4198 4199 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe) 4200 { 4201 return cdclk_state->min_cdclk[pipe]; 4202 } 4203 4204 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state) 4205 { 4206 const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state; 4207 4208 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 4209 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 4210 4211 if (new_cdclk_state && 4212 (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk || 4213 new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level)) 4214 return true; 4215 4216 return false; 4217 } 4218 4219 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk) 4220 { 4221 cdclk_state->force_min_cdclk = force_min_cdclk; 4222 } 4223 4224 void intel_cdclk_read_hw(struct intel_display *display) 4225 { 4226 struct intel_cdclk_state *cdclk_state; 4227 4228 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); 4229 4230 intel_update_cdclk(display); 4231 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 4232 cdclk_state->actual = display->cdclk.hw; 4233 cdclk_state->logical = display->cdclk.hw; 4234 } 4235 4236 static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk) 4237 { 4238 struct intel_display *display = to_intel_display(crtc_state); 4239 4240 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) { 4241 return bxt_calc_cdclk(display, min_cdclk); 4242 } else if (DISPLAY_VER(display) == 9) { 4243 int vco; 4244 4245 vco = display->cdclk.skl_preferred_vco_freq; 4246 if (vco == 0) 4247 vco = 8100000; 4248 4249 return skl_calc_cdclk(min_cdclk, vco); 4250 } else if (display->platform.broadwell) { 4251 return bdw_calc_cdclk(min_cdclk); 4252 } else if (display->platform.cherryview || display->platform.valleyview) { 4253 return vlv_calc_cdclk(display, min_cdclk); 4254 } else { 4255 return display->cdclk.max_cdclk_freq; 4256 } 4257 } 4258 4259 static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc_state, 4260 int clock, int min_cdclk) 4261 { 4262 struct intel_display *display = to_intel_display(crtc_state); 4263 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 4264 int cdclk = calc_cdclk(crtc_state, min_cdclk); 4265 4266 return min(0x10000, DIV_ROUND_UP_ULL((u64)clock << 16, ppc * cdclk)); 4267 } 4268 4269 unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) 4270 { 4271 /* FIXME use the actual min_cdclk for the pipe here */ 4272 return intel_cdclk_prefill_adjustment_worst(crtc_state); 4273 } 4274 4275 unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state) 4276 { 4277 int clock = crtc_state->hw.pipe_mode.crtc_clock; 4278 int min_cdclk; 4279 4280 /* 4281 * FIXME could perhaps consider a few more of the factors 4282 * that go the per-crtc min_cdclk. Namely anything that 4283 * only changes during full modesets. 4284 * 4285 * FIXME this assumes 1:1 scaling, but the other _worst() stuff 4286 * assumes max downscaling, so the final result will be 4287 * unrealistically bad. Figure out where the actual maximum value 4288 * lies and use that to compute a more realistic worst case 4289 * estimate... 4290 */ 4291 min_cdclk = _intel_pixel_rate_to_cdclk(crtc_state, clock); 4292 4293 return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk); 4294 } 4295 4296 int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state, 4297 unsigned int prefill_lines_unadjusted, 4298 unsigned int prefill_lines_available) 4299 { 4300 struct intel_display *display = to_intel_display(crtc_state); 4301 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 4302 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 4303 4304 return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted), 4305 ppc * prefill_lines_available); 4306 } 4307