1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/time.h> 25 26 #include "hsw_ips.h" 27 #include "i915_reg.h" 28 #include "intel_atomic.h" 29 #include "intel_atomic_plane.h" 30 #include "intel_audio.h" 31 #include "intel_bw.h" 32 #include "intel_cdclk.h" 33 #include "intel_crtc.h" 34 #include "intel_de.h" 35 #include "intel_dp.h" 36 #include "intel_display_types.h" 37 #include "intel_mchbar_regs.h" 38 #include "intel_pci_config.h" 39 #include "intel_pcode.h" 40 #include "intel_psr.h" 41 #include "intel_vdsc.h" 42 #include "vlv_sideband.h" 43 44 /** 45 * DOC: CDCLK / RAWCLK 46 * 47 * The display engine uses several different clocks to do its work. There 48 * are two main clocks involved that aren't directly related to the actual 49 * pixel clock or any symbol/bit clock of the actual output port. These 50 * are the core display clock (CDCLK) and RAWCLK. 51 * 52 * CDCLK clocks most of the display pipe logic, and thus its frequency 53 * must be high enough to support the rate at which pixels are flowing 54 * through the pipes. Downscaling must also be accounted as that increases 55 * the effective pixel rate. 56 * 57 * On several platforms the CDCLK frequency can be changed dynamically 58 * to minimize power consumption for a given display configuration. 59 * Typically changes to the CDCLK frequency require all the display pipes 60 * to be shut down while the frequency is being changed. 61 * 62 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 63 * DMC will not change the active CDCLK frequency however, so that part 64 * will still be performed by the driver directly. 65 * 66 * RAWCLK is a fixed frequency clock, often used by various auxiliary 67 * blocks such as AUX CH or backlight PWM. Hence the only thing we 68 * really need to know about RAWCLK is its frequency so that various 69 * dividers can be programmed correctly. 70 */ 71 72 struct intel_cdclk_funcs { 73 void (*get_cdclk)(struct drm_i915_private *i915, 74 struct intel_cdclk_config *cdclk_config); 75 void (*set_cdclk)(struct drm_i915_private *i915, 76 const struct intel_cdclk_config *cdclk_config, 77 enum pipe pipe); 78 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 79 u8 (*calc_voltage_level)(int cdclk); 80 }; 81 82 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, 83 struct intel_cdclk_config *cdclk_config) 84 { 85 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); 86 } 87 88 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, 89 const struct intel_cdclk_config *cdclk_config, 90 enum pipe pipe) 91 { 92 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); 93 } 94 95 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, 96 struct intel_cdclk_state *cdclk_config) 97 { 98 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); 99 } 100 101 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, 102 int cdclk) 103 { 104 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); 105 } 106 107 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 108 struct intel_cdclk_config *cdclk_config) 109 { 110 cdclk_config->cdclk = 133333; 111 } 112 113 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 114 struct intel_cdclk_config *cdclk_config) 115 { 116 cdclk_config->cdclk = 200000; 117 } 118 119 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 120 struct intel_cdclk_config *cdclk_config) 121 { 122 cdclk_config->cdclk = 266667; 123 } 124 125 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 126 struct intel_cdclk_config *cdclk_config) 127 { 128 cdclk_config->cdclk = 333333; 129 } 130 131 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 132 struct intel_cdclk_config *cdclk_config) 133 { 134 cdclk_config->cdclk = 400000; 135 } 136 137 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 138 struct intel_cdclk_config *cdclk_config) 139 { 140 cdclk_config->cdclk = 450000; 141 } 142 143 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 144 struct intel_cdclk_config *cdclk_config) 145 { 146 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 147 u16 hpllcc = 0; 148 149 /* 150 * 852GM/852GMV only supports 133 MHz and the HPLLCC 151 * encoding is different :( 152 * FIXME is this the right way to detect 852GM/852GMV? 153 */ 154 if (pdev->revision == 0x1) { 155 cdclk_config->cdclk = 133333; 156 return; 157 } 158 159 pci_bus_read_config_word(pdev->bus, 160 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 161 162 /* Assume that the hardware is in the high speed state. This 163 * should be the default. 164 */ 165 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 166 case GC_CLOCK_133_200: 167 case GC_CLOCK_133_200_2: 168 case GC_CLOCK_100_200: 169 cdclk_config->cdclk = 200000; 170 break; 171 case GC_CLOCK_166_250: 172 cdclk_config->cdclk = 250000; 173 break; 174 case GC_CLOCK_100_133: 175 cdclk_config->cdclk = 133333; 176 break; 177 case GC_CLOCK_133_266: 178 case GC_CLOCK_133_266_2: 179 case GC_CLOCK_166_266: 180 cdclk_config->cdclk = 266667; 181 break; 182 } 183 } 184 185 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 186 struct intel_cdclk_config *cdclk_config) 187 { 188 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 189 u16 gcfgc = 0; 190 191 pci_read_config_word(pdev, GCFGC, &gcfgc); 192 193 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 194 cdclk_config->cdclk = 133333; 195 return; 196 } 197 198 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 199 case GC_DISPLAY_CLOCK_333_320_MHZ: 200 cdclk_config->cdclk = 333333; 201 break; 202 default: 203 case GC_DISPLAY_CLOCK_190_200_MHZ: 204 cdclk_config->cdclk = 190000; 205 break; 206 } 207 } 208 209 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 210 struct intel_cdclk_config *cdclk_config) 211 { 212 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 213 u16 gcfgc = 0; 214 215 pci_read_config_word(pdev, GCFGC, &gcfgc); 216 217 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 218 cdclk_config->cdclk = 133333; 219 return; 220 } 221 222 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 223 case GC_DISPLAY_CLOCK_333_320_MHZ: 224 cdclk_config->cdclk = 320000; 225 break; 226 default: 227 case GC_DISPLAY_CLOCK_190_200_MHZ: 228 cdclk_config->cdclk = 200000; 229 break; 230 } 231 } 232 233 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 234 { 235 static const unsigned int blb_vco[8] = { 236 [0] = 3200000, 237 [1] = 4000000, 238 [2] = 5333333, 239 [3] = 4800000, 240 [4] = 6400000, 241 }; 242 static const unsigned int pnv_vco[8] = { 243 [0] = 3200000, 244 [1] = 4000000, 245 [2] = 5333333, 246 [3] = 4800000, 247 [4] = 2666667, 248 }; 249 static const unsigned int cl_vco[8] = { 250 [0] = 3200000, 251 [1] = 4000000, 252 [2] = 5333333, 253 [3] = 6400000, 254 [4] = 3333333, 255 [5] = 3566667, 256 [6] = 4266667, 257 }; 258 static const unsigned int elk_vco[8] = { 259 [0] = 3200000, 260 [1] = 4000000, 261 [2] = 5333333, 262 [3] = 4800000, 263 }; 264 static const unsigned int ctg_vco[8] = { 265 [0] = 3200000, 266 [1] = 4000000, 267 [2] = 5333333, 268 [3] = 6400000, 269 [4] = 2666667, 270 [5] = 4266667, 271 }; 272 const unsigned int *vco_table; 273 unsigned int vco; 274 u8 tmp = 0; 275 276 /* FIXME other chipsets? */ 277 if (IS_GM45(dev_priv)) 278 vco_table = ctg_vco; 279 else if (IS_G45(dev_priv)) 280 vco_table = elk_vco; 281 else if (IS_I965GM(dev_priv)) 282 vco_table = cl_vco; 283 else if (IS_PINEVIEW(dev_priv)) 284 vco_table = pnv_vco; 285 else if (IS_G33(dev_priv)) 286 vco_table = blb_vco; 287 else 288 return 0; 289 290 tmp = intel_de_read(dev_priv, 291 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 292 293 vco = vco_table[tmp & 0x7]; 294 if (vco == 0) 295 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 296 tmp); 297 else 298 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); 299 300 return vco; 301 } 302 303 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 304 struct intel_cdclk_config *cdclk_config) 305 { 306 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 307 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 308 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 309 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 310 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 311 const u8 *div_table; 312 unsigned int cdclk_sel; 313 u16 tmp = 0; 314 315 cdclk_config->vco = intel_hpll_vco(dev_priv); 316 317 pci_read_config_word(pdev, GCFGC, &tmp); 318 319 cdclk_sel = (tmp >> 4) & 0x7; 320 321 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 322 goto fail; 323 324 switch (cdclk_config->vco) { 325 case 3200000: 326 div_table = div_3200; 327 break; 328 case 4000000: 329 div_table = div_4000; 330 break; 331 case 4800000: 332 div_table = div_4800; 333 break; 334 case 5333333: 335 div_table = div_5333; 336 break; 337 default: 338 goto fail; 339 } 340 341 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 342 div_table[cdclk_sel]); 343 return; 344 345 fail: 346 drm_err(&dev_priv->drm, 347 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 348 cdclk_config->vco, tmp); 349 cdclk_config->cdclk = 190476; 350 } 351 352 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 353 struct intel_cdclk_config *cdclk_config) 354 { 355 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 356 u16 gcfgc = 0; 357 358 pci_read_config_word(pdev, GCFGC, &gcfgc); 359 360 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 361 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 362 cdclk_config->cdclk = 266667; 363 break; 364 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 365 cdclk_config->cdclk = 333333; 366 break; 367 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 368 cdclk_config->cdclk = 444444; 369 break; 370 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 371 cdclk_config->cdclk = 200000; 372 break; 373 default: 374 drm_err(&dev_priv->drm, 375 "Unknown pnv display core clock 0x%04x\n", gcfgc); 376 fallthrough; 377 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 378 cdclk_config->cdclk = 133333; 379 break; 380 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 381 cdclk_config->cdclk = 166667; 382 break; 383 } 384 } 385 386 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 387 struct intel_cdclk_config *cdclk_config) 388 { 389 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 390 static const u8 div_3200[] = { 16, 10, 8 }; 391 static const u8 div_4000[] = { 20, 12, 10 }; 392 static const u8 div_5333[] = { 24, 16, 14 }; 393 const u8 *div_table; 394 unsigned int cdclk_sel; 395 u16 tmp = 0; 396 397 cdclk_config->vco = intel_hpll_vco(dev_priv); 398 399 pci_read_config_word(pdev, GCFGC, &tmp); 400 401 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 402 403 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 404 goto fail; 405 406 switch (cdclk_config->vco) { 407 case 3200000: 408 div_table = div_3200; 409 break; 410 case 4000000: 411 div_table = div_4000; 412 break; 413 case 5333333: 414 div_table = div_5333; 415 break; 416 default: 417 goto fail; 418 } 419 420 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 421 div_table[cdclk_sel]); 422 return; 423 424 fail: 425 drm_err(&dev_priv->drm, 426 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 427 cdclk_config->vco, tmp); 428 cdclk_config->cdclk = 200000; 429 } 430 431 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 432 struct intel_cdclk_config *cdclk_config) 433 { 434 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 435 unsigned int cdclk_sel; 436 u16 tmp = 0; 437 438 cdclk_config->vco = intel_hpll_vco(dev_priv); 439 440 pci_read_config_word(pdev, GCFGC, &tmp); 441 442 cdclk_sel = (tmp >> 12) & 0x1; 443 444 switch (cdclk_config->vco) { 445 case 2666667: 446 case 4000000: 447 case 5333333: 448 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 449 break; 450 case 3200000: 451 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 452 break; 453 default: 454 drm_err(&dev_priv->drm, 455 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 456 cdclk_config->vco, tmp); 457 cdclk_config->cdclk = 222222; 458 break; 459 } 460 } 461 462 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 463 struct intel_cdclk_config *cdclk_config) 464 { 465 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 466 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 467 468 if (lcpll & LCPLL_CD_SOURCE_FCLK) 469 cdclk_config->cdclk = 800000; 470 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 471 cdclk_config->cdclk = 450000; 472 else if (freq == LCPLL_CLK_FREQ_450) 473 cdclk_config->cdclk = 450000; 474 else if (IS_HASWELL_ULT(dev_priv)) 475 cdclk_config->cdclk = 337500; 476 else 477 cdclk_config->cdclk = 540000; 478 } 479 480 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 481 { 482 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 483 333333 : 320000; 484 485 /* 486 * We seem to get an unstable or solid color picture at 200MHz. 487 * Not sure what's wrong. For now use 200MHz only when all pipes 488 * are off. 489 */ 490 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 491 return 400000; 492 else if (min_cdclk > 266667) 493 return freq_320; 494 else if (min_cdclk > 0) 495 return 266667; 496 else 497 return 200000; 498 } 499 500 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 501 { 502 if (IS_VALLEYVIEW(dev_priv)) { 503 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 504 return 2; 505 else if (cdclk >= 266667) 506 return 1; 507 else 508 return 0; 509 } else { 510 /* 511 * Specs are full of misinformation, but testing on actual 512 * hardware has shown that we just need to write the desired 513 * CCK divider into the Punit register. 514 */ 515 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 516 } 517 } 518 519 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 520 struct intel_cdclk_config *cdclk_config) 521 { 522 u32 val; 523 524 vlv_iosf_sb_get(dev_priv, 525 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 526 527 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 528 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 529 CCK_DISPLAY_CLOCK_CONTROL, 530 cdclk_config->vco); 531 532 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 533 534 vlv_iosf_sb_put(dev_priv, 535 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 536 537 if (IS_VALLEYVIEW(dev_priv)) 538 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 539 DSPFREQGUAR_SHIFT; 540 else 541 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 542 DSPFREQGUAR_SHIFT_CHV; 543 } 544 545 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 546 { 547 unsigned int credits, default_credits; 548 549 if (IS_CHERRYVIEW(dev_priv)) 550 default_credits = PFI_CREDIT(12); 551 else 552 default_credits = PFI_CREDIT(8); 553 554 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { 555 /* CHV suggested value is 31 or 63 */ 556 if (IS_CHERRYVIEW(dev_priv)) 557 credits = PFI_CREDIT_63; 558 else 559 credits = PFI_CREDIT(15); 560 } else { 561 credits = default_credits; 562 } 563 564 /* 565 * WA - write default credits before re-programming 566 * FIXME: should we also set the resend bit here? 567 */ 568 intel_de_write(dev_priv, GCI_CONTROL, 569 VGA_FAST_MODE_DISABLE | default_credits); 570 571 intel_de_write(dev_priv, GCI_CONTROL, 572 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 573 574 /* 575 * FIXME is this guaranteed to clear 576 * immediately or should we poll for it? 577 */ 578 drm_WARN_ON(&dev_priv->drm, 579 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); 580 } 581 582 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 583 const struct intel_cdclk_config *cdclk_config, 584 enum pipe pipe) 585 { 586 int cdclk = cdclk_config->cdclk; 587 u32 val, cmd = cdclk_config->voltage_level; 588 intel_wakeref_t wakeref; 589 590 switch (cdclk) { 591 case 400000: 592 case 333333: 593 case 320000: 594 case 266667: 595 case 200000: 596 break; 597 default: 598 MISSING_CASE(cdclk); 599 return; 600 } 601 602 /* There are cases where we can end up here with power domains 603 * off and a CDCLK frequency other than the minimum, like when 604 * issuing a modeset without actually changing any display after 605 * a system suspend. So grab the display core domain, which covers 606 * the HW blocks needed for the following programming. 607 */ 608 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 609 610 vlv_iosf_sb_get(dev_priv, 611 BIT(VLV_IOSF_SB_CCK) | 612 BIT(VLV_IOSF_SB_BUNIT) | 613 BIT(VLV_IOSF_SB_PUNIT)); 614 615 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 616 val &= ~DSPFREQGUAR_MASK; 617 val |= (cmd << DSPFREQGUAR_SHIFT); 618 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 619 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 620 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 621 50)) { 622 drm_err(&dev_priv->drm, 623 "timed out waiting for CDclk change\n"); 624 } 625 626 if (cdclk == 400000) { 627 u32 divider; 628 629 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 630 cdclk) - 1; 631 632 /* adjust cdclk divider */ 633 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 634 val &= ~CCK_FREQUENCY_VALUES; 635 val |= divider; 636 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 637 638 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 639 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 640 50)) 641 drm_err(&dev_priv->drm, 642 "timed out waiting for CDclk change\n"); 643 } 644 645 /* adjust self-refresh exit latency value */ 646 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 647 val &= ~0x7f; 648 649 /* 650 * For high bandwidth configs, we set a higher latency in the bunit 651 * so that the core display fetch happens in time to avoid underruns. 652 */ 653 if (cdclk == 400000) 654 val |= 4500 / 250; /* 4.5 usec */ 655 else 656 val |= 3000 / 250; /* 3.0 usec */ 657 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 658 659 vlv_iosf_sb_put(dev_priv, 660 BIT(VLV_IOSF_SB_CCK) | 661 BIT(VLV_IOSF_SB_BUNIT) | 662 BIT(VLV_IOSF_SB_PUNIT)); 663 664 intel_update_cdclk(dev_priv); 665 666 vlv_program_pfi_credits(dev_priv); 667 668 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 669 } 670 671 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 672 const struct intel_cdclk_config *cdclk_config, 673 enum pipe pipe) 674 { 675 int cdclk = cdclk_config->cdclk; 676 u32 val, cmd = cdclk_config->voltage_level; 677 intel_wakeref_t wakeref; 678 679 switch (cdclk) { 680 case 333333: 681 case 320000: 682 case 266667: 683 case 200000: 684 break; 685 default: 686 MISSING_CASE(cdclk); 687 return; 688 } 689 690 /* There are cases where we can end up here with power domains 691 * off and a CDCLK frequency other than the minimum, like when 692 * issuing a modeset without actually changing any display after 693 * a system suspend. So grab the display core domain, which covers 694 * the HW blocks needed for the following programming. 695 */ 696 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 697 698 vlv_punit_get(dev_priv); 699 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 700 val &= ~DSPFREQGUAR_MASK_CHV; 701 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 702 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 703 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 704 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 705 50)) { 706 drm_err(&dev_priv->drm, 707 "timed out waiting for CDclk change\n"); 708 } 709 710 vlv_punit_put(dev_priv); 711 712 intel_update_cdclk(dev_priv); 713 714 vlv_program_pfi_credits(dev_priv); 715 716 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 717 } 718 719 static int bdw_calc_cdclk(int min_cdclk) 720 { 721 if (min_cdclk > 540000) 722 return 675000; 723 else if (min_cdclk > 450000) 724 return 540000; 725 else if (min_cdclk > 337500) 726 return 450000; 727 else 728 return 337500; 729 } 730 731 static u8 bdw_calc_voltage_level(int cdclk) 732 { 733 switch (cdclk) { 734 default: 735 case 337500: 736 return 2; 737 case 450000: 738 return 0; 739 case 540000: 740 return 1; 741 case 675000: 742 return 3; 743 } 744 } 745 746 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 747 struct intel_cdclk_config *cdclk_config) 748 { 749 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 750 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 751 752 if (lcpll & LCPLL_CD_SOURCE_FCLK) 753 cdclk_config->cdclk = 800000; 754 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 755 cdclk_config->cdclk = 450000; 756 else if (freq == LCPLL_CLK_FREQ_450) 757 cdclk_config->cdclk = 450000; 758 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 759 cdclk_config->cdclk = 540000; 760 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 761 cdclk_config->cdclk = 337500; 762 else 763 cdclk_config->cdclk = 675000; 764 765 /* 766 * Can't read this out :( Let's assume it's 767 * at least what the CDCLK frequency requires. 768 */ 769 cdclk_config->voltage_level = 770 bdw_calc_voltage_level(cdclk_config->cdclk); 771 } 772 773 static u32 bdw_cdclk_freq_sel(int cdclk) 774 { 775 switch (cdclk) { 776 default: 777 MISSING_CASE(cdclk); 778 fallthrough; 779 case 337500: 780 return LCPLL_CLK_FREQ_337_5_BDW; 781 case 450000: 782 return LCPLL_CLK_FREQ_450; 783 case 540000: 784 return LCPLL_CLK_FREQ_54O_BDW; 785 case 675000: 786 return LCPLL_CLK_FREQ_675_BDW; 787 } 788 } 789 790 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 791 const struct intel_cdclk_config *cdclk_config, 792 enum pipe pipe) 793 { 794 int cdclk = cdclk_config->cdclk; 795 int ret; 796 797 if (drm_WARN(&dev_priv->drm, 798 (intel_de_read(dev_priv, LCPLL_CTL) & 799 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 800 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 801 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 802 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 803 "trying to change cdclk frequency with cdclk not enabled\n")) 804 return; 805 806 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 807 if (ret) { 808 drm_err(&dev_priv->drm, 809 "failed to inform pcode about cdclk change\n"); 810 return; 811 } 812 813 intel_de_rmw(dev_priv, LCPLL_CTL, 814 0, LCPLL_CD_SOURCE_FCLK); 815 816 /* 817 * According to the spec, it should be enough to poll for this 1 us. 818 * However, extensive testing shows that this can take longer. 819 */ 820 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 821 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 822 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 823 824 intel_de_rmw(dev_priv, LCPLL_CTL, 825 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 826 827 intel_de_rmw(dev_priv, LCPLL_CTL, 828 LCPLL_CD_SOURCE_FCLK, 0); 829 830 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 831 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 832 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); 833 834 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, 835 cdclk_config->voltage_level); 836 837 intel_de_write(dev_priv, CDCLK_FREQ, 838 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 839 840 intel_update_cdclk(dev_priv); 841 } 842 843 static int skl_calc_cdclk(int min_cdclk, int vco) 844 { 845 if (vco == 8640000) { 846 if (min_cdclk > 540000) 847 return 617143; 848 else if (min_cdclk > 432000) 849 return 540000; 850 else if (min_cdclk > 308571) 851 return 432000; 852 else 853 return 308571; 854 } else { 855 if (min_cdclk > 540000) 856 return 675000; 857 else if (min_cdclk > 450000) 858 return 540000; 859 else if (min_cdclk > 337500) 860 return 450000; 861 else 862 return 337500; 863 } 864 } 865 866 static u8 skl_calc_voltage_level(int cdclk) 867 { 868 if (cdclk > 540000) 869 return 3; 870 else if (cdclk > 450000) 871 return 2; 872 else if (cdclk > 337500) 873 return 1; 874 else 875 return 0; 876 } 877 878 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 879 struct intel_cdclk_config *cdclk_config) 880 { 881 u32 val; 882 883 cdclk_config->ref = 24000; 884 cdclk_config->vco = 0; 885 886 val = intel_de_read(dev_priv, LCPLL1_CTL); 887 if ((val & LCPLL_PLL_ENABLE) == 0) 888 return; 889 890 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) 891 return; 892 893 val = intel_de_read(dev_priv, DPLL_CTRL1); 894 895 if (drm_WARN_ON(&dev_priv->drm, 896 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 897 DPLL_CTRL1_SSC(SKL_DPLL0) | 898 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 899 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 900 return; 901 902 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 903 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 904 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 905 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 906 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 907 cdclk_config->vco = 8100000; 908 break; 909 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 910 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 911 cdclk_config->vco = 8640000; 912 break; 913 default: 914 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 915 break; 916 } 917 } 918 919 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 920 struct intel_cdclk_config *cdclk_config) 921 { 922 u32 cdctl; 923 924 skl_dpll0_update(dev_priv, cdclk_config); 925 926 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 927 928 if (cdclk_config->vco == 0) 929 goto out; 930 931 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 932 933 if (cdclk_config->vco == 8640000) { 934 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 935 case CDCLK_FREQ_450_432: 936 cdclk_config->cdclk = 432000; 937 break; 938 case CDCLK_FREQ_337_308: 939 cdclk_config->cdclk = 308571; 940 break; 941 case CDCLK_FREQ_540: 942 cdclk_config->cdclk = 540000; 943 break; 944 case CDCLK_FREQ_675_617: 945 cdclk_config->cdclk = 617143; 946 break; 947 default: 948 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 949 break; 950 } 951 } else { 952 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 953 case CDCLK_FREQ_450_432: 954 cdclk_config->cdclk = 450000; 955 break; 956 case CDCLK_FREQ_337_308: 957 cdclk_config->cdclk = 337500; 958 break; 959 case CDCLK_FREQ_540: 960 cdclk_config->cdclk = 540000; 961 break; 962 case CDCLK_FREQ_675_617: 963 cdclk_config->cdclk = 675000; 964 break; 965 default: 966 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 967 break; 968 } 969 } 970 971 out: 972 /* 973 * Can't read this out :( Let's assume it's 974 * at least what the CDCLK frequency requires. 975 */ 976 cdclk_config->voltage_level = 977 skl_calc_voltage_level(cdclk_config->cdclk); 978 } 979 980 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 981 static int skl_cdclk_decimal(int cdclk) 982 { 983 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 984 } 985 986 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 987 int vco) 988 { 989 bool changed = dev_priv->skl_preferred_vco_freq != vco; 990 991 dev_priv->skl_preferred_vco_freq = vco; 992 993 if (changed) 994 intel_update_max_cdclk(dev_priv); 995 } 996 997 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) 998 { 999 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 1000 1001 /* 1002 * We always enable DPLL0 with the lowest link rate possible, but still 1003 * taking into account the VCO required to operate the eDP panel at the 1004 * desired frequency. The usual DP link rates operate with a VCO of 1005 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1006 * The modeset code is responsible for the selection of the exact link 1007 * rate later on, with the constraint of choosing a frequency that 1008 * works with vco. 1009 */ 1010 if (vco == 8640000) 1011 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1012 else 1013 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1014 } 1015 1016 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 1017 { 1018 intel_de_rmw(dev_priv, DPLL_CTRL1, 1019 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1020 DPLL_CTRL1_SSC(SKL_DPLL0) | 1021 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1022 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1023 skl_dpll0_link_rate(dev_priv, vco)); 1024 intel_de_posting_read(dev_priv, DPLL_CTRL1); 1025 1026 intel_de_rmw(dev_priv, LCPLL1_CTL, 1027 0, LCPLL_PLL_ENABLE); 1028 1029 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1030 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); 1031 1032 dev_priv->display.cdclk.hw.vco = vco; 1033 1034 /* We'll want to keep using the current vco from now on. */ 1035 skl_set_preferred_cdclk_vco(dev_priv, vco); 1036 } 1037 1038 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 1039 { 1040 intel_de_rmw(dev_priv, LCPLL1_CTL, 1041 LCPLL_PLL_ENABLE, 0); 1042 1043 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1044 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); 1045 1046 dev_priv->display.cdclk.hw.vco = 0; 1047 } 1048 1049 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, 1050 int cdclk, int vco) 1051 { 1052 switch (cdclk) { 1053 default: 1054 drm_WARN_ON(&dev_priv->drm, 1055 cdclk != dev_priv->display.cdclk.hw.bypass); 1056 drm_WARN_ON(&dev_priv->drm, vco != 0); 1057 fallthrough; 1058 case 308571: 1059 case 337500: 1060 return CDCLK_FREQ_337_308; 1061 case 450000: 1062 case 432000: 1063 return CDCLK_FREQ_450_432; 1064 case 540000: 1065 return CDCLK_FREQ_540; 1066 case 617143: 1067 case 675000: 1068 return CDCLK_FREQ_675_617; 1069 } 1070 } 1071 1072 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 1073 const struct intel_cdclk_config *cdclk_config, 1074 enum pipe pipe) 1075 { 1076 int cdclk = cdclk_config->cdclk; 1077 int vco = cdclk_config->vco; 1078 u32 freq_select, cdclk_ctl; 1079 int ret; 1080 1081 /* 1082 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1083 * unsupported on SKL. In theory this should never happen since only 1084 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1085 * supported on SKL either, see the above WA. WARN whenever trying to 1086 * use the corresponding VCO freq as that always leads to using the 1087 * minimum 308MHz CDCLK. 1088 */ 1089 drm_WARN_ON_ONCE(&dev_priv->drm, 1090 IS_SKYLAKE(dev_priv) && vco == 8640000); 1091 1092 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1093 SKL_CDCLK_PREPARE_FOR_CHANGE, 1094 SKL_CDCLK_READY_FOR_CHANGE, 1095 SKL_CDCLK_READY_FOR_CHANGE, 3); 1096 if (ret) { 1097 drm_err(&dev_priv->drm, 1098 "Failed to inform PCU about cdclk change (%d)\n", ret); 1099 return; 1100 } 1101 1102 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); 1103 1104 if (dev_priv->display.cdclk.hw.vco != 0 && 1105 dev_priv->display.cdclk.hw.vco != vco) 1106 skl_dpll0_disable(dev_priv); 1107 1108 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); 1109 1110 if (dev_priv->display.cdclk.hw.vco != vco) { 1111 /* Wa Display #1183: skl,kbl,cfl */ 1112 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1113 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1114 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1115 } 1116 1117 /* Wa Display #1183: skl,kbl,cfl */ 1118 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1119 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1120 intel_de_posting_read(dev_priv, CDCLK_CTL); 1121 1122 if (dev_priv->display.cdclk.hw.vco != vco) 1123 skl_dpll0_enable(dev_priv, vco); 1124 1125 /* Wa Display #1183: skl,kbl,cfl */ 1126 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1127 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1128 1129 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1130 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1131 1132 /* Wa Display #1183: skl,kbl,cfl */ 1133 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1134 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1135 intel_de_posting_read(dev_priv, CDCLK_CTL); 1136 1137 /* inform PCU of the change */ 1138 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1139 cdclk_config->voltage_level); 1140 1141 intel_update_cdclk(dev_priv); 1142 } 1143 1144 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1145 { 1146 u32 cdctl, expected; 1147 1148 /* 1149 * check if the pre-os initialized the display 1150 * There is SWF18 scratchpad register defined which is set by the 1151 * pre-os which can be used by the OS drivers to check the status 1152 */ 1153 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1154 goto sanitize; 1155 1156 intel_update_cdclk(dev_priv); 1157 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1158 1159 /* Is PLL enabled and locked ? */ 1160 if (dev_priv->display.cdclk.hw.vco == 0 || 1161 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 1162 goto sanitize; 1163 1164 /* DPLL okay; verify the cdclock 1165 * 1166 * Noticed in some instances that the freq selection is correct but 1167 * decimal part is programmed wrong from BIOS where pre-os does not 1168 * enable display. Verify the same as well. 1169 */ 1170 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1171 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1172 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); 1173 if (cdctl == expected) 1174 /* All well; nothing to sanitize */ 1175 return; 1176 1177 sanitize: 1178 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1179 1180 /* force cdclk programming */ 1181 dev_priv->display.cdclk.hw.cdclk = 0; 1182 /* force full PLL disable + enable */ 1183 dev_priv->display.cdclk.hw.vco = ~0; 1184 } 1185 1186 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) 1187 { 1188 struct intel_cdclk_config cdclk_config; 1189 1190 skl_sanitize_cdclk(dev_priv); 1191 1192 if (dev_priv->display.cdclk.hw.cdclk != 0 && 1193 dev_priv->display.cdclk.hw.vco != 0) { 1194 /* 1195 * Use the current vco as our initial 1196 * guess as to what the preferred vco is. 1197 */ 1198 if (dev_priv->skl_preferred_vco_freq == 0) 1199 skl_set_preferred_cdclk_vco(dev_priv, 1200 dev_priv->display.cdclk.hw.vco); 1201 return; 1202 } 1203 1204 cdclk_config = dev_priv->display.cdclk.hw; 1205 1206 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; 1207 if (cdclk_config.vco == 0) 1208 cdclk_config.vco = 8100000; 1209 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1210 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1211 1212 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1213 } 1214 1215 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1216 { 1217 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 1218 1219 cdclk_config.cdclk = cdclk_config.bypass; 1220 cdclk_config.vco = 0; 1221 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1222 1223 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1224 } 1225 1226 struct intel_cdclk_vals { 1227 u32 cdclk; 1228 u16 refclk; 1229 u16 waveform; 1230 u8 ratio; 1231 }; 1232 1233 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1234 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1235 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1236 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1237 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1238 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1239 {} 1240 }; 1241 1242 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1243 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1244 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1245 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1246 {} 1247 }; 1248 1249 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1250 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1251 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1252 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1253 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1254 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1255 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1256 1257 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1258 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1259 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1260 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1261 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1262 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1263 1264 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1265 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1266 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1267 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1268 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1269 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1270 {} 1271 }; 1272 1273 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1274 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1275 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1276 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1277 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1278 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1279 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1280 1281 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1282 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1283 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1284 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1285 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1286 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1287 1288 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1289 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1290 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1291 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1292 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1293 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1294 {} 1295 }; 1296 1297 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1298 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1299 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1300 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1301 1302 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1303 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1304 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1305 1306 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1307 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1308 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1309 {} 1310 }; 1311 1312 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1313 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1314 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1315 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1316 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1317 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1318 1319 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1320 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1321 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1322 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1323 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1324 1325 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1326 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1327 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1328 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1329 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1330 {} 1331 }; 1332 1333 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1334 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1335 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1336 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1337 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1338 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1339 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1340 1341 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1342 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1343 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1344 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1345 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1346 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1347 1348 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1349 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1350 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1351 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1352 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1353 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1354 {} 1355 }; 1356 1357 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1358 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1359 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1360 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1361 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1362 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1363 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1364 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1365 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1366 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1367 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1368 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1369 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1370 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1371 {} 1372 }; 1373 1374 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1375 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1376 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1377 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1378 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1379 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1380 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1381 {} 1382 }; 1383 1384 static const struct intel_cdclk_vals lnl_cdclk_table[] = { 1385 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1386 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1387 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1388 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1389 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1390 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1391 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1392 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1393 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1394 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1395 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1396 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1397 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1398 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1399 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1400 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1401 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1402 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1403 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1404 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1405 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1406 {} 1407 }; 1408 1409 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 1410 { 1411 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1412 int i; 1413 1414 for (i = 0; table[i].refclk; i++) 1415 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1416 table[i].cdclk >= min_cdclk) 1417 return table[i].cdclk; 1418 1419 drm_WARN(&dev_priv->drm, 1, 1420 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1421 min_cdclk, dev_priv->display.cdclk.hw.ref); 1422 return 0; 1423 } 1424 1425 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1426 { 1427 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1428 int i; 1429 1430 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1431 return 0; 1432 1433 for (i = 0; table[i].refclk; i++) 1434 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1435 table[i].cdclk == cdclk) 1436 return dev_priv->display.cdclk.hw.ref * table[i].ratio; 1437 1438 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1439 cdclk, dev_priv->display.cdclk.hw.ref); 1440 return 0; 1441 } 1442 1443 static u8 bxt_calc_voltage_level(int cdclk) 1444 { 1445 return DIV_ROUND_UP(cdclk, 25000); 1446 } 1447 1448 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1449 const int voltage_level_max_cdclk[]) 1450 { 1451 int voltage_level; 1452 1453 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1454 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1455 return voltage_level; 1456 } 1457 1458 MISSING_CASE(cdclk); 1459 return num_voltage_levels - 1; 1460 } 1461 1462 static u8 icl_calc_voltage_level(int cdclk) 1463 { 1464 static const int icl_voltage_level_max_cdclk[] = { 1465 [0] = 312000, 1466 [1] = 556800, 1467 [2] = 652800, 1468 }; 1469 1470 return calc_voltage_level(cdclk, 1471 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1472 icl_voltage_level_max_cdclk); 1473 } 1474 1475 static u8 ehl_calc_voltage_level(int cdclk) 1476 { 1477 static const int ehl_voltage_level_max_cdclk[] = { 1478 [0] = 180000, 1479 [1] = 312000, 1480 [2] = 326400, 1481 /* 1482 * Bspec lists the limit as 556.8 MHz, but some JSL 1483 * development boards (at least) boot with 652.8 MHz 1484 */ 1485 [3] = 652800, 1486 }; 1487 1488 return calc_voltage_level(cdclk, 1489 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1490 ehl_voltage_level_max_cdclk); 1491 } 1492 1493 static u8 tgl_calc_voltage_level(int cdclk) 1494 { 1495 static const int tgl_voltage_level_max_cdclk[] = { 1496 [0] = 312000, 1497 [1] = 326400, 1498 [2] = 556800, 1499 [3] = 652800, 1500 }; 1501 1502 return calc_voltage_level(cdclk, 1503 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1504 tgl_voltage_level_max_cdclk); 1505 } 1506 1507 static u8 rplu_calc_voltage_level(int cdclk) 1508 { 1509 static const int rplu_voltage_level_max_cdclk[] = { 1510 [0] = 312000, 1511 [1] = 480000, 1512 [2] = 556800, 1513 [3] = 652800, 1514 }; 1515 1516 return calc_voltage_level(cdclk, 1517 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1518 rplu_voltage_level_max_cdclk); 1519 } 1520 1521 static void icl_readout_refclk(struct drm_i915_private *dev_priv, 1522 struct intel_cdclk_config *cdclk_config) 1523 { 1524 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1525 1526 switch (dssm) { 1527 default: 1528 MISSING_CASE(dssm); 1529 fallthrough; 1530 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1531 cdclk_config->ref = 24000; 1532 break; 1533 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1534 cdclk_config->ref = 19200; 1535 break; 1536 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1537 cdclk_config->ref = 38400; 1538 break; 1539 } 1540 } 1541 1542 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 1543 struct intel_cdclk_config *cdclk_config) 1544 { 1545 u32 val, ratio; 1546 1547 if (IS_DG2(dev_priv)) 1548 cdclk_config->ref = 38400; 1549 else if (DISPLAY_VER(dev_priv) >= 11) 1550 icl_readout_refclk(dev_priv, cdclk_config); 1551 else 1552 cdclk_config->ref = 19200; 1553 1554 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1555 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1556 (val & BXT_DE_PLL_LOCK) == 0) { 1557 /* 1558 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1559 * setting it to zero is a way to signal that. 1560 */ 1561 cdclk_config->vco = 0; 1562 return; 1563 } 1564 1565 /* 1566 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1567 * gen9lp had it in a separate PLL control register. 1568 */ 1569 if (DISPLAY_VER(dev_priv) >= 11) 1570 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1571 else 1572 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1573 1574 cdclk_config->vco = ratio * cdclk_config->ref; 1575 } 1576 1577 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1578 struct intel_cdclk_config *cdclk_config) 1579 { 1580 u32 squash_ctl = 0; 1581 u32 divider; 1582 int div; 1583 1584 bxt_de_pll_readout(dev_priv, cdclk_config); 1585 1586 if (DISPLAY_VER(dev_priv) >= 12) 1587 cdclk_config->bypass = cdclk_config->ref / 2; 1588 else if (DISPLAY_VER(dev_priv) >= 11) 1589 cdclk_config->bypass = 50000; 1590 else 1591 cdclk_config->bypass = cdclk_config->ref; 1592 1593 if (cdclk_config->vco == 0) { 1594 cdclk_config->cdclk = cdclk_config->bypass; 1595 goto out; 1596 } 1597 1598 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1599 1600 switch (divider) { 1601 case BXT_CDCLK_CD2X_DIV_SEL_1: 1602 div = 2; 1603 break; 1604 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1605 div = 3; 1606 break; 1607 case BXT_CDCLK_CD2X_DIV_SEL_2: 1608 div = 4; 1609 break; 1610 case BXT_CDCLK_CD2X_DIV_SEL_4: 1611 div = 8; 1612 break; 1613 default: 1614 MISSING_CASE(divider); 1615 return; 1616 } 1617 1618 if (HAS_CDCLK_SQUASH(dev_priv)) 1619 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); 1620 1621 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1622 u16 waveform; 1623 int size; 1624 1625 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1626 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1627 1628 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1629 cdclk_config->vco, size * div); 1630 } else { 1631 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1632 } 1633 1634 out: 1635 /* 1636 * Can't read this out :( Let's assume it's 1637 * at least what the CDCLK frequency requires. 1638 */ 1639 cdclk_config->voltage_level = 1640 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); 1641 } 1642 1643 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1644 { 1645 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1646 1647 /* Timeout 200us */ 1648 if (intel_de_wait_for_clear(dev_priv, 1649 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1650 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); 1651 1652 dev_priv->display.cdclk.hw.vco = 0; 1653 } 1654 1655 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1656 { 1657 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1658 1659 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, 1660 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1661 1662 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1663 1664 /* Timeout 200us */ 1665 if (intel_de_wait_for_set(dev_priv, 1666 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1667 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); 1668 1669 dev_priv->display.cdclk.hw.vco = vco; 1670 } 1671 1672 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1673 { 1674 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, 1675 BXT_DE_PLL_PLL_ENABLE, 0); 1676 1677 /* Timeout 200us */ 1678 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1679 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); 1680 1681 dev_priv->display.cdclk.hw.vco = 0; 1682 } 1683 1684 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1685 { 1686 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1687 u32 val; 1688 1689 val = ICL_CDCLK_PLL_RATIO(ratio); 1690 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1691 1692 val |= BXT_DE_PLL_PLL_ENABLE; 1693 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1694 1695 /* Timeout 200us */ 1696 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1697 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); 1698 1699 dev_priv->display.cdclk.hw.vco = vco; 1700 } 1701 1702 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) 1703 { 1704 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1705 u32 val; 1706 1707 /* Write PLL ratio without disabling */ 1708 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1709 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1710 1711 /* Submit freq change request */ 1712 val |= BXT_DE_PLL_FREQ_REQ; 1713 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1714 1715 /* Timeout 200us */ 1716 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, 1717 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1718 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); 1719 1720 val &= ~BXT_DE_PLL_FREQ_REQ; 1721 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1722 1723 dev_priv->display.cdclk.hw.vco = vco; 1724 } 1725 1726 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1727 { 1728 if (DISPLAY_VER(dev_priv) >= 12) { 1729 if (pipe == INVALID_PIPE) 1730 return TGL_CDCLK_CD2X_PIPE_NONE; 1731 else 1732 return TGL_CDCLK_CD2X_PIPE(pipe); 1733 } else if (DISPLAY_VER(dev_priv) >= 11) { 1734 if (pipe == INVALID_PIPE) 1735 return ICL_CDCLK_CD2X_PIPE_NONE; 1736 else 1737 return ICL_CDCLK_CD2X_PIPE(pipe); 1738 } else { 1739 if (pipe == INVALID_PIPE) 1740 return BXT_CDCLK_CD2X_PIPE_NONE; 1741 else 1742 return BXT_CDCLK_CD2X_PIPE(pipe); 1743 } 1744 } 1745 1746 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, 1747 int cdclk, int vco) 1748 { 1749 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1750 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1751 default: 1752 drm_WARN_ON(&dev_priv->drm, 1753 cdclk != dev_priv->display.cdclk.hw.bypass); 1754 drm_WARN_ON(&dev_priv->drm, vco != 0); 1755 fallthrough; 1756 case 2: 1757 return BXT_CDCLK_CD2X_DIV_SEL_1; 1758 case 3: 1759 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1760 case 4: 1761 return BXT_CDCLK_CD2X_DIV_SEL_2; 1762 case 8: 1763 return BXT_CDCLK_CD2X_DIV_SEL_4; 1764 } 1765 } 1766 1767 static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, 1768 int cdclk) 1769 { 1770 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1771 int i; 1772 1773 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1774 return 0; 1775 1776 for (i = 0; table[i].refclk; i++) 1777 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1778 table[i].cdclk == cdclk) 1779 return table[i].waveform; 1780 1781 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1782 cdclk, dev_priv->display.cdclk.hw.ref); 1783 1784 return 0xffff; 1785 } 1786 1787 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1788 { 1789 if (i915->display.cdclk.hw.vco != 0 && 1790 i915->display.cdclk.hw.vco != vco) 1791 icl_cdclk_pll_disable(i915); 1792 1793 if (i915->display.cdclk.hw.vco != vco) 1794 icl_cdclk_pll_enable(i915, vco); 1795 } 1796 1797 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1798 { 1799 if (i915->display.cdclk.hw.vco != 0 && 1800 i915->display.cdclk.hw.vco != vco) 1801 bxt_de_pll_disable(i915); 1802 1803 if (i915->display.cdclk.hw.vco != vco) 1804 bxt_de_pll_enable(i915, vco); 1805 } 1806 1807 static void dg2_cdclk_squash_program(struct drm_i915_private *i915, 1808 u16 waveform) 1809 { 1810 u32 squash_ctl = 0; 1811 1812 if (waveform) 1813 squash_ctl = CDCLK_SQUASH_ENABLE | 1814 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1815 1816 intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); 1817 } 1818 1819 static bool cdclk_pll_is_unknown(unsigned int vco) 1820 { 1821 /* 1822 * Ensure driver does not take the crawl path for the 1823 * case when the vco is set to ~0 in the 1824 * sanitize path. 1825 */ 1826 return vco == ~0; 1827 } 1828 1829 static const int cdclk_squash_len = 16; 1830 1831 static int cdclk_squash_divider(u16 waveform) 1832 { 1833 return hweight16(waveform ?: 0xffff); 1834 } 1835 1836 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915, 1837 const struct intel_cdclk_config *old_cdclk_config, 1838 const struct intel_cdclk_config *new_cdclk_config, 1839 struct intel_cdclk_config *mid_cdclk_config) 1840 { 1841 u16 old_waveform, new_waveform, mid_waveform; 1842 int div = 2; 1843 1844 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 1845 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 1846 return false; 1847 1848 /* Return if both Squash and Crawl are not present */ 1849 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) 1850 return false; 1851 1852 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); 1853 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); 1854 1855 /* Return if Squash only or Crawl only is the desired action */ 1856 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 1857 old_cdclk_config->vco == new_cdclk_config->vco || 1858 old_waveform == new_waveform) 1859 return false; 1860 1861 *mid_cdclk_config = *new_cdclk_config; 1862 1863 /* 1864 * Populate the mid_cdclk_config accordingly. 1865 * - If moving to a higher cdclk, the desired action is squashing. 1866 * The mid cdclk config should have the new (squash) waveform. 1867 * - If moving to a lower cdclk, the desired action is crawling. 1868 * The mid cdclk config should have the new vco. 1869 */ 1870 1871 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 1872 mid_cdclk_config->vco = old_cdclk_config->vco; 1873 mid_waveform = new_waveform; 1874 } else { 1875 mid_cdclk_config->vco = new_cdclk_config->vco; 1876 mid_waveform = old_waveform; 1877 } 1878 1879 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 1880 mid_cdclk_config->vco, 1881 cdclk_squash_len * div); 1882 1883 /* make sure the mid clock came out sane */ 1884 1885 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < 1886 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 1887 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > 1888 i915->display.cdclk.max_cdclk_freq); 1889 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != 1890 mid_waveform); 1891 1892 return true; 1893 } 1894 1895 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) 1896 { 1897 return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) || 1898 DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) || 1899 IS_DG2(dev_priv)) && 1900 dev_priv->display.cdclk.hw.vco > 0; 1901 } 1902 1903 static u32 bxt_cdclk_ctl(struct drm_i915_private *i915, 1904 const struct intel_cdclk_config *cdclk_config, 1905 enum pipe pipe) 1906 { 1907 int cdclk = cdclk_config->cdclk; 1908 int vco = cdclk_config->vco; 1909 int unsquashed_cdclk; 1910 u16 waveform; 1911 u32 val; 1912 1913 waveform = cdclk_squash_waveform(i915, cdclk); 1914 1915 unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len, 1916 cdclk_squash_divider(waveform)); 1917 1918 val = bxt_cdclk_cd2x_div_sel(i915, unsquashed_cdclk, vco) | 1919 bxt_cdclk_cd2x_pipe(i915, pipe); 1920 1921 /* 1922 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1923 * enable otherwise. 1924 */ 1925 if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) && 1926 cdclk >= 500000) 1927 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1928 1929 if (DISPLAY_VER(i915) >= 20) 1930 val |= MDCLK_SOURCE_SEL_CDCLK_PLL; 1931 else 1932 val |= skl_cdclk_decimal(cdclk); 1933 1934 return val; 1935 } 1936 1937 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, 1938 const struct intel_cdclk_config *cdclk_config, 1939 enum pipe pipe) 1940 { 1941 int cdclk = cdclk_config->cdclk; 1942 int vco = cdclk_config->vco; 1943 u16 waveform; 1944 1945 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && 1946 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { 1947 if (dev_priv->display.cdclk.hw.vco != vco) 1948 adlp_cdclk_pll_crawl(dev_priv, vco); 1949 } else if (DISPLAY_VER(dev_priv) >= 11) { 1950 /* wa_15010685871: dg2, mtl */ 1951 if (pll_enable_wa_needed(dev_priv)) 1952 dg2_cdclk_squash_program(dev_priv, 0); 1953 1954 icl_cdclk_pll_update(dev_priv, vco); 1955 } else 1956 bxt_cdclk_pll_update(dev_priv, vco); 1957 1958 waveform = cdclk_squash_waveform(dev_priv, cdclk); 1959 1960 if (HAS_CDCLK_SQUASH(dev_priv)) 1961 dg2_cdclk_squash_program(dev_priv, waveform); 1962 1963 intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe)); 1964 1965 if (pipe != INVALID_PIPE) 1966 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 1967 } 1968 1969 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1970 const struct intel_cdclk_config *cdclk_config, 1971 enum pipe pipe) 1972 { 1973 struct intel_cdclk_config mid_cdclk_config; 1974 int cdclk = cdclk_config->cdclk; 1975 int ret = 0; 1976 1977 /* 1978 * Inform power controller of upcoming frequency change. 1979 * Display versions 14 and beyond do not follow the PUnit 1980 * mailbox communication, skip 1981 * this step. 1982 */ 1983 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) 1984 /* NOOP */; 1985 else if (DISPLAY_VER(dev_priv) >= 11) 1986 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1987 SKL_CDCLK_PREPARE_FOR_CHANGE, 1988 SKL_CDCLK_READY_FOR_CHANGE, 1989 SKL_CDCLK_READY_FOR_CHANGE, 3); 1990 else 1991 /* 1992 * BSpec requires us to wait up to 150usec, but that leads to 1993 * timeouts; the 2ms used here is based on experiment. 1994 */ 1995 ret = snb_pcode_write_timeout(&dev_priv->uncore, 1996 HSW_PCODE_DE_WRITE_FREQ_REQ, 1997 0x80000000, 150, 2); 1998 1999 if (ret) { 2000 drm_err(&dev_priv->drm, 2001 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2002 ret, cdclk); 2003 return; 2004 } 2005 2006 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, 2007 cdclk_config, &mid_cdclk_config)) { 2008 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); 2009 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); 2010 } else { 2011 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); 2012 } 2013 2014 if (DISPLAY_VER(dev_priv) >= 14) 2015 /* 2016 * NOOP - No Pcode communication needed for 2017 * Display versions 14 and beyond 2018 */; 2019 else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) 2020 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 2021 cdclk_config->voltage_level); 2022 if (DISPLAY_VER(dev_priv) < 11) { 2023 /* 2024 * The timeout isn't specified, the 2ms used here is based on 2025 * experiment. 2026 * FIXME: Waiting for the request completion could be delayed 2027 * until the next PCODE request based on BSpec. 2028 */ 2029 ret = snb_pcode_write_timeout(&dev_priv->uncore, 2030 HSW_PCODE_DE_WRITE_FREQ_REQ, 2031 cdclk_config->voltage_level, 2032 150, 2); 2033 } 2034 if (ret) { 2035 drm_err(&dev_priv->drm, 2036 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2037 ret, cdclk); 2038 return; 2039 } 2040 2041 intel_update_cdclk(dev_priv); 2042 2043 if (DISPLAY_VER(dev_priv) >= 11) 2044 /* 2045 * Can't read out the voltage level :( 2046 * Let's just assume everything is as expected. 2047 */ 2048 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; 2049 } 2050 2051 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 2052 { 2053 u32 cdctl, expected; 2054 int cdclk, vco; 2055 2056 intel_update_cdclk(dev_priv); 2057 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 2058 2059 if (dev_priv->display.cdclk.hw.vco == 0 || 2060 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 2061 goto sanitize; 2062 2063 /* Make sure this is a legal cdclk value for the platform */ 2064 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); 2065 if (cdclk != dev_priv->display.cdclk.hw.cdclk) 2066 goto sanitize; 2067 2068 /* Make sure the VCO is correct for the cdclk */ 2069 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2070 if (vco != dev_priv->display.cdclk.hw.vco) 2071 goto sanitize; 2072 2073 /* 2074 * Some BIOS versions leave an incorrect decimal frequency value and 2075 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2076 * so sanitize this register. 2077 */ 2078 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 2079 expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE); 2080 2081 /* 2082 * Let's ignore the pipe field, since BIOS could have configured the 2083 * dividers both synching to an active pipe, or asynchronously 2084 * (PIPE_NONE). 2085 */ 2086 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 2087 expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 2088 2089 if (cdctl == expected) 2090 /* All well; nothing to sanitize */ 2091 return; 2092 2093 sanitize: 2094 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 2095 2096 /* force cdclk programming */ 2097 dev_priv->display.cdclk.hw.cdclk = 0; 2098 2099 /* force full PLL disable + enable */ 2100 dev_priv->display.cdclk.hw.vco = ~0; 2101 } 2102 2103 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 2104 { 2105 struct intel_cdclk_config cdclk_config; 2106 2107 bxt_sanitize_cdclk(dev_priv); 2108 2109 if (dev_priv->display.cdclk.hw.cdclk != 0 && 2110 dev_priv->display.cdclk.hw.vco != 0) 2111 return; 2112 2113 cdclk_config = dev_priv->display.cdclk.hw; 2114 2115 /* 2116 * FIXME: 2117 * - The initial CDCLK needs to be read from VBT. 2118 * Need to make this change after VBT has changes for BXT. 2119 */ 2120 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); 2121 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); 2122 cdclk_config.voltage_level = 2123 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 2124 2125 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 2126 } 2127 2128 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 2129 { 2130 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 2131 2132 cdclk_config.cdclk = cdclk_config.bypass; 2133 cdclk_config.vco = 0; 2134 cdclk_config.voltage_level = 2135 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 2136 2137 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 2138 } 2139 2140 /** 2141 * intel_cdclk_init_hw - Initialize CDCLK hardware 2142 * @i915: i915 device 2143 * 2144 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and 2145 * sanitizing the state of the hardware if needed. This is generally done only 2146 * during the display core initialization sequence, after which the DMC will 2147 * take care of turning CDCLK off/on as needed. 2148 */ 2149 void intel_cdclk_init_hw(struct drm_i915_private *i915) 2150 { 2151 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 2152 bxt_cdclk_init_hw(i915); 2153 else if (DISPLAY_VER(i915) == 9) 2154 skl_cdclk_init_hw(i915); 2155 } 2156 2157 /** 2158 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2159 * @i915: i915 device 2160 * 2161 * Uninitialize CDCLK. This is done only during the display core 2162 * uninitialization sequence. 2163 */ 2164 void intel_cdclk_uninit_hw(struct drm_i915_private *i915) 2165 { 2166 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 2167 bxt_cdclk_uninit_hw(i915); 2168 else if (DISPLAY_VER(i915) == 9) 2169 skl_cdclk_uninit_hw(i915); 2170 } 2171 2172 static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915, 2173 const struct intel_cdclk_config *a, 2174 const struct intel_cdclk_config *b) 2175 { 2176 u16 old_waveform; 2177 u16 new_waveform; 2178 2179 drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); 2180 2181 if (a->vco == 0 || b->vco == 0) 2182 return false; 2183 2184 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) 2185 return false; 2186 2187 old_waveform = cdclk_squash_waveform(i915, a->cdclk); 2188 new_waveform = cdclk_squash_waveform(i915, b->cdclk); 2189 2190 return a->vco != b->vco && 2191 old_waveform != new_waveform; 2192 } 2193 2194 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, 2195 const struct intel_cdclk_config *a, 2196 const struct intel_cdclk_config *b) 2197 { 2198 int a_div, b_div; 2199 2200 if (!HAS_CDCLK_CRAWL(dev_priv)) 2201 return false; 2202 2203 /* 2204 * The vco and cd2x divider will change independently 2205 * from each, so we disallow cd2x change when crawling. 2206 */ 2207 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2208 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2209 2210 return a->vco != 0 && b->vco != 0 && 2211 a->vco != b->vco && 2212 a_div == b_div && 2213 a->ref == b->ref; 2214 } 2215 2216 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, 2217 const struct intel_cdclk_config *a, 2218 const struct intel_cdclk_config *b) 2219 { 2220 /* 2221 * FIXME should store a bit more state in intel_cdclk_config 2222 * to differentiate squasher vs. cd2x divider properly. For 2223 * the moment all platforms with squasher use a fixed cd2x 2224 * divider. 2225 */ 2226 if (!HAS_CDCLK_SQUASH(dev_priv)) 2227 return false; 2228 2229 return a->cdclk != b->cdclk && 2230 a->vco != 0 && 2231 a->vco == b->vco && 2232 a->ref == b->ref; 2233 } 2234 2235 /** 2236 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK 2237 * configurations requires a modeset on all pipes 2238 * @a: first CDCLK configuration 2239 * @b: second CDCLK configuration 2240 * 2241 * Returns: 2242 * True if changing between the two CDCLK configurations 2243 * requires all pipes to be off, false if not. 2244 */ 2245 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 2246 const struct intel_cdclk_config *b) 2247 { 2248 return a->cdclk != b->cdclk || 2249 a->vco != b->vco || 2250 a->ref != b->ref; 2251 } 2252 2253 /** 2254 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2255 * configurations requires only a cd2x divider update 2256 * @dev_priv: i915 device 2257 * @a: first CDCLK configuration 2258 * @b: second CDCLK configuration 2259 * 2260 * Returns: 2261 * True if changing between the two CDCLK configurations 2262 * can be done with just a cd2x divider update, false if not. 2263 */ 2264 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 2265 const struct intel_cdclk_config *a, 2266 const struct intel_cdclk_config *b) 2267 { 2268 /* Older hw doesn't have the capability */ 2269 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) 2270 return false; 2271 2272 /* 2273 * FIXME should store a bit more state in intel_cdclk_config 2274 * to differentiate squasher vs. cd2x divider properly. For 2275 * the moment all platforms with squasher use a fixed cd2x 2276 * divider. 2277 */ 2278 if (HAS_CDCLK_SQUASH(dev_priv)) 2279 return false; 2280 2281 return a->cdclk != b->cdclk && 2282 a->vco != 0 && 2283 a->vco == b->vco && 2284 a->ref == b->ref; 2285 } 2286 2287 /** 2288 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2289 * @a: first CDCLK configuration 2290 * @b: second CDCLK configuration 2291 * 2292 * Returns: 2293 * True if the CDCLK configurations don't match, false if they do. 2294 */ 2295 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2296 const struct intel_cdclk_config *b) 2297 { 2298 return intel_cdclk_needs_modeset(a, b) || 2299 a->voltage_level != b->voltage_level; 2300 } 2301 2302 void intel_cdclk_dump_config(struct drm_i915_private *i915, 2303 const struct intel_cdclk_config *cdclk_config, 2304 const char *context) 2305 { 2306 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2307 context, cdclk_config->cdclk, cdclk_config->vco, 2308 cdclk_config->ref, cdclk_config->bypass, 2309 cdclk_config->voltage_level); 2310 } 2311 2312 static void intel_pcode_notify(struct drm_i915_private *i915, 2313 u8 voltage_level, 2314 u8 active_pipe_count, 2315 u16 cdclk, 2316 bool cdclk_update_valid, 2317 bool pipe_count_update_valid) 2318 { 2319 int ret; 2320 u32 update_mask = 0; 2321 2322 if (!IS_DG2(i915)) 2323 return; 2324 2325 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2326 2327 if (cdclk_update_valid) 2328 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2329 2330 if (pipe_count_update_valid) 2331 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2332 2333 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL, 2334 SKL_CDCLK_PREPARE_FOR_CHANGE | 2335 update_mask, 2336 SKL_CDCLK_READY_FOR_CHANGE, 2337 SKL_CDCLK_READY_FOR_CHANGE, 3); 2338 if (ret) 2339 drm_err(&i915->drm, 2340 "Failed to inform PCU about display config (err %d)\n", 2341 ret); 2342 } 2343 2344 /** 2345 * intel_set_cdclk - Push the CDCLK configuration to the hardware 2346 * @dev_priv: i915 device 2347 * @cdclk_config: new CDCLK configuration 2348 * @pipe: pipe with which to synchronize the update 2349 * 2350 * Program the hardware based on the passed in CDCLK state, 2351 * if necessary. 2352 */ 2353 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 2354 const struct intel_cdclk_config *cdclk_config, 2355 enum pipe pipe) 2356 { 2357 struct intel_encoder *encoder; 2358 2359 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) 2360 return; 2361 2362 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) 2363 return; 2364 2365 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); 2366 2367 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2368 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2369 2370 intel_psr_pause(intel_dp); 2371 } 2372 2373 intel_audio_cdclk_change_pre(dev_priv); 2374 2375 /* 2376 * Lock aux/gmbus while we change cdclk in case those 2377 * functions use cdclk. Not all platforms/ports do, 2378 * but we'll lock them all for simplicity. 2379 */ 2380 mutex_lock(&dev_priv->display.gmbus.mutex); 2381 for_each_intel_dp(&dev_priv->drm, encoder) { 2382 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2383 2384 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2385 &dev_priv->display.gmbus.mutex); 2386 } 2387 2388 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); 2389 2390 for_each_intel_dp(&dev_priv->drm, encoder) { 2391 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2392 2393 mutex_unlock(&intel_dp->aux.hw_mutex); 2394 } 2395 mutex_unlock(&dev_priv->display.gmbus.mutex); 2396 2397 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2398 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2399 2400 intel_psr_resume(intel_dp); 2401 } 2402 2403 intel_audio_cdclk_change_post(dev_priv); 2404 2405 if (drm_WARN(&dev_priv->drm, 2406 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), 2407 "cdclk state doesn't match!\n")) { 2408 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); 2409 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); 2410 } 2411 } 2412 2413 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2414 { 2415 struct drm_i915_private *i915 = to_i915(state->base.dev); 2416 const struct intel_cdclk_state *old_cdclk_state = 2417 intel_atomic_get_old_cdclk_state(state); 2418 const struct intel_cdclk_state *new_cdclk_state = 2419 intel_atomic_get_new_cdclk_state(state); 2420 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2421 bool change_cdclk, update_pipe_count; 2422 2423 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2424 &new_cdclk_state->actual) && 2425 new_cdclk_state->active_pipes == 2426 old_cdclk_state->active_pipes) 2427 return; 2428 2429 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2430 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2431 2432 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2433 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > 2434 hweight8(old_cdclk_state->active_pipes); 2435 2436 /* 2437 * According to "Sequence Before Frequency Change", 2438 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2439 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2440 * which basically means we choose the maximum of old and new CDCLK, if we know both 2441 */ 2442 if (change_cdclk) 2443 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2444 2445 /* 2446 * According to "Sequence For Pipe Count Change", 2447 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2448 * (power well is enabled) 2449 * no action if it is decreasing, before the change 2450 */ 2451 if (update_pipe_count) 2452 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2453 2454 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, 2455 change_cdclk, update_pipe_count); 2456 } 2457 2458 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2459 { 2460 struct drm_i915_private *i915 = to_i915(state->base.dev); 2461 const struct intel_cdclk_state *new_cdclk_state = 2462 intel_atomic_get_new_cdclk_state(state); 2463 const struct intel_cdclk_state *old_cdclk_state = 2464 intel_atomic_get_old_cdclk_state(state); 2465 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2466 bool update_cdclk, update_pipe_count; 2467 2468 /* According to "Sequence After Frequency Change", set voltage to used level */ 2469 voltage_level = new_cdclk_state->actual.voltage_level; 2470 2471 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2472 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < 2473 hweight8(old_cdclk_state->active_pipes); 2474 2475 /* 2476 * According to "Sequence After Frequency Change", 2477 * set bits 25:16 to current CDCLK 2478 */ 2479 if (update_cdclk) 2480 cdclk = new_cdclk_state->actual.cdclk; 2481 2482 /* 2483 * According to "Sequence For Pipe Count Change", 2484 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2485 * after the change(power well is disabled) 2486 * no action if it is increasing, after the change 2487 */ 2488 if (update_pipe_count) 2489 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2490 2491 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, 2492 update_cdclk, update_pipe_count); 2493 } 2494 2495 /** 2496 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2497 * @state: intel atomic state 2498 * 2499 * Program the hardware before updating the HW plane state based on the 2500 * new CDCLK state, if necessary. 2501 */ 2502 void 2503 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2504 { 2505 struct drm_i915_private *i915 = to_i915(state->base.dev); 2506 const struct intel_cdclk_state *old_cdclk_state = 2507 intel_atomic_get_old_cdclk_state(state); 2508 const struct intel_cdclk_state *new_cdclk_state = 2509 intel_atomic_get_new_cdclk_state(state); 2510 enum pipe pipe = new_cdclk_state->pipe; 2511 2512 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2513 &new_cdclk_state->actual)) 2514 return; 2515 2516 if (IS_DG2(i915)) 2517 intel_cdclk_pcode_pre_notify(state); 2518 2519 if (pipe == INVALID_PIPE || 2520 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { 2521 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); 2522 2523 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe); 2524 } 2525 } 2526 2527 /** 2528 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2529 * @state: intel atomic state 2530 * 2531 * Program the hardware after updating the HW plane state based on the 2532 * new CDCLK state, if necessary. 2533 */ 2534 void 2535 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2536 { 2537 struct drm_i915_private *i915 = to_i915(state->base.dev); 2538 const struct intel_cdclk_state *old_cdclk_state = 2539 intel_atomic_get_old_cdclk_state(state); 2540 const struct intel_cdclk_state *new_cdclk_state = 2541 intel_atomic_get_new_cdclk_state(state); 2542 enum pipe pipe = new_cdclk_state->pipe; 2543 2544 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2545 &new_cdclk_state->actual)) 2546 return; 2547 2548 if (IS_DG2(i915)) 2549 intel_cdclk_pcode_post_notify(state); 2550 2551 if (pipe != INVALID_PIPE && 2552 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { 2553 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); 2554 2555 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe); 2556 } 2557 } 2558 2559 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2560 { 2561 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2562 int pixel_rate = crtc_state->pixel_rate; 2563 2564 if (DISPLAY_VER(dev_priv) >= 10) 2565 return DIV_ROUND_UP(pixel_rate, 2); 2566 else if (DISPLAY_VER(dev_priv) == 9 || 2567 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2568 return pixel_rate; 2569 else if (IS_CHERRYVIEW(dev_priv)) 2570 return DIV_ROUND_UP(pixel_rate * 100, 95); 2571 else if (crtc_state->double_wide) 2572 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2573 else 2574 return DIV_ROUND_UP(pixel_rate * 100, 90); 2575 } 2576 2577 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2578 { 2579 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2580 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2581 struct intel_plane *plane; 2582 int min_cdclk = 0; 2583 2584 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 2585 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2586 2587 return min_cdclk; 2588 } 2589 2590 static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) 2591 { 2592 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2593 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2594 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 2595 int min_cdclk = 0; 2596 2597 /* 2598 * When we decide to use only one VDSC engine, since 2599 * each VDSC operates with 1 ppc throughput, pixel clock 2600 * cannot be higher than the VDSC clock (cdclk) 2601 * If there 2 VDSC engines, then pixel clock can't be higher than 2602 * VDSC clock(cdclk) * 2 and so on. 2603 */ 2604 min_cdclk = max_t(int, min_cdclk, 2605 DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances)); 2606 2607 if (crtc_state->bigjoiner_pipes) { 2608 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); 2609 2610 /* 2611 * According to Bigjoiner bw check: 2612 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock 2613 * 2614 * We have already computed compressed_bpp, so now compute the min CDCLK that 2615 * is required to support this compressed_bpp. 2616 * 2617 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) 2618 * 2619 * Since PPC = 2 with bigjoiner 2620 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits 2621 */ 2622 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; 2623 int min_cdclk_bj = 2624 (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) * 2625 pixel_clock) / (2 * bigjoiner_interface_bits); 2626 2627 min_cdclk = max(min_cdclk, min_cdclk_bj); 2628 } 2629 2630 return min_cdclk; 2631 } 2632 2633 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2634 { 2635 struct drm_i915_private *dev_priv = 2636 to_i915(crtc_state->uapi.crtc->dev); 2637 int min_cdclk; 2638 2639 if (!crtc_state->hw.enable) 2640 return 0; 2641 2642 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2643 2644 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2645 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2646 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2647 2648 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2649 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2650 * there may be audio corruption or screen corruption." This cdclk 2651 * restriction for GLK is 316.8 MHz. 2652 */ 2653 if (intel_crtc_has_dp_encoder(crtc_state) && 2654 crtc_state->has_audio && 2655 crtc_state->port_clock >= 540000 && 2656 crtc_state->lane_count == 4) { 2657 if (DISPLAY_VER(dev_priv) == 10) { 2658 /* Display WA #1145: glk */ 2659 min_cdclk = max(316800, min_cdclk); 2660 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { 2661 /* Display WA #1144: skl,bxt */ 2662 min_cdclk = max(432000, min_cdclk); 2663 } 2664 } 2665 2666 /* 2667 * According to BSpec, "The CD clock frequency must be at least twice 2668 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2669 */ 2670 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) 2671 min_cdclk = max(2 * 96000, min_cdclk); 2672 2673 /* 2674 * "For DP audio configuration, cdclk frequency shall be set to 2675 * meet the following requirements: 2676 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2677 * 270 | 320 or higher 2678 * 162 | 200 or higher" 2679 */ 2680 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2681 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2682 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2683 2684 /* 2685 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2686 * than 320000KHz. 2687 */ 2688 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2689 IS_VALLEYVIEW(dev_priv)) 2690 min_cdclk = max(320000, min_cdclk); 2691 2692 /* 2693 * On Geminilake once the CDCLK gets as low as 79200 2694 * picture gets unstable, despite that values are 2695 * correct for DSI PLL and DE PLL. 2696 */ 2697 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2698 IS_GEMINILAKE(dev_priv)) 2699 min_cdclk = max(158400, min_cdclk); 2700 2701 /* Account for additional needs from the planes */ 2702 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2703 2704 if (crtc_state->dsc.compression_enable) 2705 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2706 2707 /* 2708 * HACK. Currently for TGL/DG2 platforms we calculate 2709 * min_cdclk initially based on pixel_rate divided 2710 * by 2, accounting for also plane requirements, 2711 * however in some cases the lowest possible CDCLK 2712 * doesn't work and causing the underruns. 2713 * Explicitly stating here that this seems to be currently 2714 * rather a Hack, than final solution. 2715 */ 2716 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { 2717 /* 2718 * Clamp to max_cdclk_freq in case pixel rate is higher, 2719 * in order not to break an 8K, but still leave W/A at place. 2720 */ 2721 min_cdclk = max_t(int, min_cdclk, 2722 min_t(int, crtc_state->pixel_rate, 2723 dev_priv->display.cdclk.max_cdclk_freq)); 2724 } 2725 2726 return min_cdclk; 2727 } 2728 2729 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) 2730 { 2731 struct intel_atomic_state *state = cdclk_state->base.state; 2732 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2733 const struct intel_bw_state *bw_state; 2734 struct intel_crtc *crtc; 2735 struct intel_crtc_state *crtc_state; 2736 int min_cdclk, i; 2737 enum pipe pipe; 2738 2739 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2740 int ret; 2741 2742 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2743 if (min_cdclk < 0) 2744 return min_cdclk; 2745 2746 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2747 continue; 2748 2749 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2750 2751 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2752 if (ret) 2753 return ret; 2754 } 2755 2756 bw_state = intel_atomic_get_new_bw_state(state); 2757 if (bw_state) { 2758 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); 2759 2760 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2761 int ret; 2762 2763 cdclk_state->bw_min_cdclk = min_cdclk; 2764 2765 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2766 if (ret) 2767 return ret; 2768 } 2769 } 2770 2771 min_cdclk = max(cdclk_state->force_min_cdclk, 2772 cdclk_state->bw_min_cdclk); 2773 for_each_pipe(dev_priv, pipe) 2774 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2775 2776 /* 2777 * Avoid glk_force_audio_cdclk() causing excessive screen 2778 * blinking when multiple pipes are active by making sure 2779 * CDCLK frequency is always high enough for audio. With a 2780 * single active pipe we can always change CDCLK frequency 2781 * by changing the cd2x divider (see glk_cdclk_table[]) and 2782 * thus a full modeset won't be needed then. 2783 */ 2784 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && 2785 !is_power_of_2(cdclk_state->active_pipes)) 2786 min_cdclk = max(2 * 96000, min_cdclk); 2787 2788 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { 2789 drm_dbg_kms(&dev_priv->drm, 2790 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2791 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); 2792 return -EINVAL; 2793 } 2794 2795 return min_cdclk; 2796 } 2797 2798 /* 2799 * Account for port clock min voltage level requirements. 2800 * This only really does something on DISPLA_VER >= 11 but can be 2801 * called on earlier platforms as well. 2802 * 2803 * Note that this functions assumes that 0 is 2804 * the lowest voltage value, and higher values 2805 * correspond to increasingly higher voltages. 2806 * 2807 * Should that relationship no longer hold on 2808 * future platforms this code will need to be 2809 * adjusted. 2810 */ 2811 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) 2812 { 2813 struct intel_atomic_state *state = cdclk_state->base.state; 2814 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2815 struct intel_crtc *crtc; 2816 struct intel_crtc_state *crtc_state; 2817 u8 min_voltage_level; 2818 int i; 2819 enum pipe pipe; 2820 2821 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2822 int ret; 2823 2824 if (crtc_state->hw.enable) 2825 min_voltage_level = crtc_state->min_voltage_level; 2826 else 2827 min_voltage_level = 0; 2828 2829 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2830 continue; 2831 2832 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2833 2834 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2835 if (ret) 2836 return ret; 2837 } 2838 2839 min_voltage_level = 0; 2840 for_each_pipe(dev_priv, pipe) 2841 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2842 min_voltage_level); 2843 2844 return min_voltage_level; 2845 } 2846 2847 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2848 { 2849 struct intel_atomic_state *state = cdclk_state->base.state; 2850 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2851 int min_cdclk, cdclk; 2852 2853 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2854 if (min_cdclk < 0) 2855 return min_cdclk; 2856 2857 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2858 2859 cdclk_state->logical.cdclk = cdclk; 2860 cdclk_state->logical.voltage_level = 2861 vlv_calc_voltage_level(dev_priv, cdclk); 2862 2863 if (!cdclk_state->active_pipes) { 2864 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2865 2866 cdclk_state->actual.cdclk = cdclk; 2867 cdclk_state->actual.voltage_level = 2868 vlv_calc_voltage_level(dev_priv, cdclk); 2869 } else { 2870 cdclk_state->actual = cdclk_state->logical; 2871 } 2872 2873 return 0; 2874 } 2875 2876 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2877 { 2878 int min_cdclk, cdclk; 2879 2880 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2881 if (min_cdclk < 0) 2882 return min_cdclk; 2883 2884 cdclk = bdw_calc_cdclk(min_cdclk); 2885 2886 cdclk_state->logical.cdclk = cdclk; 2887 cdclk_state->logical.voltage_level = 2888 bdw_calc_voltage_level(cdclk); 2889 2890 if (!cdclk_state->active_pipes) { 2891 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2892 2893 cdclk_state->actual.cdclk = cdclk; 2894 cdclk_state->actual.voltage_level = 2895 bdw_calc_voltage_level(cdclk); 2896 } else { 2897 cdclk_state->actual = cdclk_state->logical; 2898 } 2899 2900 return 0; 2901 } 2902 2903 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) 2904 { 2905 struct intel_atomic_state *state = cdclk_state->base.state; 2906 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2907 struct intel_crtc *crtc; 2908 struct intel_crtc_state *crtc_state; 2909 int vco, i; 2910 2911 vco = cdclk_state->logical.vco; 2912 if (!vco) 2913 vco = dev_priv->skl_preferred_vco_freq; 2914 2915 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2916 if (!crtc_state->hw.enable) 2917 continue; 2918 2919 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2920 continue; 2921 2922 /* 2923 * DPLL0 VCO may need to be adjusted to get the correct 2924 * clock for eDP. This will affect cdclk as well. 2925 */ 2926 switch (crtc_state->port_clock / 2) { 2927 case 108000: 2928 case 216000: 2929 vco = 8640000; 2930 break; 2931 default: 2932 vco = 8100000; 2933 break; 2934 } 2935 } 2936 2937 return vco; 2938 } 2939 2940 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2941 { 2942 int min_cdclk, cdclk, vco; 2943 2944 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2945 if (min_cdclk < 0) 2946 return min_cdclk; 2947 2948 vco = skl_dpll0_vco(cdclk_state); 2949 2950 cdclk = skl_calc_cdclk(min_cdclk, vco); 2951 2952 cdclk_state->logical.vco = vco; 2953 cdclk_state->logical.cdclk = cdclk; 2954 cdclk_state->logical.voltage_level = 2955 skl_calc_voltage_level(cdclk); 2956 2957 if (!cdclk_state->active_pipes) { 2958 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 2959 2960 cdclk_state->actual.vco = vco; 2961 cdclk_state->actual.cdclk = cdclk; 2962 cdclk_state->actual.voltage_level = 2963 skl_calc_voltage_level(cdclk); 2964 } else { 2965 cdclk_state->actual = cdclk_state->logical; 2966 } 2967 2968 return 0; 2969 } 2970 2971 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2972 { 2973 struct intel_atomic_state *state = cdclk_state->base.state; 2974 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2975 int min_cdclk, min_voltage_level, cdclk, vco; 2976 2977 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2978 if (min_cdclk < 0) 2979 return min_cdclk; 2980 2981 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); 2982 if (min_voltage_level < 0) 2983 return min_voltage_level; 2984 2985 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); 2986 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2987 2988 cdclk_state->logical.vco = vco; 2989 cdclk_state->logical.cdclk = cdclk; 2990 cdclk_state->logical.voltage_level = 2991 max_t(int, min_voltage_level, 2992 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); 2993 2994 if (!cdclk_state->active_pipes) { 2995 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2996 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2997 2998 cdclk_state->actual.vco = vco; 2999 cdclk_state->actual.cdclk = cdclk; 3000 cdclk_state->actual.voltage_level = 3001 intel_cdclk_calc_voltage_level(dev_priv, cdclk); 3002 } else { 3003 cdclk_state->actual = cdclk_state->logical; 3004 } 3005 3006 return 0; 3007 } 3008 3009 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 3010 { 3011 int min_cdclk; 3012 3013 /* 3014 * We can't change the cdclk frequency, but we still want to 3015 * check that the required minimum frequency doesn't exceed 3016 * the actual cdclk frequency. 3017 */ 3018 min_cdclk = intel_compute_min_cdclk(cdclk_state); 3019 if (min_cdclk < 0) 3020 return min_cdclk; 3021 3022 return 0; 3023 } 3024 3025 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3026 { 3027 struct intel_cdclk_state *cdclk_state; 3028 3029 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3030 if (!cdclk_state) 3031 return NULL; 3032 3033 cdclk_state->pipe = INVALID_PIPE; 3034 3035 return &cdclk_state->base; 3036 } 3037 3038 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3039 struct intel_global_state *state) 3040 { 3041 kfree(state); 3042 } 3043 3044 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3045 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3046 .atomic_destroy_state = intel_cdclk_destroy_state, 3047 }; 3048 3049 struct intel_cdclk_state * 3050 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3051 { 3052 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 3053 struct intel_global_state *cdclk_state; 3054 3055 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); 3056 if (IS_ERR(cdclk_state)) 3057 return ERR_CAST(cdclk_state); 3058 3059 return to_intel_cdclk_state(cdclk_state); 3060 } 3061 3062 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 3063 bool *need_cdclk_calc) 3064 { 3065 const struct intel_cdclk_state *old_cdclk_state; 3066 const struct intel_cdclk_state *new_cdclk_state; 3067 struct intel_plane_state __maybe_unused *plane_state; 3068 struct intel_plane *plane; 3069 int ret; 3070 int i; 3071 3072 /* 3073 * active_planes bitmask has been updated, and potentially affected 3074 * planes are part of the state. We can now compute the minimum cdclk 3075 * for each plane. 3076 */ 3077 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 3078 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 3079 if (ret) 3080 return ret; 3081 } 3082 3083 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 3084 if (ret) 3085 return ret; 3086 3087 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3088 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3089 3090 if (new_cdclk_state && 3091 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 3092 *need_cdclk_calc = true; 3093 3094 return 0; 3095 } 3096 3097 int intel_cdclk_init(struct drm_i915_private *dev_priv) 3098 { 3099 struct intel_cdclk_state *cdclk_state; 3100 3101 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 3102 if (!cdclk_state) 3103 return -ENOMEM; 3104 3105 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, 3106 &cdclk_state->base, &intel_cdclk_funcs); 3107 3108 return 0; 3109 } 3110 3111 static bool intel_cdclk_need_serialize(struct drm_i915_private *i915, 3112 const struct intel_cdclk_state *old_cdclk_state, 3113 const struct intel_cdclk_state *new_cdclk_state) 3114 { 3115 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != 3116 hweight8(new_cdclk_state->active_pipes); 3117 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, 3118 &new_cdclk_state->actual); 3119 /* 3120 * We need to poke hw for gen >= 12, because we notify PCode if 3121 * pipe power well count changes. 3122 */ 3123 return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed); 3124 } 3125 3126 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3127 { 3128 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 3129 const struct intel_cdclk_state *old_cdclk_state; 3130 struct intel_cdclk_state *new_cdclk_state; 3131 enum pipe pipe = INVALID_PIPE; 3132 int ret; 3133 3134 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3135 if (IS_ERR(new_cdclk_state)) 3136 return PTR_ERR(new_cdclk_state); 3137 3138 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3139 3140 new_cdclk_state->active_pipes = 3141 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3142 3143 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); 3144 if (ret) 3145 return ret; 3146 3147 if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) { 3148 /* 3149 * Also serialize commits across all crtcs 3150 * if the actual hw needs to be poked. 3151 */ 3152 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3153 if (ret) 3154 return ret; 3155 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 3156 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 3157 intel_cdclk_changed(&old_cdclk_state->logical, 3158 &new_cdclk_state->logical)) { 3159 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3160 if (ret) 3161 return ret; 3162 } else { 3163 return 0; 3164 } 3165 3166 if (is_power_of_2(new_cdclk_state->active_pipes) && 3167 intel_cdclk_can_cd2x_update(dev_priv, 3168 &old_cdclk_state->actual, 3169 &new_cdclk_state->actual)) { 3170 struct intel_crtc *crtc; 3171 struct intel_crtc_state *crtc_state; 3172 3173 pipe = ilog2(new_cdclk_state->active_pipes); 3174 crtc = intel_crtc_for_pipe(dev_priv, pipe); 3175 3176 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3177 if (IS_ERR(crtc_state)) 3178 return PTR_ERR(crtc_state); 3179 3180 if (intel_crtc_needs_modeset(crtc_state)) 3181 pipe = INVALID_PIPE; 3182 } 3183 3184 if (intel_cdclk_can_crawl_and_squash(dev_priv, 3185 &old_cdclk_state->actual, 3186 &new_cdclk_state->actual)) { 3187 drm_dbg_kms(&dev_priv->drm, 3188 "Can change cdclk via crawling and squashing\n"); 3189 } else if (intel_cdclk_can_squash(dev_priv, 3190 &old_cdclk_state->actual, 3191 &new_cdclk_state->actual)) { 3192 drm_dbg_kms(&dev_priv->drm, 3193 "Can change cdclk via squashing\n"); 3194 } else if (intel_cdclk_can_crawl(dev_priv, 3195 &old_cdclk_state->actual, 3196 &new_cdclk_state->actual)) { 3197 drm_dbg_kms(&dev_priv->drm, 3198 "Can change cdclk via crawling\n"); 3199 } else if (pipe != INVALID_PIPE) { 3200 new_cdclk_state->pipe = pipe; 3201 3202 drm_dbg_kms(&dev_priv->drm, 3203 "Can change cdclk cd2x divider with pipe %c active\n", 3204 pipe_name(pipe)); 3205 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, 3206 &new_cdclk_state->actual)) { 3207 /* All pipes must be switched off while we change the cdclk. */ 3208 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3209 if (ret) 3210 return ret; 3211 3212 drm_dbg_kms(&dev_priv->drm, 3213 "Modeset required for cdclk change\n"); 3214 } 3215 3216 drm_dbg_kms(&dev_priv->drm, 3217 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3218 new_cdclk_state->logical.cdclk, 3219 new_cdclk_state->actual.cdclk); 3220 drm_dbg_kms(&dev_priv->drm, 3221 "New voltage level calculated to be logical %u, actual %u\n", 3222 new_cdclk_state->logical.voltage_level, 3223 new_cdclk_state->actual.voltage_level); 3224 3225 return 0; 3226 } 3227 3228 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 3229 { 3230 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; 3231 3232 if (DISPLAY_VER(dev_priv) >= 10) 3233 return 2 * max_cdclk_freq; 3234 else if (DISPLAY_VER(dev_priv) == 9 || 3235 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3236 return max_cdclk_freq; 3237 else if (IS_CHERRYVIEW(dev_priv)) 3238 return max_cdclk_freq*95/100; 3239 else if (DISPLAY_VER(dev_priv) < 4) 3240 return 2*max_cdclk_freq*90/100; 3241 else 3242 return max_cdclk_freq*90/100; 3243 } 3244 3245 /** 3246 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3247 * @dev_priv: i915 device 3248 * 3249 * Determine the maximum CDCLK frequency the platform supports, and also 3250 * derive the maximum dot clock frequency the maximum CDCLK frequency 3251 * allows. 3252 */ 3253 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 3254 { 3255 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 3256 if (dev_priv->display.cdclk.hw.ref == 24000) 3257 dev_priv->display.cdclk.max_cdclk_freq = 552000; 3258 else 3259 dev_priv->display.cdclk.max_cdclk_freq = 556800; 3260 } else if (DISPLAY_VER(dev_priv) >= 11) { 3261 if (dev_priv->display.cdclk.hw.ref == 24000) 3262 dev_priv->display.cdclk.max_cdclk_freq = 648000; 3263 else 3264 dev_priv->display.cdclk.max_cdclk_freq = 652800; 3265 } else if (IS_GEMINILAKE(dev_priv)) { 3266 dev_priv->display.cdclk.max_cdclk_freq = 316800; 3267 } else if (IS_BROXTON(dev_priv)) { 3268 dev_priv->display.cdclk.max_cdclk_freq = 624000; 3269 } else if (DISPLAY_VER(dev_priv) == 9) { 3270 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3271 int max_cdclk, vco; 3272 3273 vco = dev_priv->skl_preferred_vco_freq; 3274 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 3275 3276 /* 3277 * Use the lower (vco 8640) cdclk values as a 3278 * first guess. skl_calc_cdclk() will correct it 3279 * if the preferred vco is 8100 instead. 3280 */ 3281 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3282 max_cdclk = 617143; 3283 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3284 max_cdclk = 540000; 3285 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3286 max_cdclk = 432000; 3287 else 3288 max_cdclk = 308571; 3289 3290 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3291 } else if (IS_BROADWELL(dev_priv)) { 3292 /* 3293 * FIXME with extra cooling we can allow 3294 * 540 MHz for ULX and 675 Mhz for ULT. 3295 * How can we know if extra cooling is 3296 * available? PCI ID, VTB, something else? 3297 */ 3298 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3299 dev_priv->display.cdclk.max_cdclk_freq = 450000; 3300 else if (IS_BROADWELL_ULX(dev_priv)) 3301 dev_priv->display.cdclk.max_cdclk_freq = 450000; 3302 else if (IS_BROADWELL_ULT(dev_priv)) 3303 dev_priv->display.cdclk.max_cdclk_freq = 540000; 3304 else 3305 dev_priv->display.cdclk.max_cdclk_freq = 675000; 3306 } else if (IS_CHERRYVIEW(dev_priv)) { 3307 dev_priv->display.cdclk.max_cdclk_freq = 320000; 3308 } else if (IS_VALLEYVIEW(dev_priv)) { 3309 dev_priv->display.cdclk.max_cdclk_freq = 400000; 3310 } else { 3311 /* otherwise assume cdclk is fixed */ 3312 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; 3313 } 3314 3315 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 3316 3317 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", 3318 dev_priv->display.cdclk.max_cdclk_freq); 3319 3320 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", 3321 dev_priv->max_dotclk_freq); 3322 } 3323 3324 /** 3325 * intel_update_cdclk - Determine the current CDCLK frequency 3326 * @dev_priv: i915 device 3327 * 3328 * Determine the current CDCLK frequency. 3329 */ 3330 void intel_update_cdclk(struct drm_i915_private *dev_priv) 3331 { 3332 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); 3333 3334 /* 3335 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3336 * Programmng [sic] note: bit[9:2] should be programmed to the number 3337 * of cdclk that generates 4MHz reference clock freq which is used to 3338 * generate GMBus clock. This will vary with the cdclk freq. 3339 */ 3340 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3341 intel_de_write(dev_priv, GMBUSFREQ_VLV, 3342 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); 3343 } 3344 3345 static int dg1_rawclk(struct drm_i915_private *dev_priv) 3346 { 3347 /* 3348 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3349 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3350 */ 3351 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, 3352 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3353 3354 return 38400; 3355 } 3356 3357 static int cnp_rawclk(struct drm_i915_private *dev_priv) 3358 { 3359 u32 rawclk; 3360 int divider, fraction; 3361 3362 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3363 /* 24 MHz */ 3364 divider = 24000; 3365 fraction = 0; 3366 } else { 3367 /* 19.2 MHz */ 3368 divider = 19000; 3369 fraction = 200; 3370 } 3371 3372 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3373 if (fraction) { 3374 int numerator = 1; 3375 3376 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3377 fraction) - 1); 3378 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3379 rawclk |= ICP_RAWCLK_NUM(numerator); 3380 } 3381 3382 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); 3383 return divider + fraction; 3384 } 3385 3386 static int pch_rawclk(struct drm_i915_private *dev_priv) 3387 { 3388 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3389 } 3390 3391 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 3392 { 3393 /* RAWCLK_FREQ_VLV register updated from power well code */ 3394 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 3395 CCK_DISPLAY_REF_CLOCK_CONTROL); 3396 } 3397 3398 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) 3399 { 3400 u32 clkcfg; 3401 3402 /* 3403 * hrawclock is 1/4 the FSB frequency 3404 * 3405 * Note that this only reads the state of the FSB 3406 * straps, not the actual FSB frequency. Some BIOSen 3407 * let you configure each independently. Ideally we'd 3408 * read out the actual FSB frequency but sadly we 3409 * don't know which registers have that information, 3410 * and all the relevant docs have gone to bit heaven :( 3411 */ 3412 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; 3413 3414 if (IS_MOBILE(dev_priv)) { 3415 switch (clkcfg) { 3416 case CLKCFG_FSB_400: 3417 return 100000; 3418 case CLKCFG_FSB_533: 3419 return 133333; 3420 case CLKCFG_FSB_667: 3421 return 166667; 3422 case CLKCFG_FSB_800: 3423 return 200000; 3424 case CLKCFG_FSB_1067: 3425 return 266667; 3426 case CLKCFG_FSB_1333: 3427 return 333333; 3428 default: 3429 MISSING_CASE(clkcfg); 3430 return 133333; 3431 } 3432 } else { 3433 switch (clkcfg) { 3434 case CLKCFG_FSB_400_ALT: 3435 return 100000; 3436 case CLKCFG_FSB_533: 3437 return 133333; 3438 case CLKCFG_FSB_667: 3439 return 166667; 3440 case CLKCFG_FSB_800: 3441 return 200000; 3442 case CLKCFG_FSB_1067_ALT: 3443 return 266667; 3444 case CLKCFG_FSB_1333_ALT: 3445 return 333333; 3446 case CLKCFG_FSB_1600_ALT: 3447 return 400000; 3448 default: 3449 return 133333; 3450 } 3451 } 3452 } 3453 3454 /** 3455 * intel_read_rawclk - Determine the current RAWCLK frequency 3456 * @dev_priv: i915 device 3457 * 3458 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3459 * frequency clock so this needs to done only once. 3460 */ 3461 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 3462 { 3463 u32 freq; 3464 3465 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) 3466 /* 3467 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3468 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3469 * not need to be programmed." 3470 */ 3471 freq = 38400; 3472 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3473 freq = dg1_rawclk(dev_priv); 3474 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3475 freq = cnp_rawclk(dev_priv); 3476 else if (HAS_PCH_SPLIT(dev_priv)) 3477 freq = pch_rawclk(dev_priv); 3478 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3479 freq = vlv_hrawclk(dev_priv); 3480 else if (DISPLAY_VER(dev_priv) >= 3) 3481 freq = i9xx_hrawclk(dev_priv); 3482 else 3483 /* no rawclk on other platforms, or no need to know it */ 3484 return 0; 3485 3486 return freq; 3487 } 3488 3489 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3490 { 3491 struct drm_i915_private *i915 = m->private; 3492 3493 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); 3494 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); 3495 seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); 3496 3497 return 0; 3498 } 3499 3500 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3501 3502 void intel_cdclk_debugfs_register(struct drm_i915_private *i915) 3503 { 3504 struct drm_minor *minor = i915->drm.primary; 3505 3506 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, 3507 i915, &i915_cdclk_info_fops); 3508 } 3509 3510 static const struct intel_cdclk_funcs mtl_cdclk_funcs = { 3511 .get_cdclk = bxt_get_cdclk, 3512 .set_cdclk = bxt_set_cdclk, 3513 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3514 .calc_voltage_level = rplu_calc_voltage_level, 3515 }; 3516 3517 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3518 .get_cdclk = bxt_get_cdclk, 3519 .set_cdclk = bxt_set_cdclk, 3520 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3521 .calc_voltage_level = rplu_calc_voltage_level, 3522 }; 3523 3524 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3525 .get_cdclk = bxt_get_cdclk, 3526 .set_cdclk = bxt_set_cdclk, 3527 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3528 .calc_voltage_level = tgl_calc_voltage_level, 3529 }; 3530 3531 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3532 .get_cdclk = bxt_get_cdclk, 3533 .set_cdclk = bxt_set_cdclk, 3534 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3535 .calc_voltage_level = ehl_calc_voltage_level, 3536 }; 3537 3538 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3539 .get_cdclk = bxt_get_cdclk, 3540 .set_cdclk = bxt_set_cdclk, 3541 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3542 .calc_voltage_level = icl_calc_voltage_level, 3543 }; 3544 3545 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3546 .get_cdclk = bxt_get_cdclk, 3547 .set_cdclk = bxt_set_cdclk, 3548 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3549 .calc_voltage_level = bxt_calc_voltage_level, 3550 }; 3551 3552 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3553 .get_cdclk = skl_get_cdclk, 3554 .set_cdclk = skl_set_cdclk, 3555 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3556 }; 3557 3558 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3559 .get_cdclk = bdw_get_cdclk, 3560 .set_cdclk = bdw_set_cdclk, 3561 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3562 }; 3563 3564 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3565 .get_cdclk = vlv_get_cdclk, 3566 .set_cdclk = chv_set_cdclk, 3567 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3568 }; 3569 3570 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3571 .get_cdclk = vlv_get_cdclk, 3572 .set_cdclk = vlv_set_cdclk, 3573 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3574 }; 3575 3576 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3577 .get_cdclk = hsw_get_cdclk, 3578 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3579 }; 3580 3581 /* SNB, IVB, 965G, 945G */ 3582 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3583 .get_cdclk = fixed_400mhz_get_cdclk, 3584 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3585 }; 3586 3587 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3588 .get_cdclk = fixed_450mhz_get_cdclk, 3589 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3590 }; 3591 3592 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3593 .get_cdclk = gm45_get_cdclk, 3594 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3595 }; 3596 3597 /* G45 uses G33 */ 3598 3599 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3600 .get_cdclk = i965gm_get_cdclk, 3601 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3602 }; 3603 3604 /* i965G uses fixed 400 */ 3605 3606 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3607 .get_cdclk = pnv_get_cdclk, 3608 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3609 }; 3610 3611 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3612 .get_cdclk = g33_get_cdclk, 3613 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3614 }; 3615 3616 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3617 .get_cdclk = i945gm_get_cdclk, 3618 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3619 }; 3620 3621 /* i945G uses fixed 400 */ 3622 3623 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3624 .get_cdclk = i915gm_get_cdclk, 3625 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3626 }; 3627 3628 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3629 .get_cdclk = fixed_333mhz_get_cdclk, 3630 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3631 }; 3632 3633 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3634 .get_cdclk = fixed_266mhz_get_cdclk, 3635 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3636 }; 3637 3638 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3639 .get_cdclk = i85x_get_cdclk, 3640 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3641 }; 3642 3643 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3644 .get_cdclk = fixed_200mhz_get_cdclk, 3645 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3646 }; 3647 3648 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3649 .get_cdclk = fixed_133mhz_get_cdclk, 3650 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3651 }; 3652 3653 /** 3654 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3655 * @dev_priv: i915 device 3656 */ 3657 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 3658 { 3659 if (DISPLAY_VER(dev_priv) >= 20) { 3660 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; 3661 dev_priv->display.cdclk.table = lnl_cdclk_table; 3662 } else if (DISPLAY_VER(dev_priv) >= 14) { 3663 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; 3664 dev_priv->display.cdclk.table = mtl_cdclk_table; 3665 } else if (IS_DG2(dev_priv)) { 3666 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3667 dev_priv->display.cdclk.table = dg2_cdclk_table; 3668 } else if (IS_ALDERLAKE_P(dev_priv)) { 3669 /* Wa_22011320316:adl-p[a0] */ 3670 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 3671 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; 3672 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3673 } else if (IS_RAPTORLAKE_U(dev_priv)) { 3674 dev_priv->display.cdclk.table = rplu_cdclk_table; 3675 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; 3676 } else { 3677 dev_priv->display.cdclk.table = adlp_cdclk_table; 3678 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3679 } 3680 } else if (IS_ROCKETLAKE(dev_priv)) { 3681 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3682 dev_priv->display.cdclk.table = rkl_cdclk_table; 3683 } else if (DISPLAY_VER(dev_priv) >= 12) { 3684 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3685 dev_priv->display.cdclk.table = icl_cdclk_table; 3686 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 3687 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; 3688 dev_priv->display.cdclk.table = icl_cdclk_table; 3689 } else if (DISPLAY_VER(dev_priv) >= 11) { 3690 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; 3691 dev_priv->display.cdclk.table = icl_cdclk_table; 3692 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 3693 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; 3694 if (IS_GEMINILAKE(dev_priv)) 3695 dev_priv->display.cdclk.table = glk_cdclk_table; 3696 else 3697 dev_priv->display.cdclk.table = bxt_cdclk_table; 3698 } else if (DISPLAY_VER(dev_priv) == 9) { 3699 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; 3700 } else if (IS_BROADWELL(dev_priv)) { 3701 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; 3702 } else if (IS_HASWELL(dev_priv)) { 3703 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; 3704 } else if (IS_CHERRYVIEW(dev_priv)) { 3705 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; 3706 } else if (IS_VALLEYVIEW(dev_priv)) { 3707 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; 3708 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 3709 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3710 } else if (IS_IRONLAKE(dev_priv)) { 3711 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; 3712 } else if (IS_GM45(dev_priv)) { 3713 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; 3714 } else if (IS_G45(dev_priv)) { 3715 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3716 } else if (IS_I965GM(dev_priv)) { 3717 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; 3718 } else if (IS_I965G(dev_priv)) { 3719 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3720 } else if (IS_PINEVIEW(dev_priv)) { 3721 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; 3722 } else if (IS_G33(dev_priv)) { 3723 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3724 } else if (IS_I945GM(dev_priv)) { 3725 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; 3726 } else if (IS_I945G(dev_priv)) { 3727 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3728 } else if (IS_I915GM(dev_priv)) { 3729 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; 3730 } else if (IS_I915G(dev_priv)) { 3731 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; 3732 } else if (IS_I865G(dev_priv)) { 3733 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; 3734 } else if (IS_I85X(dev_priv)) { 3735 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; 3736 } else if (IS_I845G(dev_priv)) { 3737 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; 3738 } else if (IS_I830(dev_priv)) { 3739 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3740 } 3741 3742 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, 3743 "Unknown platform. Assuming i830\n")) 3744 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3745 } 3746