1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/time.h> 25 26 #include "soc/intel_dram.h" 27 #include "hsw_ips.h" 28 #include "i915_reg.h" 29 #include "intel_atomic.h" 30 #include "intel_atomic_plane.h" 31 #include "intel_audio.h" 32 #include "intel_bw.h" 33 #include "intel_cdclk.h" 34 #include "intel_crtc.h" 35 #include "intel_de.h" 36 #include "intel_dp.h" 37 #include "intel_display_types.h" 38 #include "intel_mchbar_regs.h" 39 #include "intel_pci_config.h" 40 #include "intel_pcode.h" 41 #include "intel_psr.h" 42 #include "intel_vdsc.h" 43 #include "skl_watermark.h" 44 #include "skl_watermark_regs.h" 45 #include "vlv_sideband.h" 46 47 /** 48 * DOC: CDCLK / RAWCLK 49 * 50 * The display engine uses several different clocks to do its work. There 51 * are two main clocks involved that aren't directly related to the actual 52 * pixel clock or any symbol/bit clock of the actual output port. These 53 * are the core display clock (CDCLK) and RAWCLK. 54 * 55 * CDCLK clocks most of the display pipe logic, and thus its frequency 56 * must be high enough to support the rate at which pixels are flowing 57 * through the pipes. Downscaling must also be accounted as that increases 58 * the effective pixel rate. 59 * 60 * On several platforms the CDCLK frequency can be changed dynamically 61 * to minimize power consumption for a given display configuration. 62 * Typically changes to the CDCLK frequency require all the display pipes 63 * to be shut down while the frequency is being changed. 64 * 65 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 66 * DMC will not change the active CDCLK frequency however, so that part 67 * will still be performed by the driver directly. 68 * 69 * There are multiple components involved in the generation of the CDCLK 70 * frequency: 71 * 72 * - We have the CDCLK PLL, which generates an output clock based on a 73 * reference clock and a ratio parameter. 74 * - The CD2X Divider, which divides the output of the PLL based on a 75 * divisor selected from a set of pre-defined choices. 76 * - The CD2X Squasher, which further divides the output based on a 77 * waveform represented as a sequence of bits where each zero 78 * "squashes out" a clock cycle. 79 * - And, finally, a fixed divider that divides the output frequency by 2. 80 * 81 * As such, the resulting CDCLK frequency can be calculated with the 82 * following formula: 83 * 84 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 85 * 86 * , where vco is the frequency generated by the PLL; cd2x_div 87 * represents the CD2X Divider; sq_len and sq_div are the bit length 88 * and the number of high bits for the CD2X Squasher waveform, respectively; 89 * and 2 represents the fixed divider. 90 * 91 * Note that some older platforms do not contain the CD2X Divider 92 * and/or CD2X Squasher, in which case we can ignore their respective 93 * factors in the formula above. 94 * 95 * Several methods exist to change the CDCLK frequency, which ones are 96 * supported depends on the platform: 97 * 98 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 99 * - CD2X divider update. Single pipe can be active as the divider update 100 * can be synchronized with the pipe's start of vblank. 101 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 102 * - Squash waveform update. Pipes can be active. 103 * - Crawl and squash can also be done back to back. Pipes can be active. 104 * 105 * RAWCLK is a fixed frequency clock, often used by various auxiliary 106 * blocks such as AUX CH or backlight PWM. Hence the only thing we 107 * really need to know about RAWCLK is its frequency so that various 108 * dividers can be programmed correctly. 109 */ 110 111 struct intel_cdclk_funcs { 112 void (*get_cdclk)(struct drm_i915_private *i915, 113 struct intel_cdclk_config *cdclk_config); 114 void (*set_cdclk)(struct drm_i915_private *i915, 115 const struct intel_cdclk_config *cdclk_config, 116 enum pipe pipe); 117 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 118 u8 (*calc_voltage_level)(int cdclk); 119 }; 120 121 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, 122 struct intel_cdclk_config *cdclk_config) 123 { 124 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); 125 } 126 127 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, 128 const struct intel_cdclk_config *cdclk_config, 129 enum pipe pipe) 130 { 131 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); 132 } 133 134 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 135 { 136 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 137 138 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(state); 139 } 140 141 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, 142 int cdclk) 143 { 144 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); 145 } 146 147 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 148 struct intel_cdclk_config *cdclk_config) 149 { 150 cdclk_config->cdclk = 133333; 151 } 152 153 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 154 struct intel_cdclk_config *cdclk_config) 155 { 156 cdclk_config->cdclk = 200000; 157 } 158 159 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 160 struct intel_cdclk_config *cdclk_config) 161 { 162 cdclk_config->cdclk = 266667; 163 } 164 165 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 166 struct intel_cdclk_config *cdclk_config) 167 { 168 cdclk_config->cdclk = 333333; 169 } 170 171 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 172 struct intel_cdclk_config *cdclk_config) 173 { 174 cdclk_config->cdclk = 400000; 175 } 176 177 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 178 struct intel_cdclk_config *cdclk_config) 179 { 180 cdclk_config->cdclk = 450000; 181 } 182 183 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 184 struct intel_cdclk_config *cdclk_config) 185 { 186 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 187 u16 hpllcc = 0; 188 189 /* 190 * 852GM/852GMV only supports 133 MHz and the HPLLCC 191 * encoding is different :( 192 * FIXME is this the right way to detect 852GM/852GMV? 193 */ 194 if (pdev->revision == 0x1) { 195 cdclk_config->cdclk = 133333; 196 return; 197 } 198 199 pci_bus_read_config_word(pdev->bus, 200 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 201 202 /* Assume that the hardware is in the high speed state. This 203 * should be the default. 204 */ 205 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 206 case GC_CLOCK_133_200: 207 case GC_CLOCK_133_200_2: 208 case GC_CLOCK_100_200: 209 cdclk_config->cdclk = 200000; 210 break; 211 case GC_CLOCK_166_250: 212 cdclk_config->cdclk = 250000; 213 break; 214 case GC_CLOCK_100_133: 215 cdclk_config->cdclk = 133333; 216 break; 217 case GC_CLOCK_133_266: 218 case GC_CLOCK_133_266_2: 219 case GC_CLOCK_166_266: 220 cdclk_config->cdclk = 266667; 221 break; 222 } 223 } 224 225 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 226 struct intel_cdclk_config *cdclk_config) 227 { 228 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 229 u16 gcfgc = 0; 230 231 pci_read_config_word(pdev, GCFGC, &gcfgc); 232 233 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 234 cdclk_config->cdclk = 133333; 235 return; 236 } 237 238 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 239 case GC_DISPLAY_CLOCK_333_320_MHZ: 240 cdclk_config->cdclk = 333333; 241 break; 242 default: 243 case GC_DISPLAY_CLOCK_190_200_MHZ: 244 cdclk_config->cdclk = 190000; 245 break; 246 } 247 } 248 249 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 250 struct intel_cdclk_config *cdclk_config) 251 { 252 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 253 u16 gcfgc = 0; 254 255 pci_read_config_word(pdev, GCFGC, &gcfgc); 256 257 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 258 cdclk_config->cdclk = 133333; 259 return; 260 } 261 262 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 263 case GC_DISPLAY_CLOCK_333_320_MHZ: 264 cdclk_config->cdclk = 320000; 265 break; 266 default: 267 case GC_DISPLAY_CLOCK_190_200_MHZ: 268 cdclk_config->cdclk = 200000; 269 break; 270 } 271 } 272 273 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 274 { 275 static const unsigned int blb_vco[8] = { 276 [0] = 3200000, 277 [1] = 4000000, 278 [2] = 5333333, 279 [3] = 4800000, 280 [4] = 6400000, 281 }; 282 static const unsigned int pnv_vco[8] = { 283 [0] = 3200000, 284 [1] = 4000000, 285 [2] = 5333333, 286 [3] = 4800000, 287 [4] = 2666667, 288 }; 289 static const unsigned int cl_vco[8] = { 290 [0] = 3200000, 291 [1] = 4000000, 292 [2] = 5333333, 293 [3] = 6400000, 294 [4] = 3333333, 295 [5] = 3566667, 296 [6] = 4266667, 297 }; 298 static const unsigned int elk_vco[8] = { 299 [0] = 3200000, 300 [1] = 4000000, 301 [2] = 5333333, 302 [3] = 4800000, 303 }; 304 static const unsigned int ctg_vco[8] = { 305 [0] = 3200000, 306 [1] = 4000000, 307 [2] = 5333333, 308 [3] = 6400000, 309 [4] = 2666667, 310 [5] = 4266667, 311 }; 312 const unsigned int *vco_table; 313 unsigned int vco; 314 u8 tmp = 0; 315 316 /* FIXME other chipsets? */ 317 if (IS_GM45(dev_priv)) 318 vco_table = ctg_vco; 319 else if (IS_G45(dev_priv)) 320 vco_table = elk_vco; 321 else if (IS_I965GM(dev_priv)) 322 vco_table = cl_vco; 323 else if (IS_PINEVIEW(dev_priv)) 324 vco_table = pnv_vco; 325 else if (IS_G33(dev_priv)) 326 vco_table = blb_vco; 327 else 328 return 0; 329 330 tmp = intel_de_read(dev_priv, 331 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 332 333 vco = vco_table[tmp & 0x7]; 334 if (vco == 0) 335 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 336 tmp); 337 else 338 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); 339 340 return vco; 341 } 342 343 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 344 struct intel_cdclk_config *cdclk_config) 345 { 346 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 347 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 348 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 349 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 350 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 351 const u8 *div_table; 352 unsigned int cdclk_sel; 353 u16 tmp = 0; 354 355 cdclk_config->vco = intel_hpll_vco(dev_priv); 356 357 pci_read_config_word(pdev, GCFGC, &tmp); 358 359 cdclk_sel = (tmp >> 4) & 0x7; 360 361 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 362 goto fail; 363 364 switch (cdclk_config->vco) { 365 case 3200000: 366 div_table = div_3200; 367 break; 368 case 4000000: 369 div_table = div_4000; 370 break; 371 case 4800000: 372 div_table = div_4800; 373 break; 374 case 5333333: 375 div_table = div_5333; 376 break; 377 default: 378 goto fail; 379 } 380 381 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 382 div_table[cdclk_sel]); 383 return; 384 385 fail: 386 drm_err(&dev_priv->drm, 387 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 388 cdclk_config->vco, tmp); 389 cdclk_config->cdclk = 190476; 390 } 391 392 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 393 struct intel_cdclk_config *cdclk_config) 394 { 395 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 396 u16 gcfgc = 0; 397 398 pci_read_config_word(pdev, GCFGC, &gcfgc); 399 400 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 401 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 402 cdclk_config->cdclk = 266667; 403 break; 404 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 405 cdclk_config->cdclk = 333333; 406 break; 407 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 408 cdclk_config->cdclk = 444444; 409 break; 410 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 411 cdclk_config->cdclk = 200000; 412 break; 413 default: 414 drm_err(&dev_priv->drm, 415 "Unknown pnv display core clock 0x%04x\n", gcfgc); 416 fallthrough; 417 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 418 cdclk_config->cdclk = 133333; 419 break; 420 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 421 cdclk_config->cdclk = 166667; 422 break; 423 } 424 } 425 426 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 427 struct intel_cdclk_config *cdclk_config) 428 { 429 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 430 static const u8 div_3200[] = { 16, 10, 8 }; 431 static const u8 div_4000[] = { 20, 12, 10 }; 432 static const u8 div_5333[] = { 24, 16, 14 }; 433 const u8 *div_table; 434 unsigned int cdclk_sel; 435 u16 tmp = 0; 436 437 cdclk_config->vco = intel_hpll_vco(dev_priv); 438 439 pci_read_config_word(pdev, GCFGC, &tmp); 440 441 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 442 443 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 444 goto fail; 445 446 switch (cdclk_config->vco) { 447 case 3200000: 448 div_table = div_3200; 449 break; 450 case 4000000: 451 div_table = div_4000; 452 break; 453 case 5333333: 454 div_table = div_5333; 455 break; 456 default: 457 goto fail; 458 } 459 460 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 461 div_table[cdclk_sel]); 462 return; 463 464 fail: 465 drm_err(&dev_priv->drm, 466 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 467 cdclk_config->vco, tmp); 468 cdclk_config->cdclk = 200000; 469 } 470 471 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 472 struct intel_cdclk_config *cdclk_config) 473 { 474 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 475 unsigned int cdclk_sel; 476 u16 tmp = 0; 477 478 cdclk_config->vco = intel_hpll_vco(dev_priv); 479 480 pci_read_config_word(pdev, GCFGC, &tmp); 481 482 cdclk_sel = (tmp >> 12) & 0x1; 483 484 switch (cdclk_config->vco) { 485 case 2666667: 486 case 4000000: 487 case 5333333: 488 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 489 break; 490 case 3200000: 491 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 492 break; 493 default: 494 drm_err(&dev_priv->drm, 495 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 496 cdclk_config->vco, tmp); 497 cdclk_config->cdclk = 222222; 498 break; 499 } 500 } 501 502 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 503 struct intel_cdclk_config *cdclk_config) 504 { 505 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 506 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 507 508 if (lcpll & LCPLL_CD_SOURCE_FCLK) 509 cdclk_config->cdclk = 800000; 510 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 511 cdclk_config->cdclk = 450000; 512 else if (freq == LCPLL_CLK_FREQ_450) 513 cdclk_config->cdclk = 450000; 514 else if (IS_HASWELL_ULT(dev_priv)) 515 cdclk_config->cdclk = 337500; 516 else 517 cdclk_config->cdclk = 540000; 518 } 519 520 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 521 { 522 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 523 333333 : 320000; 524 525 /* 526 * We seem to get an unstable or solid color picture at 200MHz. 527 * Not sure what's wrong. For now use 200MHz only when all pipes 528 * are off. 529 */ 530 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 531 return 400000; 532 else if (min_cdclk > 266667) 533 return freq_320; 534 else if (min_cdclk > 0) 535 return 266667; 536 else 537 return 200000; 538 } 539 540 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 541 { 542 if (IS_VALLEYVIEW(dev_priv)) { 543 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 544 return 2; 545 else if (cdclk >= 266667) 546 return 1; 547 else 548 return 0; 549 } else { 550 /* 551 * Specs are full of misinformation, but testing on actual 552 * hardware has shown that we just need to write the desired 553 * CCK divider into the Punit register. 554 */ 555 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 556 } 557 } 558 559 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 560 struct intel_cdclk_config *cdclk_config) 561 { 562 u32 val; 563 564 vlv_iosf_sb_get(dev_priv, 565 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 566 567 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 568 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 569 CCK_DISPLAY_CLOCK_CONTROL, 570 cdclk_config->vco); 571 572 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 573 574 vlv_iosf_sb_put(dev_priv, 575 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 576 577 if (IS_VALLEYVIEW(dev_priv)) 578 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 579 DSPFREQGUAR_SHIFT; 580 else 581 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 582 DSPFREQGUAR_SHIFT_CHV; 583 } 584 585 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 586 { 587 unsigned int credits, default_credits; 588 589 if (IS_CHERRYVIEW(dev_priv)) 590 default_credits = PFI_CREDIT(12); 591 else 592 default_credits = PFI_CREDIT(8); 593 594 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { 595 /* CHV suggested value is 31 or 63 */ 596 if (IS_CHERRYVIEW(dev_priv)) 597 credits = PFI_CREDIT_63; 598 else 599 credits = PFI_CREDIT(15); 600 } else { 601 credits = default_credits; 602 } 603 604 /* 605 * WA - write default credits before re-programming 606 * FIXME: should we also set the resend bit here? 607 */ 608 intel_de_write(dev_priv, GCI_CONTROL, 609 VGA_FAST_MODE_DISABLE | default_credits); 610 611 intel_de_write(dev_priv, GCI_CONTROL, 612 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 613 614 /* 615 * FIXME is this guaranteed to clear 616 * immediately or should we poll for it? 617 */ 618 drm_WARN_ON(&dev_priv->drm, 619 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); 620 } 621 622 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 623 const struct intel_cdclk_config *cdclk_config, 624 enum pipe pipe) 625 { 626 int cdclk = cdclk_config->cdclk; 627 u32 val, cmd = cdclk_config->voltage_level; 628 intel_wakeref_t wakeref; 629 630 switch (cdclk) { 631 case 400000: 632 case 333333: 633 case 320000: 634 case 266667: 635 case 200000: 636 break; 637 default: 638 MISSING_CASE(cdclk); 639 return; 640 } 641 642 /* There are cases where we can end up here with power domains 643 * off and a CDCLK frequency other than the minimum, like when 644 * issuing a modeset without actually changing any display after 645 * a system suspend. So grab the display core domain, which covers 646 * the HW blocks needed for the following programming. 647 */ 648 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 649 650 vlv_iosf_sb_get(dev_priv, 651 BIT(VLV_IOSF_SB_CCK) | 652 BIT(VLV_IOSF_SB_BUNIT) | 653 BIT(VLV_IOSF_SB_PUNIT)); 654 655 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 656 val &= ~DSPFREQGUAR_MASK; 657 val |= (cmd << DSPFREQGUAR_SHIFT); 658 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 659 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 660 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 661 50)) { 662 drm_err(&dev_priv->drm, 663 "timed out waiting for CDclk change\n"); 664 } 665 666 if (cdclk == 400000) { 667 u32 divider; 668 669 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 670 cdclk) - 1; 671 672 /* adjust cdclk divider */ 673 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 674 val &= ~CCK_FREQUENCY_VALUES; 675 val |= divider; 676 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 677 678 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 679 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 680 50)) 681 drm_err(&dev_priv->drm, 682 "timed out waiting for CDclk change\n"); 683 } 684 685 /* adjust self-refresh exit latency value */ 686 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 687 val &= ~0x7f; 688 689 /* 690 * For high bandwidth configs, we set a higher latency in the bunit 691 * so that the core display fetch happens in time to avoid underruns. 692 */ 693 if (cdclk == 400000) 694 val |= 4500 / 250; /* 4.5 usec */ 695 else 696 val |= 3000 / 250; /* 3.0 usec */ 697 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 698 699 vlv_iosf_sb_put(dev_priv, 700 BIT(VLV_IOSF_SB_CCK) | 701 BIT(VLV_IOSF_SB_BUNIT) | 702 BIT(VLV_IOSF_SB_PUNIT)); 703 704 intel_update_cdclk(dev_priv); 705 706 vlv_program_pfi_credits(dev_priv); 707 708 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 709 } 710 711 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 712 const struct intel_cdclk_config *cdclk_config, 713 enum pipe pipe) 714 { 715 int cdclk = cdclk_config->cdclk; 716 u32 val, cmd = cdclk_config->voltage_level; 717 intel_wakeref_t wakeref; 718 719 switch (cdclk) { 720 case 333333: 721 case 320000: 722 case 266667: 723 case 200000: 724 break; 725 default: 726 MISSING_CASE(cdclk); 727 return; 728 } 729 730 /* There are cases where we can end up here with power domains 731 * off and a CDCLK frequency other than the minimum, like when 732 * issuing a modeset without actually changing any display after 733 * a system suspend. So grab the display core domain, which covers 734 * the HW blocks needed for the following programming. 735 */ 736 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 737 738 vlv_punit_get(dev_priv); 739 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 740 val &= ~DSPFREQGUAR_MASK_CHV; 741 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 742 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 743 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 744 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 745 50)) { 746 drm_err(&dev_priv->drm, 747 "timed out waiting for CDclk change\n"); 748 } 749 750 vlv_punit_put(dev_priv); 751 752 intel_update_cdclk(dev_priv); 753 754 vlv_program_pfi_credits(dev_priv); 755 756 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 757 } 758 759 static int bdw_calc_cdclk(int min_cdclk) 760 { 761 if (min_cdclk > 540000) 762 return 675000; 763 else if (min_cdclk > 450000) 764 return 540000; 765 else if (min_cdclk > 337500) 766 return 450000; 767 else 768 return 337500; 769 } 770 771 static u8 bdw_calc_voltage_level(int cdclk) 772 { 773 switch (cdclk) { 774 default: 775 case 337500: 776 return 2; 777 case 450000: 778 return 0; 779 case 540000: 780 return 1; 781 case 675000: 782 return 3; 783 } 784 } 785 786 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 787 struct intel_cdclk_config *cdclk_config) 788 { 789 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 790 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 791 792 if (lcpll & LCPLL_CD_SOURCE_FCLK) 793 cdclk_config->cdclk = 800000; 794 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 795 cdclk_config->cdclk = 450000; 796 else if (freq == LCPLL_CLK_FREQ_450) 797 cdclk_config->cdclk = 450000; 798 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 799 cdclk_config->cdclk = 540000; 800 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 801 cdclk_config->cdclk = 337500; 802 else 803 cdclk_config->cdclk = 675000; 804 805 /* 806 * Can't read this out :( Let's assume it's 807 * at least what the CDCLK frequency requires. 808 */ 809 cdclk_config->voltage_level = 810 bdw_calc_voltage_level(cdclk_config->cdclk); 811 } 812 813 static u32 bdw_cdclk_freq_sel(int cdclk) 814 { 815 switch (cdclk) { 816 default: 817 MISSING_CASE(cdclk); 818 fallthrough; 819 case 337500: 820 return LCPLL_CLK_FREQ_337_5_BDW; 821 case 450000: 822 return LCPLL_CLK_FREQ_450; 823 case 540000: 824 return LCPLL_CLK_FREQ_54O_BDW; 825 case 675000: 826 return LCPLL_CLK_FREQ_675_BDW; 827 } 828 } 829 830 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 831 const struct intel_cdclk_config *cdclk_config, 832 enum pipe pipe) 833 { 834 int cdclk = cdclk_config->cdclk; 835 int ret; 836 837 if (drm_WARN(&dev_priv->drm, 838 (intel_de_read(dev_priv, LCPLL_CTL) & 839 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 840 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 841 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 842 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 843 "trying to change cdclk frequency with cdclk not enabled\n")) 844 return; 845 846 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 847 if (ret) { 848 drm_err(&dev_priv->drm, 849 "failed to inform pcode about cdclk change\n"); 850 return; 851 } 852 853 intel_de_rmw(dev_priv, LCPLL_CTL, 854 0, LCPLL_CD_SOURCE_FCLK); 855 856 /* 857 * According to the spec, it should be enough to poll for this 1 us. 858 * However, extensive testing shows that this can take longer. 859 */ 860 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 861 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 862 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 863 864 intel_de_rmw(dev_priv, LCPLL_CTL, 865 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 866 867 intel_de_rmw(dev_priv, LCPLL_CTL, 868 LCPLL_CD_SOURCE_FCLK, 0); 869 870 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 871 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 872 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); 873 874 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, 875 cdclk_config->voltage_level); 876 877 intel_de_write(dev_priv, CDCLK_FREQ, 878 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 879 880 intel_update_cdclk(dev_priv); 881 } 882 883 static int skl_calc_cdclk(int min_cdclk, int vco) 884 { 885 if (vco == 8640000) { 886 if (min_cdclk > 540000) 887 return 617143; 888 else if (min_cdclk > 432000) 889 return 540000; 890 else if (min_cdclk > 308571) 891 return 432000; 892 else 893 return 308571; 894 } else { 895 if (min_cdclk > 540000) 896 return 675000; 897 else if (min_cdclk > 450000) 898 return 540000; 899 else if (min_cdclk > 337500) 900 return 450000; 901 else 902 return 337500; 903 } 904 } 905 906 static u8 skl_calc_voltage_level(int cdclk) 907 { 908 if (cdclk > 540000) 909 return 3; 910 else if (cdclk > 450000) 911 return 2; 912 else if (cdclk > 337500) 913 return 1; 914 else 915 return 0; 916 } 917 918 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 919 struct intel_cdclk_config *cdclk_config) 920 { 921 u32 val; 922 923 cdclk_config->ref = 24000; 924 cdclk_config->vco = 0; 925 926 val = intel_de_read(dev_priv, LCPLL1_CTL); 927 if ((val & LCPLL_PLL_ENABLE) == 0) 928 return; 929 930 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) 931 return; 932 933 val = intel_de_read(dev_priv, DPLL_CTRL1); 934 935 if (drm_WARN_ON(&dev_priv->drm, 936 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 937 DPLL_CTRL1_SSC(SKL_DPLL0) | 938 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 939 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 940 return; 941 942 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 943 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 944 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 945 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 946 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 947 cdclk_config->vco = 8100000; 948 break; 949 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 950 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 951 cdclk_config->vco = 8640000; 952 break; 953 default: 954 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 955 break; 956 } 957 } 958 959 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 960 struct intel_cdclk_config *cdclk_config) 961 { 962 u32 cdctl; 963 964 skl_dpll0_update(dev_priv, cdclk_config); 965 966 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 967 968 if (cdclk_config->vco == 0) 969 goto out; 970 971 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 972 973 if (cdclk_config->vco == 8640000) { 974 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 975 case CDCLK_FREQ_450_432: 976 cdclk_config->cdclk = 432000; 977 break; 978 case CDCLK_FREQ_337_308: 979 cdclk_config->cdclk = 308571; 980 break; 981 case CDCLK_FREQ_540: 982 cdclk_config->cdclk = 540000; 983 break; 984 case CDCLK_FREQ_675_617: 985 cdclk_config->cdclk = 617143; 986 break; 987 default: 988 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 989 break; 990 } 991 } else { 992 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 993 case CDCLK_FREQ_450_432: 994 cdclk_config->cdclk = 450000; 995 break; 996 case CDCLK_FREQ_337_308: 997 cdclk_config->cdclk = 337500; 998 break; 999 case CDCLK_FREQ_540: 1000 cdclk_config->cdclk = 540000; 1001 break; 1002 case CDCLK_FREQ_675_617: 1003 cdclk_config->cdclk = 675000; 1004 break; 1005 default: 1006 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1007 break; 1008 } 1009 } 1010 1011 out: 1012 /* 1013 * Can't read this out :( Let's assume it's 1014 * at least what the CDCLK frequency requires. 1015 */ 1016 cdclk_config->voltage_level = 1017 skl_calc_voltage_level(cdclk_config->cdclk); 1018 } 1019 1020 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1021 static int skl_cdclk_decimal(int cdclk) 1022 { 1023 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1024 } 1025 1026 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *i915, int vco) 1027 { 1028 bool changed = i915->display.cdclk.skl_preferred_vco_freq != vco; 1029 1030 i915->display.cdclk.skl_preferred_vco_freq = vco; 1031 1032 if (changed) 1033 intel_update_max_cdclk(i915); 1034 } 1035 1036 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) 1037 { 1038 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 1039 1040 /* 1041 * We always enable DPLL0 with the lowest link rate possible, but still 1042 * taking into account the VCO required to operate the eDP panel at the 1043 * desired frequency. The usual DP link rates operate with a VCO of 1044 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1045 * The modeset code is responsible for the selection of the exact link 1046 * rate later on, with the constraint of choosing a frequency that 1047 * works with vco. 1048 */ 1049 if (vco == 8640000) 1050 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1051 else 1052 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1053 } 1054 1055 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 1056 { 1057 intel_de_rmw(dev_priv, DPLL_CTRL1, 1058 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1059 DPLL_CTRL1_SSC(SKL_DPLL0) | 1060 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1061 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1062 skl_dpll0_link_rate(dev_priv, vco)); 1063 intel_de_posting_read(dev_priv, DPLL_CTRL1); 1064 1065 intel_de_rmw(dev_priv, LCPLL1_CTL, 1066 0, LCPLL_PLL_ENABLE); 1067 1068 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1069 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); 1070 1071 dev_priv->display.cdclk.hw.vco = vco; 1072 1073 /* We'll want to keep using the current vco from now on. */ 1074 skl_set_preferred_cdclk_vco(dev_priv, vco); 1075 } 1076 1077 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 1078 { 1079 intel_de_rmw(dev_priv, LCPLL1_CTL, 1080 LCPLL_PLL_ENABLE, 0); 1081 1082 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1083 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); 1084 1085 dev_priv->display.cdclk.hw.vco = 0; 1086 } 1087 1088 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, 1089 int cdclk, int vco) 1090 { 1091 switch (cdclk) { 1092 default: 1093 drm_WARN_ON(&dev_priv->drm, 1094 cdclk != dev_priv->display.cdclk.hw.bypass); 1095 drm_WARN_ON(&dev_priv->drm, vco != 0); 1096 fallthrough; 1097 case 308571: 1098 case 337500: 1099 return CDCLK_FREQ_337_308; 1100 case 450000: 1101 case 432000: 1102 return CDCLK_FREQ_450_432; 1103 case 540000: 1104 return CDCLK_FREQ_540; 1105 case 617143: 1106 case 675000: 1107 return CDCLK_FREQ_675_617; 1108 } 1109 } 1110 1111 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 1112 const struct intel_cdclk_config *cdclk_config, 1113 enum pipe pipe) 1114 { 1115 int cdclk = cdclk_config->cdclk; 1116 int vco = cdclk_config->vco; 1117 u32 freq_select, cdclk_ctl; 1118 int ret; 1119 1120 /* 1121 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1122 * unsupported on SKL. In theory this should never happen since only 1123 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1124 * supported on SKL either, see the above WA. WARN whenever trying to 1125 * use the corresponding VCO freq as that always leads to using the 1126 * minimum 308MHz CDCLK. 1127 */ 1128 drm_WARN_ON_ONCE(&dev_priv->drm, 1129 IS_SKYLAKE(dev_priv) && vco == 8640000); 1130 1131 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1132 SKL_CDCLK_PREPARE_FOR_CHANGE, 1133 SKL_CDCLK_READY_FOR_CHANGE, 1134 SKL_CDCLK_READY_FOR_CHANGE, 3); 1135 if (ret) { 1136 drm_err(&dev_priv->drm, 1137 "Failed to inform PCU about cdclk change (%d)\n", ret); 1138 return; 1139 } 1140 1141 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); 1142 1143 if (dev_priv->display.cdclk.hw.vco != 0 && 1144 dev_priv->display.cdclk.hw.vco != vco) 1145 skl_dpll0_disable(dev_priv); 1146 1147 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); 1148 1149 if (dev_priv->display.cdclk.hw.vco != vco) { 1150 /* Wa Display #1183: skl,kbl,cfl */ 1151 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1152 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1153 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1154 } 1155 1156 /* Wa Display #1183: skl,kbl,cfl */ 1157 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1158 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1159 intel_de_posting_read(dev_priv, CDCLK_CTL); 1160 1161 if (dev_priv->display.cdclk.hw.vco != vco) 1162 skl_dpll0_enable(dev_priv, vco); 1163 1164 /* Wa Display #1183: skl,kbl,cfl */ 1165 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1166 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1167 1168 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1169 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1170 1171 /* Wa Display #1183: skl,kbl,cfl */ 1172 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1173 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1174 intel_de_posting_read(dev_priv, CDCLK_CTL); 1175 1176 /* inform PCU of the change */ 1177 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1178 cdclk_config->voltage_level); 1179 1180 intel_update_cdclk(dev_priv); 1181 } 1182 1183 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1184 { 1185 u32 cdctl, expected; 1186 1187 /* 1188 * check if the pre-os initialized the display 1189 * There is SWF18 scratchpad register defined which is set by the 1190 * pre-os which can be used by the OS drivers to check the status 1191 */ 1192 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1193 goto sanitize; 1194 1195 intel_update_cdclk(dev_priv); 1196 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1197 1198 /* Is PLL enabled and locked ? */ 1199 if (dev_priv->display.cdclk.hw.vco == 0 || 1200 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 1201 goto sanitize; 1202 1203 /* DPLL okay; verify the cdclock 1204 * 1205 * Noticed in some instances that the freq selection is correct but 1206 * decimal part is programmed wrong from BIOS where pre-os does not 1207 * enable display. Verify the same as well. 1208 */ 1209 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1210 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1211 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); 1212 if (cdctl == expected) 1213 /* All well; nothing to sanitize */ 1214 return; 1215 1216 sanitize: 1217 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1218 1219 /* force cdclk programming */ 1220 dev_priv->display.cdclk.hw.cdclk = 0; 1221 /* force full PLL disable + enable */ 1222 dev_priv->display.cdclk.hw.vco = ~0; 1223 } 1224 1225 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) 1226 { 1227 struct intel_cdclk_config cdclk_config; 1228 1229 skl_sanitize_cdclk(dev_priv); 1230 1231 if (dev_priv->display.cdclk.hw.cdclk != 0 && 1232 dev_priv->display.cdclk.hw.vco != 0) { 1233 /* 1234 * Use the current vco as our initial 1235 * guess as to what the preferred vco is. 1236 */ 1237 if (dev_priv->display.cdclk.skl_preferred_vco_freq == 0) 1238 skl_set_preferred_cdclk_vco(dev_priv, 1239 dev_priv->display.cdclk.hw.vco); 1240 return; 1241 } 1242 1243 cdclk_config = dev_priv->display.cdclk.hw; 1244 1245 cdclk_config.vco = dev_priv->display.cdclk.skl_preferred_vco_freq; 1246 if (cdclk_config.vco == 0) 1247 cdclk_config.vco = 8100000; 1248 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1249 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1250 1251 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1252 } 1253 1254 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1255 { 1256 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 1257 1258 cdclk_config.cdclk = cdclk_config.bypass; 1259 cdclk_config.vco = 0; 1260 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1261 1262 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1263 } 1264 1265 struct intel_cdclk_vals { 1266 u32 cdclk; 1267 u16 refclk; 1268 u16 waveform; 1269 u8 ratio; 1270 }; 1271 1272 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1273 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1274 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1275 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1276 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1277 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1278 {} 1279 }; 1280 1281 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1282 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1283 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1284 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1285 {} 1286 }; 1287 1288 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1289 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1290 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1291 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1292 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1293 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1294 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1295 1296 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1297 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1298 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1299 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1300 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1301 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1302 1303 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1304 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1305 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1306 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1307 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1308 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1309 {} 1310 }; 1311 1312 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1313 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1314 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1315 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1316 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1317 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1318 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1319 1320 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1321 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1322 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1323 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1324 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1325 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1326 1327 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1328 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1329 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1330 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1331 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1332 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1333 {} 1334 }; 1335 1336 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1337 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1338 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1339 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1340 1341 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1342 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1343 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1344 1345 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1346 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1347 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1348 {} 1349 }; 1350 1351 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1352 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1353 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1354 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1355 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1356 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1357 1358 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1359 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1360 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1361 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1362 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1363 1364 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1365 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1366 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1367 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1368 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1369 {} 1370 }; 1371 1372 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1373 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1374 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1375 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1376 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1377 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1378 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1379 1380 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1381 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1382 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1383 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1384 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1385 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1386 1387 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1388 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1389 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1390 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1391 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1392 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1393 {} 1394 }; 1395 1396 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1397 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1398 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1399 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1400 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1401 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1402 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1403 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1404 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1405 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1406 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1407 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1408 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1409 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1410 {} 1411 }; 1412 1413 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1414 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1415 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1416 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1417 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1418 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1419 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1420 {} 1421 }; 1422 1423 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1424 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1425 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1426 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1427 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1428 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1429 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1430 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1431 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1432 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1433 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1434 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1435 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1436 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1437 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1438 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1439 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1440 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1441 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1442 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1443 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1444 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1445 {} 1446 }; 1447 1448 /* 1449 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1450 */ 1451 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1452 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1453 {} 1454 }; 1455 1456 static const int cdclk_squash_len = 16; 1457 1458 static int cdclk_squash_divider(u16 waveform) 1459 { 1460 return hweight16(waveform ?: 0xffff); 1461 } 1462 1463 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1464 { 1465 /* 2 * cd2x divider */ 1466 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1467 cdclk * cdclk_squash_len); 1468 } 1469 1470 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 1471 { 1472 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1473 int i; 1474 1475 for (i = 0; table[i].refclk; i++) 1476 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1477 table[i].cdclk >= min_cdclk) 1478 return table[i].cdclk; 1479 1480 drm_WARN(&dev_priv->drm, 1, 1481 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1482 min_cdclk, dev_priv->display.cdclk.hw.ref); 1483 return 0; 1484 } 1485 1486 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1487 { 1488 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1489 int i; 1490 1491 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1492 return 0; 1493 1494 for (i = 0; table[i].refclk; i++) 1495 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1496 table[i].cdclk == cdclk) 1497 return dev_priv->display.cdclk.hw.ref * table[i].ratio; 1498 1499 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1500 cdclk, dev_priv->display.cdclk.hw.ref); 1501 return 0; 1502 } 1503 1504 static u8 bxt_calc_voltage_level(int cdclk) 1505 { 1506 return DIV_ROUND_UP(cdclk, 25000); 1507 } 1508 1509 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1510 const int voltage_level_max_cdclk[]) 1511 { 1512 int voltage_level; 1513 1514 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1515 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1516 return voltage_level; 1517 } 1518 1519 MISSING_CASE(cdclk); 1520 return num_voltage_levels - 1; 1521 } 1522 1523 static u8 icl_calc_voltage_level(int cdclk) 1524 { 1525 static const int icl_voltage_level_max_cdclk[] = { 1526 [0] = 312000, 1527 [1] = 556800, 1528 [2] = 652800, 1529 }; 1530 1531 return calc_voltage_level(cdclk, 1532 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1533 icl_voltage_level_max_cdclk); 1534 } 1535 1536 static u8 ehl_calc_voltage_level(int cdclk) 1537 { 1538 static const int ehl_voltage_level_max_cdclk[] = { 1539 [0] = 180000, 1540 [1] = 312000, 1541 [2] = 326400, 1542 /* 1543 * Bspec lists the limit as 556.8 MHz, but some JSL 1544 * development boards (at least) boot with 652.8 MHz 1545 */ 1546 [3] = 652800, 1547 }; 1548 1549 return calc_voltage_level(cdclk, 1550 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1551 ehl_voltage_level_max_cdclk); 1552 } 1553 1554 static u8 tgl_calc_voltage_level(int cdclk) 1555 { 1556 static const int tgl_voltage_level_max_cdclk[] = { 1557 [0] = 312000, 1558 [1] = 326400, 1559 [2] = 556800, 1560 [3] = 652800, 1561 }; 1562 1563 return calc_voltage_level(cdclk, 1564 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1565 tgl_voltage_level_max_cdclk); 1566 } 1567 1568 static u8 rplu_calc_voltage_level(int cdclk) 1569 { 1570 static const int rplu_voltage_level_max_cdclk[] = { 1571 [0] = 312000, 1572 [1] = 480000, 1573 [2] = 556800, 1574 [3] = 652800, 1575 }; 1576 1577 return calc_voltage_level(cdclk, 1578 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1579 rplu_voltage_level_max_cdclk); 1580 } 1581 1582 static void icl_readout_refclk(struct drm_i915_private *dev_priv, 1583 struct intel_cdclk_config *cdclk_config) 1584 { 1585 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1586 1587 switch (dssm) { 1588 default: 1589 MISSING_CASE(dssm); 1590 fallthrough; 1591 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1592 cdclk_config->ref = 24000; 1593 break; 1594 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1595 cdclk_config->ref = 19200; 1596 break; 1597 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1598 cdclk_config->ref = 38400; 1599 break; 1600 } 1601 } 1602 1603 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 1604 struct intel_cdclk_config *cdclk_config) 1605 { 1606 u32 val, ratio; 1607 1608 if (IS_DG2(dev_priv)) 1609 cdclk_config->ref = 38400; 1610 else if (DISPLAY_VER(dev_priv) >= 11) 1611 icl_readout_refclk(dev_priv, cdclk_config); 1612 else 1613 cdclk_config->ref = 19200; 1614 1615 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1616 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1617 (val & BXT_DE_PLL_LOCK) == 0) { 1618 /* 1619 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1620 * setting it to zero is a way to signal that. 1621 */ 1622 cdclk_config->vco = 0; 1623 return; 1624 } 1625 1626 /* 1627 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1628 * gen9lp had it in a separate PLL control register. 1629 */ 1630 if (DISPLAY_VER(dev_priv) >= 11) 1631 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1632 else 1633 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1634 1635 cdclk_config->vco = ratio * cdclk_config->ref; 1636 } 1637 1638 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1639 struct intel_cdclk_config *cdclk_config) 1640 { 1641 u32 squash_ctl = 0; 1642 u32 divider; 1643 int div; 1644 1645 bxt_de_pll_readout(dev_priv, cdclk_config); 1646 1647 if (DISPLAY_VER(dev_priv) >= 12) 1648 cdclk_config->bypass = cdclk_config->ref / 2; 1649 else if (DISPLAY_VER(dev_priv) >= 11) 1650 cdclk_config->bypass = 50000; 1651 else 1652 cdclk_config->bypass = cdclk_config->ref; 1653 1654 if (cdclk_config->vco == 0) { 1655 cdclk_config->cdclk = cdclk_config->bypass; 1656 goto out; 1657 } 1658 1659 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1660 1661 switch (divider) { 1662 case BXT_CDCLK_CD2X_DIV_SEL_1: 1663 div = 2; 1664 break; 1665 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1666 div = 3; 1667 break; 1668 case BXT_CDCLK_CD2X_DIV_SEL_2: 1669 div = 4; 1670 break; 1671 case BXT_CDCLK_CD2X_DIV_SEL_4: 1672 div = 8; 1673 break; 1674 default: 1675 MISSING_CASE(divider); 1676 return; 1677 } 1678 1679 if (HAS_CDCLK_SQUASH(dev_priv)) 1680 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); 1681 1682 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1683 u16 waveform; 1684 int size; 1685 1686 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1687 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1688 1689 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1690 cdclk_config->vco, size * div); 1691 } else { 1692 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1693 } 1694 1695 out: 1696 if (DISPLAY_VER(dev_priv) >= 20) 1697 cdclk_config->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN; 1698 /* 1699 * Can't read this out :( Let's assume it's 1700 * at least what the CDCLK frequency requires. 1701 */ 1702 cdclk_config->voltage_level = 1703 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); 1704 } 1705 1706 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1707 { 1708 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1709 1710 /* Timeout 200us */ 1711 if (intel_de_wait_for_clear(dev_priv, 1712 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1713 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); 1714 1715 dev_priv->display.cdclk.hw.vco = 0; 1716 } 1717 1718 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1719 { 1720 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1721 1722 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, 1723 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1724 1725 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1726 1727 /* Timeout 200us */ 1728 if (intel_de_wait_for_set(dev_priv, 1729 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1730 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); 1731 1732 dev_priv->display.cdclk.hw.vco = vco; 1733 } 1734 1735 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1736 { 1737 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, 1738 BXT_DE_PLL_PLL_ENABLE, 0); 1739 1740 /* Timeout 200us */ 1741 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1742 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); 1743 1744 dev_priv->display.cdclk.hw.vco = 0; 1745 } 1746 1747 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1748 { 1749 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1750 u32 val; 1751 1752 val = ICL_CDCLK_PLL_RATIO(ratio); 1753 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1754 1755 val |= BXT_DE_PLL_PLL_ENABLE; 1756 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1757 1758 /* Timeout 200us */ 1759 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1760 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); 1761 1762 dev_priv->display.cdclk.hw.vco = vco; 1763 } 1764 1765 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) 1766 { 1767 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1768 u32 val; 1769 1770 /* Write PLL ratio without disabling */ 1771 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1772 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1773 1774 /* Submit freq change request */ 1775 val |= BXT_DE_PLL_FREQ_REQ; 1776 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1777 1778 /* Timeout 200us */ 1779 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, 1780 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1781 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); 1782 1783 val &= ~BXT_DE_PLL_FREQ_REQ; 1784 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1785 1786 dev_priv->display.cdclk.hw.vco = vco; 1787 } 1788 1789 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1790 { 1791 if (DISPLAY_VER(dev_priv) >= 12) { 1792 if (pipe == INVALID_PIPE) 1793 return TGL_CDCLK_CD2X_PIPE_NONE; 1794 else 1795 return TGL_CDCLK_CD2X_PIPE(pipe); 1796 } else if (DISPLAY_VER(dev_priv) >= 11) { 1797 if (pipe == INVALID_PIPE) 1798 return ICL_CDCLK_CD2X_PIPE_NONE; 1799 else 1800 return ICL_CDCLK_CD2X_PIPE(pipe); 1801 } else { 1802 if (pipe == INVALID_PIPE) 1803 return BXT_CDCLK_CD2X_PIPE_NONE; 1804 else 1805 return BXT_CDCLK_CD2X_PIPE(pipe); 1806 } 1807 } 1808 1809 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, 1810 int cdclk, int vco, u16 waveform) 1811 { 1812 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1813 switch (cdclk_divider(cdclk, vco, waveform)) { 1814 default: 1815 drm_WARN_ON(&dev_priv->drm, 1816 cdclk != dev_priv->display.cdclk.hw.bypass); 1817 drm_WARN_ON(&dev_priv->drm, vco != 0); 1818 fallthrough; 1819 case 2: 1820 return BXT_CDCLK_CD2X_DIV_SEL_1; 1821 case 3: 1822 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1823 case 4: 1824 return BXT_CDCLK_CD2X_DIV_SEL_2; 1825 case 8: 1826 return BXT_CDCLK_CD2X_DIV_SEL_4; 1827 } 1828 } 1829 1830 static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv, 1831 int cdclk) 1832 { 1833 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1834 int i; 1835 1836 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1837 return 0; 1838 1839 for (i = 0; table[i].refclk; i++) 1840 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1841 table[i].cdclk == cdclk) 1842 return table[i].waveform; 1843 1844 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1845 cdclk, dev_priv->display.cdclk.hw.ref); 1846 1847 return 0xffff; 1848 } 1849 1850 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1851 { 1852 if (i915->display.cdclk.hw.vco != 0 && 1853 i915->display.cdclk.hw.vco != vco) 1854 icl_cdclk_pll_disable(i915); 1855 1856 if (i915->display.cdclk.hw.vco != vco) 1857 icl_cdclk_pll_enable(i915, vco); 1858 } 1859 1860 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1861 { 1862 if (i915->display.cdclk.hw.vco != 0 && 1863 i915->display.cdclk.hw.vco != vco) 1864 bxt_de_pll_disable(i915); 1865 1866 if (i915->display.cdclk.hw.vco != vco) 1867 bxt_de_pll_enable(i915, vco); 1868 } 1869 1870 static void dg2_cdclk_squash_program(struct drm_i915_private *i915, 1871 u16 waveform) 1872 { 1873 u32 squash_ctl = 0; 1874 1875 if (waveform) 1876 squash_ctl = CDCLK_SQUASH_ENABLE | 1877 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1878 1879 intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); 1880 } 1881 1882 static bool cdclk_pll_is_unknown(unsigned int vco) 1883 { 1884 /* 1885 * Ensure driver does not take the crawl path for the 1886 * case when the vco is set to ~0 in the 1887 * sanitize path. 1888 */ 1889 return vco == ~0; 1890 } 1891 1892 static bool mdclk_source_is_cdclk_pll(struct drm_i915_private *i915) 1893 { 1894 return DISPLAY_VER(i915) >= 20; 1895 } 1896 1897 static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915) 1898 { 1899 if (mdclk_source_is_cdclk_pll(i915)) 1900 return MDCLK_SOURCE_SEL_CDCLK_PLL; 1901 1902 return MDCLK_SOURCE_SEL_CD2XCLK; 1903 } 1904 1905 int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, 1906 const struct intel_cdclk_config *cdclk_config) 1907 { 1908 if (mdclk_source_is_cdclk_pll(i915)) 1909 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 1910 1911 /* Otherwise, source for MDCLK is CD2XCLK. */ 1912 return 2; 1913 } 1914 1915 static void xe2lpd_mdclk_cdclk_ratio_program(struct drm_i915_private *i915, 1916 const struct intel_cdclk_config *cdclk_config) 1917 { 1918 intel_dbuf_mdclk_cdclk_ratio_update(i915, 1919 intel_mdclk_cdclk_ratio(i915, cdclk_config), 1920 cdclk_config->joined_mbus); 1921 } 1922 1923 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915, 1924 const struct intel_cdclk_config *old_cdclk_config, 1925 const struct intel_cdclk_config *new_cdclk_config, 1926 struct intel_cdclk_config *mid_cdclk_config) 1927 { 1928 u16 old_waveform, new_waveform, mid_waveform; 1929 int old_div, new_div, mid_div; 1930 1931 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 1932 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 1933 return false; 1934 1935 /* Return if both Squash and Crawl are not present */ 1936 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) 1937 return false; 1938 1939 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); 1940 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); 1941 1942 /* Return if Squash only or Crawl only is the desired action */ 1943 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 1944 old_cdclk_config->vco == new_cdclk_config->vco || 1945 old_waveform == new_waveform) 1946 return false; 1947 1948 old_div = cdclk_divider(old_cdclk_config->cdclk, 1949 old_cdclk_config->vco, old_waveform); 1950 new_div = cdclk_divider(new_cdclk_config->cdclk, 1951 new_cdclk_config->vco, new_waveform); 1952 1953 /* 1954 * Should not happen currently. We might need more midpoint 1955 * transitions if we need to also change the cd2x divider. 1956 */ 1957 if (drm_WARN_ON(&i915->drm, old_div != new_div)) 1958 return false; 1959 1960 *mid_cdclk_config = *new_cdclk_config; 1961 1962 /* 1963 * Populate the mid_cdclk_config accordingly. 1964 * - If moving to a higher cdclk, the desired action is squashing. 1965 * The mid cdclk config should have the new (squash) waveform. 1966 * - If moving to a lower cdclk, the desired action is crawling. 1967 * The mid cdclk config should have the new vco. 1968 */ 1969 1970 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 1971 mid_cdclk_config->vco = old_cdclk_config->vco; 1972 mid_div = old_div; 1973 mid_waveform = new_waveform; 1974 } else { 1975 mid_cdclk_config->vco = new_cdclk_config->vco; 1976 mid_div = new_div; 1977 mid_waveform = old_waveform; 1978 } 1979 1980 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 1981 mid_cdclk_config->vco, 1982 cdclk_squash_len * mid_div); 1983 1984 /* make sure the mid clock came out sane */ 1985 1986 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < 1987 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 1988 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > 1989 i915->display.cdclk.max_cdclk_freq); 1990 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != 1991 mid_waveform); 1992 1993 return true; 1994 } 1995 1996 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) 1997 { 1998 return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) || 1999 DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) || 2000 IS_DG2(dev_priv)) && 2001 dev_priv->display.cdclk.hw.vco > 0; 2002 } 2003 2004 static u32 bxt_cdclk_ctl(struct drm_i915_private *i915, 2005 const struct intel_cdclk_config *cdclk_config, 2006 enum pipe pipe) 2007 { 2008 int cdclk = cdclk_config->cdclk; 2009 int vco = cdclk_config->vco; 2010 u16 waveform; 2011 u32 val; 2012 2013 waveform = cdclk_squash_waveform(i915, cdclk); 2014 2015 val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) | 2016 bxt_cdclk_cd2x_pipe(i915, pipe); 2017 2018 /* 2019 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2020 * enable otherwise. 2021 */ 2022 if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) && 2023 cdclk >= 500000) 2024 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2025 2026 if (DISPLAY_VER(i915) >= 20) 2027 val |= xe2lpd_mdclk_source_sel(i915); 2028 else 2029 val |= skl_cdclk_decimal(cdclk); 2030 2031 return val; 2032 } 2033 2034 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, 2035 const struct intel_cdclk_config *cdclk_config, 2036 enum pipe pipe) 2037 { 2038 int cdclk = cdclk_config->cdclk; 2039 int vco = cdclk_config->vco; 2040 2041 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && 2042 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { 2043 if (dev_priv->display.cdclk.hw.vco != vco) 2044 adlp_cdclk_pll_crawl(dev_priv, vco); 2045 } else if (DISPLAY_VER(dev_priv) >= 11) { 2046 /* wa_15010685871: dg2, mtl */ 2047 if (pll_enable_wa_needed(dev_priv)) 2048 dg2_cdclk_squash_program(dev_priv, 0); 2049 2050 icl_cdclk_pll_update(dev_priv, vco); 2051 } else 2052 bxt_cdclk_pll_update(dev_priv, vco); 2053 2054 if (HAS_CDCLK_SQUASH(dev_priv)) { 2055 u16 waveform = cdclk_squash_waveform(dev_priv, cdclk); 2056 2057 dg2_cdclk_squash_program(dev_priv, waveform); 2058 } 2059 2060 intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe)); 2061 2062 if (pipe != INVALID_PIPE) 2063 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 2064 } 2065 2066 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 2067 const struct intel_cdclk_config *cdclk_config, 2068 enum pipe pipe) 2069 { 2070 struct intel_cdclk_config mid_cdclk_config; 2071 int cdclk = cdclk_config->cdclk; 2072 int ret = 0; 2073 2074 /* 2075 * Inform power controller of upcoming frequency change. 2076 * Display versions 14 and beyond do not follow the PUnit 2077 * mailbox communication, skip 2078 * this step. 2079 */ 2080 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) 2081 /* NOOP */; 2082 else if (DISPLAY_VER(dev_priv) >= 11) 2083 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 2084 SKL_CDCLK_PREPARE_FOR_CHANGE, 2085 SKL_CDCLK_READY_FOR_CHANGE, 2086 SKL_CDCLK_READY_FOR_CHANGE, 3); 2087 else 2088 /* 2089 * BSpec requires us to wait up to 150usec, but that leads to 2090 * timeouts; the 2ms used here is based on experiment. 2091 */ 2092 ret = snb_pcode_write_timeout(&dev_priv->uncore, 2093 HSW_PCODE_DE_WRITE_FREQ_REQ, 2094 0x80000000, 150, 2); 2095 2096 if (ret) { 2097 drm_err(&dev_priv->drm, 2098 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2099 ret, cdclk); 2100 return; 2101 } 2102 2103 if (DISPLAY_VER(dev_priv) >= 20 && cdclk < dev_priv->display.cdclk.hw.cdclk) 2104 xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config); 2105 2106 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, 2107 cdclk_config, &mid_cdclk_config)) { 2108 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); 2109 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); 2110 } else { 2111 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); 2112 } 2113 2114 if (DISPLAY_VER(dev_priv) >= 20 && cdclk > dev_priv->display.cdclk.hw.cdclk) 2115 xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config); 2116 2117 if (DISPLAY_VER(dev_priv) >= 14) 2118 /* 2119 * NOOP - No Pcode communication needed for 2120 * Display versions 14 and beyond 2121 */; 2122 else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) 2123 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 2124 cdclk_config->voltage_level); 2125 if (DISPLAY_VER(dev_priv) < 11) { 2126 /* 2127 * The timeout isn't specified, the 2ms used here is based on 2128 * experiment. 2129 * FIXME: Waiting for the request completion could be delayed 2130 * until the next PCODE request based on BSpec. 2131 */ 2132 ret = snb_pcode_write_timeout(&dev_priv->uncore, 2133 HSW_PCODE_DE_WRITE_FREQ_REQ, 2134 cdclk_config->voltage_level, 2135 150, 2); 2136 } 2137 if (ret) { 2138 drm_err(&dev_priv->drm, 2139 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2140 ret, cdclk); 2141 return; 2142 } 2143 2144 intel_update_cdclk(dev_priv); 2145 2146 if (DISPLAY_VER(dev_priv) >= 11) 2147 /* 2148 * Can't read out the voltage level :( 2149 * Let's just assume everything is as expected. 2150 */ 2151 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; 2152 } 2153 2154 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 2155 { 2156 u32 cdctl, expected; 2157 int cdclk, vco; 2158 2159 intel_update_cdclk(dev_priv); 2160 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 2161 2162 if (dev_priv->display.cdclk.hw.vco == 0 || 2163 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 2164 goto sanitize; 2165 2166 /* Make sure this is a legal cdclk value for the platform */ 2167 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); 2168 if (cdclk != dev_priv->display.cdclk.hw.cdclk) 2169 goto sanitize; 2170 2171 /* Make sure the VCO is correct for the cdclk */ 2172 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2173 if (vco != dev_priv->display.cdclk.hw.vco) 2174 goto sanitize; 2175 2176 /* 2177 * Some BIOS versions leave an incorrect decimal frequency value and 2178 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2179 * so sanitize this register. 2180 */ 2181 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 2182 expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE); 2183 2184 /* 2185 * Let's ignore the pipe field, since BIOS could have configured the 2186 * dividers both synching to an active pipe, or asynchronously 2187 * (PIPE_NONE). 2188 */ 2189 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 2190 expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 2191 2192 if (cdctl == expected) 2193 /* All well; nothing to sanitize */ 2194 return; 2195 2196 sanitize: 2197 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 2198 2199 /* force cdclk programming */ 2200 dev_priv->display.cdclk.hw.cdclk = 0; 2201 2202 /* force full PLL disable + enable */ 2203 dev_priv->display.cdclk.hw.vco = ~0; 2204 } 2205 2206 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 2207 { 2208 struct intel_cdclk_config cdclk_config; 2209 2210 bxt_sanitize_cdclk(dev_priv); 2211 2212 if (dev_priv->display.cdclk.hw.cdclk != 0 && 2213 dev_priv->display.cdclk.hw.vco != 0) 2214 return; 2215 2216 cdclk_config = dev_priv->display.cdclk.hw; 2217 2218 /* 2219 * FIXME: 2220 * - The initial CDCLK needs to be read from VBT. 2221 * Need to make this change after VBT has changes for BXT. 2222 */ 2223 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); 2224 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); 2225 cdclk_config.voltage_level = 2226 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 2227 2228 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 2229 } 2230 2231 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 2232 { 2233 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 2234 2235 cdclk_config.cdclk = cdclk_config.bypass; 2236 cdclk_config.vco = 0; 2237 cdclk_config.voltage_level = 2238 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 2239 2240 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 2241 } 2242 2243 /** 2244 * intel_cdclk_init_hw - Initialize CDCLK hardware 2245 * @i915: i915 device 2246 * 2247 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and 2248 * sanitizing the state of the hardware if needed. This is generally done only 2249 * during the display core initialization sequence, after which the DMC will 2250 * take care of turning CDCLK off/on as needed. 2251 */ 2252 void intel_cdclk_init_hw(struct drm_i915_private *i915) 2253 { 2254 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 2255 bxt_cdclk_init_hw(i915); 2256 else if (DISPLAY_VER(i915) == 9) 2257 skl_cdclk_init_hw(i915); 2258 } 2259 2260 /** 2261 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2262 * @i915: i915 device 2263 * 2264 * Uninitialize CDCLK. This is done only during the display core 2265 * uninitialization sequence. 2266 */ 2267 void intel_cdclk_uninit_hw(struct drm_i915_private *i915) 2268 { 2269 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 2270 bxt_cdclk_uninit_hw(i915); 2271 else if (DISPLAY_VER(i915) == 9) 2272 skl_cdclk_uninit_hw(i915); 2273 } 2274 2275 static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915, 2276 const struct intel_cdclk_config *a, 2277 const struct intel_cdclk_config *b) 2278 { 2279 u16 old_waveform; 2280 u16 new_waveform; 2281 2282 drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); 2283 2284 if (a->vco == 0 || b->vco == 0) 2285 return false; 2286 2287 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) 2288 return false; 2289 2290 old_waveform = cdclk_squash_waveform(i915, a->cdclk); 2291 new_waveform = cdclk_squash_waveform(i915, b->cdclk); 2292 2293 return a->vco != b->vco && 2294 old_waveform != new_waveform; 2295 } 2296 2297 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, 2298 const struct intel_cdclk_config *a, 2299 const struct intel_cdclk_config *b) 2300 { 2301 int a_div, b_div; 2302 2303 if (!HAS_CDCLK_CRAWL(dev_priv)) 2304 return false; 2305 2306 /* 2307 * The vco and cd2x divider will change independently 2308 * from each, so we disallow cd2x change when crawling. 2309 */ 2310 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2311 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2312 2313 return a->vco != 0 && b->vco != 0 && 2314 a->vco != b->vco && 2315 a_div == b_div && 2316 a->ref == b->ref; 2317 } 2318 2319 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, 2320 const struct intel_cdclk_config *a, 2321 const struct intel_cdclk_config *b) 2322 { 2323 /* 2324 * FIXME should store a bit more state in intel_cdclk_config 2325 * to differentiate squasher vs. cd2x divider properly. For 2326 * the moment all platforms with squasher use a fixed cd2x 2327 * divider. 2328 */ 2329 if (!HAS_CDCLK_SQUASH(dev_priv)) 2330 return false; 2331 2332 return a->cdclk != b->cdclk && 2333 a->vco != 0 && 2334 a->vco == b->vco && 2335 a->ref == b->ref; 2336 } 2337 2338 /** 2339 * intel_cdclk_clock_changed - Check whether the clock changed 2340 * @a: first CDCLK configuration 2341 * @b: second CDCLK configuration 2342 * 2343 * Returns: 2344 * True if CDCLK changed in a way that requires re-programming and 2345 * False otherwise. 2346 */ 2347 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2348 const struct intel_cdclk_config *b) 2349 { 2350 return a->cdclk != b->cdclk || 2351 a->vco != b->vco || 2352 a->ref != b->ref; 2353 } 2354 2355 /** 2356 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2357 * configurations requires only a cd2x divider update 2358 * @dev_priv: i915 device 2359 * @a: first CDCLK configuration 2360 * @b: second CDCLK configuration 2361 * 2362 * Returns: 2363 * True if changing between the two CDCLK configurations 2364 * can be done with just a cd2x divider update, false if not. 2365 */ 2366 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 2367 const struct intel_cdclk_config *a, 2368 const struct intel_cdclk_config *b) 2369 { 2370 /* Older hw doesn't have the capability */ 2371 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) 2372 return false; 2373 2374 /* 2375 * FIXME should store a bit more state in intel_cdclk_config 2376 * to differentiate squasher vs. cd2x divider properly. For 2377 * the moment all platforms with squasher use a fixed cd2x 2378 * divider. 2379 */ 2380 if (HAS_CDCLK_SQUASH(dev_priv)) 2381 return false; 2382 2383 return a->cdclk != b->cdclk && 2384 a->vco != 0 && 2385 a->vco == b->vco && 2386 a->ref == b->ref; 2387 } 2388 2389 /** 2390 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2391 * @a: first CDCLK configuration 2392 * @b: second CDCLK configuration 2393 * 2394 * Returns: 2395 * True if the CDCLK configurations don't match, false if they do. 2396 */ 2397 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2398 const struct intel_cdclk_config *b) 2399 { 2400 return intel_cdclk_clock_changed(a, b) || 2401 a->voltage_level != b->voltage_level; 2402 } 2403 2404 void intel_cdclk_dump_config(struct drm_i915_private *i915, 2405 const struct intel_cdclk_config *cdclk_config, 2406 const char *context) 2407 { 2408 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2409 context, cdclk_config->cdclk, cdclk_config->vco, 2410 cdclk_config->ref, cdclk_config->bypass, 2411 cdclk_config->voltage_level); 2412 } 2413 2414 static void intel_pcode_notify(struct drm_i915_private *i915, 2415 u8 voltage_level, 2416 u8 active_pipe_count, 2417 u16 cdclk, 2418 bool cdclk_update_valid, 2419 bool pipe_count_update_valid) 2420 { 2421 int ret; 2422 u32 update_mask = 0; 2423 2424 if (!IS_DG2(i915)) 2425 return; 2426 2427 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2428 2429 if (cdclk_update_valid) 2430 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2431 2432 if (pipe_count_update_valid) 2433 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2434 2435 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL, 2436 SKL_CDCLK_PREPARE_FOR_CHANGE | 2437 update_mask, 2438 SKL_CDCLK_READY_FOR_CHANGE, 2439 SKL_CDCLK_READY_FOR_CHANGE, 3); 2440 if (ret) 2441 drm_err(&i915->drm, 2442 "Failed to inform PCU about display config (err %d)\n", 2443 ret); 2444 } 2445 2446 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 2447 const struct intel_cdclk_config *cdclk_config, 2448 enum pipe pipe, const char *context) 2449 { 2450 struct intel_encoder *encoder; 2451 2452 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) 2453 return; 2454 2455 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) 2456 return; 2457 2458 intel_cdclk_dump_config(dev_priv, cdclk_config, context); 2459 2460 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2461 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2462 2463 intel_psr_pause(intel_dp); 2464 } 2465 2466 intel_audio_cdclk_change_pre(dev_priv); 2467 2468 /* 2469 * Lock aux/gmbus while we change cdclk in case those 2470 * functions use cdclk. Not all platforms/ports do, 2471 * but we'll lock them all for simplicity. 2472 */ 2473 mutex_lock(&dev_priv->display.gmbus.mutex); 2474 for_each_intel_dp(&dev_priv->drm, encoder) { 2475 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2476 2477 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2478 &dev_priv->display.gmbus.mutex); 2479 } 2480 2481 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); 2482 2483 for_each_intel_dp(&dev_priv->drm, encoder) { 2484 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2485 2486 mutex_unlock(&intel_dp->aux.hw_mutex); 2487 } 2488 mutex_unlock(&dev_priv->display.gmbus.mutex); 2489 2490 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2491 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2492 2493 intel_psr_resume(intel_dp); 2494 } 2495 2496 intel_audio_cdclk_change_post(dev_priv); 2497 2498 if (drm_WARN(&dev_priv->drm, 2499 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), 2500 "cdclk state doesn't match!\n")) { 2501 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); 2502 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); 2503 } 2504 } 2505 2506 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2507 { 2508 struct drm_i915_private *i915 = to_i915(state->base.dev); 2509 const struct intel_cdclk_state *old_cdclk_state = 2510 intel_atomic_get_old_cdclk_state(state); 2511 const struct intel_cdclk_state *new_cdclk_state = 2512 intel_atomic_get_new_cdclk_state(state); 2513 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2514 bool change_cdclk, update_pipe_count; 2515 2516 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2517 &new_cdclk_state->actual) && 2518 new_cdclk_state->active_pipes == 2519 old_cdclk_state->active_pipes) 2520 return; 2521 2522 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2523 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2524 2525 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2526 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > 2527 hweight8(old_cdclk_state->active_pipes); 2528 2529 /* 2530 * According to "Sequence Before Frequency Change", 2531 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2532 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2533 * which basically means we choose the maximum of old and new CDCLK, if we know both 2534 */ 2535 if (change_cdclk) 2536 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2537 2538 /* 2539 * According to "Sequence For Pipe Count Change", 2540 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2541 * (power well is enabled) 2542 * no action if it is decreasing, before the change 2543 */ 2544 if (update_pipe_count) 2545 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2546 2547 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, 2548 change_cdclk, update_pipe_count); 2549 } 2550 2551 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2552 { 2553 struct drm_i915_private *i915 = to_i915(state->base.dev); 2554 const struct intel_cdclk_state *new_cdclk_state = 2555 intel_atomic_get_new_cdclk_state(state); 2556 const struct intel_cdclk_state *old_cdclk_state = 2557 intel_atomic_get_old_cdclk_state(state); 2558 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2559 bool update_cdclk, update_pipe_count; 2560 2561 /* According to "Sequence After Frequency Change", set voltage to used level */ 2562 voltage_level = new_cdclk_state->actual.voltage_level; 2563 2564 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2565 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < 2566 hweight8(old_cdclk_state->active_pipes); 2567 2568 /* 2569 * According to "Sequence After Frequency Change", 2570 * set bits 25:16 to current CDCLK 2571 */ 2572 if (update_cdclk) 2573 cdclk = new_cdclk_state->actual.cdclk; 2574 2575 /* 2576 * According to "Sequence For Pipe Count Change", 2577 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2578 * after the change(power well is disabled) 2579 * no action if it is increasing, after the change 2580 */ 2581 if (update_pipe_count) 2582 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2583 2584 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, 2585 update_cdclk, update_pipe_count); 2586 } 2587 2588 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2589 { 2590 const struct intel_cdclk_state *old_cdclk_state = 2591 intel_atomic_get_old_cdclk_state(state); 2592 const struct intel_cdclk_state *new_cdclk_state = 2593 intel_atomic_get_new_cdclk_state(state); 2594 2595 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2596 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2597 } 2598 2599 /** 2600 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2601 * @state: intel atomic state 2602 * 2603 * Program the hardware before updating the HW plane state based on the 2604 * new CDCLK state, if necessary. 2605 */ 2606 void 2607 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2608 { 2609 struct drm_i915_private *i915 = to_i915(state->base.dev); 2610 const struct intel_cdclk_state *old_cdclk_state = 2611 intel_atomic_get_old_cdclk_state(state); 2612 const struct intel_cdclk_state *new_cdclk_state = 2613 intel_atomic_get_new_cdclk_state(state); 2614 struct intel_cdclk_config cdclk_config; 2615 enum pipe pipe; 2616 2617 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2618 &new_cdclk_state->actual)) 2619 return; 2620 2621 if (IS_DG2(i915)) 2622 intel_cdclk_pcode_pre_notify(state); 2623 2624 if (new_cdclk_state->disable_pipes) { 2625 cdclk_config = new_cdclk_state->actual; 2626 pipe = INVALID_PIPE; 2627 } else { 2628 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2629 cdclk_config = new_cdclk_state->actual; 2630 pipe = new_cdclk_state->pipe; 2631 } else { 2632 cdclk_config = old_cdclk_state->actual; 2633 pipe = INVALID_PIPE; 2634 } 2635 2636 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2637 old_cdclk_state->actual.voltage_level); 2638 } 2639 2640 /* 2641 * mbus joining will be changed later by 2642 * intel_dbuf_mbus_{pre,post}_ddb_update() 2643 */ 2644 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2645 2646 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); 2647 2648 intel_set_cdclk(i915, &cdclk_config, pipe, 2649 "Pre changing CDCLK to"); 2650 } 2651 2652 /** 2653 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2654 * @state: intel atomic state 2655 * 2656 * Program the hardware after updating the HW plane state based on the 2657 * new CDCLK state, if necessary. 2658 */ 2659 void 2660 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2661 { 2662 struct drm_i915_private *i915 = to_i915(state->base.dev); 2663 const struct intel_cdclk_state *old_cdclk_state = 2664 intel_atomic_get_old_cdclk_state(state); 2665 const struct intel_cdclk_state *new_cdclk_state = 2666 intel_atomic_get_new_cdclk_state(state); 2667 enum pipe pipe; 2668 2669 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2670 &new_cdclk_state->actual)) 2671 return; 2672 2673 if (IS_DG2(i915)) 2674 intel_cdclk_pcode_post_notify(state); 2675 2676 if (!new_cdclk_state->disable_pipes && 2677 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2678 pipe = new_cdclk_state->pipe; 2679 else 2680 pipe = INVALID_PIPE; 2681 2682 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); 2683 2684 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe, 2685 "Post changing CDCLK to"); 2686 } 2687 2688 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2689 { 2690 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2691 int pixel_rate = crtc_state->pixel_rate; 2692 2693 if (DISPLAY_VER(dev_priv) >= 10) 2694 return DIV_ROUND_UP(pixel_rate, 2); 2695 else if (DISPLAY_VER(dev_priv) == 9 || 2696 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2697 return pixel_rate; 2698 else if (IS_CHERRYVIEW(dev_priv)) 2699 return DIV_ROUND_UP(pixel_rate * 100, 95); 2700 else if (crtc_state->double_wide) 2701 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2702 else 2703 return DIV_ROUND_UP(pixel_rate * 100, 90); 2704 } 2705 2706 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2707 { 2708 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2709 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2710 struct intel_plane *plane; 2711 int min_cdclk = 0; 2712 2713 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 2714 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2715 2716 return min_cdclk; 2717 } 2718 2719 static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) 2720 { 2721 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2722 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2723 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 2724 int min_cdclk = 0; 2725 2726 /* 2727 * When we decide to use only one VDSC engine, since 2728 * each VDSC operates with 1 ppc throughput, pixel clock 2729 * cannot be higher than the VDSC clock (cdclk) 2730 * If there 2 VDSC engines, then pixel clock can't be higher than 2731 * VDSC clock(cdclk) * 2 and so on. 2732 */ 2733 min_cdclk = max_t(int, min_cdclk, 2734 DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances)); 2735 2736 if (crtc_state->joiner_pipes) { 2737 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); 2738 2739 /* 2740 * According to Bigjoiner bw check: 2741 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock 2742 * 2743 * We have already computed compressed_bpp, so now compute the min CDCLK that 2744 * is required to support this compressed_bpp. 2745 * 2746 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) 2747 * 2748 * Since PPC = 2 with bigjoiner 2749 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits 2750 */ 2751 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; 2752 int min_cdclk_bj = 2753 (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) * 2754 pixel_clock) / (2 * bigjoiner_interface_bits); 2755 2756 min_cdclk = max(min_cdclk, min_cdclk_bj); 2757 } 2758 2759 return min_cdclk; 2760 } 2761 2762 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2763 { 2764 struct drm_i915_private *dev_priv = 2765 to_i915(crtc_state->uapi.crtc->dev); 2766 int min_cdclk; 2767 2768 if (!crtc_state->hw.enable) 2769 return 0; 2770 2771 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2772 2773 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2774 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2775 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2776 2777 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2778 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2779 * there may be audio corruption or screen corruption." This cdclk 2780 * restriction for GLK is 316.8 MHz. 2781 */ 2782 if (intel_crtc_has_dp_encoder(crtc_state) && 2783 crtc_state->has_audio && 2784 crtc_state->port_clock >= 540000 && 2785 crtc_state->lane_count == 4) { 2786 if (DISPLAY_VER(dev_priv) == 10) { 2787 /* Display WA #1145: glk */ 2788 min_cdclk = max(316800, min_cdclk); 2789 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { 2790 /* Display WA #1144: skl,bxt */ 2791 min_cdclk = max(432000, min_cdclk); 2792 } 2793 } 2794 2795 /* 2796 * According to BSpec, "The CD clock frequency must be at least twice 2797 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2798 */ 2799 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) 2800 min_cdclk = max(2 * 96000, min_cdclk); 2801 2802 /* 2803 * "For DP audio configuration, cdclk frequency shall be set to 2804 * meet the following requirements: 2805 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2806 * 270 | 320 or higher 2807 * 162 | 200 or higher" 2808 */ 2809 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2810 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2811 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2812 2813 /* 2814 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2815 * than 320000KHz. 2816 */ 2817 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2818 IS_VALLEYVIEW(dev_priv)) 2819 min_cdclk = max(320000, min_cdclk); 2820 2821 /* 2822 * On Geminilake once the CDCLK gets as low as 79200 2823 * picture gets unstable, despite that values are 2824 * correct for DSI PLL and DE PLL. 2825 */ 2826 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2827 IS_GEMINILAKE(dev_priv)) 2828 min_cdclk = max(158400, min_cdclk); 2829 2830 /* Account for additional needs from the planes */ 2831 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2832 2833 if (crtc_state->dsc.compression_enable) 2834 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2835 2836 return min_cdclk; 2837 } 2838 2839 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 2840 { 2841 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2842 struct intel_cdclk_state *cdclk_state = 2843 intel_atomic_get_new_cdclk_state(state); 2844 const struct intel_bw_state *bw_state; 2845 struct intel_crtc *crtc; 2846 struct intel_crtc_state *crtc_state; 2847 int min_cdclk, i; 2848 enum pipe pipe; 2849 2850 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2851 int ret; 2852 2853 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2854 if (min_cdclk < 0) 2855 return min_cdclk; 2856 2857 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2858 continue; 2859 2860 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2861 2862 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2863 if (ret) 2864 return ret; 2865 } 2866 2867 bw_state = intel_atomic_get_new_bw_state(state); 2868 if (bw_state) { 2869 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); 2870 2871 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2872 int ret; 2873 2874 cdclk_state->bw_min_cdclk = min_cdclk; 2875 2876 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2877 if (ret) 2878 return ret; 2879 } 2880 } 2881 2882 min_cdclk = max(cdclk_state->force_min_cdclk, 2883 cdclk_state->bw_min_cdclk); 2884 for_each_pipe(dev_priv, pipe) 2885 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2886 2887 /* 2888 * Avoid glk_force_audio_cdclk() causing excessive screen 2889 * blinking when multiple pipes are active by making sure 2890 * CDCLK frequency is always high enough for audio. With a 2891 * single active pipe we can always change CDCLK frequency 2892 * by changing the cd2x divider (see glk_cdclk_table[]) and 2893 * thus a full modeset won't be needed then. 2894 */ 2895 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && 2896 !is_power_of_2(cdclk_state->active_pipes)) 2897 min_cdclk = max(2 * 96000, min_cdclk); 2898 2899 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { 2900 drm_dbg_kms(&dev_priv->drm, 2901 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2902 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); 2903 return -EINVAL; 2904 } 2905 2906 return min_cdclk; 2907 } 2908 2909 /* 2910 * Account for port clock min voltage level requirements. 2911 * This only really does something on DISPLA_VER >= 11 but can be 2912 * called on earlier platforms as well. 2913 * 2914 * Note that this functions assumes that 0 is 2915 * the lowest voltage value, and higher values 2916 * correspond to increasingly higher voltages. 2917 * 2918 * Should that relationship no longer hold on 2919 * future platforms this code will need to be 2920 * adjusted. 2921 */ 2922 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 2923 { 2924 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2925 struct intel_cdclk_state *cdclk_state = 2926 intel_atomic_get_new_cdclk_state(state); 2927 struct intel_crtc *crtc; 2928 struct intel_crtc_state *crtc_state; 2929 u8 min_voltage_level; 2930 int i; 2931 enum pipe pipe; 2932 2933 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2934 int ret; 2935 2936 if (crtc_state->hw.enable) 2937 min_voltage_level = crtc_state->min_voltage_level; 2938 else 2939 min_voltage_level = 0; 2940 2941 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2942 continue; 2943 2944 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2945 2946 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2947 if (ret) 2948 return ret; 2949 } 2950 2951 min_voltage_level = 0; 2952 for_each_pipe(dev_priv, pipe) 2953 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2954 min_voltage_level); 2955 2956 return min_voltage_level; 2957 } 2958 2959 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 2960 { 2961 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2962 struct intel_cdclk_state *cdclk_state = 2963 intel_atomic_get_new_cdclk_state(state); 2964 int min_cdclk, cdclk; 2965 2966 min_cdclk = intel_compute_min_cdclk(state); 2967 if (min_cdclk < 0) 2968 return min_cdclk; 2969 2970 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2971 2972 cdclk_state->logical.cdclk = cdclk; 2973 cdclk_state->logical.voltage_level = 2974 vlv_calc_voltage_level(dev_priv, cdclk); 2975 2976 if (!cdclk_state->active_pipes) { 2977 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2978 2979 cdclk_state->actual.cdclk = cdclk; 2980 cdclk_state->actual.voltage_level = 2981 vlv_calc_voltage_level(dev_priv, cdclk); 2982 } else { 2983 cdclk_state->actual = cdclk_state->logical; 2984 } 2985 2986 return 0; 2987 } 2988 2989 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 2990 { 2991 struct intel_cdclk_state *cdclk_state = 2992 intel_atomic_get_new_cdclk_state(state); 2993 int min_cdclk, cdclk; 2994 2995 min_cdclk = intel_compute_min_cdclk(state); 2996 if (min_cdclk < 0) 2997 return min_cdclk; 2998 2999 cdclk = bdw_calc_cdclk(min_cdclk); 3000 3001 cdclk_state->logical.cdclk = cdclk; 3002 cdclk_state->logical.voltage_level = 3003 bdw_calc_voltage_level(cdclk); 3004 3005 if (!cdclk_state->active_pipes) { 3006 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 3007 3008 cdclk_state->actual.cdclk = cdclk; 3009 cdclk_state->actual.voltage_level = 3010 bdw_calc_voltage_level(cdclk); 3011 } else { 3012 cdclk_state->actual = cdclk_state->logical; 3013 } 3014 3015 return 0; 3016 } 3017 3018 static int skl_dpll0_vco(struct intel_atomic_state *state) 3019 { 3020 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 3021 struct intel_cdclk_state *cdclk_state = 3022 intel_atomic_get_new_cdclk_state(state); 3023 struct intel_crtc *crtc; 3024 struct intel_crtc_state *crtc_state; 3025 int vco, i; 3026 3027 vco = cdclk_state->logical.vco; 3028 if (!vco) 3029 vco = dev_priv->display.cdclk.skl_preferred_vco_freq; 3030 3031 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 3032 if (!crtc_state->hw.enable) 3033 continue; 3034 3035 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3036 continue; 3037 3038 /* 3039 * DPLL0 VCO may need to be adjusted to get the correct 3040 * clock for eDP. This will affect cdclk as well. 3041 */ 3042 switch (crtc_state->port_clock / 2) { 3043 case 108000: 3044 case 216000: 3045 vco = 8640000; 3046 break; 3047 default: 3048 vco = 8100000; 3049 break; 3050 } 3051 } 3052 3053 return vco; 3054 } 3055 3056 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3057 { 3058 struct intel_cdclk_state *cdclk_state = 3059 intel_atomic_get_new_cdclk_state(state); 3060 int min_cdclk, cdclk, vco; 3061 3062 min_cdclk = intel_compute_min_cdclk(state); 3063 if (min_cdclk < 0) 3064 return min_cdclk; 3065 3066 vco = skl_dpll0_vco(state); 3067 3068 cdclk = skl_calc_cdclk(min_cdclk, vco); 3069 3070 cdclk_state->logical.vco = vco; 3071 cdclk_state->logical.cdclk = cdclk; 3072 cdclk_state->logical.voltage_level = 3073 skl_calc_voltage_level(cdclk); 3074 3075 if (!cdclk_state->active_pipes) { 3076 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3077 3078 cdclk_state->actual.vco = vco; 3079 cdclk_state->actual.cdclk = cdclk; 3080 cdclk_state->actual.voltage_level = 3081 skl_calc_voltage_level(cdclk); 3082 } else { 3083 cdclk_state->actual = cdclk_state->logical; 3084 } 3085 3086 return 0; 3087 } 3088 3089 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3090 { 3091 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 3092 struct intel_cdclk_state *cdclk_state = 3093 intel_atomic_get_new_cdclk_state(state); 3094 int min_cdclk, min_voltage_level, cdclk, vco; 3095 3096 min_cdclk = intel_compute_min_cdclk(state); 3097 if (min_cdclk < 0) 3098 return min_cdclk; 3099 3100 min_voltage_level = bxt_compute_min_voltage_level(state); 3101 if (min_voltage_level < 0) 3102 return min_voltage_level; 3103 3104 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); 3105 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 3106 3107 cdclk_state->logical.vco = vco; 3108 cdclk_state->logical.cdclk = cdclk; 3109 cdclk_state->logical.voltage_level = 3110 max_t(int, min_voltage_level, 3111 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); 3112 3113 if (!cdclk_state->active_pipes) { 3114 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 3115 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 3116 3117 cdclk_state->actual.vco = vco; 3118 cdclk_state->actual.cdclk = cdclk; 3119 cdclk_state->actual.voltage_level = 3120 intel_cdclk_calc_voltage_level(dev_priv, cdclk); 3121 } else { 3122 cdclk_state->actual = cdclk_state->logical; 3123 } 3124 3125 return 0; 3126 } 3127 3128 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3129 { 3130 int min_cdclk; 3131 3132 /* 3133 * We can't change the cdclk frequency, but we still want to 3134 * check that the required minimum frequency doesn't exceed 3135 * the actual cdclk frequency. 3136 */ 3137 min_cdclk = intel_compute_min_cdclk(state); 3138 if (min_cdclk < 0) 3139 return min_cdclk; 3140 3141 return 0; 3142 } 3143 3144 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3145 { 3146 struct intel_cdclk_state *cdclk_state; 3147 3148 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3149 if (!cdclk_state) 3150 return NULL; 3151 3152 cdclk_state->pipe = INVALID_PIPE; 3153 cdclk_state->disable_pipes = false; 3154 3155 return &cdclk_state->base; 3156 } 3157 3158 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3159 struct intel_global_state *state) 3160 { 3161 kfree(state); 3162 } 3163 3164 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3165 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3166 .atomic_destroy_state = intel_cdclk_destroy_state, 3167 }; 3168 3169 struct intel_cdclk_state * 3170 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3171 { 3172 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 3173 struct intel_global_state *cdclk_state; 3174 3175 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); 3176 if (IS_ERR(cdclk_state)) 3177 return ERR_CAST(cdclk_state); 3178 3179 return to_intel_cdclk_state(cdclk_state); 3180 } 3181 3182 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 3183 bool *need_cdclk_calc) 3184 { 3185 const struct intel_cdclk_state *old_cdclk_state; 3186 const struct intel_cdclk_state *new_cdclk_state; 3187 struct intel_plane_state __maybe_unused *plane_state; 3188 struct intel_plane *plane; 3189 int ret; 3190 int i; 3191 3192 /* 3193 * active_planes bitmask has been updated, and potentially affected 3194 * planes are part of the state. We can now compute the minimum cdclk 3195 * for each plane. 3196 */ 3197 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 3198 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 3199 if (ret) 3200 return ret; 3201 } 3202 3203 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 3204 if (ret) 3205 return ret; 3206 3207 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3208 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3209 3210 if (new_cdclk_state && 3211 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 3212 *need_cdclk_calc = true; 3213 3214 return 0; 3215 } 3216 3217 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3218 { 3219 struct intel_cdclk_state *cdclk_state; 3220 3221 cdclk_state = intel_atomic_get_cdclk_state(state); 3222 if (IS_ERR(cdclk_state)) 3223 return PTR_ERR(cdclk_state); 3224 3225 cdclk_state->actual.joined_mbus = joined_mbus; 3226 cdclk_state->logical.joined_mbus = joined_mbus; 3227 3228 return intel_atomic_lock_global_state(&cdclk_state->base); 3229 } 3230 3231 int intel_cdclk_init(struct drm_i915_private *dev_priv) 3232 { 3233 struct intel_cdclk_state *cdclk_state; 3234 3235 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 3236 if (!cdclk_state) 3237 return -ENOMEM; 3238 3239 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, 3240 &cdclk_state->base, &intel_cdclk_funcs); 3241 3242 return 0; 3243 } 3244 3245 static bool intel_cdclk_need_serialize(struct drm_i915_private *i915, 3246 const struct intel_cdclk_state *old_cdclk_state, 3247 const struct intel_cdclk_state *new_cdclk_state) 3248 { 3249 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != 3250 hweight8(new_cdclk_state->active_pipes); 3251 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, 3252 &new_cdclk_state->actual); 3253 /* 3254 * We need to poke hw for gen >= 12, because we notify PCode if 3255 * pipe power well count changes. 3256 */ 3257 return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed); 3258 } 3259 3260 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3261 { 3262 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 3263 const struct intel_cdclk_state *old_cdclk_state; 3264 struct intel_cdclk_state *new_cdclk_state; 3265 enum pipe pipe = INVALID_PIPE; 3266 int ret; 3267 3268 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3269 if (IS_ERR(new_cdclk_state)) 3270 return PTR_ERR(new_cdclk_state); 3271 3272 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3273 3274 new_cdclk_state->active_pipes = 3275 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3276 3277 ret = intel_cdclk_modeset_calc_cdclk(state); 3278 if (ret) 3279 return ret; 3280 3281 if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) { 3282 /* 3283 * Also serialize commits across all crtcs 3284 * if the actual hw needs to be poked. 3285 */ 3286 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3287 if (ret) 3288 return ret; 3289 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 3290 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 3291 intel_cdclk_changed(&old_cdclk_state->logical, 3292 &new_cdclk_state->logical)) { 3293 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3294 if (ret) 3295 return ret; 3296 } else { 3297 return 0; 3298 } 3299 3300 if (is_power_of_2(new_cdclk_state->active_pipes) && 3301 intel_cdclk_can_cd2x_update(dev_priv, 3302 &old_cdclk_state->actual, 3303 &new_cdclk_state->actual)) { 3304 struct intel_crtc *crtc; 3305 struct intel_crtc_state *crtc_state; 3306 3307 pipe = ilog2(new_cdclk_state->active_pipes); 3308 crtc = intel_crtc_for_pipe(dev_priv, pipe); 3309 3310 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3311 if (IS_ERR(crtc_state)) 3312 return PTR_ERR(crtc_state); 3313 3314 if (intel_crtc_needs_modeset(crtc_state)) 3315 pipe = INVALID_PIPE; 3316 } 3317 3318 if (intel_cdclk_can_crawl_and_squash(dev_priv, 3319 &old_cdclk_state->actual, 3320 &new_cdclk_state->actual)) { 3321 drm_dbg_kms(&dev_priv->drm, 3322 "Can change cdclk via crawling and squashing\n"); 3323 } else if (intel_cdclk_can_squash(dev_priv, 3324 &old_cdclk_state->actual, 3325 &new_cdclk_state->actual)) { 3326 drm_dbg_kms(&dev_priv->drm, 3327 "Can change cdclk via squashing\n"); 3328 } else if (intel_cdclk_can_crawl(dev_priv, 3329 &old_cdclk_state->actual, 3330 &new_cdclk_state->actual)) { 3331 drm_dbg_kms(&dev_priv->drm, 3332 "Can change cdclk via crawling\n"); 3333 } else if (pipe != INVALID_PIPE) { 3334 new_cdclk_state->pipe = pipe; 3335 3336 drm_dbg_kms(&dev_priv->drm, 3337 "Can change cdclk cd2x divider with pipe %c active\n", 3338 pipe_name(pipe)); 3339 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3340 &new_cdclk_state->actual)) { 3341 /* All pipes must be switched off while we change the cdclk. */ 3342 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3343 if (ret) 3344 return ret; 3345 3346 new_cdclk_state->disable_pipes = true; 3347 3348 drm_dbg_kms(&dev_priv->drm, 3349 "Modeset required for cdclk change\n"); 3350 } 3351 3352 if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) != 3353 intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) { 3354 int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual); 3355 3356 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3357 if (ret) 3358 return ret; 3359 } 3360 3361 drm_dbg_kms(&dev_priv->drm, 3362 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3363 new_cdclk_state->logical.cdclk, 3364 new_cdclk_state->actual.cdclk); 3365 drm_dbg_kms(&dev_priv->drm, 3366 "New voltage level calculated to be logical %u, actual %u\n", 3367 new_cdclk_state->logical.voltage_level, 3368 new_cdclk_state->actual.voltage_level); 3369 3370 return 0; 3371 } 3372 3373 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 3374 { 3375 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; 3376 3377 if (DISPLAY_VER(dev_priv) >= 10) 3378 return 2 * max_cdclk_freq; 3379 else if (DISPLAY_VER(dev_priv) == 9 || 3380 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3381 return max_cdclk_freq; 3382 else if (IS_CHERRYVIEW(dev_priv)) 3383 return max_cdclk_freq*95/100; 3384 else if (DISPLAY_VER(dev_priv) < 4) 3385 return 2*max_cdclk_freq*90/100; 3386 else 3387 return max_cdclk_freq*90/100; 3388 } 3389 3390 /** 3391 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3392 * @dev_priv: i915 device 3393 * 3394 * Determine the maximum CDCLK frequency the platform supports, and also 3395 * derive the maximum dot clock frequency the maximum CDCLK frequency 3396 * allows. 3397 */ 3398 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 3399 { 3400 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 3401 if (dev_priv->display.cdclk.hw.ref == 24000) 3402 dev_priv->display.cdclk.max_cdclk_freq = 552000; 3403 else 3404 dev_priv->display.cdclk.max_cdclk_freq = 556800; 3405 } else if (DISPLAY_VER(dev_priv) >= 11) { 3406 if (dev_priv->display.cdclk.hw.ref == 24000) 3407 dev_priv->display.cdclk.max_cdclk_freq = 648000; 3408 else 3409 dev_priv->display.cdclk.max_cdclk_freq = 652800; 3410 } else if (IS_GEMINILAKE(dev_priv)) { 3411 dev_priv->display.cdclk.max_cdclk_freq = 316800; 3412 } else if (IS_BROXTON(dev_priv)) { 3413 dev_priv->display.cdclk.max_cdclk_freq = 624000; 3414 } else if (DISPLAY_VER(dev_priv) == 9) { 3415 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3416 int max_cdclk, vco; 3417 3418 vco = dev_priv->display.cdclk.skl_preferred_vco_freq; 3419 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 3420 3421 /* 3422 * Use the lower (vco 8640) cdclk values as a 3423 * first guess. skl_calc_cdclk() will correct it 3424 * if the preferred vco is 8100 instead. 3425 */ 3426 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3427 max_cdclk = 617143; 3428 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3429 max_cdclk = 540000; 3430 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3431 max_cdclk = 432000; 3432 else 3433 max_cdclk = 308571; 3434 3435 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3436 } else if (IS_BROADWELL(dev_priv)) { 3437 /* 3438 * FIXME with extra cooling we can allow 3439 * 540 MHz for ULX and 675 Mhz for ULT. 3440 * How can we know if extra cooling is 3441 * available? PCI ID, VTB, something else? 3442 */ 3443 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3444 dev_priv->display.cdclk.max_cdclk_freq = 450000; 3445 else if (IS_BROADWELL_ULX(dev_priv)) 3446 dev_priv->display.cdclk.max_cdclk_freq = 450000; 3447 else if (IS_BROADWELL_ULT(dev_priv)) 3448 dev_priv->display.cdclk.max_cdclk_freq = 540000; 3449 else 3450 dev_priv->display.cdclk.max_cdclk_freq = 675000; 3451 } else if (IS_CHERRYVIEW(dev_priv)) { 3452 dev_priv->display.cdclk.max_cdclk_freq = 320000; 3453 } else if (IS_VALLEYVIEW(dev_priv)) { 3454 dev_priv->display.cdclk.max_cdclk_freq = 400000; 3455 } else { 3456 /* otherwise assume cdclk is fixed */ 3457 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; 3458 } 3459 3460 dev_priv->display.cdclk.max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 3461 3462 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", 3463 dev_priv->display.cdclk.max_cdclk_freq); 3464 3465 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", 3466 dev_priv->display.cdclk.max_dotclk_freq); 3467 } 3468 3469 /** 3470 * intel_update_cdclk - Determine the current CDCLK frequency 3471 * @dev_priv: i915 device 3472 * 3473 * Determine the current CDCLK frequency. 3474 */ 3475 void intel_update_cdclk(struct drm_i915_private *dev_priv) 3476 { 3477 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); 3478 3479 /* 3480 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3481 * Programmng [sic] note: bit[9:2] should be programmed to the number 3482 * of cdclk that generates 4MHz reference clock freq which is used to 3483 * generate GMBus clock. This will vary with the cdclk freq. 3484 */ 3485 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3486 intel_de_write(dev_priv, GMBUSFREQ_VLV, 3487 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); 3488 } 3489 3490 static int dg1_rawclk(struct drm_i915_private *dev_priv) 3491 { 3492 /* 3493 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3494 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3495 */ 3496 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, 3497 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3498 3499 return 38400; 3500 } 3501 3502 static int cnp_rawclk(struct drm_i915_private *dev_priv) 3503 { 3504 u32 rawclk; 3505 int divider, fraction; 3506 3507 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3508 /* 24 MHz */ 3509 divider = 24000; 3510 fraction = 0; 3511 } else { 3512 /* 19.2 MHz */ 3513 divider = 19000; 3514 fraction = 200; 3515 } 3516 3517 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3518 if (fraction) { 3519 int numerator = 1; 3520 3521 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3522 fraction) - 1); 3523 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3524 rawclk |= ICP_RAWCLK_NUM(numerator); 3525 } 3526 3527 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); 3528 return divider + fraction; 3529 } 3530 3531 static int pch_rawclk(struct drm_i915_private *dev_priv) 3532 { 3533 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3534 } 3535 3536 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 3537 { 3538 /* RAWCLK_FREQ_VLV register updated from power well code */ 3539 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 3540 CCK_DISPLAY_REF_CLOCK_CONTROL); 3541 } 3542 3543 static int i9xx_hrawclk(struct drm_i915_private *i915) 3544 { 3545 /* hrawclock is 1/4 the FSB frequency */ 3546 return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); 3547 } 3548 3549 /** 3550 * intel_read_rawclk - Determine the current RAWCLK frequency 3551 * @dev_priv: i915 device 3552 * 3553 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3554 * frequency clock so this needs to done only once. 3555 */ 3556 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 3557 { 3558 u32 freq; 3559 3560 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) 3561 /* 3562 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3563 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3564 * not need to be programmed." 3565 */ 3566 freq = 38400; 3567 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3568 freq = dg1_rawclk(dev_priv); 3569 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3570 freq = cnp_rawclk(dev_priv); 3571 else if (HAS_PCH_SPLIT(dev_priv)) 3572 freq = pch_rawclk(dev_priv); 3573 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3574 freq = vlv_hrawclk(dev_priv); 3575 else if (DISPLAY_VER(dev_priv) >= 3) 3576 freq = i9xx_hrawclk(dev_priv); 3577 else 3578 /* no rawclk on other platforms, or no need to know it */ 3579 return 0; 3580 3581 return freq; 3582 } 3583 3584 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3585 { 3586 struct drm_i915_private *i915 = m->private; 3587 3588 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); 3589 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); 3590 seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->display.cdclk.max_dotclk_freq); 3591 3592 return 0; 3593 } 3594 3595 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3596 3597 void intel_cdclk_debugfs_register(struct drm_i915_private *i915) 3598 { 3599 struct drm_minor *minor = i915->drm.primary; 3600 3601 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, 3602 i915, &i915_cdclk_info_fops); 3603 } 3604 3605 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3606 .get_cdclk = bxt_get_cdclk, 3607 .set_cdclk = bxt_set_cdclk, 3608 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3609 .calc_voltage_level = rplu_calc_voltage_level, 3610 }; 3611 3612 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3613 .get_cdclk = bxt_get_cdclk, 3614 .set_cdclk = bxt_set_cdclk, 3615 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3616 .calc_voltage_level = tgl_calc_voltage_level, 3617 }; 3618 3619 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3620 .get_cdclk = bxt_get_cdclk, 3621 .set_cdclk = bxt_set_cdclk, 3622 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3623 .calc_voltage_level = ehl_calc_voltage_level, 3624 }; 3625 3626 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3627 .get_cdclk = bxt_get_cdclk, 3628 .set_cdclk = bxt_set_cdclk, 3629 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3630 .calc_voltage_level = icl_calc_voltage_level, 3631 }; 3632 3633 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3634 .get_cdclk = bxt_get_cdclk, 3635 .set_cdclk = bxt_set_cdclk, 3636 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3637 .calc_voltage_level = bxt_calc_voltage_level, 3638 }; 3639 3640 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3641 .get_cdclk = skl_get_cdclk, 3642 .set_cdclk = skl_set_cdclk, 3643 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3644 }; 3645 3646 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3647 .get_cdclk = bdw_get_cdclk, 3648 .set_cdclk = bdw_set_cdclk, 3649 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3650 }; 3651 3652 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3653 .get_cdclk = vlv_get_cdclk, 3654 .set_cdclk = chv_set_cdclk, 3655 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3656 }; 3657 3658 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3659 .get_cdclk = vlv_get_cdclk, 3660 .set_cdclk = vlv_set_cdclk, 3661 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3662 }; 3663 3664 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3665 .get_cdclk = hsw_get_cdclk, 3666 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3667 }; 3668 3669 /* SNB, IVB, 965G, 945G */ 3670 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3671 .get_cdclk = fixed_400mhz_get_cdclk, 3672 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3673 }; 3674 3675 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3676 .get_cdclk = fixed_450mhz_get_cdclk, 3677 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3678 }; 3679 3680 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3681 .get_cdclk = gm45_get_cdclk, 3682 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3683 }; 3684 3685 /* G45 uses G33 */ 3686 3687 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3688 .get_cdclk = i965gm_get_cdclk, 3689 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3690 }; 3691 3692 /* i965G uses fixed 400 */ 3693 3694 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3695 .get_cdclk = pnv_get_cdclk, 3696 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3697 }; 3698 3699 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3700 .get_cdclk = g33_get_cdclk, 3701 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3702 }; 3703 3704 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3705 .get_cdclk = i945gm_get_cdclk, 3706 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3707 }; 3708 3709 /* i945G uses fixed 400 */ 3710 3711 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3712 .get_cdclk = i915gm_get_cdclk, 3713 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3714 }; 3715 3716 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3717 .get_cdclk = fixed_333mhz_get_cdclk, 3718 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3719 }; 3720 3721 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3722 .get_cdclk = fixed_266mhz_get_cdclk, 3723 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3724 }; 3725 3726 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3727 .get_cdclk = i85x_get_cdclk, 3728 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3729 }; 3730 3731 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3732 .get_cdclk = fixed_200mhz_get_cdclk, 3733 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3734 }; 3735 3736 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3737 .get_cdclk = fixed_133mhz_get_cdclk, 3738 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3739 }; 3740 3741 /** 3742 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3743 * @dev_priv: i915 device 3744 */ 3745 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 3746 { 3747 if (DISPLAY_VER(dev_priv) >= 20) { 3748 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; 3749 dev_priv->display.cdclk.table = xe2lpd_cdclk_table; 3750 } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) { 3751 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; 3752 dev_priv->display.cdclk.table = xe2hpd_cdclk_table; 3753 } else if (DISPLAY_VER(dev_priv) >= 14) { 3754 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; 3755 dev_priv->display.cdclk.table = mtl_cdclk_table; 3756 } else if (IS_DG2(dev_priv)) { 3757 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3758 dev_priv->display.cdclk.table = dg2_cdclk_table; 3759 } else if (IS_ALDERLAKE_P(dev_priv)) { 3760 /* Wa_22011320316:adl-p[a0] */ 3761 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 3762 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; 3763 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3764 } else if (IS_RAPTORLAKE_U(dev_priv)) { 3765 dev_priv->display.cdclk.table = rplu_cdclk_table; 3766 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; 3767 } else { 3768 dev_priv->display.cdclk.table = adlp_cdclk_table; 3769 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3770 } 3771 } else if (IS_ROCKETLAKE(dev_priv)) { 3772 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3773 dev_priv->display.cdclk.table = rkl_cdclk_table; 3774 } else if (DISPLAY_VER(dev_priv) >= 12) { 3775 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3776 dev_priv->display.cdclk.table = icl_cdclk_table; 3777 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 3778 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; 3779 dev_priv->display.cdclk.table = icl_cdclk_table; 3780 } else if (DISPLAY_VER(dev_priv) >= 11) { 3781 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; 3782 dev_priv->display.cdclk.table = icl_cdclk_table; 3783 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 3784 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; 3785 if (IS_GEMINILAKE(dev_priv)) 3786 dev_priv->display.cdclk.table = glk_cdclk_table; 3787 else 3788 dev_priv->display.cdclk.table = bxt_cdclk_table; 3789 } else if (DISPLAY_VER(dev_priv) == 9) { 3790 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; 3791 } else if (IS_BROADWELL(dev_priv)) { 3792 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; 3793 } else if (IS_HASWELL(dev_priv)) { 3794 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; 3795 } else if (IS_CHERRYVIEW(dev_priv)) { 3796 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; 3797 } else if (IS_VALLEYVIEW(dev_priv)) { 3798 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; 3799 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 3800 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3801 } else if (IS_IRONLAKE(dev_priv)) { 3802 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; 3803 } else if (IS_GM45(dev_priv)) { 3804 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; 3805 } else if (IS_G45(dev_priv)) { 3806 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3807 } else if (IS_I965GM(dev_priv)) { 3808 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; 3809 } else if (IS_I965G(dev_priv)) { 3810 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3811 } else if (IS_PINEVIEW(dev_priv)) { 3812 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; 3813 } else if (IS_G33(dev_priv)) { 3814 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3815 } else if (IS_I945GM(dev_priv)) { 3816 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; 3817 } else if (IS_I945G(dev_priv)) { 3818 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3819 } else if (IS_I915GM(dev_priv)) { 3820 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; 3821 } else if (IS_I915G(dev_priv)) { 3822 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; 3823 } else if (IS_I865G(dev_priv)) { 3824 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; 3825 } else if (IS_I85X(dev_priv)) { 3826 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; 3827 } else if (IS_I845G(dev_priv)) { 3828 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; 3829 } else if (IS_I830(dev_priv)) { 3830 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3831 } 3832 3833 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, 3834 "Unknown platform. Assuming i830\n")) 3835 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3836 } 3837