1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/time.h> 26 27 #include <drm/drm_fixed.h> 28 29 #include "soc/intel_dram.h" 30 31 #include "hsw_ips.h" 32 #include "i915_drv.h" 33 #include "i915_reg.h" 34 #include "intel_atomic.h" 35 #include "intel_atomic_plane.h" 36 #include "intel_audio.h" 37 #include "intel_bw.h" 38 #include "intel_cdclk.h" 39 #include "intel_crtc.h" 40 #include "intel_de.h" 41 #include "intel_display_types.h" 42 #include "intel_mchbar_regs.h" 43 #include "intel_pci_config.h" 44 #include "intel_pcode.h" 45 #include "intel_psr.h" 46 #include "intel_vdsc.h" 47 #include "skl_watermark.h" 48 #include "skl_watermark_regs.h" 49 #include "vlv_dsi.h" 50 #include "vlv_sideband.h" 51 52 /** 53 * DOC: CDCLK / RAWCLK 54 * 55 * The display engine uses several different clocks to do its work. There 56 * are two main clocks involved that aren't directly related to the actual 57 * pixel clock or any symbol/bit clock of the actual output port. These 58 * are the core display clock (CDCLK) and RAWCLK. 59 * 60 * CDCLK clocks most of the display pipe logic, and thus its frequency 61 * must be high enough to support the rate at which pixels are flowing 62 * through the pipes. Downscaling must also be accounted as that increases 63 * the effective pixel rate. 64 * 65 * On several platforms the CDCLK frequency can be changed dynamically 66 * to minimize power consumption for a given display configuration. 67 * Typically changes to the CDCLK frequency require all the display pipes 68 * to be shut down while the frequency is being changed. 69 * 70 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 71 * DMC will not change the active CDCLK frequency however, so that part 72 * will still be performed by the driver directly. 73 * 74 * There are multiple components involved in the generation of the CDCLK 75 * frequency: 76 * 77 * - We have the CDCLK PLL, which generates an output clock based on a 78 * reference clock and a ratio parameter. 79 * - The CD2X Divider, which divides the output of the PLL based on a 80 * divisor selected from a set of pre-defined choices. 81 * - The CD2X Squasher, which further divides the output based on a 82 * waveform represented as a sequence of bits where each zero 83 * "squashes out" a clock cycle. 84 * - And, finally, a fixed divider that divides the output frequency by 2. 85 * 86 * As such, the resulting CDCLK frequency can be calculated with the 87 * following formula: 88 * 89 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 90 * 91 * , where vco is the frequency generated by the PLL; cd2x_div 92 * represents the CD2X Divider; sq_len and sq_div are the bit length 93 * and the number of high bits for the CD2X Squasher waveform, respectively; 94 * and 2 represents the fixed divider. 95 * 96 * Note that some older platforms do not contain the CD2X Divider 97 * and/or CD2X Squasher, in which case we can ignore their respective 98 * factors in the formula above. 99 * 100 * Several methods exist to change the CDCLK frequency, which ones are 101 * supported depends on the platform: 102 * 103 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 104 * - CD2X divider update. Single pipe can be active as the divider update 105 * can be synchronized with the pipe's start of vblank. 106 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 107 * - Squash waveform update. Pipes can be active. 108 * - Crawl and squash can also be done back to back. Pipes can be active. 109 * 110 * RAWCLK is a fixed frequency clock, often used by various auxiliary 111 * blocks such as AUX CH or backlight PWM. Hence the only thing we 112 * really need to know about RAWCLK is its frequency so that various 113 * dividers can be programmed correctly. 114 */ 115 116 struct intel_cdclk_funcs { 117 void (*get_cdclk)(struct intel_display *display, 118 struct intel_cdclk_config *cdclk_config); 119 void (*set_cdclk)(struct intel_display *display, 120 const struct intel_cdclk_config *cdclk_config, 121 enum pipe pipe); 122 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 123 u8 (*calc_voltage_level)(int cdclk); 124 }; 125 126 void intel_cdclk_get_cdclk(struct intel_display *display, 127 struct intel_cdclk_config *cdclk_config) 128 { 129 display->funcs.cdclk->get_cdclk(display, cdclk_config); 130 } 131 132 static void intel_cdclk_set_cdclk(struct intel_display *display, 133 const struct intel_cdclk_config *cdclk_config, 134 enum pipe pipe) 135 { 136 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); 137 } 138 139 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 140 { 141 struct intel_display *display = to_intel_display(state); 142 143 return display->funcs.cdclk->modeset_calc_cdclk(state); 144 } 145 146 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, 147 int cdclk) 148 { 149 return display->funcs.cdclk->calc_voltage_level(cdclk); 150 } 151 152 static void fixed_133mhz_get_cdclk(struct intel_display *display, 153 struct intel_cdclk_config *cdclk_config) 154 { 155 cdclk_config->cdclk = 133333; 156 } 157 158 static void fixed_200mhz_get_cdclk(struct intel_display *display, 159 struct intel_cdclk_config *cdclk_config) 160 { 161 cdclk_config->cdclk = 200000; 162 } 163 164 static void fixed_266mhz_get_cdclk(struct intel_display *display, 165 struct intel_cdclk_config *cdclk_config) 166 { 167 cdclk_config->cdclk = 266667; 168 } 169 170 static void fixed_333mhz_get_cdclk(struct intel_display *display, 171 struct intel_cdclk_config *cdclk_config) 172 { 173 cdclk_config->cdclk = 333333; 174 } 175 176 static void fixed_400mhz_get_cdclk(struct intel_display *display, 177 struct intel_cdclk_config *cdclk_config) 178 { 179 cdclk_config->cdclk = 400000; 180 } 181 182 static void fixed_450mhz_get_cdclk(struct intel_display *display, 183 struct intel_cdclk_config *cdclk_config) 184 { 185 cdclk_config->cdclk = 450000; 186 } 187 188 static void i85x_get_cdclk(struct intel_display *display, 189 struct intel_cdclk_config *cdclk_config) 190 { 191 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 192 u16 hpllcc = 0; 193 194 /* 195 * 852GM/852GMV only supports 133 MHz and the HPLLCC 196 * encoding is different :( 197 * FIXME is this the right way to detect 852GM/852GMV? 198 */ 199 if (pdev->revision == 0x1) { 200 cdclk_config->cdclk = 133333; 201 return; 202 } 203 204 pci_bus_read_config_word(pdev->bus, 205 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 206 207 /* Assume that the hardware is in the high speed state. This 208 * should be the default. 209 */ 210 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 211 case GC_CLOCK_133_200: 212 case GC_CLOCK_133_200_2: 213 case GC_CLOCK_100_200: 214 cdclk_config->cdclk = 200000; 215 break; 216 case GC_CLOCK_166_250: 217 cdclk_config->cdclk = 250000; 218 break; 219 case GC_CLOCK_100_133: 220 cdclk_config->cdclk = 133333; 221 break; 222 case GC_CLOCK_133_266: 223 case GC_CLOCK_133_266_2: 224 case GC_CLOCK_166_266: 225 cdclk_config->cdclk = 266667; 226 break; 227 } 228 } 229 230 static void i915gm_get_cdclk(struct intel_display *display, 231 struct intel_cdclk_config *cdclk_config) 232 { 233 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 234 u16 gcfgc = 0; 235 236 pci_read_config_word(pdev, GCFGC, &gcfgc); 237 238 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 239 cdclk_config->cdclk = 133333; 240 return; 241 } 242 243 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 244 case GC_DISPLAY_CLOCK_333_320_MHZ: 245 cdclk_config->cdclk = 333333; 246 break; 247 default: 248 case GC_DISPLAY_CLOCK_190_200_MHZ: 249 cdclk_config->cdclk = 190000; 250 break; 251 } 252 } 253 254 static void i945gm_get_cdclk(struct intel_display *display, 255 struct intel_cdclk_config *cdclk_config) 256 { 257 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 258 u16 gcfgc = 0; 259 260 pci_read_config_word(pdev, GCFGC, &gcfgc); 261 262 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 263 cdclk_config->cdclk = 133333; 264 return; 265 } 266 267 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 268 case GC_DISPLAY_CLOCK_333_320_MHZ: 269 cdclk_config->cdclk = 320000; 270 break; 271 default: 272 case GC_DISPLAY_CLOCK_190_200_MHZ: 273 cdclk_config->cdclk = 200000; 274 break; 275 } 276 } 277 278 static unsigned int intel_hpll_vco(struct intel_display *display) 279 { 280 static const unsigned int blb_vco[8] = { 281 [0] = 3200000, 282 [1] = 4000000, 283 [2] = 5333333, 284 [3] = 4800000, 285 [4] = 6400000, 286 }; 287 static const unsigned int pnv_vco[8] = { 288 [0] = 3200000, 289 [1] = 4000000, 290 [2] = 5333333, 291 [3] = 4800000, 292 [4] = 2666667, 293 }; 294 static const unsigned int cl_vco[8] = { 295 [0] = 3200000, 296 [1] = 4000000, 297 [2] = 5333333, 298 [3] = 6400000, 299 [4] = 3333333, 300 [5] = 3566667, 301 [6] = 4266667, 302 }; 303 static const unsigned int elk_vco[8] = { 304 [0] = 3200000, 305 [1] = 4000000, 306 [2] = 5333333, 307 [3] = 4800000, 308 }; 309 static const unsigned int ctg_vco[8] = { 310 [0] = 3200000, 311 [1] = 4000000, 312 [2] = 5333333, 313 [3] = 6400000, 314 [4] = 2666667, 315 [5] = 4266667, 316 }; 317 struct drm_i915_private *dev_priv = to_i915(display->drm); 318 const unsigned int *vco_table; 319 unsigned int vco; 320 u8 tmp = 0; 321 322 /* FIXME other chipsets? */ 323 if (IS_GM45(dev_priv)) 324 vco_table = ctg_vco; 325 else if (IS_G45(dev_priv)) 326 vco_table = elk_vco; 327 else if (IS_I965GM(dev_priv)) 328 vco_table = cl_vco; 329 else if (IS_PINEVIEW(dev_priv)) 330 vco_table = pnv_vco; 331 else if (IS_G33(dev_priv)) 332 vco_table = blb_vco; 333 else 334 return 0; 335 336 tmp = intel_de_read(display, 337 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 338 339 vco = vco_table[tmp & 0x7]; 340 if (vco == 0) 341 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 342 tmp); 343 else 344 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); 345 346 return vco; 347 } 348 349 static void g33_get_cdclk(struct intel_display *display, 350 struct intel_cdclk_config *cdclk_config) 351 { 352 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 353 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 354 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 355 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 356 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 357 const u8 *div_table; 358 unsigned int cdclk_sel; 359 u16 tmp = 0; 360 361 cdclk_config->vco = intel_hpll_vco(display); 362 363 pci_read_config_word(pdev, GCFGC, &tmp); 364 365 cdclk_sel = (tmp >> 4) & 0x7; 366 367 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 368 goto fail; 369 370 switch (cdclk_config->vco) { 371 case 3200000: 372 div_table = div_3200; 373 break; 374 case 4000000: 375 div_table = div_4000; 376 break; 377 case 4800000: 378 div_table = div_4800; 379 break; 380 case 5333333: 381 div_table = div_5333; 382 break; 383 default: 384 goto fail; 385 } 386 387 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 388 div_table[cdclk_sel]); 389 return; 390 391 fail: 392 drm_err(display->drm, 393 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 394 cdclk_config->vco, tmp); 395 cdclk_config->cdclk = 190476; 396 } 397 398 static void pnv_get_cdclk(struct intel_display *display, 399 struct intel_cdclk_config *cdclk_config) 400 { 401 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 402 u16 gcfgc = 0; 403 404 pci_read_config_word(pdev, GCFGC, &gcfgc); 405 406 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 407 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 408 cdclk_config->cdclk = 266667; 409 break; 410 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 411 cdclk_config->cdclk = 333333; 412 break; 413 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 414 cdclk_config->cdclk = 444444; 415 break; 416 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 417 cdclk_config->cdclk = 200000; 418 break; 419 default: 420 drm_err(display->drm, 421 "Unknown pnv display core clock 0x%04x\n", gcfgc); 422 fallthrough; 423 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 424 cdclk_config->cdclk = 133333; 425 break; 426 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 427 cdclk_config->cdclk = 166667; 428 break; 429 } 430 } 431 432 static void i965gm_get_cdclk(struct intel_display *display, 433 struct intel_cdclk_config *cdclk_config) 434 { 435 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 436 static const u8 div_3200[] = { 16, 10, 8 }; 437 static const u8 div_4000[] = { 20, 12, 10 }; 438 static const u8 div_5333[] = { 24, 16, 14 }; 439 const u8 *div_table; 440 unsigned int cdclk_sel; 441 u16 tmp = 0; 442 443 cdclk_config->vco = intel_hpll_vco(display); 444 445 pci_read_config_word(pdev, GCFGC, &tmp); 446 447 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 448 449 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 450 goto fail; 451 452 switch (cdclk_config->vco) { 453 case 3200000: 454 div_table = div_3200; 455 break; 456 case 4000000: 457 div_table = div_4000; 458 break; 459 case 5333333: 460 div_table = div_5333; 461 break; 462 default: 463 goto fail; 464 } 465 466 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 467 div_table[cdclk_sel]); 468 return; 469 470 fail: 471 drm_err(display->drm, 472 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 473 cdclk_config->vco, tmp); 474 cdclk_config->cdclk = 200000; 475 } 476 477 static void gm45_get_cdclk(struct intel_display *display, 478 struct intel_cdclk_config *cdclk_config) 479 { 480 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 481 unsigned int cdclk_sel; 482 u16 tmp = 0; 483 484 cdclk_config->vco = intel_hpll_vco(display); 485 486 pci_read_config_word(pdev, GCFGC, &tmp); 487 488 cdclk_sel = (tmp >> 12) & 0x1; 489 490 switch (cdclk_config->vco) { 491 case 2666667: 492 case 4000000: 493 case 5333333: 494 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 495 break; 496 case 3200000: 497 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 498 break; 499 default: 500 drm_err(display->drm, 501 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 502 cdclk_config->vco, tmp); 503 cdclk_config->cdclk = 222222; 504 break; 505 } 506 } 507 508 static void hsw_get_cdclk(struct intel_display *display, 509 struct intel_cdclk_config *cdclk_config) 510 { 511 struct drm_i915_private *dev_priv = to_i915(display->drm); 512 u32 lcpll = intel_de_read(display, LCPLL_CTL); 513 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 514 515 if (lcpll & LCPLL_CD_SOURCE_FCLK) 516 cdclk_config->cdclk = 800000; 517 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 518 cdclk_config->cdclk = 450000; 519 else if (freq == LCPLL_CLK_FREQ_450) 520 cdclk_config->cdclk = 450000; 521 else if (IS_HASWELL_ULT(dev_priv)) 522 cdclk_config->cdclk = 337500; 523 else 524 cdclk_config->cdclk = 540000; 525 } 526 527 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) 528 { 529 struct drm_i915_private *dev_priv = to_i915(display->drm); 530 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 531 333333 : 320000; 532 533 /* 534 * We seem to get an unstable or solid color picture at 200MHz. 535 * Not sure what's wrong. For now use 200MHz only when all pipes 536 * are off. 537 */ 538 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 539 return 400000; 540 else if (min_cdclk > 266667) 541 return freq_320; 542 else if (min_cdclk > 0) 543 return 266667; 544 else 545 return 200000; 546 } 547 548 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 549 { 550 struct drm_i915_private *dev_priv = to_i915(display->drm); 551 552 if (IS_VALLEYVIEW(dev_priv)) { 553 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 554 return 2; 555 else if (cdclk >= 266667) 556 return 1; 557 else 558 return 0; 559 } else { 560 /* 561 * Specs are full of misinformation, but testing on actual 562 * hardware has shown that we just need to write the desired 563 * CCK divider into the Punit register. 564 */ 565 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 566 } 567 } 568 569 static void vlv_get_cdclk(struct intel_display *display, 570 struct intel_cdclk_config *cdclk_config) 571 { 572 struct drm_i915_private *dev_priv = to_i915(display->drm); 573 u32 val; 574 575 vlv_iosf_sb_get(dev_priv, 576 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 577 578 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 579 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 580 CCK_DISPLAY_CLOCK_CONTROL, 581 cdclk_config->vco); 582 583 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 584 585 vlv_iosf_sb_put(dev_priv, 586 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 587 588 if (IS_VALLEYVIEW(dev_priv)) 589 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 590 DSPFREQGUAR_SHIFT; 591 else 592 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 593 DSPFREQGUAR_SHIFT_CHV; 594 } 595 596 static void vlv_program_pfi_credits(struct intel_display *display) 597 { 598 struct drm_i915_private *dev_priv = to_i915(display->drm); 599 unsigned int credits, default_credits; 600 601 if (IS_CHERRYVIEW(dev_priv)) 602 default_credits = PFI_CREDIT(12); 603 else 604 default_credits = PFI_CREDIT(8); 605 606 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 607 /* CHV suggested value is 31 or 63 */ 608 if (IS_CHERRYVIEW(dev_priv)) 609 credits = PFI_CREDIT_63; 610 else 611 credits = PFI_CREDIT(15); 612 } else { 613 credits = default_credits; 614 } 615 616 /* 617 * WA - write default credits before re-programming 618 * FIXME: should we also set the resend bit here? 619 */ 620 intel_de_write(display, GCI_CONTROL, 621 VGA_FAST_MODE_DISABLE | default_credits); 622 623 intel_de_write(display, GCI_CONTROL, 624 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 625 626 /* 627 * FIXME is this guaranteed to clear 628 * immediately or should we poll for it? 629 */ 630 drm_WARN_ON(display->drm, 631 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); 632 } 633 634 static void vlv_set_cdclk(struct intel_display *display, 635 const struct intel_cdclk_config *cdclk_config, 636 enum pipe pipe) 637 { 638 struct drm_i915_private *dev_priv = to_i915(display->drm); 639 int cdclk = cdclk_config->cdclk; 640 u32 val, cmd = cdclk_config->voltage_level; 641 intel_wakeref_t wakeref; 642 643 switch (cdclk) { 644 case 400000: 645 case 333333: 646 case 320000: 647 case 266667: 648 case 200000: 649 break; 650 default: 651 MISSING_CASE(cdclk); 652 return; 653 } 654 655 /* There are cases where we can end up here with power domains 656 * off and a CDCLK frequency other than the minimum, like when 657 * issuing a modeset without actually changing any display after 658 * a system suspend. So grab the display core domain, which covers 659 * the HW blocks needed for the following programming. 660 */ 661 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 662 663 vlv_iosf_sb_get(dev_priv, 664 BIT(VLV_IOSF_SB_CCK) | 665 BIT(VLV_IOSF_SB_BUNIT) | 666 BIT(VLV_IOSF_SB_PUNIT)); 667 668 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 669 val &= ~DSPFREQGUAR_MASK; 670 val |= (cmd << DSPFREQGUAR_SHIFT); 671 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 672 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 673 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 674 50)) { 675 drm_err(display->drm, 676 "timed out waiting for CDclk change\n"); 677 } 678 679 if (cdclk == 400000) { 680 u32 divider; 681 682 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 683 cdclk) - 1; 684 685 /* adjust cdclk divider */ 686 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 687 val &= ~CCK_FREQUENCY_VALUES; 688 val |= divider; 689 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 690 691 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 692 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 693 50)) 694 drm_err(display->drm, 695 "timed out waiting for CDclk change\n"); 696 } 697 698 /* adjust self-refresh exit latency value */ 699 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 700 val &= ~0x7f; 701 702 /* 703 * For high bandwidth configs, we set a higher latency in the bunit 704 * so that the core display fetch happens in time to avoid underruns. 705 */ 706 if (cdclk == 400000) 707 val |= 4500 / 250; /* 4.5 usec */ 708 else 709 val |= 3000 / 250; /* 3.0 usec */ 710 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 711 712 vlv_iosf_sb_put(dev_priv, 713 BIT(VLV_IOSF_SB_CCK) | 714 BIT(VLV_IOSF_SB_BUNIT) | 715 BIT(VLV_IOSF_SB_PUNIT)); 716 717 intel_update_cdclk(display); 718 719 vlv_program_pfi_credits(display); 720 721 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 722 } 723 724 static void chv_set_cdclk(struct intel_display *display, 725 const struct intel_cdclk_config *cdclk_config, 726 enum pipe pipe) 727 { 728 struct drm_i915_private *dev_priv = to_i915(display->drm); 729 int cdclk = cdclk_config->cdclk; 730 u32 val, cmd = cdclk_config->voltage_level; 731 intel_wakeref_t wakeref; 732 733 switch (cdclk) { 734 case 333333: 735 case 320000: 736 case 266667: 737 case 200000: 738 break; 739 default: 740 MISSING_CASE(cdclk); 741 return; 742 } 743 744 /* There are cases where we can end up here with power domains 745 * off and a CDCLK frequency other than the minimum, like when 746 * issuing a modeset without actually changing any display after 747 * a system suspend. So grab the display core domain, which covers 748 * the HW blocks needed for the following programming. 749 */ 750 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 751 752 vlv_punit_get(dev_priv); 753 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 754 val &= ~DSPFREQGUAR_MASK_CHV; 755 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 756 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 757 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 758 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 759 50)) { 760 drm_err(display->drm, 761 "timed out waiting for CDclk change\n"); 762 } 763 764 vlv_punit_put(dev_priv); 765 766 intel_update_cdclk(display); 767 768 vlv_program_pfi_credits(display); 769 770 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 771 } 772 773 static int bdw_calc_cdclk(int min_cdclk) 774 { 775 if (min_cdclk > 540000) 776 return 675000; 777 else if (min_cdclk > 450000) 778 return 540000; 779 else if (min_cdclk > 337500) 780 return 450000; 781 else 782 return 337500; 783 } 784 785 static u8 bdw_calc_voltage_level(int cdclk) 786 { 787 switch (cdclk) { 788 default: 789 case 337500: 790 return 2; 791 case 450000: 792 return 0; 793 case 540000: 794 return 1; 795 case 675000: 796 return 3; 797 } 798 } 799 800 static void bdw_get_cdclk(struct intel_display *display, 801 struct intel_cdclk_config *cdclk_config) 802 { 803 u32 lcpll = intel_de_read(display, LCPLL_CTL); 804 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 805 806 if (lcpll & LCPLL_CD_SOURCE_FCLK) 807 cdclk_config->cdclk = 800000; 808 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 809 cdclk_config->cdclk = 450000; 810 else if (freq == LCPLL_CLK_FREQ_450) 811 cdclk_config->cdclk = 450000; 812 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 813 cdclk_config->cdclk = 540000; 814 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 815 cdclk_config->cdclk = 337500; 816 else 817 cdclk_config->cdclk = 675000; 818 819 /* 820 * Can't read this out :( Let's assume it's 821 * at least what the CDCLK frequency requires. 822 */ 823 cdclk_config->voltage_level = 824 bdw_calc_voltage_level(cdclk_config->cdclk); 825 } 826 827 static u32 bdw_cdclk_freq_sel(int cdclk) 828 { 829 switch (cdclk) { 830 default: 831 MISSING_CASE(cdclk); 832 fallthrough; 833 case 337500: 834 return LCPLL_CLK_FREQ_337_5_BDW; 835 case 450000: 836 return LCPLL_CLK_FREQ_450; 837 case 540000: 838 return LCPLL_CLK_FREQ_54O_BDW; 839 case 675000: 840 return LCPLL_CLK_FREQ_675_BDW; 841 } 842 } 843 844 static void bdw_set_cdclk(struct intel_display *display, 845 const struct intel_cdclk_config *cdclk_config, 846 enum pipe pipe) 847 { 848 struct drm_i915_private *dev_priv = to_i915(display->drm); 849 int cdclk = cdclk_config->cdclk; 850 int ret; 851 852 if (drm_WARN(display->drm, 853 (intel_de_read(display, LCPLL_CTL) & 854 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 855 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 856 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 857 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 858 "trying to change cdclk frequency with cdclk not enabled\n")) 859 return; 860 861 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 862 if (ret) { 863 drm_err(display->drm, 864 "failed to inform pcode about cdclk change\n"); 865 return; 866 } 867 868 intel_de_rmw(display, LCPLL_CTL, 869 0, LCPLL_CD_SOURCE_FCLK); 870 871 /* 872 * According to the spec, it should be enough to poll for this 1 us. 873 * However, extensive testing shows that this can take longer. 874 */ 875 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & 876 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 877 drm_err(display->drm, "Switching to FCLK failed\n"); 878 879 intel_de_rmw(display, LCPLL_CTL, 880 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 881 882 intel_de_rmw(display, LCPLL_CTL, 883 LCPLL_CD_SOURCE_FCLK, 0); 884 885 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & 886 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 887 drm_err(display->drm, "Switching back to LCPLL failed\n"); 888 889 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, 890 cdclk_config->voltage_level); 891 892 intel_de_write(display, CDCLK_FREQ, 893 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 894 895 intel_update_cdclk(display); 896 } 897 898 static int skl_calc_cdclk(int min_cdclk, int vco) 899 { 900 if (vco == 8640000) { 901 if (min_cdclk > 540000) 902 return 617143; 903 else if (min_cdclk > 432000) 904 return 540000; 905 else if (min_cdclk > 308571) 906 return 432000; 907 else 908 return 308571; 909 } else { 910 if (min_cdclk > 540000) 911 return 675000; 912 else if (min_cdclk > 450000) 913 return 540000; 914 else if (min_cdclk > 337500) 915 return 450000; 916 else 917 return 337500; 918 } 919 } 920 921 static u8 skl_calc_voltage_level(int cdclk) 922 { 923 if (cdclk > 540000) 924 return 3; 925 else if (cdclk > 450000) 926 return 2; 927 else if (cdclk > 337500) 928 return 1; 929 else 930 return 0; 931 } 932 933 static void skl_dpll0_update(struct intel_display *display, 934 struct intel_cdclk_config *cdclk_config) 935 { 936 u32 val; 937 938 cdclk_config->ref = 24000; 939 cdclk_config->vco = 0; 940 941 val = intel_de_read(display, LCPLL1_CTL); 942 if ((val & LCPLL_PLL_ENABLE) == 0) 943 return; 944 945 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) 946 return; 947 948 val = intel_de_read(display, DPLL_CTRL1); 949 950 if (drm_WARN_ON(display->drm, 951 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 952 DPLL_CTRL1_SSC(SKL_DPLL0) | 953 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 954 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 955 return; 956 957 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 958 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 959 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 960 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 961 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 962 cdclk_config->vco = 8100000; 963 break; 964 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 965 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 966 cdclk_config->vco = 8640000; 967 break; 968 default: 969 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 970 break; 971 } 972 } 973 974 static void skl_get_cdclk(struct intel_display *display, 975 struct intel_cdclk_config *cdclk_config) 976 { 977 u32 cdctl; 978 979 skl_dpll0_update(display, cdclk_config); 980 981 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 982 983 if (cdclk_config->vco == 0) 984 goto out; 985 986 cdctl = intel_de_read(display, CDCLK_CTL); 987 988 if (cdclk_config->vco == 8640000) { 989 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 990 case CDCLK_FREQ_450_432: 991 cdclk_config->cdclk = 432000; 992 break; 993 case CDCLK_FREQ_337_308: 994 cdclk_config->cdclk = 308571; 995 break; 996 case CDCLK_FREQ_540: 997 cdclk_config->cdclk = 540000; 998 break; 999 case CDCLK_FREQ_675_617: 1000 cdclk_config->cdclk = 617143; 1001 break; 1002 default: 1003 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1004 break; 1005 } 1006 } else { 1007 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1008 case CDCLK_FREQ_450_432: 1009 cdclk_config->cdclk = 450000; 1010 break; 1011 case CDCLK_FREQ_337_308: 1012 cdclk_config->cdclk = 337500; 1013 break; 1014 case CDCLK_FREQ_540: 1015 cdclk_config->cdclk = 540000; 1016 break; 1017 case CDCLK_FREQ_675_617: 1018 cdclk_config->cdclk = 675000; 1019 break; 1020 default: 1021 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1022 break; 1023 } 1024 } 1025 1026 out: 1027 /* 1028 * Can't read this out :( Let's assume it's 1029 * at least what the CDCLK frequency requires. 1030 */ 1031 cdclk_config->voltage_level = 1032 skl_calc_voltage_level(cdclk_config->cdclk); 1033 } 1034 1035 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1036 static int skl_cdclk_decimal(int cdclk) 1037 { 1038 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1039 } 1040 1041 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) 1042 { 1043 bool changed = display->cdclk.skl_preferred_vco_freq != vco; 1044 1045 display->cdclk.skl_preferred_vco_freq = vco; 1046 1047 if (changed) 1048 intel_update_max_cdclk(display); 1049 } 1050 1051 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) 1052 { 1053 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 1054 1055 /* 1056 * We always enable DPLL0 with the lowest link rate possible, but still 1057 * taking into account the VCO required to operate the eDP panel at the 1058 * desired frequency. The usual DP link rates operate with a VCO of 1059 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1060 * The modeset code is responsible for the selection of the exact link 1061 * rate later on, with the constraint of choosing a frequency that 1062 * works with vco. 1063 */ 1064 if (vco == 8640000) 1065 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1066 else 1067 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1068 } 1069 1070 static void skl_dpll0_enable(struct intel_display *display, int vco) 1071 { 1072 intel_de_rmw(display, DPLL_CTRL1, 1073 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1074 DPLL_CTRL1_SSC(SKL_DPLL0) | 1075 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1076 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1077 skl_dpll0_link_rate(display, vco)); 1078 intel_de_posting_read(display, DPLL_CTRL1); 1079 1080 intel_de_rmw(display, LCPLL1_CTL, 1081 0, LCPLL_PLL_ENABLE); 1082 1083 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1084 drm_err(display->drm, "DPLL0 not locked\n"); 1085 1086 display->cdclk.hw.vco = vco; 1087 1088 /* We'll want to keep using the current vco from now on. */ 1089 skl_set_preferred_cdclk_vco(display, vco); 1090 } 1091 1092 static void skl_dpll0_disable(struct intel_display *display) 1093 { 1094 intel_de_rmw(display, LCPLL1_CTL, 1095 LCPLL_PLL_ENABLE, 0); 1096 1097 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1098 drm_err(display->drm, "Couldn't disable DPLL0\n"); 1099 1100 display->cdclk.hw.vco = 0; 1101 } 1102 1103 static u32 skl_cdclk_freq_sel(struct intel_display *display, 1104 int cdclk, int vco) 1105 { 1106 switch (cdclk) { 1107 default: 1108 drm_WARN_ON(display->drm, 1109 cdclk != display->cdclk.hw.bypass); 1110 drm_WARN_ON(display->drm, vco != 0); 1111 fallthrough; 1112 case 308571: 1113 case 337500: 1114 return CDCLK_FREQ_337_308; 1115 case 450000: 1116 case 432000: 1117 return CDCLK_FREQ_450_432; 1118 case 540000: 1119 return CDCLK_FREQ_540; 1120 case 617143: 1121 case 675000: 1122 return CDCLK_FREQ_675_617; 1123 } 1124 } 1125 1126 static void skl_set_cdclk(struct intel_display *display, 1127 const struct intel_cdclk_config *cdclk_config, 1128 enum pipe pipe) 1129 { 1130 struct drm_i915_private *dev_priv = to_i915(display->drm); 1131 int cdclk = cdclk_config->cdclk; 1132 int vco = cdclk_config->vco; 1133 u32 freq_select, cdclk_ctl; 1134 int ret; 1135 1136 /* 1137 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1138 * unsupported on SKL. In theory this should never happen since only 1139 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1140 * supported on SKL either, see the above WA. WARN whenever trying to 1141 * use the corresponding VCO freq as that always leads to using the 1142 * minimum 308MHz CDCLK. 1143 */ 1144 drm_WARN_ON_ONCE(display->drm, 1145 IS_SKYLAKE(dev_priv) && vco == 8640000); 1146 1147 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1148 SKL_CDCLK_PREPARE_FOR_CHANGE, 1149 SKL_CDCLK_READY_FOR_CHANGE, 1150 SKL_CDCLK_READY_FOR_CHANGE, 3); 1151 if (ret) { 1152 drm_err(display->drm, 1153 "Failed to inform PCU about cdclk change (%d)\n", ret); 1154 return; 1155 } 1156 1157 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); 1158 1159 if (display->cdclk.hw.vco != 0 && 1160 display->cdclk.hw.vco != vco) 1161 skl_dpll0_disable(display); 1162 1163 cdclk_ctl = intel_de_read(display, CDCLK_CTL); 1164 1165 if (display->cdclk.hw.vco != vco) { 1166 /* Wa Display #1183: skl,kbl,cfl */ 1167 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1168 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1169 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1170 } 1171 1172 /* Wa Display #1183: skl,kbl,cfl */ 1173 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1174 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1175 intel_de_posting_read(display, CDCLK_CTL); 1176 1177 if (display->cdclk.hw.vco != vco) 1178 skl_dpll0_enable(display, vco); 1179 1180 /* Wa Display #1183: skl,kbl,cfl */ 1181 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1182 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1183 1184 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1185 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1186 1187 /* Wa Display #1183: skl,kbl,cfl */ 1188 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1189 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1190 intel_de_posting_read(display, CDCLK_CTL); 1191 1192 /* inform PCU of the change */ 1193 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1194 cdclk_config->voltage_level); 1195 1196 intel_update_cdclk(display); 1197 } 1198 1199 static void skl_sanitize_cdclk(struct intel_display *display) 1200 { 1201 u32 cdctl, expected; 1202 1203 /* 1204 * check if the pre-os initialized the display 1205 * There is SWF18 scratchpad register defined which is set by the 1206 * pre-os which can be used by the OS drivers to check the status 1207 */ 1208 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1209 goto sanitize; 1210 1211 intel_update_cdclk(display); 1212 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1213 1214 /* Is PLL enabled and locked ? */ 1215 if (display->cdclk.hw.vco == 0 || 1216 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 1217 goto sanitize; 1218 1219 /* DPLL okay; verify the cdclock 1220 * 1221 * Noticed in some instances that the freq selection is correct but 1222 * decimal part is programmed wrong from BIOS where pre-os does not 1223 * enable display. Verify the same as well. 1224 */ 1225 cdctl = intel_de_read(display, CDCLK_CTL); 1226 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1227 skl_cdclk_decimal(display->cdclk.hw.cdclk); 1228 if (cdctl == expected) 1229 /* All well; nothing to sanitize */ 1230 return; 1231 1232 sanitize: 1233 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 1234 1235 /* force cdclk programming */ 1236 display->cdclk.hw.cdclk = 0; 1237 /* force full PLL disable + enable */ 1238 display->cdclk.hw.vco = ~0; 1239 } 1240 1241 static void skl_cdclk_init_hw(struct intel_display *display) 1242 { 1243 struct intel_cdclk_config cdclk_config; 1244 1245 skl_sanitize_cdclk(display); 1246 1247 if (display->cdclk.hw.cdclk != 0 && 1248 display->cdclk.hw.vco != 0) { 1249 /* 1250 * Use the current vco as our initial 1251 * guess as to what the preferred vco is. 1252 */ 1253 if (display->cdclk.skl_preferred_vco_freq == 0) 1254 skl_set_preferred_cdclk_vco(display, 1255 display->cdclk.hw.vco); 1256 return; 1257 } 1258 1259 cdclk_config = display->cdclk.hw; 1260 1261 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; 1262 if (cdclk_config.vco == 0) 1263 cdclk_config.vco = 8100000; 1264 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1265 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1266 1267 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1268 } 1269 1270 static void skl_cdclk_uninit_hw(struct intel_display *display) 1271 { 1272 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 1273 1274 cdclk_config.cdclk = cdclk_config.bypass; 1275 cdclk_config.vco = 0; 1276 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1277 1278 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1279 } 1280 1281 struct intel_cdclk_vals { 1282 u32 cdclk; 1283 u16 refclk; 1284 u16 waveform; 1285 u8 ratio; 1286 }; 1287 1288 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1289 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1290 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1291 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1292 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1293 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1294 {} 1295 }; 1296 1297 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1298 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1299 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1300 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1301 {} 1302 }; 1303 1304 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1305 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1306 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1307 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1308 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1309 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1310 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1311 1312 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1313 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1314 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1315 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1316 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1317 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1318 1319 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1320 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1321 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1322 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1323 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1324 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1325 {} 1326 }; 1327 1328 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1329 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1330 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1331 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1332 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1333 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1334 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1335 1336 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1337 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1338 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1339 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1340 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1341 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1342 1343 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1344 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1345 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1346 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1347 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1348 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1349 {} 1350 }; 1351 1352 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1353 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1354 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1355 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1356 1357 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1358 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1359 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1360 1361 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1362 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1363 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1364 {} 1365 }; 1366 1367 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1368 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1369 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1370 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1371 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1372 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1373 1374 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1375 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1376 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1377 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1378 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1379 1380 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1381 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1382 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1383 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1384 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1385 {} 1386 }; 1387 1388 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1389 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1390 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1391 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1392 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1393 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1394 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1395 1396 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1397 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1398 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1399 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1400 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1401 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1402 1403 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1404 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1405 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1406 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1407 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1408 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1409 {} 1410 }; 1411 1412 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1413 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1414 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1415 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1416 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1417 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1418 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1419 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1420 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1421 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1422 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1423 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1424 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1425 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1426 {} 1427 }; 1428 1429 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1430 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1431 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1432 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1433 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1434 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1435 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1436 {} 1437 }; 1438 1439 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1440 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1441 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1442 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1443 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1444 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1445 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1446 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1447 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1448 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1449 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1450 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1451 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1452 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1453 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1454 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1455 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1456 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1457 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1458 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1459 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1460 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1461 {} 1462 }; 1463 1464 /* 1465 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1466 */ 1467 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1468 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1469 {} 1470 }; 1471 1472 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { 1473 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1474 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1475 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1476 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1477 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1478 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1479 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1480 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1481 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1482 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff }, 1483 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff }, 1484 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff }, 1485 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff }, 1486 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1487 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1488 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1489 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1490 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1491 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1492 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1493 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1494 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1495 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1496 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1497 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1498 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1499 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1500 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1501 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1502 {} 1503 }; 1504 1505 static const int cdclk_squash_len = 16; 1506 1507 static int cdclk_squash_divider(u16 waveform) 1508 { 1509 return hweight16(waveform ?: 0xffff); 1510 } 1511 1512 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1513 { 1514 /* 2 * cd2x divider */ 1515 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1516 cdclk * cdclk_squash_len); 1517 } 1518 1519 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 1520 { 1521 const struct intel_cdclk_vals *table = display->cdclk.table; 1522 int i; 1523 1524 for (i = 0; table[i].refclk; i++) 1525 if (table[i].refclk == display->cdclk.hw.ref && 1526 table[i].cdclk >= min_cdclk) 1527 return table[i].cdclk; 1528 1529 drm_WARN(display->drm, 1, 1530 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1531 min_cdclk, display->cdclk.hw.ref); 1532 return 0; 1533 } 1534 1535 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) 1536 { 1537 const struct intel_cdclk_vals *table = display->cdclk.table; 1538 int i; 1539 1540 if (cdclk == display->cdclk.hw.bypass) 1541 return 0; 1542 1543 for (i = 0; table[i].refclk; i++) 1544 if (table[i].refclk == display->cdclk.hw.ref && 1545 table[i].cdclk == cdclk) 1546 return display->cdclk.hw.ref * table[i].ratio; 1547 1548 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1549 cdclk, display->cdclk.hw.ref); 1550 return 0; 1551 } 1552 1553 static u8 bxt_calc_voltage_level(int cdclk) 1554 { 1555 return DIV_ROUND_UP(cdclk, 25000); 1556 } 1557 1558 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1559 const int voltage_level_max_cdclk[]) 1560 { 1561 int voltage_level; 1562 1563 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1564 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1565 return voltage_level; 1566 } 1567 1568 MISSING_CASE(cdclk); 1569 return num_voltage_levels - 1; 1570 } 1571 1572 static u8 icl_calc_voltage_level(int cdclk) 1573 { 1574 static const int icl_voltage_level_max_cdclk[] = { 1575 [0] = 312000, 1576 [1] = 556800, 1577 [2] = 652800, 1578 }; 1579 1580 return calc_voltage_level(cdclk, 1581 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1582 icl_voltage_level_max_cdclk); 1583 } 1584 1585 static u8 ehl_calc_voltage_level(int cdclk) 1586 { 1587 static const int ehl_voltage_level_max_cdclk[] = { 1588 [0] = 180000, 1589 [1] = 312000, 1590 [2] = 326400, 1591 /* 1592 * Bspec lists the limit as 556.8 MHz, but some JSL 1593 * development boards (at least) boot with 652.8 MHz 1594 */ 1595 [3] = 652800, 1596 }; 1597 1598 return calc_voltage_level(cdclk, 1599 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1600 ehl_voltage_level_max_cdclk); 1601 } 1602 1603 static u8 tgl_calc_voltage_level(int cdclk) 1604 { 1605 static const int tgl_voltage_level_max_cdclk[] = { 1606 [0] = 312000, 1607 [1] = 326400, 1608 [2] = 556800, 1609 [3] = 652800, 1610 }; 1611 1612 return calc_voltage_level(cdclk, 1613 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1614 tgl_voltage_level_max_cdclk); 1615 } 1616 1617 static u8 rplu_calc_voltage_level(int cdclk) 1618 { 1619 static const int rplu_voltage_level_max_cdclk[] = { 1620 [0] = 312000, 1621 [1] = 480000, 1622 [2] = 556800, 1623 [3] = 652800, 1624 }; 1625 1626 return calc_voltage_level(cdclk, 1627 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1628 rplu_voltage_level_max_cdclk); 1629 } 1630 1631 static u8 xe3lpd_calc_voltage_level(int cdclk) 1632 { 1633 /* 1634 * Starting with xe3lpd power controller does not need the voltage 1635 * index when doing the modeset update. This function is best left 1636 * defined but returning 0 to the mask. 1637 */ 1638 return 0; 1639 } 1640 1641 static void icl_readout_refclk(struct intel_display *display, 1642 struct intel_cdclk_config *cdclk_config) 1643 { 1644 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1645 1646 switch (dssm) { 1647 default: 1648 MISSING_CASE(dssm); 1649 fallthrough; 1650 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1651 cdclk_config->ref = 24000; 1652 break; 1653 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1654 cdclk_config->ref = 19200; 1655 break; 1656 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1657 cdclk_config->ref = 38400; 1658 break; 1659 } 1660 } 1661 1662 static void bxt_de_pll_readout(struct intel_display *display, 1663 struct intel_cdclk_config *cdclk_config) 1664 { 1665 struct drm_i915_private *dev_priv = to_i915(display->drm); 1666 u32 val, ratio; 1667 1668 if (IS_DG2(dev_priv)) 1669 cdclk_config->ref = 38400; 1670 else if (DISPLAY_VER(display) >= 11) 1671 icl_readout_refclk(display, cdclk_config); 1672 else 1673 cdclk_config->ref = 19200; 1674 1675 val = intel_de_read(display, BXT_DE_PLL_ENABLE); 1676 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1677 (val & BXT_DE_PLL_LOCK) == 0) { 1678 /* 1679 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1680 * setting it to zero is a way to signal that. 1681 */ 1682 cdclk_config->vco = 0; 1683 return; 1684 } 1685 1686 /* 1687 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1688 * gen9lp had it in a separate PLL control register. 1689 */ 1690 if (DISPLAY_VER(display) >= 11) 1691 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1692 else 1693 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1694 1695 cdclk_config->vco = ratio * cdclk_config->ref; 1696 } 1697 1698 static void bxt_get_cdclk(struct intel_display *display, 1699 struct intel_cdclk_config *cdclk_config) 1700 { 1701 u32 squash_ctl = 0; 1702 u32 divider; 1703 int div; 1704 1705 bxt_de_pll_readout(display, cdclk_config); 1706 1707 if (DISPLAY_VER(display) >= 12) 1708 cdclk_config->bypass = cdclk_config->ref / 2; 1709 else if (DISPLAY_VER(display) >= 11) 1710 cdclk_config->bypass = 50000; 1711 else 1712 cdclk_config->bypass = cdclk_config->ref; 1713 1714 if (cdclk_config->vco == 0) { 1715 cdclk_config->cdclk = cdclk_config->bypass; 1716 goto out; 1717 } 1718 1719 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1720 1721 switch (divider) { 1722 case BXT_CDCLK_CD2X_DIV_SEL_1: 1723 div = 2; 1724 break; 1725 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1726 div = 3; 1727 break; 1728 case BXT_CDCLK_CD2X_DIV_SEL_2: 1729 div = 4; 1730 break; 1731 case BXT_CDCLK_CD2X_DIV_SEL_4: 1732 div = 8; 1733 break; 1734 default: 1735 MISSING_CASE(divider); 1736 return; 1737 } 1738 1739 if (HAS_CDCLK_SQUASH(display)) 1740 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); 1741 1742 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1743 u16 waveform; 1744 int size; 1745 1746 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1747 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1748 1749 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1750 cdclk_config->vco, size * div); 1751 } else { 1752 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1753 } 1754 1755 out: 1756 if (DISPLAY_VER(display) >= 20) 1757 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 1758 /* 1759 * Can't read this out :( Let's assume it's 1760 * at least what the CDCLK frequency requires. 1761 */ 1762 cdclk_config->voltage_level = 1763 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); 1764 } 1765 1766 static void bxt_de_pll_disable(struct intel_display *display) 1767 { 1768 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); 1769 1770 /* Timeout 200us */ 1771 if (intel_de_wait_for_clear(display, 1772 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1773 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); 1774 1775 display->cdclk.hw.vco = 0; 1776 } 1777 1778 static void bxt_de_pll_enable(struct intel_display *display, int vco) 1779 { 1780 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1781 1782 intel_de_rmw(display, BXT_DE_PLL_CTL, 1783 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1784 1785 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1786 1787 /* Timeout 200us */ 1788 if (intel_de_wait_for_set(display, 1789 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1790 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); 1791 1792 display->cdclk.hw.vco = vco; 1793 } 1794 1795 static void icl_cdclk_pll_disable(struct intel_display *display) 1796 { 1797 intel_de_rmw(display, BXT_DE_PLL_ENABLE, 1798 BXT_DE_PLL_PLL_ENABLE, 0); 1799 1800 /* Timeout 200us */ 1801 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1802 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); 1803 1804 display->cdclk.hw.vco = 0; 1805 } 1806 1807 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) 1808 { 1809 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1810 u32 val; 1811 1812 val = ICL_CDCLK_PLL_RATIO(ratio); 1813 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1814 1815 val |= BXT_DE_PLL_PLL_ENABLE; 1816 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1817 1818 /* Timeout 200us */ 1819 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1820 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); 1821 1822 display->cdclk.hw.vco = vco; 1823 } 1824 1825 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) 1826 { 1827 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1828 u32 val; 1829 1830 /* Write PLL ratio without disabling */ 1831 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1832 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1833 1834 /* Submit freq change request */ 1835 val |= BXT_DE_PLL_FREQ_REQ; 1836 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1837 1838 /* Timeout 200us */ 1839 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, 1840 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1841 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); 1842 1843 val &= ~BXT_DE_PLL_FREQ_REQ; 1844 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1845 1846 display->cdclk.hw.vco = vco; 1847 } 1848 1849 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 1850 { 1851 if (DISPLAY_VER(display) >= 12) { 1852 if (pipe == INVALID_PIPE) 1853 return TGL_CDCLK_CD2X_PIPE_NONE; 1854 else 1855 return TGL_CDCLK_CD2X_PIPE(pipe); 1856 } else if (DISPLAY_VER(display) >= 11) { 1857 if (pipe == INVALID_PIPE) 1858 return ICL_CDCLK_CD2X_PIPE_NONE; 1859 else 1860 return ICL_CDCLK_CD2X_PIPE(pipe); 1861 } else { 1862 if (pipe == INVALID_PIPE) 1863 return BXT_CDCLK_CD2X_PIPE_NONE; 1864 else 1865 return BXT_CDCLK_CD2X_PIPE(pipe); 1866 } 1867 } 1868 1869 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 1870 int cdclk, int vco, u16 waveform) 1871 { 1872 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1873 switch (cdclk_divider(cdclk, vco, waveform)) { 1874 default: 1875 drm_WARN_ON(display->drm, 1876 cdclk != display->cdclk.hw.bypass); 1877 drm_WARN_ON(display->drm, vco != 0); 1878 fallthrough; 1879 case 2: 1880 return BXT_CDCLK_CD2X_DIV_SEL_1; 1881 case 3: 1882 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1883 case 4: 1884 return BXT_CDCLK_CD2X_DIV_SEL_2; 1885 case 8: 1886 return BXT_CDCLK_CD2X_DIV_SEL_4; 1887 } 1888 } 1889 1890 static u16 cdclk_squash_waveform(struct intel_display *display, 1891 int cdclk) 1892 { 1893 const struct intel_cdclk_vals *table = display->cdclk.table; 1894 int i; 1895 1896 if (cdclk == display->cdclk.hw.bypass) 1897 return 0; 1898 1899 for (i = 0; table[i].refclk; i++) 1900 if (table[i].refclk == display->cdclk.hw.ref && 1901 table[i].cdclk == cdclk) 1902 return table[i].waveform; 1903 1904 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1905 cdclk, display->cdclk.hw.ref); 1906 1907 return 0xffff; 1908 } 1909 1910 static void icl_cdclk_pll_update(struct intel_display *display, int vco) 1911 { 1912 if (display->cdclk.hw.vco != 0 && 1913 display->cdclk.hw.vco != vco) 1914 icl_cdclk_pll_disable(display); 1915 1916 if (display->cdclk.hw.vco != vco) 1917 icl_cdclk_pll_enable(display, vco); 1918 } 1919 1920 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) 1921 { 1922 if (display->cdclk.hw.vco != 0 && 1923 display->cdclk.hw.vco != vco) 1924 bxt_de_pll_disable(display); 1925 1926 if (display->cdclk.hw.vco != vco) 1927 bxt_de_pll_enable(display, vco); 1928 } 1929 1930 static void dg2_cdclk_squash_program(struct intel_display *display, 1931 u16 waveform) 1932 { 1933 u32 squash_ctl = 0; 1934 1935 if (waveform) 1936 squash_ctl = CDCLK_SQUASH_ENABLE | 1937 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1938 1939 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); 1940 } 1941 1942 static bool cdclk_pll_is_unknown(unsigned int vco) 1943 { 1944 /* 1945 * Ensure driver does not take the crawl path for the 1946 * case when the vco is set to ~0 in the 1947 * sanitize path. 1948 */ 1949 return vco == ~0; 1950 } 1951 1952 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) 1953 { 1954 return DISPLAY_VER(display) >= 20; 1955 } 1956 1957 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) 1958 { 1959 if (mdclk_source_is_cdclk_pll(display)) 1960 return MDCLK_SOURCE_SEL_CDCLK_PLL; 1961 1962 return MDCLK_SOURCE_SEL_CD2XCLK; 1963 } 1964 1965 int intel_mdclk_cdclk_ratio(struct intel_display *display, 1966 const struct intel_cdclk_config *cdclk_config) 1967 { 1968 if (mdclk_source_is_cdclk_pll(display)) 1969 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 1970 1971 /* Otherwise, source for MDCLK is CD2XCLK. */ 1972 return 2; 1973 } 1974 1975 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, 1976 const struct intel_cdclk_config *cdclk_config) 1977 { 1978 struct drm_i915_private *i915 = to_i915(display->drm); 1979 1980 intel_dbuf_mdclk_cdclk_ratio_update(i915, 1981 intel_mdclk_cdclk_ratio(display, cdclk_config), 1982 cdclk_config->joined_mbus); 1983 } 1984 1985 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, 1986 const struct intel_cdclk_config *old_cdclk_config, 1987 const struct intel_cdclk_config *new_cdclk_config, 1988 struct intel_cdclk_config *mid_cdclk_config) 1989 { 1990 u16 old_waveform, new_waveform, mid_waveform; 1991 int old_div, new_div, mid_div; 1992 1993 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 1994 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 1995 return false; 1996 1997 /* Return if both Squash and Crawl are not present */ 1998 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 1999 return false; 2000 2001 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); 2002 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); 2003 2004 /* Return if Squash only or Crawl only is the desired action */ 2005 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 2006 old_cdclk_config->vco == new_cdclk_config->vco || 2007 old_waveform == new_waveform) 2008 return false; 2009 2010 old_div = cdclk_divider(old_cdclk_config->cdclk, 2011 old_cdclk_config->vco, old_waveform); 2012 new_div = cdclk_divider(new_cdclk_config->cdclk, 2013 new_cdclk_config->vco, new_waveform); 2014 2015 /* 2016 * Should not happen currently. We might need more midpoint 2017 * transitions if we need to also change the cd2x divider. 2018 */ 2019 if (drm_WARN_ON(display->drm, old_div != new_div)) 2020 return false; 2021 2022 *mid_cdclk_config = *new_cdclk_config; 2023 2024 /* 2025 * Populate the mid_cdclk_config accordingly. 2026 * - If moving to a higher cdclk, the desired action is squashing. 2027 * The mid cdclk config should have the new (squash) waveform. 2028 * - If moving to a lower cdclk, the desired action is crawling. 2029 * The mid cdclk config should have the new vco. 2030 */ 2031 2032 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 2033 mid_cdclk_config->vco = old_cdclk_config->vco; 2034 mid_div = old_div; 2035 mid_waveform = new_waveform; 2036 } else { 2037 mid_cdclk_config->vco = new_cdclk_config->vco; 2038 mid_div = new_div; 2039 mid_waveform = old_waveform; 2040 } 2041 2042 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 2043 mid_cdclk_config->vco, 2044 cdclk_squash_len * mid_div); 2045 2046 /* make sure the mid clock came out sane */ 2047 2048 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < 2049 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 2050 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > 2051 display->cdclk.max_cdclk_freq); 2052 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != 2053 mid_waveform); 2054 2055 return true; 2056 } 2057 2058 static bool pll_enable_wa_needed(struct intel_display *display) 2059 { 2060 struct drm_i915_private *dev_priv = to_i915(display->drm); 2061 2062 return (DISPLAY_VERx100(display) == 2000 || 2063 DISPLAY_VERx100(display) == 1400 || 2064 IS_DG2(dev_priv)) && 2065 display->cdclk.hw.vco > 0; 2066 } 2067 2068 static u32 bxt_cdclk_ctl(struct intel_display *display, 2069 const struct intel_cdclk_config *cdclk_config, 2070 enum pipe pipe) 2071 { 2072 struct drm_i915_private *i915 = to_i915(display->drm); 2073 int cdclk = cdclk_config->cdclk; 2074 int vco = cdclk_config->vco; 2075 u16 waveform; 2076 u32 val; 2077 2078 waveform = cdclk_squash_waveform(display, cdclk); 2079 2080 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | 2081 bxt_cdclk_cd2x_pipe(display, pipe); 2082 2083 /* 2084 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2085 * enable otherwise. 2086 */ 2087 if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) && 2088 cdclk >= 500000) 2089 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2090 2091 if (DISPLAY_VER(display) >= 20) 2092 val |= xe2lpd_mdclk_source_sel(display); 2093 else 2094 val |= skl_cdclk_decimal(cdclk); 2095 2096 return val; 2097 } 2098 2099 static void _bxt_set_cdclk(struct intel_display *display, 2100 const struct intel_cdclk_config *cdclk_config, 2101 enum pipe pipe) 2102 { 2103 int cdclk = cdclk_config->cdclk; 2104 int vco = cdclk_config->vco; 2105 2106 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && 2107 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { 2108 if (display->cdclk.hw.vco != vco) 2109 adlp_cdclk_pll_crawl(display, vco); 2110 } else if (DISPLAY_VER(display) >= 11) { 2111 /* wa_15010685871: dg2, mtl */ 2112 if (pll_enable_wa_needed(display)) 2113 dg2_cdclk_squash_program(display, 0); 2114 2115 icl_cdclk_pll_update(display, vco); 2116 } else { 2117 bxt_cdclk_pll_update(display, vco); 2118 } 2119 2120 if (HAS_CDCLK_SQUASH(display)) { 2121 u16 waveform = cdclk_squash_waveform(display, cdclk); 2122 2123 dg2_cdclk_squash_program(display, waveform); 2124 } 2125 2126 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); 2127 2128 if (pipe != INVALID_PIPE) 2129 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 2130 } 2131 2132 static void bxt_set_cdclk(struct intel_display *display, 2133 const struct intel_cdclk_config *cdclk_config, 2134 enum pipe pipe) 2135 { 2136 struct drm_i915_private *dev_priv = to_i915(display->drm); 2137 struct intel_cdclk_config mid_cdclk_config; 2138 int cdclk = cdclk_config->cdclk; 2139 int ret = 0; 2140 2141 /* 2142 * Inform power controller of upcoming frequency change. 2143 * Display versions 14 and beyond do not follow the PUnit 2144 * mailbox communication, skip 2145 * this step. 2146 */ 2147 if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv)) 2148 /* NOOP */; 2149 else if (DISPLAY_VER(display) >= 11) 2150 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 2151 SKL_CDCLK_PREPARE_FOR_CHANGE, 2152 SKL_CDCLK_READY_FOR_CHANGE, 2153 SKL_CDCLK_READY_FOR_CHANGE, 3); 2154 else 2155 /* 2156 * BSpec requires us to wait up to 150usec, but that leads to 2157 * timeouts; the 2ms used here is based on experiment. 2158 */ 2159 ret = snb_pcode_write_timeout(&dev_priv->uncore, 2160 HSW_PCODE_DE_WRITE_FREQ_REQ, 2161 0x80000000, 150, 2); 2162 2163 if (ret) { 2164 drm_err(display->drm, 2165 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2166 ret, cdclk); 2167 return; 2168 } 2169 2170 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) 2171 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2172 2173 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, 2174 cdclk_config, &mid_cdclk_config)) { 2175 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); 2176 _bxt_set_cdclk(display, cdclk_config, pipe); 2177 } else { 2178 _bxt_set_cdclk(display, cdclk_config, pipe); 2179 } 2180 2181 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) 2182 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2183 2184 if (DISPLAY_VER(display) >= 14) 2185 /* 2186 * NOOP - No Pcode communication needed for 2187 * Display versions 14 and beyond 2188 */; 2189 else if (DISPLAY_VER(display) >= 11 && !IS_DG2(dev_priv)) 2190 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 2191 cdclk_config->voltage_level); 2192 if (DISPLAY_VER(display) < 11) { 2193 /* 2194 * The timeout isn't specified, the 2ms used here is based on 2195 * experiment. 2196 * FIXME: Waiting for the request completion could be delayed 2197 * until the next PCODE request based on BSpec. 2198 */ 2199 ret = snb_pcode_write_timeout(&dev_priv->uncore, 2200 HSW_PCODE_DE_WRITE_FREQ_REQ, 2201 cdclk_config->voltage_level, 2202 150, 2); 2203 } 2204 if (ret) { 2205 drm_err(display->drm, 2206 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2207 ret, cdclk); 2208 return; 2209 } 2210 2211 intel_update_cdclk(display); 2212 2213 if (DISPLAY_VER(display) >= 11) 2214 /* 2215 * Can't read out the voltage level :( 2216 * Let's just assume everything is as expected. 2217 */ 2218 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; 2219 } 2220 2221 static void bxt_sanitize_cdclk(struct intel_display *display) 2222 { 2223 u32 cdctl, expected; 2224 int cdclk, vco; 2225 2226 intel_update_cdclk(display); 2227 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 2228 2229 if (display->cdclk.hw.vco == 0 || 2230 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 2231 goto sanitize; 2232 2233 /* Make sure this is a legal cdclk value for the platform */ 2234 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); 2235 if (cdclk != display->cdclk.hw.cdclk) 2236 goto sanitize; 2237 2238 /* Make sure the VCO is correct for the cdclk */ 2239 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 2240 if (vco != display->cdclk.hw.vco) 2241 goto sanitize; 2242 2243 /* 2244 * Some BIOS versions leave an incorrect decimal frequency value and 2245 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2246 * so sanitize this register. 2247 */ 2248 cdctl = intel_de_read(display, CDCLK_CTL); 2249 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); 2250 2251 /* 2252 * Let's ignore the pipe field, since BIOS could have configured the 2253 * dividers both synching to an active pipe, or asynchronously 2254 * (PIPE_NONE). 2255 */ 2256 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2257 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2258 2259 if (cdctl == expected) 2260 /* All well; nothing to sanitize */ 2261 return; 2262 2263 sanitize: 2264 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 2265 2266 /* force cdclk programming */ 2267 display->cdclk.hw.cdclk = 0; 2268 2269 /* force full PLL disable + enable */ 2270 display->cdclk.hw.vco = ~0; 2271 } 2272 2273 static void bxt_cdclk_init_hw(struct intel_display *display) 2274 { 2275 struct intel_cdclk_config cdclk_config; 2276 2277 bxt_sanitize_cdclk(display); 2278 2279 if (display->cdclk.hw.cdclk != 0 && 2280 display->cdclk.hw.vco != 0) 2281 return; 2282 2283 cdclk_config = display->cdclk.hw; 2284 2285 /* 2286 * FIXME: 2287 * - The initial CDCLK needs to be read from VBT. 2288 * Need to make this change after VBT has changes for BXT. 2289 */ 2290 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); 2291 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); 2292 cdclk_config.voltage_level = 2293 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2294 2295 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2296 } 2297 2298 static void bxt_cdclk_uninit_hw(struct intel_display *display) 2299 { 2300 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 2301 2302 cdclk_config.cdclk = cdclk_config.bypass; 2303 cdclk_config.vco = 0; 2304 cdclk_config.voltage_level = 2305 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2306 2307 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2308 } 2309 2310 /** 2311 * intel_cdclk_init_hw - Initialize CDCLK hardware 2312 * @display: display instance 2313 * 2314 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and 2315 * sanitizing the state of the hardware if needed. This is generally done only 2316 * during the display core initialization sequence, after which the DMC will 2317 * take care of turning CDCLK off/on as needed. 2318 */ 2319 void intel_cdclk_init_hw(struct intel_display *display) 2320 { 2321 struct drm_i915_private *i915 = to_i915(display->drm); 2322 2323 if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) 2324 bxt_cdclk_init_hw(display); 2325 else if (DISPLAY_VER(display) == 9) 2326 skl_cdclk_init_hw(display); 2327 } 2328 2329 /** 2330 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2331 * @display: display instance 2332 * 2333 * Uninitialize CDCLK. This is done only during the display core 2334 * uninitialization sequence. 2335 */ 2336 void intel_cdclk_uninit_hw(struct intel_display *display) 2337 { 2338 struct drm_i915_private *i915 = to_i915(display->drm); 2339 2340 if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) 2341 bxt_cdclk_uninit_hw(display); 2342 else if (DISPLAY_VER(display) == 9) 2343 skl_cdclk_uninit_hw(display); 2344 } 2345 2346 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, 2347 const struct intel_cdclk_config *a, 2348 const struct intel_cdclk_config *b) 2349 { 2350 u16 old_waveform; 2351 u16 new_waveform; 2352 2353 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); 2354 2355 if (a->vco == 0 || b->vco == 0) 2356 return false; 2357 2358 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2359 return false; 2360 2361 old_waveform = cdclk_squash_waveform(display, a->cdclk); 2362 new_waveform = cdclk_squash_waveform(display, b->cdclk); 2363 2364 return a->vco != b->vco && 2365 old_waveform != new_waveform; 2366 } 2367 2368 static bool intel_cdclk_can_crawl(struct intel_display *display, 2369 const struct intel_cdclk_config *a, 2370 const struct intel_cdclk_config *b) 2371 { 2372 int a_div, b_div; 2373 2374 if (!HAS_CDCLK_CRAWL(display)) 2375 return false; 2376 2377 /* 2378 * The vco and cd2x divider will change independently 2379 * from each, so we disallow cd2x change when crawling. 2380 */ 2381 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2382 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2383 2384 return a->vco != 0 && b->vco != 0 && 2385 a->vco != b->vco && 2386 a_div == b_div && 2387 a->ref == b->ref; 2388 } 2389 2390 static bool intel_cdclk_can_squash(struct intel_display *display, 2391 const struct intel_cdclk_config *a, 2392 const struct intel_cdclk_config *b) 2393 { 2394 /* 2395 * FIXME should store a bit more state in intel_cdclk_config 2396 * to differentiate squasher vs. cd2x divider properly. For 2397 * the moment all platforms with squasher use a fixed cd2x 2398 * divider. 2399 */ 2400 if (!HAS_CDCLK_SQUASH(display)) 2401 return false; 2402 2403 return a->cdclk != b->cdclk && 2404 a->vco != 0 && 2405 a->vco == b->vco && 2406 a->ref == b->ref; 2407 } 2408 2409 /** 2410 * intel_cdclk_clock_changed - Check whether the clock changed 2411 * @a: first CDCLK configuration 2412 * @b: second CDCLK configuration 2413 * 2414 * Returns: 2415 * True if CDCLK changed in a way that requires re-programming and 2416 * False otherwise. 2417 */ 2418 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2419 const struct intel_cdclk_config *b) 2420 { 2421 return a->cdclk != b->cdclk || 2422 a->vco != b->vco || 2423 a->ref != b->ref; 2424 } 2425 2426 /** 2427 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2428 * configurations requires only a cd2x divider update 2429 * @display: display instance 2430 * @a: first CDCLK configuration 2431 * @b: second CDCLK configuration 2432 * 2433 * Returns: 2434 * True if changing between the two CDCLK configurations 2435 * can be done with just a cd2x divider update, false if not. 2436 */ 2437 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, 2438 const struct intel_cdclk_config *a, 2439 const struct intel_cdclk_config *b) 2440 { 2441 struct drm_i915_private *dev_priv = to_i915(display->drm); 2442 2443 /* Older hw doesn't have the capability */ 2444 if (DISPLAY_VER(display) < 10 && !IS_BROXTON(dev_priv)) 2445 return false; 2446 2447 /* 2448 * FIXME should store a bit more state in intel_cdclk_config 2449 * to differentiate squasher vs. cd2x divider properly. For 2450 * the moment all platforms with squasher use a fixed cd2x 2451 * divider. 2452 */ 2453 if (HAS_CDCLK_SQUASH(display)) 2454 return false; 2455 2456 return a->cdclk != b->cdclk && 2457 a->vco != 0 && 2458 a->vco == b->vco && 2459 a->ref == b->ref; 2460 } 2461 2462 /** 2463 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2464 * @a: first CDCLK configuration 2465 * @b: second CDCLK configuration 2466 * 2467 * Returns: 2468 * True if the CDCLK configurations don't match, false if they do. 2469 */ 2470 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2471 const struct intel_cdclk_config *b) 2472 { 2473 return intel_cdclk_clock_changed(a, b) || 2474 a->voltage_level != b->voltage_level; 2475 } 2476 2477 void intel_cdclk_dump_config(struct intel_display *display, 2478 const struct intel_cdclk_config *cdclk_config, 2479 const char *context) 2480 { 2481 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2482 context, cdclk_config->cdclk, cdclk_config->vco, 2483 cdclk_config->ref, cdclk_config->bypass, 2484 cdclk_config->voltage_level); 2485 } 2486 2487 static void intel_pcode_notify(struct intel_display *display, 2488 u8 voltage_level, 2489 u8 active_pipe_count, 2490 u16 cdclk, 2491 bool cdclk_update_valid, 2492 bool pipe_count_update_valid) 2493 { 2494 struct drm_i915_private *i915 = to_i915(display->drm); 2495 int ret; 2496 u32 update_mask = 0; 2497 2498 if (!IS_DG2(i915)) 2499 return; 2500 2501 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2502 2503 if (cdclk_update_valid) 2504 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2505 2506 if (pipe_count_update_valid) 2507 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2508 2509 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL, 2510 SKL_CDCLK_PREPARE_FOR_CHANGE | 2511 update_mask, 2512 SKL_CDCLK_READY_FOR_CHANGE, 2513 SKL_CDCLK_READY_FOR_CHANGE, 3); 2514 if (ret) 2515 drm_err(display->drm, 2516 "Failed to inform PCU about display config (err %d)\n", 2517 ret); 2518 } 2519 2520 static void intel_set_cdclk(struct intel_display *display, 2521 const struct intel_cdclk_config *cdclk_config, 2522 enum pipe pipe, const char *context) 2523 { 2524 struct drm_i915_private *dev_priv = to_i915(display->drm); 2525 struct intel_encoder *encoder; 2526 2527 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) 2528 return; 2529 2530 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) 2531 return; 2532 2533 intel_cdclk_dump_config(display, cdclk_config, context); 2534 2535 for_each_intel_encoder_with_psr(display->drm, encoder) { 2536 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2537 2538 intel_psr_pause(intel_dp); 2539 } 2540 2541 intel_audio_cdclk_change_pre(dev_priv); 2542 2543 /* 2544 * Lock aux/gmbus while we change cdclk in case those 2545 * functions use cdclk. Not all platforms/ports do, 2546 * but we'll lock them all for simplicity. 2547 */ 2548 mutex_lock(&display->gmbus.mutex); 2549 for_each_intel_dp(display->drm, encoder) { 2550 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2551 2552 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2553 &display->gmbus.mutex); 2554 } 2555 2556 intel_cdclk_set_cdclk(display, cdclk_config, pipe); 2557 2558 for_each_intel_dp(display->drm, encoder) { 2559 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2560 2561 mutex_unlock(&intel_dp->aux.hw_mutex); 2562 } 2563 mutex_unlock(&display->gmbus.mutex); 2564 2565 for_each_intel_encoder_with_psr(display->drm, encoder) { 2566 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2567 2568 intel_psr_resume(intel_dp); 2569 } 2570 2571 intel_audio_cdclk_change_post(dev_priv); 2572 2573 if (drm_WARN(display->drm, 2574 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), 2575 "cdclk state doesn't match!\n")) { 2576 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); 2577 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); 2578 } 2579 } 2580 2581 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2582 { 2583 struct intel_display *display = to_intel_display(state); 2584 const struct intel_cdclk_state *old_cdclk_state = 2585 intel_atomic_get_old_cdclk_state(state); 2586 const struct intel_cdclk_state *new_cdclk_state = 2587 intel_atomic_get_new_cdclk_state(state); 2588 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2589 bool change_cdclk, update_pipe_count; 2590 2591 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2592 &new_cdclk_state->actual) && 2593 new_cdclk_state->active_pipes == 2594 old_cdclk_state->active_pipes) 2595 return; 2596 2597 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2598 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2599 2600 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2601 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > 2602 hweight8(old_cdclk_state->active_pipes); 2603 2604 /* 2605 * According to "Sequence Before Frequency Change", 2606 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2607 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2608 * which basically means we choose the maximum of old and new CDCLK, if we know both 2609 */ 2610 if (change_cdclk) 2611 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2612 2613 /* 2614 * According to "Sequence For Pipe Count Change", 2615 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2616 * (power well is enabled) 2617 * no action if it is decreasing, before the change 2618 */ 2619 if (update_pipe_count) 2620 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2621 2622 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2623 change_cdclk, update_pipe_count); 2624 } 2625 2626 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2627 { 2628 struct intel_display *display = to_intel_display(state); 2629 const struct intel_cdclk_state *new_cdclk_state = 2630 intel_atomic_get_new_cdclk_state(state); 2631 const struct intel_cdclk_state *old_cdclk_state = 2632 intel_atomic_get_old_cdclk_state(state); 2633 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2634 bool update_cdclk, update_pipe_count; 2635 2636 /* According to "Sequence After Frequency Change", set voltage to used level */ 2637 voltage_level = new_cdclk_state->actual.voltage_level; 2638 2639 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2640 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < 2641 hweight8(old_cdclk_state->active_pipes); 2642 2643 /* 2644 * According to "Sequence After Frequency Change", 2645 * set bits 25:16 to current CDCLK 2646 */ 2647 if (update_cdclk) 2648 cdclk = new_cdclk_state->actual.cdclk; 2649 2650 /* 2651 * According to "Sequence For Pipe Count Change", 2652 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2653 * after the change(power well is disabled) 2654 * no action if it is increasing, after the change 2655 */ 2656 if (update_pipe_count) 2657 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2658 2659 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2660 update_cdclk, update_pipe_count); 2661 } 2662 2663 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2664 { 2665 const struct intel_cdclk_state *old_cdclk_state = 2666 intel_atomic_get_old_cdclk_state(state); 2667 const struct intel_cdclk_state *new_cdclk_state = 2668 intel_atomic_get_new_cdclk_state(state); 2669 2670 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2671 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2672 } 2673 2674 /** 2675 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2676 * @state: intel atomic state 2677 * 2678 * Program the hardware before updating the HW plane state based on the 2679 * new CDCLK state, if necessary. 2680 */ 2681 void 2682 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2683 { 2684 struct intel_display *display = to_intel_display(state); 2685 struct drm_i915_private *i915 = to_i915(display->drm); 2686 const struct intel_cdclk_state *old_cdclk_state = 2687 intel_atomic_get_old_cdclk_state(state); 2688 const struct intel_cdclk_state *new_cdclk_state = 2689 intel_atomic_get_new_cdclk_state(state); 2690 struct intel_cdclk_config cdclk_config; 2691 enum pipe pipe; 2692 2693 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2694 &new_cdclk_state->actual)) 2695 return; 2696 2697 if (IS_DG2(i915)) 2698 intel_cdclk_pcode_pre_notify(state); 2699 2700 if (new_cdclk_state->disable_pipes) { 2701 cdclk_config = new_cdclk_state->actual; 2702 pipe = INVALID_PIPE; 2703 } else { 2704 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2705 cdclk_config = new_cdclk_state->actual; 2706 pipe = new_cdclk_state->pipe; 2707 } else { 2708 cdclk_config = old_cdclk_state->actual; 2709 pipe = INVALID_PIPE; 2710 } 2711 2712 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2713 old_cdclk_state->actual.voltage_level); 2714 } 2715 2716 /* 2717 * mbus joining will be changed later by 2718 * intel_dbuf_mbus_{pre,post}_ddb_update() 2719 */ 2720 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2721 2722 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2723 2724 intel_set_cdclk(display, &cdclk_config, pipe, 2725 "Pre changing CDCLK to"); 2726 } 2727 2728 /** 2729 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2730 * @state: intel atomic state 2731 * 2732 * Program the hardware after updating the HW plane state based on the 2733 * new CDCLK state, if necessary. 2734 */ 2735 void 2736 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2737 { 2738 struct intel_display *display = to_intel_display(state); 2739 struct drm_i915_private *i915 = to_i915(display->drm); 2740 const struct intel_cdclk_state *old_cdclk_state = 2741 intel_atomic_get_old_cdclk_state(state); 2742 const struct intel_cdclk_state *new_cdclk_state = 2743 intel_atomic_get_new_cdclk_state(state); 2744 enum pipe pipe; 2745 2746 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2747 &new_cdclk_state->actual)) 2748 return; 2749 2750 if (IS_DG2(i915)) 2751 intel_cdclk_pcode_post_notify(state); 2752 2753 if (!new_cdclk_state->disable_pipes && 2754 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2755 pipe = new_cdclk_state->pipe; 2756 else 2757 pipe = INVALID_PIPE; 2758 2759 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2760 2761 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, 2762 "Post changing CDCLK to"); 2763 } 2764 2765 /* pixels per CDCLK */ 2766 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) 2767 { 2768 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; 2769 } 2770 2771 /* max pixel rate as % of CDCLK (not accounting for PPC) */ 2772 static int intel_cdclk_guardband(struct intel_display *display) 2773 { 2774 struct drm_i915_private *dev_priv = to_i915(display->drm); 2775 2776 if (DISPLAY_VER(display) >= 9 || 2777 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2778 return 100; 2779 else if (IS_CHERRYVIEW(dev_priv)) 2780 return 95; 2781 else 2782 return 90; 2783 } 2784 2785 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2786 { 2787 struct intel_display *display = to_intel_display(crtc_state); 2788 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 2789 int guardband = intel_cdclk_guardband(display); 2790 int pixel_rate = crtc_state->pixel_rate; 2791 2792 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); 2793 } 2794 2795 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2796 { 2797 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2798 struct intel_display *display = to_intel_display(crtc); 2799 struct intel_plane *plane; 2800 int min_cdclk = 0; 2801 2802 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2803 min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]); 2804 2805 return min_cdclk; 2806 } 2807 2808 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2809 { 2810 int min_cdclk; 2811 2812 if (!crtc_state->hw.enable) 2813 return 0; 2814 2815 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2816 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state)); 2817 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state)); 2818 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); 2819 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state)); 2820 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2821 2822 return min_cdclk; 2823 } 2824 2825 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 2826 { 2827 struct intel_display *display = to_intel_display(state); 2828 struct drm_i915_private *dev_priv = to_i915(display->drm); 2829 struct intel_cdclk_state *cdclk_state = 2830 intel_atomic_get_new_cdclk_state(state); 2831 const struct intel_bw_state *bw_state; 2832 struct intel_crtc *crtc; 2833 struct intel_crtc_state *crtc_state; 2834 int min_cdclk, i; 2835 enum pipe pipe; 2836 2837 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2838 int ret; 2839 2840 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2841 if (min_cdclk < 0) 2842 return min_cdclk; 2843 2844 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2845 continue; 2846 2847 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2848 2849 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2850 if (ret) 2851 return ret; 2852 } 2853 2854 bw_state = intel_atomic_get_new_bw_state(state); 2855 if (bw_state) { 2856 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); 2857 2858 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2859 int ret; 2860 2861 cdclk_state->bw_min_cdclk = min_cdclk; 2862 2863 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2864 if (ret) 2865 return ret; 2866 } 2867 } 2868 2869 min_cdclk = max(cdclk_state->force_min_cdclk, 2870 cdclk_state->bw_min_cdclk); 2871 for_each_pipe(display, pipe) 2872 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); 2873 2874 /* 2875 * Avoid glk_force_audio_cdclk() causing excessive screen 2876 * blinking when multiple pipes are active by making sure 2877 * CDCLK frequency is always high enough for audio. With a 2878 * single active pipe we can always change CDCLK frequency 2879 * by changing the cd2x divider (see glk_cdclk_table[]) and 2880 * thus a full modeset won't be needed then. 2881 */ 2882 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && 2883 !is_power_of_2(cdclk_state->active_pipes)) 2884 min_cdclk = max(min_cdclk, 2 * 96000); 2885 2886 if (min_cdclk > display->cdclk.max_cdclk_freq) { 2887 drm_dbg_kms(display->drm, 2888 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2889 min_cdclk, display->cdclk.max_cdclk_freq); 2890 return -EINVAL; 2891 } 2892 2893 return min_cdclk; 2894 } 2895 2896 /* 2897 * Account for port clock min voltage level requirements. 2898 * This only really does something on DISPLA_VER >= 11 but can be 2899 * called on earlier platforms as well. 2900 * 2901 * Note that this functions assumes that 0 is 2902 * the lowest voltage value, and higher values 2903 * correspond to increasingly higher voltages. 2904 * 2905 * Should that relationship no longer hold on 2906 * future platforms this code will need to be 2907 * adjusted. 2908 */ 2909 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 2910 { 2911 struct intel_display *display = to_intel_display(state); 2912 struct intel_cdclk_state *cdclk_state = 2913 intel_atomic_get_new_cdclk_state(state); 2914 struct intel_crtc *crtc; 2915 struct intel_crtc_state *crtc_state; 2916 u8 min_voltage_level; 2917 int i; 2918 enum pipe pipe; 2919 2920 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2921 int ret; 2922 2923 if (crtc_state->hw.enable) 2924 min_voltage_level = crtc_state->min_voltage_level; 2925 else 2926 min_voltage_level = 0; 2927 2928 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2929 continue; 2930 2931 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2932 2933 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2934 if (ret) 2935 return ret; 2936 } 2937 2938 min_voltage_level = 0; 2939 for_each_pipe(display, pipe) 2940 min_voltage_level = max(min_voltage_level, 2941 cdclk_state->min_voltage_level[pipe]); 2942 2943 return min_voltage_level; 2944 } 2945 2946 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 2947 { 2948 struct intel_display *display = to_intel_display(state); 2949 struct intel_cdclk_state *cdclk_state = 2950 intel_atomic_get_new_cdclk_state(state); 2951 int min_cdclk, cdclk; 2952 2953 min_cdclk = intel_compute_min_cdclk(state); 2954 if (min_cdclk < 0) 2955 return min_cdclk; 2956 2957 cdclk = vlv_calc_cdclk(display, min_cdclk); 2958 2959 cdclk_state->logical.cdclk = cdclk; 2960 cdclk_state->logical.voltage_level = 2961 vlv_calc_voltage_level(display, cdclk); 2962 2963 if (!cdclk_state->active_pipes) { 2964 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); 2965 2966 cdclk_state->actual.cdclk = cdclk; 2967 cdclk_state->actual.voltage_level = 2968 vlv_calc_voltage_level(display, cdclk); 2969 } else { 2970 cdclk_state->actual = cdclk_state->logical; 2971 } 2972 2973 return 0; 2974 } 2975 2976 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 2977 { 2978 struct intel_cdclk_state *cdclk_state = 2979 intel_atomic_get_new_cdclk_state(state); 2980 int min_cdclk, cdclk; 2981 2982 min_cdclk = intel_compute_min_cdclk(state); 2983 if (min_cdclk < 0) 2984 return min_cdclk; 2985 2986 cdclk = bdw_calc_cdclk(min_cdclk); 2987 2988 cdclk_state->logical.cdclk = cdclk; 2989 cdclk_state->logical.voltage_level = 2990 bdw_calc_voltage_level(cdclk); 2991 2992 if (!cdclk_state->active_pipes) { 2993 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2994 2995 cdclk_state->actual.cdclk = cdclk; 2996 cdclk_state->actual.voltage_level = 2997 bdw_calc_voltage_level(cdclk); 2998 } else { 2999 cdclk_state->actual = cdclk_state->logical; 3000 } 3001 3002 return 0; 3003 } 3004 3005 static int skl_dpll0_vco(struct intel_atomic_state *state) 3006 { 3007 struct intel_display *display = to_intel_display(state); 3008 struct intel_cdclk_state *cdclk_state = 3009 intel_atomic_get_new_cdclk_state(state); 3010 struct intel_crtc *crtc; 3011 struct intel_crtc_state *crtc_state; 3012 int vco, i; 3013 3014 vco = cdclk_state->logical.vco; 3015 if (!vco) 3016 vco = display->cdclk.skl_preferred_vco_freq; 3017 3018 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 3019 if (!crtc_state->hw.enable) 3020 continue; 3021 3022 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3023 continue; 3024 3025 /* 3026 * DPLL0 VCO may need to be adjusted to get the correct 3027 * clock for eDP. This will affect cdclk as well. 3028 */ 3029 switch (crtc_state->port_clock / 2) { 3030 case 108000: 3031 case 216000: 3032 vco = 8640000; 3033 break; 3034 default: 3035 vco = 8100000; 3036 break; 3037 } 3038 } 3039 3040 return vco; 3041 } 3042 3043 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3044 { 3045 struct intel_cdclk_state *cdclk_state = 3046 intel_atomic_get_new_cdclk_state(state); 3047 int min_cdclk, cdclk, vco; 3048 3049 min_cdclk = intel_compute_min_cdclk(state); 3050 if (min_cdclk < 0) 3051 return min_cdclk; 3052 3053 vco = skl_dpll0_vco(state); 3054 3055 cdclk = skl_calc_cdclk(min_cdclk, vco); 3056 3057 cdclk_state->logical.vco = vco; 3058 cdclk_state->logical.cdclk = cdclk; 3059 cdclk_state->logical.voltage_level = 3060 skl_calc_voltage_level(cdclk); 3061 3062 if (!cdclk_state->active_pipes) { 3063 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3064 3065 cdclk_state->actual.vco = vco; 3066 cdclk_state->actual.cdclk = cdclk; 3067 cdclk_state->actual.voltage_level = 3068 skl_calc_voltage_level(cdclk); 3069 } else { 3070 cdclk_state->actual = cdclk_state->logical; 3071 } 3072 3073 return 0; 3074 } 3075 3076 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3077 { 3078 struct intel_display *display = to_intel_display(state); 3079 struct intel_cdclk_state *cdclk_state = 3080 intel_atomic_get_new_cdclk_state(state); 3081 int min_cdclk, min_voltage_level, cdclk, vco; 3082 3083 min_cdclk = intel_compute_min_cdclk(state); 3084 if (min_cdclk < 0) 3085 return min_cdclk; 3086 3087 min_voltage_level = bxt_compute_min_voltage_level(state); 3088 if (min_voltage_level < 0) 3089 return min_voltage_level; 3090 3091 cdclk = bxt_calc_cdclk(display, min_cdclk); 3092 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3093 3094 cdclk_state->logical.vco = vco; 3095 cdclk_state->logical.cdclk = cdclk; 3096 cdclk_state->logical.voltage_level = 3097 max_t(int, min_voltage_level, 3098 intel_cdclk_calc_voltage_level(display, cdclk)); 3099 3100 if (!cdclk_state->active_pipes) { 3101 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); 3102 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3103 3104 cdclk_state->actual.vco = vco; 3105 cdclk_state->actual.cdclk = cdclk; 3106 cdclk_state->actual.voltage_level = 3107 intel_cdclk_calc_voltage_level(display, cdclk); 3108 } else { 3109 cdclk_state->actual = cdclk_state->logical; 3110 } 3111 3112 return 0; 3113 } 3114 3115 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3116 { 3117 int min_cdclk; 3118 3119 /* 3120 * We can't change the cdclk frequency, but we still want to 3121 * check that the required minimum frequency doesn't exceed 3122 * the actual cdclk frequency. 3123 */ 3124 min_cdclk = intel_compute_min_cdclk(state); 3125 if (min_cdclk < 0) 3126 return min_cdclk; 3127 3128 return 0; 3129 } 3130 3131 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3132 { 3133 struct intel_cdclk_state *cdclk_state; 3134 3135 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3136 if (!cdclk_state) 3137 return NULL; 3138 3139 cdclk_state->pipe = INVALID_PIPE; 3140 cdclk_state->disable_pipes = false; 3141 3142 return &cdclk_state->base; 3143 } 3144 3145 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3146 struct intel_global_state *state) 3147 { 3148 kfree(state); 3149 } 3150 3151 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3152 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3153 .atomic_destroy_state = intel_cdclk_destroy_state, 3154 }; 3155 3156 struct intel_cdclk_state * 3157 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3158 { 3159 struct intel_display *display = to_intel_display(state); 3160 struct intel_global_state *cdclk_state; 3161 3162 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); 3163 if (IS_ERR(cdclk_state)) 3164 return ERR_CAST(cdclk_state); 3165 3166 return to_intel_cdclk_state(cdclk_state); 3167 } 3168 3169 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 3170 bool *need_cdclk_calc) 3171 { 3172 const struct intel_cdclk_state *old_cdclk_state; 3173 const struct intel_cdclk_state *new_cdclk_state; 3174 struct intel_plane_state __maybe_unused *plane_state; 3175 struct intel_plane *plane; 3176 int ret; 3177 int i; 3178 3179 /* 3180 * active_planes bitmask has been updated, and potentially affected 3181 * planes are part of the state. We can now compute the minimum cdclk 3182 * for each plane. 3183 */ 3184 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 3185 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 3186 if (ret) 3187 return ret; 3188 } 3189 3190 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 3191 if (ret) 3192 return ret; 3193 3194 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3195 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3196 3197 if (new_cdclk_state && 3198 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 3199 *need_cdclk_calc = true; 3200 3201 return 0; 3202 } 3203 3204 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3205 { 3206 struct intel_cdclk_state *cdclk_state; 3207 3208 cdclk_state = intel_atomic_get_cdclk_state(state); 3209 if (IS_ERR(cdclk_state)) 3210 return PTR_ERR(cdclk_state); 3211 3212 cdclk_state->actual.joined_mbus = joined_mbus; 3213 cdclk_state->logical.joined_mbus = joined_mbus; 3214 3215 return intel_atomic_lock_global_state(&cdclk_state->base); 3216 } 3217 3218 int intel_cdclk_init(struct intel_display *display) 3219 { 3220 struct intel_cdclk_state *cdclk_state; 3221 3222 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 3223 if (!cdclk_state) 3224 return -ENOMEM; 3225 3226 intel_atomic_global_obj_init(display, &display->cdclk.obj, 3227 &cdclk_state->base, &intel_cdclk_funcs); 3228 3229 return 0; 3230 } 3231 3232 static bool intel_cdclk_need_serialize(struct intel_display *display, 3233 const struct intel_cdclk_state *old_cdclk_state, 3234 const struct intel_cdclk_state *new_cdclk_state) 3235 { 3236 struct drm_i915_private *i915 = to_i915(display->drm); 3237 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != 3238 hweight8(new_cdclk_state->active_pipes); 3239 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, 3240 &new_cdclk_state->actual); 3241 /* 3242 * We need to poke hw for gen >= 12, because we notify PCode if 3243 * pipe power well count changes. 3244 */ 3245 return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed); 3246 } 3247 3248 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3249 { 3250 struct intel_display *display = to_intel_display(state); 3251 const struct intel_cdclk_state *old_cdclk_state; 3252 struct intel_cdclk_state *new_cdclk_state; 3253 enum pipe pipe = INVALID_PIPE; 3254 int ret; 3255 3256 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3257 if (IS_ERR(new_cdclk_state)) 3258 return PTR_ERR(new_cdclk_state); 3259 3260 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3261 3262 new_cdclk_state->active_pipes = 3263 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3264 3265 ret = intel_cdclk_modeset_calc_cdclk(state); 3266 if (ret) 3267 return ret; 3268 3269 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { 3270 /* 3271 * Also serialize commits across all crtcs 3272 * if the actual hw needs to be poked. 3273 */ 3274 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3275 if (ret) 3276 return ret; 3277 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 3278 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 3279 intel_cdclk_changed(&old_cdclk_state->logical, 3280 &new_cdclk_state->logical)) { 3281 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3282 if (ret) 3283 return ret; 3284 } else { 3285 return 0; 3286 } 3287 3288 if (is_power_of_2(new_cdclk_state->active_pipes) && 3289 intel_cdclk_can_cd2x_update(display, 3290 &old_cdclk_state->actual, 3291 &new_cdclk_state->actual)) { 3292 struct intel_crtc *crtc; 3293 struct intel_crtc_state *crtc_state; 3294 3295 pipe = ilog2(new_cdclk_state->active_pipes); 3296 crtc = intel_crtc_for_pipe(display, pipe); 3297 3298 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3299 if (IS_ERR(crtc_state)) 3300 return PTR_ERR(crtc_state); 3301 3302 if (intel_crtc_needs_modeset(crtc_state)) 3303 pipe = INVALID_PIPE; 3304 } 3305 3306 if (intel_cdclk_can_crawl_and_squash(display, 3307 &old_cdclk_state->actual, 3308 &new_cdclk_state->actual)) { 3309 drm_dbg_kms(display->drm, 3310 "Can change cdclk via crawling and squashing\n"); 3311 } else if (intel_cdclk_can_squash(display, 3312 &old_cdclk_state->actual, 3313 &new_cdclk_state->actual)) { 3314 drm_dbg_kms(display->drm, 3315 "Can change cdclk via squashing\n"); 3316 } else if (intel_cdclk_can_crawl(display, 3317 &old_cdclk_state->actual, 3318 &new_cdclk_state->actual)) { 3319 drm_dbg_kms(display->drm, 3320 "Can change cdclk via crawling\n"); 3321 } else if (pipe != INVALID_PIPE) { 3322 new_cdclk_state->pipe = pipe; 3323 3324 drm_dbg_kms(display->drm, 3325 "Can change cdclk cd2x divider with pipe %c active\n", 3326 pipe_name(pipe)); 3327 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3328 &new_cdclk_state->actual)) { 3329 /* All pipes must be switched off while we change the cdclk. */ 3330 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3331 if (ret) 3332 return ret; 3333 3334 new_cdclk_state->disable_pipes = true; 3335 3336 drm_dbg_kms(display->drm, 3337 "Modeset required for cdclk change\n"); 3338 } 3339 3340 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != 3341 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { 3342 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); 3343 3344 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3345 if (ret) 3346 return ret; 3347 } 3348 3349 drm_dbg_kms(display->drm, 3350 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3351 new_cdclk_state->logical.cdclk, 3352 new_cdclk_state->actual.cdclk); 3353 drm_dbg_kms(display->drm, 3354 "New voltage level calculated to be logical %u, actual %u\n", 3355 new_cdclk_state->logical.voltage_level, 3356 new_cdclk_state->actual.voltage_level); 3357 3358 return 0; 3359 } 3360 3361 static int intel_compute_max_dotclk(struct intel_display *display) 3362 { 3363 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); 3364 int guardband = intel_cdclk_guardband(display); 3365 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3366 3367 return ppc * max_cdclk_freq * guardband / 100; 3368 } 3369 3370 /** 3371 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3372 * @display: display instance 3373 * 3374 * Determine the maximum CDCLK frequency the platform supports, and also 3375 * derive the maximum dot clock frequency the maximum CDCLK frequency 3376 * allows. 3377 */ 3378 void intel_update_max_cdclk(struct intel_display *display) 3379 { 3380 struct drm_i915_private *dev_priv = to_i915(display->drm); 3381 3382 if (DISPLAY_VER(display) >= 30) { 3383 display->cdclk.max_cdclk_freq = 691200; 3384 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 3385 if (display->cdclk.hw.ref == 24000) 3386 display->cdclk.max_cdclk_freq = 552000; 3387 else 3388 display->cdclk.max_cdclk_freq = 556800; 3389 } else if (DISPLAY_VER(display) >= 11) { 3390 if (display->cdclk.hw.ref == 24000) 3391 display->cdclk.max_cdclk_freq = 648000; 3392 else 3393 display->cdclk.max_cdclk_freq = 652800; 3394 } else if (IS_GEMINILAKE(dev_priv)) { 3395 display->cdclk.max_cdclk_freq = 316800; 3396 } else if (IS_BROXTON(dev_priv)) { 3397 display->cdclk.max_cdclk_freq = 624000; 3398 } else if (DISPLAY_VER(display) == 9) { 3399 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3400 int max_cdclk, vco; 3401 3402 vco = display->cdclk.skl_preferred_vco_freq; 3403 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 3404 3405 /* 3406 * Use the lower (vco 8640) cdclk values as a 3407 * first guess. skl_calc_cdclk() will correct it 3408 * if the preferred vco is 8100 instead. 3409 */ 3410 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3411 max_cdclk = 617143; 3412 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3413 max_cdclk = 540000; 3414 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3415 max_cdclk = 432000; 3416 else 3417 max_cdclk = 308571; 3418 3419 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3420 } else if (IS_BROADWELL(dev_priv)) { 3421 /* 3422 * FIXME with extra cooling we can allow 3423 * 540 MHz for ULX and 675 Mhz for ULT. 3424 * How can we know if extra cooling is 3425 * available? PCI ID, VTB, something else? 3426 */ 3427 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3428 display->cdclk.max_cdclk_freq = 450000; 3429 else if (IS_BROADWELL_ULX(dev_priv)) 3430 display->cdclk.max_cdclk_freq = 450000; 3431 else if (IS_BROADWELL_ULT(dev_priv)) 3432 display->cdclk.max_cdclk_freq = 540000; 3433 else 3434 display->cdclk.max_cdclk_freq = 675000; 3435 } else if (IS_CHERRYVIEW(dev_priv)) { 3436 display->cdclk.max_cdclk_freq = 320000; 3437 } else if (IS_VALLEYVIEW(dev_priv)) { 3438 display->cdclk.max_cdclk_freq = 400000; 3439 } else { 3440 /* otherwise assume cdclk is fixed */ 3441 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; 3442 } 3443 3444 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); 3445 3446 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", 3447 display->cdclk.max_cdclk_freq); 3448 3449 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", 3450 display->cdclk.max_dotclk_freq); 3451 } 3452 3453 /** 3454 * intel_update_cdclk - Determine the current CDCLK frequency 3455 * @display: display instance 3456 * 3457 * Determine the current CDCLK frequency. 3458 */ 3459 void intel_update_cdclk(struct intel_display *display) 3460 { 3461 struct drm_i915_private *dev_priv = to_i915(display->drm); 3462 3463 intel_cdclk_get_cdclk(display, &display->cdclk.hw); 3464 3465 /* 3466 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3467 * Programmng [sic] note: bit[9:2] should be programmed to the number 3468 * of cdclk that generates 4MHz reference clock freq which is used to 3469 * generate GMBus clock. This will vary with the cdclk freq. 3470 */ 3471 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3472 intel_de_write(display, GMBUSFREQ_VLV, 3473 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); 3474 } 3475 3476 static int dg1_rawclk(struct intel_display *display) 3477 { 3478 /* 3479 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3480 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3481 */ 3482 intel_de_write(display, PCH_RAWCLK_FREQ, 3483 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3484 3485 return 38400; 3486 } 3487 3488 static int cnp_rawclk(struct intel_display *display) 3489 { 3490 struct drm_i915_private *dev_priv = to_i915(display->drm); 3491 int divider, fraction; 3492 u32 rawclk; 3493 3494 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3495 /* 24 MHz */ 3496 divider = 24000; 3497 fraction = 0; 3498 } else { 3499 /* 19.2 MHz */ 3500 divider = 19000; 3501 fraction = 200; 3502 } 3503 3504 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3505 if (fraction) { 3506 int numerator = 1; 3507 3508 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3509 fraction) - 1); 3510 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3511 rawclk |= ICP_RAWCLK_NUM(numerator); 3512 } 3513 3514 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); 3515 return divider + fraction; 3516 } 3517 3518 static int pch_rawclk(struct intel_display *display) 3519 { 3520 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3521 } 3522 3523 static int vlv_hrawclk(struct intel_display *display) 3524 { 3525 struct drm_i915_private *dev_priv = to_i915(display->drm); 3526 3527 /* RAWCLK_FREQ_VLV register updated from power well code */ 3528 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 3529 CCK_DISPLAY_REF_CLOCK_CONTROL); 3530 } 3531 3532 static int i9xx_hrawclk(struct intel_display *display) 3533 { 3534 struct drm_i915_private *i915 = to_i915(display->drm); 3535 3536 /* hrawclock is 1/4 the FSB frequency */ 3537 return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); 3538 } 3539 3540 /** 3541 * intel_read_rawclk - Determine the current RAWCLK frequency 3542 * @display: display instance 3543 * 3544 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3545 * frequency clock so this needs to done only once. 3546 */ 3547 u32 intel_read_rawclk(struct intel_display *display) 3548 { 3549 struct drm_i915_private *dev_priv = to_i915(display->drm); 3550 u32 freq; 3551 3552 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) 3553 /* 3554 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3555 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3556 * not need to be programmed." 3557 */ 3558 freq = 38400; 3559 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3560 freq = dg1_rawclk(display); 3561 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3562 freq = cnp_rawclk(display); 3563 else if (HAS_PCH_SPLIT(dev_priv)) 3564 freq = pch_rawclk(display); 3565 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3566 freq = vlv_hrawclk(display); 3567 else if (DISPLAY_VER(display) >= 3) 3568 freq = i9xx_hrawclk(display); 3569 else 3570 /* no rawclk on other platforms, or no need to know it */ 3571 return 0; 3572 3573 return freq; 3574 } 3575 3576 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3577 { 3578 struct intel_display *display = m->private; 3579 3580 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); 3581 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); 3582 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); 3583 3584 return 0; 3585 } 3586 3587 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3588 3589 void intel_cdclk_debugfs_register(struct intel_display *display) 3590 { 3591 struct drm_minor *minor = display->drm->primary; 3592 3593 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, 3594 display, &i915_cdclk_info_fops); 3595 } 3596 3597 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { 3598 .get_cdclk = bxt_get_cdclk, 3599 .set_cdclk = bxt_set_cdclk, 3600 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3601 .calc_voltage_level = xe3lpd_calc_voltage_level, 3602 }; 3603 3604 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3605 .get_cdclk = bxt_get_cdclk, 3606 .set_cdclk = bxt_set_cdclk, 3607 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3608 .calc_voltage_level = rplu_calc_voltage_level, 3609 }; 3610 3611 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3612 .get_cdclk = bxt_get_cdclk, 3613 .set_cdclk = bxt_set_cdclk, 3614 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3615 .calc_voltage_level = tgl_calc_voltage_level, 3616 }; 3617 3618 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3619 .get_cdclk = bxt_get_cdclk, 3620 .set_cdclk = bxt_set_cdclk, 3621 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3622 .calc_voltage_level = ehl_calc_voltage_level, 3623 }; 3624 3625 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3626 .get_cdclk = bxt_get_cdclk, 3627 .set_cdclk = bxt_set_cdclk, 3628 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3629 .calc_voltage_level = icl_calc_voltage_level, 3630 }; 3631 3632 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3633 .get_cdclk = bxt_get_cdclk, 3634 .set_cdclk = bxt_set_cdclk, 3635 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3636 .calc_voltage_level = bxt_calc_voltage_level, 3637 }; 3638 3639 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3640 .get_cdclk = skl_get_cdclk, 3641 .set_cdclk = skl_set_cdclk, 3642 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3643 }; 3644 3645 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3646 .get_cdclk = bdw_get_cdclk, 3647 .set_cdclk = bdw_set_cdclk, 3648 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3649 }; 3650 3651 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3652 .get_cdclk = vlv_get_cdclk, 3653 .set_cdclk = chv_set_cdclk, 3654 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3655 }; 3656 3657 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3658 .get_cdclk = vlv_get_cdclk, 3659 .set_cdclk = vlv_set_cdclk, 3660 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3661 }; 3662 3663 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3664 .get_cdclk = hsw_get_cdclk, 3665 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3666 }; 3667 3668 /* SNB, IVB, 965G, 945G */ 3669 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3670 .get_cdclk = fixed_400mhz_get_cdclk, 3671 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3672 }; 3673 3674 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3675 .get_cdclk = fixed_450mhz_get_cdclk, 3676 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3677 }; 3678 3679 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3680 .get_cdclk = gm45_get_cdclk, 3681 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3682 }; 3683 3684 /* G45 uses G33 */ 3685 3686 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3687 .get_cdclk = i965gm_get_cdclk, 3688 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3689 }; 3690 3691 /* i965G uses fixed 400 */ 3692 3693 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3694 .get_cdclk = pnv_get_cdclk, 3695 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3696 }; 3697 3698 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3699 .get_cdclk = g33_get_cdclk, 3700 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3701 }; 3702 3703 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3704 .get_cdclk = i945gm_get_cdclk, 3705 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3706 }; 3707 3708 /* i945G uses fixed 400 */ 3709 3710 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3711 .get_cdclk = i915gm_get_cdclk, 3712 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3713 }; 3714 3715 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3716 .get_cdclk = fixed_333mhz_get_cdclk, 3717 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3718 }; 3719 3720 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3721 .get_cdclk = fixed_266mhz_get_cdclk, 3722 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3723 }; 3724 3725 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3726 .get_cdclk = i85x_get_cdclk, 3727 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3728 }; 3729 3730 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3731 .get_cdclk = fixed_200mhz_get_cdclk, 3732 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3733 }; 3734 3735 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3736 .get_cdclk = fixed_133mhz_get_cdclk, 3737 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3738 }; 3739 3740 /** 3741 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3742 * @display: display instance 3743 */ 3744 void intel_init_cdclk_hooks(struct intel_display *display) 3745 { 3746 struct drm_i915_private *dev_priv = to_i915(display->drm); 3747 3748 if (DISPLAY_VER(display) >= 30) { 3749 display->funcs.cdclk = &xe3lpd_cdclk_funcs; 3750 display->cdclk.table = xe3lpd_cdclk_table; 3751 } else if (DISPLAY_VER(display) >= 20) { 3752 display->funcs.cdclk = &rplu_cdclk_funcs; 3753 display->cdclk.table = xe2lpd_cdclk_table; 3754 } else if (DISPLAY_VERx100(display) >= 1401) { 3755 display->funcs.cdclk = &rplu_cdclk_funcs; 3756 display->cdclk.table = xe2hpd_cdclk_table; 3757 } else if (DISPLAY_VER(display) >= 14) { 3758 display->funcs.cdclk = &rplu_cdclk_funcs; 3759 display->cdclk.table = mtl_cdclk_table; 3760 } else if (IS_DG2(dev_priv)) { 3761 display->funcs.cdclk = &tgl_cdclk_funcs; 3762 display->cdclk.table = dg2_cdclk_table; 3763 } else if (IS_ALDERLAKE_P(dev_priv)) { 3764 /* Wa_22011320316:adl-p[a0] */ 3765 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 3766 display->cdclk.table = adlp_a_step_cdclk_table; 3767 display->funcs.cdclk = &tgl_cdclk_funcs; 3768 } else if (IS_RAPTORLAKE_U(dev_priv)) { 3769 display->cdclk.table = rplu_cdclk_table; 3770 display->funcs.cdclk = &rplu_cdclk_funcs; 3771 } else { 3772 display->cdclk.table = adlp_cdclk_table; 3773 display->funcs.cdclk = &tgl_cdclk_funcs; 3774 } 3775 } else if (IS_ROCKETLAKE(dev_priv)) { 3776 display->funcs.cdclk = &tgl_cdclk_funcs; 3777 display->cdclk.table = rkl_cdclk_table; 3778 } else if (DISPLAY_VER(display) >= 12) { 3779 display->funcs.cdclk = &tgl_cdclk_funcs; 3780 display->cdclk.table = icl_cdclk_table; 3781 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 3782 display->funcs.cdclk = &ehl_cdclk_funcs; 3783 display->cdclk.table = icl_cdclk_table; 3784 } else if (DISPLAY_VER(display) >= 11) { 3785 display->funcs.cdclk = &icl_cdclk_funcs; 3786 display->cdclk.table = icl_cdclk_table; 3787 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 3788 display->funcs.cdclk = &bxt_cdclk_funcs; 3789 if (IS_GEMINILAKE(dev_priv)) 3790 display->cdclk.table = glk_cdclk_table; 3791 else 3792 display->cdclk.table = bxt_cdclk_table; 3793 } else if (DISPLAY_VER(display) == 9) { 3794 display->funcs.cdclk = &skl_cdclk_funcs; 3795 } else if (IS_BROADWELL(dev_priv)) { 3796 display->funcs.cdclk = &bdw_cdclk_funcs; 3797 } else if (IS_HASWELL(dev_priv)) { 3798 display->funcs.cdclk = &hsw_cdclk_funcs; 3799 } else if (IS_CHERRYVIEW(dev_priv)) { 3800 display->funcs.cdclk = &chv_cdclk_funcs; 3801 } else if (IS_VALLEYVIEW(dev_priv)) { 3802 display->funcs.cdclk = &vlv_cdclk_funcs; 3803 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 3804 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3805 } else if (IS_IRONLAKE(dev_priv)) { 3806 display->funcs.cdclk = &ilk_cdclk_funcs; 3807 } else if (IS_GM45(dev_priv)) { 3808 display->funcs.cdclk = &gm45_cdclk_funcs; 3809 } else if (IS_G45(dev_priv)) { 3810 display->funcs.cdclk = &g33_cdclk_funcs; 3811 } else if (IS_I965GM(dev_priv)) { 3812 display->funcs.cdclk = &i965gm_cdclk_funcs; 3813 } else if (IS_I965G(dev_priv)) { 3814 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3815 } else if (IS_PINEVIEW(dev_priv)) { 3816 display->funcs.cdclk = &pnv_cdclk_funcs; 3817 } else if (IS_G33(dev_priv)) { 3818 display->funcs.cdclk = &g33_cdclk_funcs; 3819 } else if (IS_I945GM(dev_priv)) { 3820 display->funcs.cdclk = &i945gm_cdclk_funcs; 3821 } else if (IS_I945G(dev_priv)) { 3822 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3823 } else if (IS_I915GM(dev_priv)) { 3824 display->funcs.cdclk = &i915gm_cdclk_funcs; 3825 } else if (IS_I915G(dev_priv)) { 3826 display->funcs.cdclk = &i915g_cdclk_funcs; 3827 } else if (IS_I865G(dev_priv)) { 3828 display->funcs.cdclk = &i865g_cdclk_funcs; 3829 } else if (IS_I85X(dev_priv)) { 3830 display->funcs.cdclk = &i85x_cdclk_funcs; 3831 } else if (IS_I845G(dev_priv)) { 3832 display->funcs.cdclk = &i845g_cdclk_funcs; 3833 } else if (IS_I830(dev_priv)) { 3834 display->funcs.cdclk = &i830_cdclk_funcs; 3835 } 3836 3837 if (drm_WARN(display->drm, !display->funcs.cdclk, 3838 "Unknown platform. Assuming i830\n")) 3839 display->funcs.cdclk = &i830_cdclk_funcs; 3840 } 3841