1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/time.h> 25 26 #include "hsw_ips.h" 27 #include "i915_reg.h" 28 #include "intel_atomic.h" 29 #include "intel_atomic_plane.h" 30 #include "intel_audio.h" 31 #include "intel_bw.h" 32 #include "intel_cdclk.h" 33 #include "intel_crtc.h" 34 #include "intel_de.h" 35 #include "intel_dp.h" 36 #include "intel_display_types.h" 37 #include "intel_mchbar_regs.h" 38 #include "intel_pci_config.h" 39 #include "intel_pcode.h" 40 #include "intel_psr.h" 41 #include "intel_vdsc.h" 42 #include "vlv_sideband.h" 43 44 /** 45 * DOC: CDCLK / RAWCLK 46 * 47 * The display engine uses several different clocks to do its work. There 48 * are two main clocks involved that aren't directly related to the actual 49 * pixel clock or any symbol/bit clock of the actual output port. These 50 * are the core display clock (CDCLK) and RAWCLK. 51 * 52 * CDCLK clocks most of the display pipe logic, and thus its frequency 53 * must be high enough to support the rate at which pixels are flowing 54 * through the pipes. Downscaling must also be accounted as that increases 55 * the effective pixel rate. 56 * 57 * On several platforms the CDCLK frequency can be changed dynamically 58 * to minimize power consumption for a given display configuration. 59 * Typically changes to the CDCLK frequency require all the display pipes 60 * to be shut down while the frequency is being changed. 61 * 62 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 63 * DMC will not change the active CDCLK frequency however, so that part 64 * will still be performed by the driver directly. 65 * 66 * RAWCLK is a fixed frequency clock, often used by various auxiliary 67 * blocks such as AUX CH or backlight PWM. Hence the only thing we 68 * really need to know about RAWCLK is its frequency so that various 69 * dividers can be programmed correctly. 70 */ 71 72 struct intel_cdclk_funcs { 73 void (*get_cdclk)(struct drm_i915_private *i915, 74 struct intel_cdclk_config *cdclk_config); 75 void (*set_cdclk)(struct drm_i915_private *i915, 76 const struct intel_cdclk_config *cdclk_config, 77 enum pipe pipe); 78 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 79 u8 (*calc_voltage_level)(int cdclk); 80 }; 81 82 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, 83 struct intel_cdclk_config *cdclk_config) 84 { 85 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); 86 } 87 88 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, 89 const struct intel_cdclk_config *cdclk_config, 90 enum pipe pipe) 91 { 92 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); 93 } 94 95 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, 96 struct intel_cdclk_state *cdclk_config) 97 { 98 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); 99 } 100 101 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, 102 int cdclk) 103 { 104 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); 105 } 106 107 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, 108 struct intel_cdclk_config *cdclk_config) 109 { 110 cdclk_config->cdclk = 133333; 111 } 112 113 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, 114 struct intel_cdclk_config *cdclk_config) 115 { 116 cdclk_config->cdclk = 200000; 117 } 118 119 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, 120 struct intel_cdclk_config *cdclk_config) 121 { 122 cdclk_config->cdclk = 266667; 123 } 124 125 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, 126 struct intel_cdclk_config *cdclk_config) 127 { 128 cdclk_config->cdclk = 333333; 129 } 130 131 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, 132 struct intel_cdclk_config *cdclk_config) 133 { 134 cdclk_config->cdclk = 400000; 135 } 136 137 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, 138 struct intel_cdclk_config *cdclk_config) 139 { 140 cdclk_config->cdclk = 450000; 141 } 142 143 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, 144 struct intel_cdclk_config *cdclk_config) 145 { 146 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 147 u16 hpllcc = 0; 148 149 /* 150 * 852GM/852GMV only supports 133 MHz and the HPLLCC 151 * encoding is different :( 152 * FIXME is this the right way to detect 852GM/852GMV? 153 */ 154 if (pdev->revision == 0x1) { 155 cdclk_config->cdclk = 133333; 156 return; 157 } 158 159 pci_bus_read_config_word(pdev->bus, 160 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 161 162 /* Assume that the hardware is in the high speed state. This 163 * should be the default. 164 */ 165 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 166 case GC_CLOCK_133_200: 167 case GC_CLOCK_133_200_2: 168 case GC_CLOCK_100_200: 169 cdclk_config->cdclk = 200000; 170 break; 171 case GC_CLOCK_166_250: 172 cdclk_config->cdclk = 250000; 173 break; 174 case GC_CLOCK_100_133: 175 cdclk_config->cdclk = 133333; 176 break; 177 case GC_CLOCK_133_266: 178 case GC_CLOCK_133_266_2: 179 case GC_CLOCK_166_266: 180 cdclk_config->cdclk = 266667; 181 break; 182 } 183 } 184 185 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, 186 struct intel_cdclk_config *cdclk_config) 187 { 188 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 189 u16 gcfgc = 0; 190 191 pci_read_config_word(pdev, GCFGC, &gcfgc); 192 193 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 194 cdclk_config->cdclk = 133333; 195 return; 196 } 197 198 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 199 case GC_DISPLAY_CLOCK_333_320_MHZ: 200 cdclk_config->cdclk = 333333; 201 break; 202 default: 203 case GC_DISPLAY_CLOCK_190_200_MHZ: 204 cdclk_config->cdclk = 190000; 205 break; 206 } 207 } 208 209 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, 210 struct intel_cdclk_config *cdclk_config) 211 { 212 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 213 u16 gcfgc = 0; 214 215 pci_read_config_word(pdev, GCFGC, &gcfgc); 216 217 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 218 cdclk_config->cdclk = 133333; 219 return; 220 } 221 222 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 223 case GC_DISPLAY_CLOCK_333_320_MHZ: 224 cdclk_config->cdclk = 320000; 225 break; 226 default: 227 case GC_DISPLAY_CLOCK_190_200_MHZ: 228 cdclk_config->cdclk = 200000; 229 break; 230 } 231 } 232 233 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) 234 { 235 static const unsigned int blb_vco[8] = { 236 [0] = 3200000, 237 [1] = 4000000, 238 [2] = 5333333, 239 [3] = 4800000, 240 [4] = 6400000, 241 }; 242 static const unsigned int pnv_vco[8] = { 243 [0] = 3200000, 244 [1] = 4000000, 245 [2] = 5333333, 246 [3] = 4800000, 247 [4] = 2666667, 248 }; 249 static const unsigned int cl_vco[8] = { 250 [0] = 3200000, 251 [1] = 4000000, 252 [2] = 5333333, 253 [3] = 6400000, 254 [4] = 3333333, 255 [5] = 3566667, 256 [6] = 4266667, 257 }; 258 static const unsigned int elk_vco[8] = { 259 [0] = 3200000, 260 [1] = 4000000, 261 [2] = 5333333, 262 [3] = 4800000, 263 }; 264 static const unsigned int ctg_vco[8] = { 265 [0] = 3200000, 266 [1] = 4000000, 267 [2] = 5333333, 268 [3] = 6400000, 269 [4] = 2666667, 270 [5] = 4266667, 271 }; 272 const unsigned int *vco_table; 273 unsigned int vco; 274 u8 tmp = 0; 275 276 /* FIXME other chipsets? */ 277 if (IS_GM45(dev_priv)) 278 vco_table = ctg_vco; 279 else if (IS_G45(dev_priv)) 280 vco_table = elk_vco; 281 else if (IS_I965GM(dev_priv)) 282 vco_table = cl_vco; 283 else if (IS_PINEVIEW(dev_priv)) 284 vco_table = pnv_vco; 285 else if (IS_G33(dev_priv)) 286 vco_table = blb_vco; 287 else 288 return 0; 289 290 tmp = intel_de_read(dev_priv, 291 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 292 293 vco = vco_table[tmp & 0x7]; 294 if (vco == 0) 295 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 296 tmp); 297 else 298 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); 299 300 return vco; 301 } 302 303 static void g33_get_cdclk(struct drm_i915_private *dev_priv, 304 struct intel_cdclk_config *cdclk_config) 305 { 306 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 307 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 308 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 309 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 310 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 311 const u8 *div_table; 312 unsigned int cdclk_sel; 313 u16 tmp = 0; 314 315 cdclk_config->vco = intel_hpll_vco(dev_priv); 316 317 pci_read_config_word(pdev, GCFGC, &tmp); 318 319 cdclk_sel = (tmp >> 4) & 0x7; 320 321 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 322 goto fail; 323 324 switch (cdclk_config->vco) { 325 case 3200000: 326 div_table = div_3200; 327 break; 328 case 4000000: 329 div_table = div_4000; 330 break; 331 case 4800000: 332 div_table = div_4800; 333 break; 334 case 5333333: 335 div_table = div_5333; 336 break; 337 default: 338 goto fail; 339 } 340 341 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 342 div_table[cdclk_sel]); 343 return; 344 345 fail: 346 drm_err(&dev_priv->drm, 347 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 348 cdclk_config->vco, tmp); 349 cdclk_config->cdclk = 190476; 350 } 351 352 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, 353 struct intel_cdclk_config *cdclk_config) 354 { 355 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 356 u16 gcfgc = 0; 357 358 pci_read_config_word(pdev, GCFGC, &gcfgc); 359 360 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 361 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 362 cdclk_config->cdclk = 266667; 363 break; 364 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 365 cdclk_config->cdclk = 333333; 366 break; 367 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 368 cdclk_config->cdclk = 444444; 369 break; 370 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 371 cdclk_config->cdclk = 200000; 372 break; 373 default: 374 drm_err(&dev_priv->drm, 375 "Unknown pnv display core clock 0x%04x\n", gcfgc); 376 fallthrough; 377 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 378 cdclk_config->cdclk = 133333; 379 break; 380 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 381 cdclk_config->cdclk = 166667; 382 break; 383 } 384 } 385 386 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, 387 struct intel_cdclk_config *cdclk_config) 388 { 389 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 390 static const u8 div_3200[] = { 16, 10, 8 }; 391 static const u8 div_4000[] = { 20, 12, 10 }; 392 static const u8 div_5333[] = { 24, 16, 14 }; 393 const u8 *div_table; 394 unsigned int cdclk_sel; 395 u16 tmp = 0; 396 397 cdclk_config->vco = intel_hpll_vco(dev_priv); 398 399 pci_read_config_word(pdev, GCFGC, &tmp); 400 401 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 402 403 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 404 goto fail; 405 406 switch (cdclk_config->vco) { 407 case 3200000: 408 div_table = div_3200; 409 break; 410 case 4000000: 411 div_table = div_4000; 412 break; 413 case 5333333: 414 div_table = div_5333; 415 break; 416 default: 417 goto fail; 418 } 419 420 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 421 div_table[cdclk_sel]); 422 return; 423 424 fail: 425 drm_err(&dev_priv->drm, 426 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 427 cdclk_config->vco, tmp); 428 cdclk_config->cdclk = 200000; 429 } 430 431 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, 432 struct intel_cdclk_config *cdclk_config) 433 { 434 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 435 unsigned int cdclk_sel; 436 u16 tmp = 0; 437 438 cdclk_config->vco = intel_hpll_vco(dev_priv); 439 440 pci_read_config_word(pdev, GCFGC, &tmp); 441 442 cdclk_sel = (tmp >> 12) & 0x1; 443 444 switch (cdclk_config->vco) { 445 case 2666667: 446 case 4000000: 447 case 5333333: 448 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 449 break; 450 case 3200000: 451 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 452 break; 453 default: 454 drm_err(&dev_priv->drm, 455 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 456 cdclk_config->vco, tmp); 457 cdclk_config->cdclk = 222222; 458 break; 459 } 460 } 461 462 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, 463 struct intel_cdclk_config *cdclk_config) 464 { 465 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 466 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 467 468 if (lcpll & LCPLL_CD_SOURCE_FCLK) 469 cdclk_config->cdclk = 800000; 470 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 471 cdclk_config->cdclk = 450000; 472 else if (freq == LCPLL_CLK_FREQ_450) 473 cdclk_config->cdclk = 450000; 474 else if (IS_HASWELL_ULT(dev_priv)) 475 cdclk_config->cdclk = 337500; 476 else 477 cdclk_config->cdclk = 540000; 478 } 479 480 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 481 { 482 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 483 333333 : 320000; 484 485 /* 486 * We seem to get an unstable or solid color picture at 200MHz. 487 * Not sure what's wrong. For now use 200MHz only when all pipes 488 * are off. 489 */ 490 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 491 return 400000; 492 else if (min_cdclk > 266667) 493 return freq_320; 494 else if (min_cdclk > 0) 495 return 266667; 496 else 497 return 200000; 498 } 499 500 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) 501 { 502 if (IS_VALLEYVIEW(dev_priv)) { 503 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 504 return 2; 505 else if (cdclk >= 266667) 506 return 1; 507 else 508 return 0; 509 } else { 510 /* 511 * Specs are full of misinformation, but testing on actual 512 * hardware has shown that we just need to write the desired 513 * CCK divider into the Punit register. 514 */ 515 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 516 } 517 } 518 519 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, 520 struct intel_cdclk_config *cdclk_config) 521 { 522 u32 val; 523 524 vlv_iosf_sb_get(dev_priv, 525 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 526 527 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 528 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 529 CCK_DISPLAY_CLOCK_CONTROL, 530 cdclk_config->vco); 531 532 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 533 534 vlv_iosf_sb_put(dev_priv, 535 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 536 537 if (IS_VALLEYVIEW(dev_priv)) 538 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 539 DSPFREQGUAR_SHIFT; 540 else 541 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 542 DSPFREQGUAR_SHIFT_CHV; 543 } 544 545 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) 546 { 547 unsigned int credits, default_credits; 548 549 if (IS_CHERRYVIEW(dev_priv)) 550 default_credits = PFI_CREDIT(12); 551 else 552 default_credits = PFI_CREDIT(8); 553 554 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { 555 /* CHV suggested value is 31 or 63 */ 556 if (IS_CHERRYVIEW(dev_priv)) 557 credits = PFI_CREDIT_63; 558 else 559 credits = PFI_CREDIT(15); 560 } else { 561 credits = default_credits; 562 } 563 564 /* 565 * WA - write default credits before re-programming 566 * FIXME: should we also set the resend bit here? 567 */ 568 intel_de_write(dev_priv, GCI_CONTROL, 569 VGA_FAST_MODE_DISABLE | default_credits); 570 571 intel_de_write(dev_priv, GCI_CONTROL, 572 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 573 574 /* 575 * FIXME is this guaranteed to clear 576 * immediately or should we poll for it? 577 */ 578 drm_WARN_ON(&dev_priv->drm, 579 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); 580 } 581 582 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, 583 const struct intel_cdclk_config *cdclk_config, 584 enum pipe pipe) 585 { 586 int cdclk = cdclk_config->cdclk; 587 u32 val, cmd = cdclk_config->voltage_level; 588 intel_wakeref_t wakeref; 589 590 switch (cdclk) { 591 case 400000: 592 case 333333: 593 case 320000: 594 case 266667: 595 case 200000: 596 break; 597 default: 598 MISSING_CASE(cdclk); 599 return; 600 } 601 602 /* There are cases where we can end up here with power domains 603 * off and a CDCLK frequency other than the minimum, like when 604 * issuing a modeset without actually changing any display after 605 * a system suspend. So grab the display core domain, which covers 606 * the HW blocks needed for the following programming. 607 */ 608 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 609 610 vlv_iosf_sb_get(dev_priv, 611 BIT(VLV_IOSF_SB_CCK) | 612 BIT(VLV_IOSF_SB_BUNIT) | 613 BIT(VLV_IOSF_SB_PUNIT)); 614 615 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 616 val &= ~DSPFREQGUAR_MASK; 617 val |= (cmd << DSPFREQGUAR_SHIFT); 618 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 619 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 620 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 621 50)) { 622 drm_err(&dev_priv->drm, 623 "timed out waiting for CDclk change\n"); 624 } 625 626 if (cdclk == 400000) { 627 u32 divider; 628 629 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 630 cdclk) - 1; 631 632 /* adjust cdclk divider */ 633 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 634 val &= ~CCK_FREQUENCY_VALUES; 635 val |= divider; 636 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 637 638 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 639 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 640 50)) 641 drm_err(&dev_priv->drm, 642 "timed out waiting for CDclk change\n"); 643 } 644 645 /* adjust self-refresh exit latency value */ 646 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 647 val &= ~0x7f; 648 649 /* 650 * For high bandwidth configs, we set a higher latency in the bunit 651 * so that the core display fetch happens in time to avoid underruns. 652 */ 653 if (cdclk == 400000) 654 val |= 4500 / 250; /* 4.5 usec */ 655 else 656 val |= 3000 / 250; /* 3.0 usec */ 657 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 658 659 vlv_iosf_sb_put(dev_priv, 660 BIT(VLV_IOSF_SB_CCK) | 661 BIT(VLV_IOSF_SB_BUNIT) | 662 BIT(VLV_IOSF_SB_PUNIT)); 663 664 intel_update_cdclk(dev_priv); 665 666 vlv_program_pfi_credits(dev_priv); 667 668 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 669 } 670 671 static void chv_set_cdclk(struct drm_i915_private *dev_priv, 672 const struct intel_cdclk_config *cdclk_config, 673 enum pipe pipe) 674 { 675 int cdclk = cdclk_config->cdclk; 676 u32 val, cmd = cdclk_config->voltage_level; 677 intel_wakeref_t wakeref; 678 679 switch (cdclk) { 680 case 333333: 681 case 320000: 682 case 266667: 683 case 200000: 684 break; 685 default: 686 MISSING_CASE(cdclk); 687 return; 688 } 689 690 /* There are cases where we can end up here with power domains 691 * off and a CDCLK frequency other than the minimum, like when 692 * issuing a modeset without actually changing any display after 693 * a system suspend. So grab the display core domain, which covers 694 * the HW blocks needed for the following programming. 695 */ 696 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 697 698 vlv_punit_get(dev_priv); 699 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 700 val &= ~DSPFREQGUAR_MASK_CHV; 701 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 702 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 703 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 704 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 705 50)) { 706 drm_err(&dev_priv->drm, 707 "timed out waiting for CDclk change\n"); 708 } 709 710 vlv_punit_put(dev_priv); 711 712 intel_update_cdclk(dev_priv); 713 714 vlv_program_pfi_credits(dev_priv); 715 716 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 717 } 718 719 static int bdw_calc_cdclk(int min_cdclk) 720 { 721 if (min_cdclk > 540000) 722 return 675000; 723 else if (min_cdclk > 450000) 724 return 540000; 725 else if (min_cdclk > 337500) 726 return 450000; 727 else 728 return 337500; 729 } 730 731 static u8 bdw_calc_voltage_level(int cdclk) 732 { 733 switch (cdclk) { 734 default: 735 case 337500: 736 return 2; 737 case 450000: 738 return 0; 739 case 540000: 740 return 1; 741 case 675000: 742 return 3; 743 } 744 } 745 746 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, 747 struct intel_cdclk_config *cdclk_config) 748 { 749 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); 750 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 751 752 if (lcpll & LCPLL_CD_SOURCE_FCLK) 753 cdclk_config->cdclk = 800000; 754 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 755 cdclk_config->cdclk = 450000; 756 else if (freq == LCPLL_CLK_FREQ_450) 757 cdclk_config->cdclk = 450000; 758 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 759 cdclk_config->cdclk = 540000; 760 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 761 cdclk_config->cdclk = 337500; 762 else 763 cdclk_config->cdclk = 675000; 764 765 /* 766 * Can't read this out :( Let's assume it's 767 * at least what the CDCLK frequency requires. 768 */ 769 cdclk_config->voltage_level = 770 bdw_calc_voltage_level(cdclk_config->cdclk); 771 } 772 773 static u32 bdw_cdclk_freq_sel(int cdclk) 774 { 775 switch (cdclk) { 776 default: 777 MISSING_CASE(cdclk); 778 fallthrough; 779 case 337500: 780 return LCPLL_CLK_FREQ_337_5_BDW; 781 case 450000: 782 return LCPLL_CLK_FREQ_450; 783 case 540000: 784 return LCPLL_CLK_FREQ_54O_BDW; 785 case 675000: 786 return LCPLL_CLK_FREQ_675_BDW; 787 } 788 } 789 790 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, 791 const struct intel_cdclk_config *cdclk_config, 792 enum pipe pipe) 793 { 794 int cdclk = cdclk_config->cdclk; 795 int ret; 796 797 if (drm_WARN(&dev_priv->drm, 798 (intel_de_read(dev_priv, LCPLL_CTL) & 799 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 800 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 801 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 802 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 803 "trying to change cdclk frequency with cdclk not enabled\n")) 804 return; 805 806 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 807 if (ret) { 808 drm_err(&dev_priv->drm, 809 "failed to inform pcode about cdclk change\n"); 810 return; 811 } 812 813 intel_de_rmw(dev_priv, LCPLL_CTL, 814 0, LCPLL_CD_SOURCE_FCLK); 815 816 /* 817 * According to the spec, it should be enough to poll for this 1 us. 818 * However, extensive testing shows that this can take longer. 819 */ 820 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 821 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 822 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 823 824 intel_de_rmw(dev_priv, LCPLL_CTL, 825 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 826 827 intel_de_rmw(dev_priv, LCPLL_CTL, 828 LCPLL_CD_SOURCE_FCLK, 0); 829 830 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 831 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 832 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); 833 834 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, 835 cdclk_config->voltage_level); 836 837 intel_de_write(dev_priv, CDCLK_FREQ, 838 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 839 840 intel_update_cdclk(dev_priv); 841 } 842 843 static int skl_calc_cdclk(int min_cdclk, int vco) 844 { 845 if (vco == 8640000) { 846 if (min_cdclk > 540000) 847 return 617143; 848 else if (min_cdclk > 432000) 849 return 540000; 850 else if (min_cdclk > 308571) 851 return 432000; 852 else 853 return 308571; 854 } else { 855 if (min_cdclk > 540000) 856 return 675000; 857 else if (min_cdclk > 450000) 858 return 540000; 859 else if (min_cdclk > 337500) 860 return 450000; 861 else 862 return 337500; 863 } 864 } 865 866 static u8 skl_calc_voltage_level(int cdclk) 867 { 868 if (cdclk > 540000) 869 return 3; 870 else if (cdclk > 450000) 871 return 2; 872 else if (cdclk > 337500) 873 return 1; 874 else 875 return 0; 876 } 877 878 static void skl_dpll0_update(struct drm_i915_private *dev_priv, 879 struct intel_cdclk_config *cdclk_config) 880 { 881 u32 val; 882 883 cdclk_config->ref = 24000; 884 cdclk_config->vco = 0; 885 886 val = intel_de_read(dev_priv, LCPLL1_CTL); 887 if ((val & LCPLL_PLL_ENABLE) == 0) 888 return; 889 890 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) 891 return; 892 893 val = intel_de_read(dev_priv, DPLL_CTRL1); 894 895 if (drm_WARN_ON(&dev_priv->drm, 896 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 897 DPLL_CTRL1_SSC(SKL_DPLL0) | 898 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 899 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 900 return; 901 902 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 903 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 904 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 905 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 906 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 907 cdclk_config->vco = 8100000; 908 break; 909 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 910 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 911 cdclk_config->vco = 8640000; 912 break; 913 default: 914 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 915 break; 916 } 917 } 918 919 static void skl_get_cdclk(struct drm_i915_private *dev_priv, 920 struct intel_cdclk_config *cdclk_config) 921 { 922 u32 cdctl; 923 924 skl_dpll0_update(dev_priv, cdclk_config); 925 926 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 927 928 if (cdclk_config->vco == 0) 929 goto out; 930 931 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 932 933 if (cdclk_config->vco == 8640000) { 934 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 935 case CDCLK_FREQ_450_432: 936 cdclk_config->cdclk = 432000; 937 break; 938 case CDCLK_FREQ_337_308: 939 cdclk_config->cdclk = 308571; 940 break; 941 case CDCLK_FREQ_540: 942 cdclk_config->cdclk = 540000; 943 break; 944 case CDCLK_FREQ_675_617: 945 cdclk_config->cdclk = 617143; 946 break; 947 default: 948 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 949 break; 950 } 951 } else { 952 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 953 case CDCLK_FREQ_450_432: 954 cdclk_config->cdclk = 450000; 955 break; 956 case CDCLK_FREQ_337_308: 957 cdclk_config->cdclk = 337500; 958 break; 959 case CDCLK_FREQ_540: 960 cdclk_config->cdclk = 540000; 961 break; 962 case CDCLK_FREQ_675_617: 963 cdclk_config->cdclk = 675000; 964 break; 965 default: 966 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 967 break; 968 } 969 } 970 971 out: 972 /* 973 * Can't read this out :( Let's assume it's 974 * at least what the CDCLK frequency requires. 975 */ 976 cdclk_config->voltage_level = 977 skl_calc_voltage_level(cdclk_config->cdclk); 978 } 979 980 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 981 static int skl_cdclk_decimal(int cdclk) 982 { 983 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 984 } 985 986 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, 987 int vco) 988 { 989 bool changed = dev_priv->skl_preferred_vco_freq != vco; 990 991 dev_priv->skl_preferred_vco_freq = vco; 992 993 if (changed) 994 intel_update_max_cdclk(dev_priv); 995 } 996 997 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) 998 { 999 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 1000 1001 /* 1002 * We always enable DPLL0 with the lowest link rate possible, but still 1003 * taking into account the VCO required to operate the eDP panel at the 1004 * desired frequency. The usual DP link rates operate with a VCO of 1005 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1006 * The modeset code is responsible for the selection of the exact link 1007 * rate later on, with the constraint of choosing a frequency that 1008 * works with vco. 1009 */ 1010 if (vco == 8640000) 1011 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1012 else 1013 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1014 } 1015 1016 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 1017 { 1018 intel_de_rmw(dev_priv, DPLL_CTRL1, 1019 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1020 DPLL_CTRL1_SSC(SKL_DPLL0) | 1021 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1022 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1023 skl_dpll0_link_rate(dev_priv, vco)); 1024 intel_de_posting_read(dev_priv, DPLL_CTRL1); 1025 1026 intel_de_rmw(dev_priv, LCPLL1_CTL, 1027 0, LCPLL_PLL_ENABLE); 1028 1029 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1030 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); 1031 1032 dev_priv->display.cdclk.hw.vco = vco; 1033 1034 /* We'll want to keep using the current vco from now on. */ 1035 skl_set_preferred_cdclk_vco(dev_priv, vco); 1036 } 1037 1038 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) 1039 { 1040 intel_de_rmw(dev_priv, LCPLL1_CTL, 1041 LCPLL_PLL_ENABLE, 0); 1042 1043 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1044 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); 1045 1046 dev_priv->display.cdclk.hw.vco = 0; 1047 } 1048 1049 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, 1050 int cdclk, int vco) 1051 { 1052 switch (cdclk) { 1053 default: 1054 drm_WARN_ON(&dev_priv->drm, 1055 cdclk != dev_priv->display.cdclk.hw.bypass); 1056 drm_WARN_ON(&dev_priv->drm, vco != 0); 1057 fallthrough; 1058 case 308571: 1059 case 337500: 1060 return CDCLK_FREQ_337_308; 1061 case 450000: 1062 case 432000: 1063 return CDCLK_FREQ_450_432; 1064 case 540000: 1065 return CDCLK_FREQ_540; 1066 case 617143: 1067 case 675000: 1068 return CDCLK_FREQ_675_617; 1069 } 1070 } 1071 1072 static void skl_set_cdclk(struct drm_i915_private *dev_priv, 1073 const struct intel_cdclk_config *cdclk_config, 1074 enum pipe pipe) 1075 { 1076 int cdclk = cdclk_config->cdclk; 1077 int vco = cdclk_config->vco; 1078 u32 freq_select, cdclk_ctl; 1079 int ret; 1080 1081 /* 1082 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1083 * unsupported on SKL. In theory this should never happen since only 1084 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1085 * supported on SKL either, see the above WA. WARN whenever trying to 1086 * use the corresponding VCO freq as that always leads to using the 1087 * minimum 308MHz CDCLK. 1088 */ 1089 drm_WARN_ON_ONCE(&dev_priv->drm, 1090 IS_SKYLAKE(dev_priv) && vco == 8640000); 1091 1092 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1093 SKL_CDCLK_PREPARE_FOR_CHANGE, 1094 SKL_CDCLK_READY_FOR_CHANGE, 1095 SKL_CDCLK_READY_FOR_CHANGE, 3); 1096 if (ret) { 1097 drm_err(&dev_priv->drm, 1098 "Failed to inform PCU about cdclk change (%d)\n", ret); 1099 return; 1100 } 1101 1102 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); 1103 1104 if (dev_priv->display.cdclk.hw.vco != 0 && 1105 dev_priv->display.cdclk.hw.vco != vco) 1106 skl_dpll0_disable(dev_priv); 1107 1108 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); 1109 1110 if (dev_priv->display.cdclk.hw.vco != vco) { 1111 /* Wa Display #1183: skl,kbl,cfl */ 1112 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1113 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1114 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1115 } 1116 1117 /* Wa Display #1183: skl,kbl,cfl */ 1118 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1119 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1120 intel_de_posting_read(dev_priv, CDCLK_CTL); 1121 1122 if (dev_priv->display.cdclk.hw.vco != vco) 1123 skl_dpll0_enable(dev_priv, vco); 1124 1125 /* Wa Display #1183: skl,kbl,cfl */ 1126 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1127 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1128 1129 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1130 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1131 1132 /* Wa Display #1183: skl,kbl,cfl */ 1133 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1134 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); 1135 intel_de_posting_read(dev_priv, CDCLK_CTL); 1136 1137 /* inform PCU of the change */ 1138 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1139 cdclk_config->voltage_level); 1140 1141 intel_update_cdclk(dev_priv); 1142 } 1143 1144 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) 1145 { 1146 u32 cdctl, expected; 1147 1148 /* 1149 * check if the pre-os initialized the display 1150 * There is SWF18 scratchpad register defined which is set by the 1151 * pre-os which can be used by the OS drivers to check the status 1152 */ 1153 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1154 goto sanitize; 1155 1156 intel_update_cdclk(dev_priv); 1157 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 1158 1159 /* Is PLL enabled and locked ? */ 1160 if (dev_priv->display.cdclk.hw.vco == 0 || 1161 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 1162 goto sanitize; 1163 1164 /* DPLL okay; verify the cdclock 1165 * 1166 * Noticed in some instances that the freq selection is correct but 1167 * decimal part is programmed wrong from BIOS where pre-os does not 1168 * enable display. Verify the same as well. 1169 */ 1170 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 1171 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1172 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); 1173 if (cdctl == expected) 1174 /* All well; nothing to sanitize */ 1175 return; 1176 1177 sanitize: 1178 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 1179 1180 /* force cdclk programming */ 1181 dev_priv->display.cdclk.hw.cdclk = 0; 1182 /* force full PLL disable + enable */ 1183 dev_priv->display.cdclk.hw.vco = ~0; 1184 } 1185 1186 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) 1187 { 1188 struct intel_cdclk_config cdclk_config; 1189 1190 skl_sanitize_cdclk(dev_priv); 1191 1192 if (dev_priv->display.cdclk.hw.cdclk != 0 && 1193 dev_priv->display.cdclk.hw.vco != 0) { 1194 /* 1195 * Use the current vco as our initial 1196 * guess as to what the preferred vco is. 1197 */ 1198 if (dev_priv->skl_preferred_vco_freq == 0) 1199 skl_set_preferred_cdclk_vco(dev_priv, 1200 dev_priv->display.cdclk.hw.vco); 1201 return; 1202 } 1203 1204 cdclk_config = dev_priv->display.cdclk.hw; 1205 1206 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; 1207 if (cdclk_config.vco == 0) 1208 cdclk_config.vco = 8100000; 1209 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1210 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1211 1212 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1213 } 1214 1215 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 1216 { 1217 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 1218 1219 cdclk_config.cdclk = cdclk_config.bypass; 1220 cdclk_config.vco = 0; 1221 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1222 1223 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 1224 } 1225 1226 struct intel_cdclk_vals { 1227 u32 cdclk; 1228 u16 refclk; 1229 u16 waveform; 1230 u8 divider; /* CD2X divider * 2 */ 1231 u8 ratio; 1232 }; 1233 1234 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1235 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 }, 1236 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 }, 1237 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 }, 1238 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 }, 1239 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 }, 1240 {} 1241 }; 1242 1243 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1244 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 }, 1245 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 }, 1246 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 }, 1247 {} 1248 }; 1249 1250 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1251 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 }, 1252 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1253 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1254 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 }, 1255 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1256 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1257 1258 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 }, 1259 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1260 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1261 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 }, 1262 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1263 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1264 1265 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 }, 1266 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1267 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1268 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 }, 1269 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1270 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1271 {} 1272 }; 1273 1274 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1275 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 }, 1276 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 }, 1277 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 }, 1278 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 }, 1279 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 }, 1280 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 }, 1281 1282 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 }, 1283 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 }, 1284 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 }, 1285 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 }, 1286 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 }, 1287 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 }, 1288 1289 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 }, 1290 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 }, 1291 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 }, 1292 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 }, 1293 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 }, 1294 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 }, 1295 {} 1296 }; 1297 1298 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1299 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1300 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1301 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1302 1303 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1304 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1305 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1306 1307 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1308 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1309 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1310 {} 1311 }; 1312 1313 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1314 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, 1315 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1316 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1317 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1318 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1319 1320 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 }, 1321 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1322 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1323 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1324 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1325 1326 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 }, 1327 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1328 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1329 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1330 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1331 {} 1332 }; 1333 1334 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1335 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 }, 1336 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 }, 1337 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 }, 1338 { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 }, 1339 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 }, 1340 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 }, 1341 1342 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 }, 1343 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 }, 1344 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 }, 1345 { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 }, 1346 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 }, 1347 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 }, 1348 1349 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 }, 1350 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 }, 1351 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 }, 1352 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 }, 1353 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 }, 1354 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 }, 1355 {} 1356 }; 1357 1358 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1359 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 }, 1360 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 }, 1361 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 }, 1362 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a }, 1363 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa }, 1364 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a }, 1365 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 }, 1366 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 }, 1367 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee }, 1368 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de }, 1369 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe }, 1370 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe }, 1371 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff }, 1372 {} 1373 }; 1374 1375 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1376 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a }, 1377 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 }, 1378 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 }, 1379 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 }, 1380 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 }, 1381 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 }, 1382 {} 1383 }; 1384 1385 static const struct intel_cdclk_vals lnl_cdclk_table[] = { 1386 { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa }, 1387 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a }, 1388 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 }, 1389 { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 }, 1390 { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee }, 1391 { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de }, 1392 { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe }, 1393 { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe }, 1394 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff }, 1395 { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 }, 1396 { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee }, 1397 { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de }, 1398 { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe }, 1399 { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe }, 1400 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff }, 1401 { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe }, 1402 { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe }, 1403 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff }, 1404 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe }, 1405 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe }, 1406 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff }, 1407 {} 1408 }; 1409 1410 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) 1411 { 1412 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1413 int i; 1414 1415 for (i = 0; table[i].refclk; i++) 1416 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1417 table[i].cdclk >= min_cdclk) 1418 return table[i].cdclk; 1419 1420 drm_WARN(&dev_priv->drm, 1, 1421 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1422 min_cdclk, dev_priv->display.cdclk.hw.ref); 1423 return 0; 1424 } 1425 1426 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) 1427 { 1428 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1429 int i; 1430 1431 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1432 return 0; 1433 1434 for (i = 0; table[i].refclk; i++) 1435 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1436 table[i].cdclk == cdclk) 1437 return dev_priv->display.cdclk.hw.ref * table[i].ratio; 1438 1439 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1440 cdclk, dev_priv->display.cdclk.hw.ref); 1441 return 0; 1442 } 1443 1444 static u8 bxt_calc_voltage_level(int cdclk) 1445 { 1446 return DIV_ROUND_UP(cdclk, 25000); 1447 } 1448 1449 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1450 const int voltage_level_max_cdclk[]) 1451 { 1452 int voltage_level; 1453 1454 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1455 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1456 return voltage_level; 1457 } 1458 1459 MISSING_CASE(cdclk); 1460 return num_voltage_levels - 1; 1461 } 1462 1463 static u8 icl_calc_voltage_level(int cdclk) 1464 { 1465 static const int icl_voltage_level_max_cdclk[] = { 1466 [0] = 312000, 1467 [1] = 556800, 1468 [2] = 652800, 1469 }; 1470 1471 return calc_voltage_level(cdclk, 1472 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1473 icl_voltage_level_max_cdclk); 1474 } 1475 1476 static u8 ehl_calc_voltage_level(int cdclk) 1477 { 1478 static const int ehl_voltage_level_max_cdclk[] = { 1479 [0] = 180000, 1480 [1] = 312000, 1481 [2] = 326400, 1482 /* 1483 * Bspec lists the limit as 556.8 MHz, but some JSL 1484 * development boards (at least) boot with 652.8 MHz 1485 */ 1486 [3] = 652800, 1487 }; 1488 1489 return calc_voltage_level(cdclk, 1490 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1491 ehl_voltage_level_max_cdclk); 1492 } 1493 1494 static u8 tgl_calc_voltage_level(int cdclk) 1495 { 1496 static const int tgl_voltage_level_max_cdclk[] = { 1497 [0] = 312000, 1498 [1] = 326400, 1499 [2] = 556800, 1500 [3] = 652800, 1501 }; 1502 1503 return calc_voltage_level(cdclk, 1504 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1505 tgl_voltage_level_max_cdclk); 1506 } 1507 1508 static u8 rplu_calc_voltage_level(int cdclk) 1509 { 1510 static const int rplu_voltage_level_max_cdclk[] = { 1511 [0] = 312000, 1512 [1] = 480000, 1513 [2] = 556800, 1514 [3] = 652800, 1515 }; 1516 1517 return calc_voltage_level(cdclk, 1518 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1519 rplu_voltage_level_max_cdclk); 1520 } 1521 1522 static void icl_readout_refclk(struct drm_i915_private *dev_priv, 1523 struct intel_cdclk_config *cdclk_config) 1524 { 1525 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1526 1527 switch (dssm) { 1528 default: 1529 MISSING_CASE(dssm); 1530 fallthrough; 1531 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1532 cdclk_config->ref = 24000; 1533 break; 1534 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1535 cdclk_config->ref = 19200; 1536 break; 1537 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1538 cdclk_config->ref = 38400; 1539 break; 1540 } 1541 } 1542 1543 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, 1544 struct intel_cdclk_config *cdclk_config) 1545 { 1546 u32 val, ratio; 1547 1548 if (IS_DG2(dev_priv)) 1549 cdclk_config->ref = 38400; 1550 else if (DISPLAY_VER(dev_priv) >= 11) 1551 icl_readout_refclk(dev_priv, cdclk_config); 1552 else 1553 cdclk_config->ref = 19200; 1554 1555 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); 1556 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1557 (val & BXT_DE_PLL_LOCK) == 0) { 1558 /* 1559 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1560 * setting it to zero is a way to signal that. 1561 */ 1562 cdclk_config->vco = 0; 1563 return; 1564 } 1565 1566 /* 1567 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1568 * gen9lp had it in a separate PLL control register. 1569 */ 1570 if (DISPLAY_VER(dev_priv) >= 11) 1571 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1572 else 1573 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1574 1575 cdclk_config->vco = ratio * cdclk_config->ref; 1576 } 1577 1578 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 1579 struct intel_cdclk_config *cdclk_config) 1580 { 1581 u32 squash_ctl = 0; 1582 u32 divider; 1583 int div; 1584 1585 bxt_de_pll_readout(dev_priv, cdclk_config); 1586 1587 if (DISPLAY_VER(dev_priv) >= 12) 1588 cdclk_config->bypass = cdclk_config->ref / 2; 1589 else if (DISPLAY_VER(dev_priv) >= 11) 1590 cdclk_config->bypass = 50000; 1591 else 1592 cdclk_config->bypass = cdclk_config->ref; 1593 1594 if (cdclk_config->vco == 0) { 1595 cdclk_config->cdclk = cdclk_config->bypass; 1596 goto out; 1597 } 1598 1599 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1600 1601 switch (divider) { 1602 case BXT_CDCLK_CD2X_DIV_SEL_1: 1603 div = 2; 1604 break; 1605 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1606 div = 3; 1607 break; 1608 case BXT_CDCLK_CD2X_DIV_SEL_2: 1609 div = 4; 1610 break; 1611 case BXT_CDCLK_CD2X_DIV_SEL_4: 1612 div = 8; 1613 break; 1614 default: 1615 MISSING_CASE(divider); 1616 return; 1617 } 1618 1619 if (HAS_CDCLK_SQUASH(dev_priv)) 1620 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); 1621 1622 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1623 u16 waveform; 1624 int size; 1625 1626 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1627 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1628 1629 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1630 cdclk_config->vco, size * div); 1631 } else { 1632 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1633 } 1634 1635 out: 1636 /* 1637 * Can't read this out :( Let's assume it's 1638 * at least what the CDCLK frequency requires. 1639 */ 1640 cdclk_config->voltage_level = 1641 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); 1642 } 1643 1644 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) 1645 { 1646 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); 1647 1648 /* Timeout 200us */ 1649 if (intel_de_wait_for_clear(dev_priv, 1650 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1651 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); 1652 1653 dev_priv->display.cdclk.hw.vco = 0; 1654 } 1655 1656 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) 1657 { 1658 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1659 1660 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, 1661 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1662 1663 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1664 1665 /* Timeout 200us */ 1666 if (intel_de_wait_for_set(dev_priv, 1667 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1668 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); 1669 1670 dev_priv->display.cdclk.hw.vco = vco; 1671 } 1672 1673 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) 1674 { 1675 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, 1676 BXT_DE_PLL_PLL_ENABLE, 0); 1677 1678 /* Timeout 200us */ 1679 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1680 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); 1681 1682 dev_priv->display.cdclk.hw.vco = 0; 1683 } 1684 1685 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) 1686 { 1687 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1688 u32 val; 1689 1690 val = ICL_CDCLK_PLL_RATIO(ratio); 1691 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1692 1693 val |= BXT_DE_PLL_PLL_ENABLE; 1694 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1695 1696 /* Timeout 200us */ 1697 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1698 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); 1699 1700 dev_priv->display.cdclk.hw.vco = vco; 1701 } 1702 1703 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) 1704 { 1705 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); 1706 u32 val; 1707 1708 /* Write PLL ratio without disabling */ 1709 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1710 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1711 1712 /* Submit freq change request */ 1713 val |= BXT_DE_PLL_FREQ_REQ; 1714 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1715 1716 /* Timeout 200us */ 1717 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, 1718 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1719 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); 1720 1721 val &= ~BXT_DE_PLL_FREQ_REQ; 1722 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); 1723 1724 dev_priv->display.cdclk.hw.vco = vco; 1725 } 1726 1727 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) 1728 { 1729 if (DISPLAY_VER(dev_priv) >= 12) { 1730 if (pipe == INVALID_PIPE) 1731 return TGL_CDCLK_CD2X_PIPE_NONE; 1732 else 1733 return TGL_CDCLK_CD2X_PIPE(pipe); 1734 } else if (DISPLAY_VER(dev_priv) >= 11) { 1735 if (pipe == INVALID_PIPE) 1736 return ICL_CDCLK_CD2X_PIPE_NONE; 1737 else 1738 return ICL_CDCLK_CD2X_PIPE(pipe); 1739 } else { 1740 if (pipe == INVALID_PIPE) 1741 return BXT_CDCLK_CD2X_PIPE_NONE; 1742 else 1743 return BXT_CDCLK_CD2X_PIPE(pipe); 1744 } 1745 } 1746 1747 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, 1748 int cdclk, int vco) 1749 { 1750 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1751 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { 1752 default: 1753 drm_WARN_ON(&dev_priv->drm, 1754 cdclk != dev_priv->display.cdclk.hw.bypass); 1755 drm_WARN_ON(&dev_priv->drm, vco != 0); 1756 fallthrough; 1757 case 2: 1758 return BXT_CDCLK_CD2X_DIV_SEL_1; 1759 case 3: 1760 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1761 case 4: 1762 return BXT_CDCLK_CD2X_DIV_SEL_2; 1763 case 8: 1764 return BXT_CDCLK_CD2X_DIV_SEL_4; 1765 } 1766 } 1767 1768 static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, 1769 int cdclk) 1770 { 1771 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; 1772 int i; 1773 1774 if (cdclk == dev_priv->display.cdclk.hw.bypass) 1775 return 0; 1776 1777 for (i = 0; table[i].refclk; i++) 1778 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && 1779 table[i].cdclk == cdclk) 1780 return table[i].waveform; 1781 1782 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", 1783 cdclk, dev_priv->display.cdclk.hw.ref); 1784 1785 return 0xffff; 1786 } 1787 1788 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1789 { 1790 if (i915->display.cdclk.hw.vco != 0 && 1791 i915->display.cdclk.hw.vco != vco) 1792 icl_cdclk_pll_disable(i915); 1793 1794 if (i915->display.cdclk.hw.vco != vco) 1795 icl_cdclk_pll_enable(i915, vco); 1796 } 1797 1798 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) 1799 { 1800 if (i915->display.cdclk.hw.vco != 0 && 1801 i915->display.cdclk.hw.vco != vco) 1802 bxt_de_pll_disable(i915); 1803 1804 if (i915->display.cdclk.hw.vco != vco) 1805 bxt_de_pll_enable(i915, vco); 1806 } 1807 1808 static void dg2_cdclk_squash_program(struct drm_i915_private *i915, 1809 u16 waveform) 1810 { 1811 u32 squash_ctl = 0; 1812 1813 if (waveform) 1814 squash_ctl = CDCLK_SQUASH_ENABLE | 1815 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1816 1817 intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); 1818 } 1819 1820 static bool cdclk_pll_is_unknown(unsigned int vco) 1821 { 1822 /* 1823 * Ensure driver does not take the crawl path for the 1824 * case when the vco is set to ~0 in the 1825 * sanitize path. 1826 */ 1827 return vco == ~0; 1828 } 1829 1830 static const int cdclk_squash_len = 16; 1831 1832 static int cdclk_squash_divider(u16 waveform) 1833 { 1834 return hweight16(waveform ?: 0xffff); 1835 } 1836 1837 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915, 1838 const struct intel_cdclk_config *old_cdclk_config, 1839 const struct intel_cdclk_config *new_cdclk_config, 1840 struct intel_cdclk_config *mid_cdclk_config) 1841 { 1842 u16 old_waveform, new_waveform, mid_waveform; 1843 int div = 2; 1844 1845 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 1846 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 1847 return false; 1848 1849 /* Return if both Squash and Crawl are not present */ 1850 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) 1851 return false; 1852 1853 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); 1854 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); 1855 1856 /* Return if Squash only or Crawl only is the desired action */ 1857 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 1858 old_cdclk_config->vco == new_cdclk_config->vco || 1859 old_waveform == new_waveform) 1860 return false; 1861 1862 *mid_cdclk_config = *new_cdclk_config; 1863 1864 /* 1865 * Populate the mid_cdclk_config accordingly. 1866 * - If moving to a higher cdclk, the desired action is squashing. 1867 * The mid cdclk config should have the new (squash) waveform. 1868 * - If moving to a lower cdclk, the desired action is crawling. 1869 * The mid cdclk config should have the new vco. 1870 */ 1871 1872 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 1873 mid_cdclk_config->vco = old_cdclk_config->vco; 1874 mid_waveform = new_waveform; 1875 } else { 1876 mid_cdclk_config->vco = new_cdclk_config->vco; 1877 mid_waveform = old_waveform; 1878 } 1879 1880 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 1881 mid_cdclk_config->vco, 1882 cdclk_squash_len * div); 1883 1884 /* make sure the mid clock came out sane */ 1885 1886 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < 1887 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 1888 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > 1889 i915->display.cdclk.max_cdclk_freq); 1890 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != 1891 mid_waveform); 1892 1893 return true; 1894 } 1895 1896 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) 1897 { 1898 return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) || 1899 DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) || 1900 IS_DG2(dev_priv)) && 1901 dev_priv->display.cdclk.hw.vco > 0; 1902 } 1903 1904 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, 1905 const struct intel_cdclk_config *cdclk_config, 1906 enum pipe pipe) 1907 { 1908 int cdclk = cdclk_config->cdclk; 1909 int vco = cdclk_config->vco; 1910 int unsquashed_cdclk; 1911 u16 waveform; 1912 u32 val; 1913 1914 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && 1915 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { 1916 if (dev_priv->display.cdclk.hw.vco != vco) 1917 adlp_cdclk_pll_crawl(dev_priv, vco); 1918 } else if (DISPLAY_VER(dev_priv) >= 11) { 1919 /* wa_15010685871: dg2, mtl */ 1920 if (pll_enable_wa_needed(dev_priv)) 1921 dg2_cdclk_squash_program(dev_priv, 0); 1922 1923 icl_cdclk_pll_update(dev_priv, vco); 1924 } else 1925 bxt_cdclk_pll_update(dev_priv, vco); 1926 1927 waveform = cdclk_squash_waveform(dev_priv, cdclk); 1928 1929 unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len, 1930 cdclk_squash_divider(waveform)); 1931 1932 if (HAS_CDCLK_SQUASH(dev_priv)) 1933 dg2_cdclk_squash_program(dev_priv, waveform); 1934 1935 val = bxt_cdclk_cd2x_div_sel(dev_priv, unsquashed_cdclk, vco) | 1936 bxt_cdclk_cd2x_pipe(dev_priv, pipe); 1937 1938 /* 1939 * Disable SSA Precharge when CD clock frequency < 500 MHz, 1940 * enable otherwise. 1941 */ 1942 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1943 cdclk >= 500000) 1944 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 1945 1946 if (DISPLAY_VER(dev_priv) >= 20) 1947 val |= MDCLK_SOURCE_SEL_CDCLK_PLL; 1948 else 1949 val |= skl_cdclk_decimal(cdclk); 1950 1951 intel_de_write(dev_priv, CDCLK_CTL, val); 1952 1953 if (pipe != INVALID_PIPE) 1954 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); 1955 } 1956 1957 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 1958 const struct intel_cdclk_config *cdclk_config, 1959 enum pipe pipe) 1960 { 1961 struct intel_cdclk_config mid_cdclk_config; 1962 int cdclk = cdclk_config->cdclk; 1963 int ret = 0; 1964 1965 /* 1966 * Inform power controller of upcoming frequency change. 1967 * Display versions 14 and beyond do not follow the PUnit 1968 * mailbox communication, skip 1969 * this step. 1970 */ 1971 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) 1972 /* NOOP */; 1973 else if (DISPLAY_VER(dev_priv) >= 11) 1974 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1975 SKL_CDCLK_PREPARE_FOR_CHANGE, 1976 SKL_CDCLK_READY_FOR_CHANGE, 1977 SKL_CDCLK_READY_FOR_CHANGE, 3); 1978 else 1979 /* 1980 * BSpec requires us to wait up to 150usec, but that leads to 1981 * timeouts; the 2ms used here is based on experiment. 1982 */ 1983 ret = snb_pcode_write_timeout(&dev_priv->uncore, 1984 HSW_PCODE_DE_WRITE_FREQ_REQ, 1985 0x80000000, 150, 2); 1986 1987 if (ret) { 1988 drm_err(&dev_priv->drm, 1989 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 1990 ret, cdclk); 1991 return; 1992 } 1993 1994 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, 1995 cdclk_config, &mid_cdclk_config)) { 1996 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); 1997 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); 1998 } else { 1999 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); 2000 } 2001 2002 if (DISPLAY_VER(dev_priv) >= 14) 2003 /* 2004 * NOOP - No Pcode communication needed for 2005 * Display versions 14 and beyond 2006 */; 2007 else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) 2008 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 2009 cdclk_config->voltage_level); 2010 if (DISPLAY_VER(dev_priv) < 11) { 2011 /* 2012 * The timeout isn't specified, the 2ms used here is based on 2013 * experiment. 2014 * FIXME: Waiting for the request completion could be delayed 2015 * until the next PCODE request based on BSpec. 2016 */ 2017 ret = snb_pcode_write_timeout(&dev_priv->uncore, 2018 HSW_PCODE_DE_WRITE_FREQ_REQ, 2019 cdclk_config->voltage_level, 2020 150, 2); 2021 } 2022 if (ret) { 2023 drm_err(&dev_priv->drm, 2024 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2025 ret, cdclk); 2026 return; 2027 } 2028 2029 intel_update_cdclk(dev_priv); 2030 2031 if (DISPLAY_VER(dev_priv) >= 11) 2032 /* 2033 * Can't read out the voltage level :( 2034 * Let's just assume everything is as expected. 2035 */ 2036 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; 2037 } 2038 2039 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 2040 { 2041 u32 cdctl, expected; 2042 int cdclk, clock, vco; 2043 2044 intel_update_cdclk(dev_priv); 2045 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); 2046 2047 if (dev_priv->display.cdclk.hw.vco == 0 || 2048 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) 2049 goto sanitize; 2050 2051 /* DPLL okay; verify the cdclock 2052 * 2053 * Some BIOS versions leave an incorrect decimal frequency value and 2054 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2055 * so sanitize this register. 2056 */ 2057 cdctl = intel_de_read(dev_priv, CDCLK_CTL); 2058 /* 2059 * Let's ignore the pipe field, since BIOS could have configured the 2060 * dividers both synching to an active pipe, or asynchronously 2061 * (PIPE_NONE). 2062 */ 2063 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); 2064 2065 /* Make sure this is a legal cdclk value for the platform */ 2066 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); 2067 if (cdclk != dev_priv->display.cdclk.hw.cdclk) 2068 goto sanitize; 2069 2070 /* Make sure the VCO is correct for the cdclk */ 2071 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2072 if (vco != dev_priv->display.cdclk.hw.vco) 2073 goto sanitize; 2074 2075 expected = skl_cdclk_decimal(cdclk); 2076 2077 /* Figure out what CD2X divider we should be using for this cdclk */ 2078 if (HAS_CDCLK_SQUASH(dev_priv)) 2079 clock = dev_priv->display.cdclk.hw.vco / 2; 2080 else 2081 clock = dev_priv->display.cdclk.hw.cdclk; 2082 2083 expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock, 2084 dev_priv->display.cdclk.hw.vco); 2085 2086 /* 2087 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2088 * enable otherwise. 2089 */ 2090 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 2091 dev_priv->display.cdclk.hw.cdclk >= 500000) 2092 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2093 2094 if (cdctl == expected) 2095 /* All well; nothing to sanitize */ 2096 return; 2097 2098 sanitize: 2099 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); 2100 2101 /* force cdclk programming */ 2102 dev_priv->display.cdclk.hw.cdclk = 0; 2103 2104 /* force full PLL disable + enable */ 2105 dev_priv->display.cdclk.hw.vco = ~0; 2106 } 2107 2108 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 2109 { 2110 struct intel_cdclk_config cdclk_config; 2111 2112 bxt_sanitize_cdclk(dev_priv); 2113 2114 if (dev_priv->display.cdclk.hw.cdclk != 0 && 2115 dev_priv->display.cdclk.hw.vco != 0) 2116 return; 2117 2118 cdclk_config = dev_priv->display.cdclk.hw; 2119 2120 /* 2121 * FIXME: 2122 * - The initial CDCLK needs to be read from VBT. 2123 * Need to make this change after VBT has changes for BXT. 2124 */ 2125 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); 2126 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); 2127 cdclk_config.voltage_level = 2128 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 2129 2130 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 2131 } 2132 2133 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 2134 { 2135 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; 2136 2137 cdclk_config.cdclk = cdclk_config.bypass; 2138 cdclk_config.vco = 0; 2139 cdclk_config.voltage_level = 2140 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); 2141 2142 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); 2143 } 2144 2145 /** 2146 * intel_cdclk_init_hw - Initialize CDCLK hardware 2147 * @i915: i915 device 2148 * 2149 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and 2150 * sanitizing the state of the hardware if needed. This is generally done only 2151 * during the display core initialization sequence, after which the DMC will 2152 * take care of turning CDCLK off/on as needed. 2153 */ 2154 void intel_cdclk_init_hw(struct drm_i915_private *i915) 2155 { 2156 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 2157 bxt_cdclk_init_hw(i915); 2158 else if (DISPLAY_VER(i915) == 9) 2159 skl_cdclk_init_hw(i915); 2160 } 2161 2162 /** 2163 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2164 * @i915: i915 device 2165 * 2166 * Uninitialize CDCLK. This is done only during the display core 2167 * uninitialization sequence. 2168 */ 2169 void intel_cdclk_uninit_hw(struct drm_i915_private *i915) 2170 { 2171 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) 2172 bxt_cdclk_uninit_hw(i915); 2173 else if (DISPLAY_VER(i915) == 9) 2174 skl_cdclk_uninit_hw(i915); 2175 } 2176 2177 static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915, 2178 const struct intel_cdclk_config *a, 2179 const struct intel_cdclk_config *b) 2180 { 2181 u16 old_waveform; 2182 u16 new_waveform; 2183 2184 drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); 2185 2186 if (a->vco == 0 || b->vco == 0) 2187 return false; 2188 2189 if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) 2190 return false; 2191 2192 old_waveform = cdclk_squash_waveform(i915, a->cdclk); 2193 new_waveform = cdclk_squash_waveform(i915, b->cdclk); 2194 2195 return a->vco != b->vco && 2196 old_waveform != new_waveform; 2197 } 2198 2199 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, 2200 const struct intel_cdclk_config *a, 2201 const struct intel_cdclk_config *b) 2202 { 2203 int a_div, b_div; 2204 2205 if (!HAS_CDCLK_CRAWL(dev_priv)) 2206 return false; 2207 2208 /* 2209 * The vco and cd2x divider will change independently 2210 * from each, so we disallow cd2x change when crawling. 2211 */ 2212 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2213 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2214 2215 return a->vco != 0 && b->vco != 0 && 2216 a->vco != b->vco && 2217 a_div == b_div && 2218 a->ref == b->ref; 2219 } 2220 2221 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, 2222 const struct intel_cdclk_config *a, 2223 const struct intel_cdclk_config *b) 2224 { 2225 /* 2226 * FIXME should store a bit more state in intel_cdclk_config 2227 * to differentiate squasher vs. cd2x divider properly. For 2228 * the moment all platforms with squasher use a fixed cd2x 2229 * divider. 2230 */ 2231 if (!HAS_CDCLK_SQUASH(dev_priv)) 2232 return false; 2233 2234 return a->cdclk != b->cdclk && 2235 a->vco != 0 && 2236 a->vco == b->vco && 2237 a->ref == b->ref; 2238 } 2239 2240 /** 2241 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK 2242 * configurations requires a modeset on all pipes 2243 * @a: first CDCLK configuration 2244 * @b: second CDCLK configuration 2245 * 2246 * Returns: 2247 * True if changing between the two CDCLK configurations 2248 * requires all pipes to be off, false if not. 2249 */ 2250 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, 2251 const struct intel_cdclk_config *b) 2252 { 2253 return a->cdclk != b->cdclk || 2254 a->vco != b->vco || 2255 a->ref != b->ref; 2256 } 2257 2258 /** 2259 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2260 * configurations requires only a cd2x divider update 2261 * @dev_priv: i915 device 2262 * @a: first CDCLK configuration 2263 * @b: second CDCLK configuration 2264 * 2265 * Returns: 2266 * True if changing between the two CDCLK configurations 2267 * can be done with just a cd2x divider update, false if not. 2268 */ 2269 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 2270 const struct intel_cdclk_config *a, 2271 const struct intel_cdclk_config *b) 2272 { 2273 /* Older hw doesn't have the capability */ 2274 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) 2275 return false; 2276 2277 /* 2278 * FIXME should store a bit more state in intel_cdclk_config 2279 * to differentiate squasher vs. cd2x divider properly. For 2280 * the moment all platforms with squasher use a fixed cd2x 2281 * divider. 2282 */ 2283 if (HAS_CDCLK_SQUASH(dev_priv)) 2284 return false; 2285 2286 return a->cdclk != b->cdclk && 2287 a->vco != 0 && 2288 a->vco == b->vco && 2289 a->ref == b->ref; 2290 } 2291 2292 /** 2293 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2294 * @a: first CDCLK configuration 2295 * @b: second CDCLK configuration 2296 * 2297 * Returns: 2298 * True if the CDCLK configurations don't match, false if they do. 2299 */ 2300 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2301 const struct intel_cdclk_config *b) 2302 { 2303 return intel_cdclk_needs_modeset(a, b) || 2304 a->voltage_level != b->voltage_level; 2305 } 2306 2307 void intel_cdclk_dump_config(struct drm_i915_private *i915, 2308 const struct intel_cdclk_config *cdclk_config, 2309 const char *context) 2310 { 2311 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2312 context, cdclk_config->cdclk, cdclk_config->vco, 2313 cdclk_config->ref, cdclk_config->bypass, 2314 cdclk_config->voltage_level); 2315 } 2316 2317 static void intel_pcode_notify(struct drm_i915_private *i915, 2318 u8 voltage_level, 2319 u8 active_pipe_count, 2320 u16 cdclk, 2321 bool cdclk_update_valid, 2322 bool pipe_count_update_valid) 2323 { 2324 int ret; 2325 u32 update_mask = 0; 2326 2327 if (!IS_DG2(i915)) 2328 return; 2329 2330 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2331 2332 if (cdclk_update_valid) 2333 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2334 2335 if (pipe_count_update_valid) 2336 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2337 2338 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL, 2339 SKL_CDCLK_PREPARE_FOR_CHANGE | 2340 update_mask, 2341 SKL_CDCLK_READY_FOR_CHANGE, 2342 SKL_CDCLK_READY_FOR_CHANGE, 3); 2343 if (ret) 2344 drm_err(&i915->drm, 2345 "Failed to inform PCU about display config (err %d)\n", 2346 ret); 2347 } 2348 2349 /** 2350 * intel_set_cdclk - Push the CDCLK configuration to the hardware 2351 * @dev_priv: i915 device 2352 * @cdclk_config: new CDCLK configuration 2353 * @pipe: pipe with which to synchronize the update 2354 * 2355 * Program the hardware based on the passed in CDCLK state, 2356 * if necessary. 2357 */ 2358 static void intel_set_cdclk(struct drm_i915_private *dev_priv, 2359 const struct intel_cdclk_config *cdclk_config, 2360 enum pipe pipe) 2361 { 2362 struct intel_encoder *encoder; 2363 2364 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) 2365 return; 2366 2367 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) 2368 return; 2369 2370 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); 2371 2372 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2373 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2374 2375 intel_psr_pause(intel_dp); 2376 } 2377 2378 intel_audio_cdclk_change_pre(dev_priv); 2379 2380 /* 2381 * Lock aux/gmbus while we change cdclk in case those 2382 * functions use cdclk. Not all platforms/ports do, 2383 * but we'll lock them all for simplicity. 2384 */ 2385 mutex_lock(&dev_priv->display.gmbus.mutex); 2386 for_each_intel_dp(&dev_priv->drm, encoder) { 2387 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2388 2389 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2390 &dev_priv->display.gmbus.mutex); 2391 } 2392 2393 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); 2394 2395 for_each_intel_dp(&dev_priv->drm, encoder) { 2396 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2397 2398 mutex_unlock(&intel_dp->aux.hw_mutex); 2399 } 2400 mutex_unlock(&dev_priv->display.gmbus.mutex); 2401 2402 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { 2403 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2404 2405 intel_psr_resume(intel_dp); 2406 } 2407 2408 intel_audio_cdclk_change_post(dev_priv); 2409 2410 if (drm_WARN(&dev_priv->drm, 2411 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), 2412 "cdclk state doesn't match!\n")) { 2413 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); 2414 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); 2415 } 2416 } 2417 2418 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2419 { 2420 struct drm_i915_private *i915 = to_i915(state->base.dev); 2421 const struct intel_cdclk_state *old_cdclk_state = 2422 intel_atomic_get_old_cdclk_state(state); 2423 const struct intel_cdclk_state *new_cdclk_state = 2424 intel_atomic_get_new_cdclk_state(state); 2425 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2426 bool change_cdclk, update_pipe_count; 2427 2428 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2429 &new_cdclk_state->actual) && 2430 new_cdclk_state->active_pipes == 2431 old_cdclk_state->active_pipes) 2432 return; 2433 2434 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2435 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2436 2437 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2438 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > 2439 hweight8(old_cdclk_state->active_pipes); 2440 2441 /* 2442 * According to "Sequence Before Frequency Change", 2443 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2444 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2445 * which basically means we choose the maximum of old and new CDCLK, if we know both 2446 */ 2447 if (change_cdclk) 2448 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2449 2450 /* 2451 * According to "Sequence For Pipe Count Change", 2452 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2453 * (power well is enabled) 2454 * no action if it is decreasing, before the change 2455 */ 2456 if (update_pipe_count) 2457 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2458 2459 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, 2460 change_cdclk, update_pipe_count); 2461 } 2462 2463 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2464 { 2465 struct drm_i915_private *i915 = to_i915(state->base.dev); 2466 const struct intel_cdclk_state *new_cdclk_state = 2467 intel_atomic_get_new_cdclk_state(state); 2468 const struct intel_cdclk_state *old_cdclk_state = 2469 intel_atomic_get_old_cdclk_state(state); 2470 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2471 bool update_cdclk, update_pipe_count; 2472 2473 /* According to "Sequence After Frequency Change", set voltage to used level */ 2474 voltage_level = new_cdclk_state->actual.voltage_level; 2475 2476 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2477 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < 2478 hweight8(old_cdclk_state->active_pipes); 2479 2480 /* 2481 * According to "Sequence After Frequency Change", 2482 * set bits 25:16 to current CDCLK 2483 */ 2484 if (update_cdclk) 2485 cdclk = new_cdclk_state->actual.cdclk; 2486 2487 /* 2488 * According to "Sequence For Pipe Count Change", 2489 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2490 * after the change(power well is disabled) 2491 * no action if it is increasing, after the change 2492 */ 2493 if (update_pipe_count) 2494 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2495 2496 intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, 2497 update_cdclk, update_pipe_count); 2498 } 2499 2500 /** 2501 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2502 * @state: intel atomic state 2503 * 2504 * Program the hardware before updating the HW plane state based on the 2505 * new CDCLK state, if necessary. 2506 */ 2507 void 2508 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2509 { 2510 struct drm_i915_private *i915 = to_i915(state->base.dev); 2511 const struct intel_cdclk_state *old_cdclk_state = 2512 intel_atomic_get_old_cdclk_state(state); 2513 const struct intel_cdclk_state *new_cdclk_state = 2514 intel_atomic_get_new_cdclk_state(state); 2515 enum pipe pipe = new_cdclk_state->pipe; 2516 2517 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2518 &new_cdclk_state->actual)) 2519 return; 2520 2521 if (IS_DG2(i915)) 2522 intel_cdclk_pcode_pre_notify(state); 2523 2524 if (pipe == INVALID_PIPE || 2525 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { 2526 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); 2527 2528 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe); 2529 } 2530 } 2531 2532 /** 2533 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2534 * @state: intel atomic state 2535 * 2536 * Program the hardware after updating the HW plane state based on the 2537 * new CDCLK state, if necessary. 2538 */ 2539 void 2540 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2541 { 2542 struct drm_i915_private *i915 = to_i915(state->base.dev); 2543 const struct intel_cdclk_state *old_cdclk_state = 2544 intel_atomic_get_old_cdclk_state(state); 2545 const struct intel_cdclk_state *new_cdclk_state = 2546 intel_atomic_get_new_cdclk_state(state); 2547 enum pipe pipe = new_cdclk_state->pipe; 2548 2549 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2550 &new_cdclk_state->actual)) 2551 return; 2552 2553 if (IS_DG2(i915)) 2554 intel_cdclk_pcode_post_notify(state); 2555 2556 if (pipe != INVALID_PIPE && 2557 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { 2558 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); 2559 2560 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe); 2561 } 2562 } 2563 2564 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2565 { 2566 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 2567 int pixel_rate = crtc_state->pixel_rate; 2568 2569 if (DISPLAY_VER(dev_priv) >= 10) 2570 return DIV_ROUND_UP(pixel_rate, 2); 2571 else if (DISPLAY_VER(dev_priv) == 9 || 2572 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2573 return pixel_rate; 2574 else if (IS_CHERRYVIEW(dev_priv)) 2575 return DIV_ROUND_UP(pixel_rate * 100, 95); 2576 else if (crtc_state->double_wide) 2577 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2578 else 2579 return DIV_ROUND_UP(pixel_rate * 100, 90); 2580 } 2581 2582 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2583 { 2584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2585 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2586 struct intel_plane *plane; 2587 int min_cdclk = 0; 2588 2589 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) 2590 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2591 2592 return min_cdclk; 2593 } 2594 2595 static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) 2596 { 2597 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2598 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2599 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 2600 int min_cdclk = 0; 2601 2602 /* 2603 * When we decide to use only one VDSC engine, since 2604 * each VDSC operates with 1 ppc throughput, pixel clock 2605 * cannot be higher than the VDSC clock (cdclk) 2606 * If there 2 VDSC engines, then pixel clock can't be higher than 2607 * VDSC clock(cdclk) * 2 and so on. 2608 */ 2609 min_cdclk = max_t(int, min_cdclk, 2610 DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances)); 2611 2612 if (crtc_state->bigjoiner_pipes) { 2613 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); 2614 2615 /* 2616 * According to Bigjoiner bw check: 2617 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock 2618 * 2619 * We have already computed compressed_bpp, so now compute the min CDCLK that 2620 * is required to support this compressed_bpp. 2621 * 2622 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) 2623 * 2624 * Since PPC = 2 with bigjoiner 2625 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits 2626 */ 2627 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; 2628 int min_cdclk_bj = 2629 (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) * 2630 pixel_clock) / (2 * bigjoiner_interface_bits); 2631 2632 min_cdclk = max(min_cdclk, min_cdclk_bj); 2633 } 2634 2635 return min_cdclk; 2636 } 2637 2638 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2639 { 2640 struct drm_i915_private *dev_priv = 2641 to_i915(crtc_state->uapi.crtc->dev); 2642 int min_cdclk; 2643 2644 if (!crtc_state->hw.enable) 2645 return 0; 2646 2647 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2648 2649 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2650 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2651 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2652 2653 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2654 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2655 * there may be audio corruption or screen corruption." This cdclk 2656 * restriction for GLK is 316.8 MHz. 2657 */ 2658 if (intel_crtc_has_dp_encoder(crtc_state) && 2659 crtc_state->has_audio && 2660 crtc_state->port_clock >= 540000 && 2661 crtc_state->lane_count == 4) { 2662 if (DISPLAY_VER(dev_priv) == 10) { 2663 /* Display WA #1145: glk */ 2664 min_cdclk = max(316800, min_cdclk); 2665 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { 2666 /* Display WA #1144: skl,bxt */ 2667 min_cdclk = max(432000, min_cdclk); 2668 } 2669 } 2670 2671 /* 2672 * According to BSpec, "The CD clock frequency must be at least twice 2673 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2674 */ 2675 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) 2676 min_cdclk = max(2 * 96000, min_cdclk); 2677 2678 /* 2679 * "For DP audio configuration, cdclk frequency shall be set to 2680 * meet the following requirements: 2681 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2682 * 270 | 320 or higher 2683 * 162 | 200 or higher" 2684 */ 2685 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2686 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2687 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2688 2689 /* 2690 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2691 * than 320000KHz. 2692 */ 2693 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2694 IS_VALLEYVIEW(dev_priv)) 2695 min_cdclk = max(320000, min_cdclk); 2696 2697 /* 2698 * On Geminilake once the CDCLK gets as low as 79200 2699 * picture gets unstable, despite that values are 2700 * correct for DSI PLL and DE PLL. 2701 */ 2702 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2703 IS_GEMINILAKE(dev_priv)) 2704 min_cdclk = max(158400, min_cdclk); 2705 2706 /* Account for additional needs from the planes */ 2707 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2708 2709 if (crtc_state->dsc.compression_enable) 2710 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2711 2712 /* 2713 * HACK. Currently for TGL/DG2 platforms we calculate 2714 * min_cdclk initially based on pixel_rate divided 2715 * by 2, accounting for also plane requirements, 2716 * however in some cases the lowest possible CDCLK 2717 * doesn't work and causing the underruns. 2718 * Explicitly stating here that this seems to be currently 2719 * rather a Hack, than final solution. 2720 */ 2721 if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) { 2722 /* 2723 * Clamp to max_cdclk_freq in case pixel rate is higher, 2724 * in order not to break an 8K, but still leave W/A at place. 2725 */ 2726 min_cdclk = max_t(int, min_cdclk, 2727 min_t(int, crtc_state->pixel_rate, 2728 dev_priv->display.cdclk.max_cdclk_freq)); 2729 } 2730 2731 return min_cdclk; 2732 } 2733 2734 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) 2735 { 2736 struct intel_atomic_state *state = cdclk_state->base.state; 2737 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2738 const struct intel_bw_state *bw_state; 2739 struct intel_crtc *crtc; 2740 struct intel_crtc_state *crtc_state; 2741 int min_cdclk, i; 2742 enum pipe pipe; 2743 2744 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2745 int ret; 2746 2747 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2748 if (min_cdclk < 0) 2749 return min_cdclk; 2750 2751 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2752 continue; 2753 2754 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2755 2756 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2757 if (ret) 2758 return ret; 2759 } 2760 2761 bw_state = intel_atomic_get_new_bw_state(state); 2762 if (bw_state) { 2763 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); 2764 2765 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2766 int ret; 2767 2768 cdclk_state->bw_min_cdclk = min_cdclk; 2769 2770 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2771 if (ret) 2772 return ret; 2773 } 2774 } 2775 2776 min_cdclk = max(cdclk_state->force_min_cdclk, 2777 cdclk_state->bw_min_cdclk); 2778 for_each_pipe(dev_priv, pipe) 2779 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2780 2781 /* 2782 * Avoid glk_force_audio_cdclk() causing excessive screen 2783 * blinking when multiple pipes are active by making sure 2784 * CDCLK frequency is always high enough for audio. With a 2785 * single active pipe we can always change CDCLK frequency 2786 * by changing the cd2x divider (see glk_cdclk_table[]) and 2787 * thus a full modeset won't be needed then. 2788 */ 2789 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && 2790 !is_power_of_2(cdclk_state->active_pipes)) 2791 min_cdclk = max(2 * 96000, min_cdclk); 2792 2793 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { 2794 drm_dbg_kms(&dev_priv->drm, 2795 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2796 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); 2797 return -EINVAL; 2798 } 2799 2800 return min_cdclk; 2801 } 2802 2803 /* 2804 * Account for port clock min voltage level requirements. 2805 * This only really does something on DISPLA_VER >= 11 but can be 2806 * called on earlier platforms as well. 2807 * 2808 * Note that this functions assumes that 0 is 2809 * the lowest voltage value, and higher values 2810 * correspond to increasingly higher voltages. 2811 * 2812 * Should that relationship no longer hold on 2813 * future platforms this code will need to be 2814 * adjusted. 2815 */ 2816 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) 2817 { 2818 struct intel_atomic_state *state = cdclk_state->base.state; 2819 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2820 struct intel_crtc *crtc; 2821 struct intel_crtc_state *crtc_state; 2822 u8 min_voltage_level; 2823 int i; 2824 enum pipe pipe; 2825 2826 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2827 int ret; 2828 2829 if (crtc_state->hw.enable) 2830 min_voltage_level = crtc_state->min_voltage_level; 2831 else 2832 min_voltage_level = 0; 2833 2834 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2835 continue; 2836 2837 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2838 2839 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2840 if (ret) 2841 return ret; 2842 } 2843 2844 min_voltage_level = 0; 2845 for_each_pipe(dev_priv, pipe) 2846 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2847 min_voltage_level); 2848 2849 return min_voltage_level; 2850 } 2851 2852 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2853 { 2854 struct intel_atomic_state *state = cdclk_state->base.state; 2855 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2856 int min_cdclk, cdclk; 2857 2858 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2859 if (min_cdclk < 0) 2860 return min_cdclk; 2861 2862 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); 2863 2864 cdclk_state->logical.cdclk = cdclk; 2865 cdclk_state->logical.voltage_level = 2866 vlv_calc_voltage_level(dev_priv, cdclk); 2867 2868 if (!cdclk_state->active_pipes) { 2869 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 2870 2871 cdclk_state->actual.cdclk = cdclk; 2872 cdclk_state->actual.voltage_level = 2873 vlv_calc_voltage_level(dev_priv, cdclk); 2874 } else { 2875 cdclk_state->actual = cdclk_state->logical; 2876 } 2877 2878 return 0; 2879 } 2880 2881 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2882 { 2883 int min_cdclk, cdclk; 2884 2885 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2886 if (min_cdclk < 0) 2887 return min_cdclk; 2888 2889 cdclk = bdw_calc_cdclk(min_cdclk); 2890 2891 cdclk_state->logical.cdclk = cdclk; 2892 cdclk_state->logical.voltage_level = 2893 bdw_calc_voltage_level(cdclk); 2894 2895 if (!cdclk_state->active_pipes) { 2896 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 2897 2898 cdclk_state->actual.cdclk = cdclk; 2899 cdclk_state->actual.voltage_level = 2900 bdw_calc_voltage_level(cdclk); 2901 } else { 2902 cdclk_state->actual = cdclk_state->logical; 2903 } 2904 2905 return 0; 2906 } 2907 2908 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) 2909 { 2910 struct intel_atomic_state *state = cdclk_state->base.state; 2911 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2912 struct intel_crtc *crtc; 2913 struct intel_crtc_state *crtc_state; 2914 int vco, i; 2915 2916 vco = cdclk_state->logical.vco; 2917 if (!vco) 2918 vco = dev_priv->skl_preferred_vco_freq; 2919 2920 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2921 if (!crtc_state->hw.enable) 2922 continue; 2923 2924 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 2925 continue; 2926 2927 /* 2928 * DPLL0 VCO may need to be adjusted to get the correct 2929 * clock for eDP. This will affect cdclk as well. 2930 */ 2931 switch (crtc_state->port_clock / 2) { 2932 case 108000: 2933 case 216000: 2934 vco = 8640000; 2935 break; 2936 default: 2937 vco = 8100000; 2938 break; 2939 } 2940 } 2941 2942 return vco; 2943 } 2944 2945 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2946 { 2947 int min_cdclk, cdclk, vco; 2948 2949 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2950 if (min_cdclk < 0) 2951 return min_cdclk; 2952 2953 vco = skl_dpll0_vco(cdclk_state); 2954 2955 cdclk = skl_calc_cdclk(min_cdclk, vco); 2956 2957 cdclk_state->logical.vco = vco; 2958 cdclk_state->logical.cdclk = cdclk; 2959 cdclk_state->logical.voltage_level = 2960 skl_calc_voltage_level(cdclk); 2961 2962 if (!cdclk_state->active_pipes) { 2963 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 2964 2965 cdclk_state->actual.vco = vco; 2966 cdclk_state->actual.cdclk = cdclk; 2967 cdclk_state->actual.voltage_level = 2968 skl_calc_voltage_level(cdclk); 2969 } else { 2970 cdclk_state->actual = cdclk_state->logical; 2971 } 2972 2973 return 0; 2974 } 2975 2976 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 2977 { 2978 struct intel_atomic_state *state = cdclk_state->base.state; 2979 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 2980 int min_cdclk, min_voltage_level, cdclk, vco; 2981 2982 min_cdclk = intel_compute_min_cdclk(cdclk_state); 2983 if (min_cdclk < 0) 2984 return min_cdclk; 2985 2986 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); 2987 if (min_voltage_level < 0) 2988 return min_voltage_level; 2989 2990 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); 2991 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 2992 2993 cdclk_state->logical.vco = vco; 2994 cdclk_state->logical.cdclk = cdclk; 2995 cdclk_state->logical.voltage_level = 2996 max_t(int, min_voltage_level, 2997 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); 2998 2999 if (!cdclk_state->active_pipes) { 3000 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); 3001 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); 3002 3003 cdclk_state->actual.vco = vco; 3004 cdclk_state->actual.cdclk = cdclk; 3005 cdclk_state->actual.voltage_level = 3006 intel_cdclk_calc_voltage_level(dev_priv, cdclk); 3007 } else { 3008 cdclk_state->actual = cdclk_state->logical; 3009 } 3010 3011 return 0; 3012 } 3013 3014 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 3015 { 3016 int min_cdclk; 3017 3018 /* 3019 * We can't change the cdclk frequency, but we still want to 3020 * check that the required minimum frequency doesn't exceed 3021 * the actual cdclk frequency. 3022 */ 3023 min_cdclk = intel_compute_min_cdclk(cdclk_state); 3024 if (min_cdclk < 0) 3025 return min_cdclk; 3026 3027 return 0; 3028 } 3029 3030 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3031 { 3032 struct intel_cdclk_state *cdclk_state; 3033 3034 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3035 if (!cdclk_state) 3036 return NULL; 3037 3038 cdclk_state->pipe = INVALID_PIPE; 3039 3040 return &cdclk_state->base; 3041 } 3042 3043 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3044 struct intel_global_state *state) 3045 { 3046 kfree(state); 3047 } 3048 3049 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3050 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3051 .atomic_destroy_state = intel_cdclk_destroy_state, 3052 }; 3053 3054 struct intel_cdclk_state * 3055 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3056 { 3057 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 3058 struct intel_global_state *cdclk_state; 3059 3060 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); 3061 if (IS_ERR(cdclk_state)) 3062 return ERR_CAST(cdclk_state); 3063 3064 return to_intel_cdclk_state(cdclk_state); 3065 } 3066 3067 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 3068 bool *need_cdclk_calc) 3069 { 3070 const struct intel_cdclk_state *old_cdclk_state; 3071 const struct intel_cdclk_state *new_cdclk_state; 3072 struct intel_plane_state __maybe_unused *plane_state; 3073 struct intel_plane *plane; 3074 int ret; 3075 int i; 3076 3077 /* 3078 * active_planes bitmask has been updated, and potentially affected 3079 * planes are part of the state. We can now compute the minimum cdclk 3080 * for each plane. 3081 */ 3082 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 3083 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 3084 if (ret) 3085 return ret; 3086 } 3087 3088 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 3089 if (ret) 3090 return ret; 3091 3092 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3093 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3094 3095 if (new_cdclk_state && 3096 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 3097 *need_cdclk_calc = true; 3098 3099 return 0; 3100 } 3101 3102 int intel_cdclk_init(struct drm_i915_private *dev_priv) 3103 { 3104 struct intel_cdclk_state *cdclk_state; 3105 3106 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 3107 if (!cdclk_state) 3108 return -ENOMEM; 3109 3110 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, 3111 &cdclk_state->base, &intel_cdclk_funcs); 3112 3113 return 0; 3114 } 3115 3116 static bool intel_cdclk_need_serialize(struct drm_i915_private *i915, 3117 const struct intel_cdclk_state *old_cdclk_state, 3118 const struct intel_cdclk_state *new_cdclk_state) 3119 { 3120 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != 3121 hweight8(new_cdclk_state->active_pipes); 3122 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, 3123 &new_cdclk_state->actual); 3124 /* 3125 * We need to poke hw for gen >= 12, because we notify PCode if 3126 * pipe power well count changes. 3127 */ 3128 return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed); 3129 } 3130 3131 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3132 { 3133 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 3134 const struct intel_cdclk_state *old_cdclk_state; 3135 struct intel_cdclk_state *new_cdclk_state; 3136 enum pipe pipe = INVALID_PIPE; 3137 int ret; 3138 3139 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3140 if (IS_ERR(new_cdclk_state)) 3141 return PTR_ERR(new_cdclk_state); 3142 3143 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3144 3145 new_cdclk_state->active_pipes = 3146 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3147 3148 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); 3149 if (ret) 3150 return ret; 3151 3152 if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) { 3153 /* 3154 * Also serialize commits across all crtcs 3155 * if the actual hw needs to be poked. 3156 */ 3157 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3158 if (ret) 3159 return ret; 3160 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 3161 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 3162 intel_cdclk_changed(&old_cdclk_state->logical, 3163 &new_cdclk_state->logical)) { 3164 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3165 if (ret) 3166 return ret; 3167 } else { 3168 return 0; 3169 } 3170 3171 if (is_power_of_2(new_cdclk_state->active_pipes) && 3172 intel_cdclk_can_cd2x_update(dev_priv, 3173 &old_cdclk_state->actual, 3174 &new_cdclk_state->actual)) { 3175 struct intel_crtc *crtc; 3176 struct intel_crtc_state *crtc_state; 3177 3178 pipe = ilog2(new_cdclk_state->active_pipes); 3179 crtc = intel_crtc_for_pipe(dev_priv, pipe); 3180 3181 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3182 if (IS_ERR(crtc_state)) 3183 return PTR_ERR(crtc_state); 3184 3185 if (intel_crtc_needs_modeset(crtc_state)) 3186 pipe = INVALID_PIPE; 3187 } 3188 3189 if (intel_cdclk_can_crawl_and_squash(dev_priv, 3190 &old_cdclk_state->actual, 3191 &new_cdclk_state->actual)) { 3192 drm_dbg_kms(&dev_priv->drm, 3193 "Can change cdclk via crawling and squashing\n"); 3194 } else if (intel_cdclk_can_squash(dev_priv, 3195 &old_cdclk_state->actual, 3196 &new_cdclk_state->actual)) { 3197 drm_dbg_kms(&dev_priv->drm, 3198 "Can change cdclk via squashing\n"); 3199 } else if (intel_cdclk_can_crawl(dev_priv, 3200 &old_cdclk_state->actual, 3201 &new_cdclk_state->actual)) { 3202 drm_dbg_kms(&dev_priv->drm, 3203 "Can change cdclk via crawling\n"); 3204 } else if (pipe != INVALID_PIPE) { 3205 new_cdclk_state->pipe = pipe; 3206 3207 drm_dbg_kms(&dev_priv->drm, 3208 "Can change cdclk cd2x divider with pipe %c active\n", 3209 pipe_name(pipe)); 3210 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, 3211 &new_cdclk_state->actual)) { 3212 /* All pipes must be switched off while we change the cdclk. */ 3213 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3214 if (ret) 3215 return ret; 3216 3217 drm_dbg_kms(&dev_priv->drm, 3218 "Modeset required for cdclk change\n"); 3219 } 3220 3221 drm_dbg_kms(&dev_priv->drm, 3222 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3223 new_cdclk_state->logical.cdclk, 3224 new_cdclk_state->actual.cdclk); 3225 drm_dbg_kms(&dev_priv->drm, 3226 "New voltage level calculated to be logical %u, actual %u\n", 3227 new_cdclk_state->logical.voltage_level, 3228 new_cdclk_state->actual.voltage_level); 3229 3230 return 0; 3231 } 3232 3233 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) 3234 { 3235 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; 3236 3237 if (DISPLAY_VER(dev_priv) >= 10) 3238 return 2 * max_cdclk_freq; 3239 else if (DISPLAY_VER(dev_priv) == 9 || 3240 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3241 return max_cdclk_freq; 3242 else if (IS_CHERRYVIEW(dev_priv)) 3243 return max_cdclk_freq*95/100; 3244 else if (DISPLAY_VER(dev_priv) < 4) 3245 return 2*max_cdclk_freq*90/100; 3246 else 3247 return max_cdclk_freq*90/100; 3248 } 3249 3250 /** 3251 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3252 * @dev_priv: i915 device 3253 * 3254 * Determine the maximum CDCLK frequency the platform supports, and also 3255 * derive the maximum dot clock frequency the maximum CDCLK frequency 3256 * allows. 3257 */ 3258 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 3259 { 3260 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 3261 if (dev_priv->display.cdclk.hw.ref == 24000) 3262 dev_priv->display.cdclk.max_cdclk_freq = 552000; 3263 else 3264 dev_priv->display.cdclk.max_cdclk_freq = 556800; 3265 } else if (DISPLAY_VER(dev_priv) >= 11) { 3266 if (dev_priv->display.cdclk.hw.ref == 24000) 3267 dev_priv->display.cdclk.max_cdclk_freq = 648000; 3268 else 3269 dev_priv->display.cdclk.max_cdclk_freq = 652800; 3270 } else if (IS_GEMINILAKE(dev_priv)) { 3271 dev_priv->display.cdclk.max_cdclk_freq = 316800; 3272 } else if (IS_BROXTON(dev_priv)) { 3273 dev_priv->display.cdclk.max_cdclk_freq = 624000; 3274 } else if (DISPLAY_VER(dev_priv) == 9) { 3275 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3276 int max_cdclk, vco; 3277 3278 vco = dev_priv->skl_preferred_vco_freq; 3279 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); 3280 3281 /* 3282 * Use the lower (vco 8640) cdclk values as a 3283 * first guess. skl_calc_cdclk() will correct it 3284 * if the preferred vco is 8100 instead. 3285 */ 3286 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3287 max_cdclk = 617143; 3288 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3289 max_cdclk = 540000; 3290 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3291 max_cdclk = 432000; 3292 else 3293 max_cdclk = 308571; 3294 3295 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3296 } else if (IS_BROADWELL(dev_priv)) { 3297 /* 3298 * FIXME with extra cooling we can allow 3299 * 540 MHz for ULX and 675 Mhz for ULT. 3300 * How can we know if extra cooling is 3301 * available? PCI ID, VTB, something else? 3302 */ 3303 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3304 dev_priv->display.cdclk.max_cdclk_freq = 450000; 3305 else if (IS_BROADWELL_ULX(dev_priv)) 3306 dev_priv->display.cdclk.max_cdclk_freq = 450000; 3307 else if (IS_BROADWELL_ULT(dev_priv)) 3308 dev_priv->display.cdclk.max_cdclk_freq = 540000; 3309 else 3310 dev_priv->display.cdclk.max_cdclk_freq = 675000; 3311 } else if (IS_CHERRYVIEW(dev_priv)) { 3312 dev_priv->display.cdclk.max_cdclk_freq = 320000; 3313 } else if (IS_VALLEYVIEW(dev_priv)) { 3314 dev_priv->display.cdclk.max_cdclk_freq = 400000; 3315 } else { 3316 /* otherwise assume cdclk is fixed */ 3317 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; 3318 } 3319 3320 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); 3321 3322 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", 3323 dev_priv->display.cdclk.max_cdclk_freq); 3324 3325 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", 3326 dev_priv->max_dotclk_freq); 3327 } 3328 3329 /** 3330 * intel_update_cdclk - Determine the current CDCLK frequency 3331 * @dev_priv: i915 device 3332 * 3333 * Determine the current CDCLK frequency. 3334 */ 3335 void intel_update_cdclk(struct drm_i915_private *dev_priv) 3336 { 3337 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); 3338 3339 /* 3340 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3341 * Programmng [sic] note: bit[9:2] should be programmed to the number 3342 * of cdclk that generates 4MHz reference clock freq which is used to 3343 * generate GMBus clock. This will vary with the cdclk freq. 3344 */ 3345 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3346 intel_de_write(dev_priv, GMBUSFREQ_VLV, 3347 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); 3348 } 3349 3350 static int dg1_rawclk(struct drm_i915_private *dev_priv) 3351 { 3352 /* 3353 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3354 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3355 */ 3356 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, 3357 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3358 3359 return 38400; 3360 } 3361 3362 static int cnp_rawclk(struct drm_i915_private *dev_priv) 3363 { 3364 u32 rawclk; 3365 int divider, fraction; 3366 3367 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3368 /* 24 MHz */ 3369 divider = 24000; 3370 fraction = 0; 3371 } else { 3372 /* 19.2 MHz */ 3373 divider = 19000; 3374 fraction = 200; 3375 } 3376 3377 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3378 if (fraction) { 3379 int numerator = 1; 3380 3381 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3382 fraction) - 1); 3383 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3384 rawclk |= ICP_RAWCLK_NUM(numerator); 3385 } 3386 3387 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); 3388 return divider + fraction; 3389 } 3390 3391 static int pch_rawclk(struct drm_i915_private *dev_priv) 3392 { 3393 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3394 } 3395 3396 static int vlv_hrawclk(struct drm_i915_private *dev_priv) 3397 { 3398 /* RAWCLK_FREQ_VLV register updated from power well code */ 3399 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 3400 CCK_DISPLAY_REF_CLOCK_CONTROL); 3401 } 3402 3403 static int i9xx_hrawclk(struct drm_i915_private *dev_priv) 3404 { 3405 u32 clkcfg; 3406 3407 /* 3408 * hrawclock is 1/4 the FSB frequency 3409 * 3410 * Note that this only reads the state of the FSB 3411 * straps, not the actual FSB frequency. Some BIOSen 3412 * let you configure each independently. Ideally we'd 3413 * read out the actual FSB frequency but sadly we 3414 * don't know which registers have that information, 3415 * and all the relevant docs have gone to bit heaven :( 3416 */ 3417 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; 3418 3419 if (IS_MOBILE(dev_priv)) { 3420 switch (clkcfg) { 3421 case CLKCFG_FSB_400: 3422 return 100000; 3423 case CLKCFG_FSB_533: 3424 return 133333; 3425 case CLKCFG_FSB_667: 3426 return 166667; 3427 case CLKCFG_FSB_800: 3428 return 200000; 3429 case CLKCFG_FSB_1067: 3430 return 266667; 3431 case CLKCFG_FSB_1333: 3432 return 333333; 3433 default: 3434 MISSING_CASE(clkcfg); 3435 return 133333; 3436 } 3437 } else { 3438 switch (clkcfg) { 3439 case CLKCFG_FSB_400_ALT: 3440 return 100000; 3441 case CLKCFG_FSB_533: 3442 return 133333; 3443 case CLKCFG_FSB_667: 3444 return 166667; 3445 case CLKCFG_FSB_800: 3446 return 200000; 3447 case CLKCFG_FSB_1067_ALT: 3448 return 266667; 3449 case CLKCFG_FSB_1333_ALT: 3450 return 333333; 3451 case CLKCFG_FSB_1600_ALT: 3452 return 400000; 3453 default: 3454 return 133333; 3455 } 3456 } 3457 } 3458 3459 /** 3460 * intel_read_rawclk - Determine the current RAWCLK frequency 3461 * @dev_priv: i915 device 3462 * 3463 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3464 * frequency clock so this needs to done only once. 3465 */ 3466 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 3467 { 3468 u32 freq; 3469 3470 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3471 freq = dg1_rawclk(dev_priv); 3472 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) 3473 /* 3474 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3475 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3476 * not need to be programmed." 3477 */ 3478 freq = 38400; 3479 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3480 freq = cnp_rawclk(dev_priv); 3481 else if (HAS_PCH_SPLIT(dev_priv)) 3482 freq = pch_rawclk(dev_priv); 3483 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3484 freq = vlv_hrawclk(dev_priv); 3485 else if (DISPLAY_VER(dev_priv) >= 3) 3486 freq = i9xx_hrawclk(dev_priv); 3487 else 3488 /* no rawclk on other platforms, or no need to know it */ 3489 return 0; 3490 3491 return freq; 3492 } 3493 3494 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3495 { 3496 struct drm_i915_private *i915 = m->private; 3497 3498 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); 3499 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); 3500 seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); 3501 3502 return 0; 3503 } 3504 3505 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3506 3507 void intel_cdclk_debugfs_register(struct drm_i915_private *i915) 3508 { 3509 struct drm_minor *minor = i915->drm.primary; 3510 3511 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, 3512 i915, &i915_cdclk_info_fops); 3513 } 3514 3515 static const struct intel_cdclk_funcs mtl_cdclk_funcs = { 3516 .get_cdclk = bxt_get_cdclk, 3517 .set_cdclk = bxt_set_cdclk, 3518 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3519 .calc_voltage_level = rplu_calc_voltage_level, 3520 }; 3521 3522 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3523 .get_cdclk = bxt_get_cdclk, 3524 .set_cdclk = bxt_set_cdclk, 3525 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3526 .calc_voltage_level = rplu_calc_voltage_level, 3527 }; 3528 3529 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3530 .get_cdclk = bxt_get_cdclk, 3531 .set_cdclk = bxt_set_cdclk, 3532 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3533 .calc_voltage_level = tgl_calc_voltage_level, 3534 }; 3535 3536 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3537 .get_cdclk = bxt_get_cdclk, 3538 .set_cdclk = bxt_set_cdclk, 3539 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3540 .calc_voltage_level = ehl_calc_voltage_level, 3541 }; 3542 3543 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3544 .get_cdclk = bxt_get_cdclk, 3545 .set_cdclk = bxt_set_cdclk, 3546 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3547 .calc_voltage_level = icl_calc_voltage_level, 3548 }; 3549 3550 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3551 .get_cdclk = bxt_get_cdclk, 3552 .set_cdclk = bxt_set_cdclk, 3553 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3554 .calc_voltage_level = bxt_calc_voltage_level, 3555 }; 3556 3557 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3558 .get_cdclk = skl_get_cdclk, 3559 .set_cdclk = skl_set_cdclk, 3560 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3561 }; 3562 3563 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3564 .get_cdclk = bdw_get_cdclk, 3565 .set_cdclk = bdw_set_cdclk, 3566 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3567 }; 3568 3569 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3570 .get_cdclk = vlv_get_cdclk, 3571 .set_cdclk = chv_set_cdclk, 3572 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3573 }; 3574 3575 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3576 .get_cdclk = vlv_get_cdclk, 3577 .set_cdclk = vlv_set_cdclk, 3578 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3579 }; 3580 3581 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3582 .get_cdclk = hsw_get_cdclk, 3583 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3584 }; 3585 3586 /* SNB, IVB, 965G, 945G */ 3587 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3588 .get_cdclk = fixed_400mhz_get_cdclk, 3589 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3590 }; 3591 3592 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3593 .get_cdclk = fixed_450mhz_get_cdclk, 3594 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3595 }; 3596 3597 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3598 .get_cdclk = gm45_get_cdclk, 3599 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3600 }; 3601 3602 /* G45 uses G33 */ 3603 3604 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3605 .get_cdclk = i965gm_get_cdclk, 3606 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3607 }; 3608 3609 /* i965G uses fixed 400 */ 3610 3611 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3612 .get_cdclk = pnv_get_cdclk, 3613 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3614 }; 3615 3616 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3617 .get_cdclk = g33_get_cdclk, 3618 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3619 }; 3620 3621 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3622 .get_cdclk = i945gm_get_cdclk, 3623 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3624 }; 3625 3626 /* i945G uses fixed 400 */ 3627 3628 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3629 .get_cdclk = i915gm_get_cdclk, 3630 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3631 }; 3632 3633 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3634 .get_cdclk = fixed_333mhz_get_cdclk, 3635 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3636 }; 3637 3638 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3639 .get_cdclk = fixed_266mhz_get_cdclk, 3640 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3641 }; 3642 3643 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3644 .get_cdclk = i85x_get_cdclk, 3645 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3646 }; 3647 3648 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3649 .get_cdclk = fixed_200mhz_get_cdclk, 3650 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3651 }; 3652 3653 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3654 .get_cdclk = fixed_133mhz_get_cdclk, 3655 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3656 }; 3657 3658 /** 3659 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3660 * @dev_priv: i915 device 3661 */ 3662 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 3663 { 3664 if (DISPLAY_VER(dev_priv) >= 20) { 3665 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; 3666 dev_priv->display.cdclk.table = lnl_cdclk_table; 3667 } else if (DISPLAY_VER(dev_priv) >= 14) { 3668 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; 3669 dev_priv->display.cdclk.table = mtl_cdclk_table; 3670 } else if (IS_DG2(dev_priv)) { 3671 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3672 dev_priv->display.cdclk.table = dg2_cdclk_table; 3673 } else if (IS_ALDERLAKE_P(dev_priv)) { 3674 /* Wa_22011320316:adl-p[a0] */ 3675 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 3676 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; 3677 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3678 } else if (IS_RAPTORLAKE_U(dev_priv)) { 3679 dev_priv->display.cdclk.table = rplu_cdclk_table; 3680 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; 3681 } else { 3682 dev_priv->display.cdclk.table = adlp_cdclk_table; 3683 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3684 } 3685 } else if (IS_ROCKETLAKE(dev_priv)) { 3686 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3687 dev_priv->display.cdclk.table = rkl_cdclk_table; 3688 } else if (DISPLAY_VER(dev_priv) >= 12) { 3689 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; 3690 dev_priv->display.cdclk.table = icl_cdclk_table; 3691 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 3692 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; 3693 dev_priv->display.cdclk.table = icl_cdclk_table; 3694 } else if (DISPLAY_VER(dev_priv) >= 11) { 3695 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; 3696 dev_priv->display.cdclk.table = icl_cdclk_table; 3697 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 3698 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; 3699 if (IS_GEMINILAKE(dev_priv)) 3700 dev_priv->display.cdclk.table = glk_cdclk_table; 3701 else 3702 dev_priv->display.cdclk.table = bxt_cdclk_table; 3703 } else if (DISPLAY_VER(dev_priv) == 9) { 3704 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; 3705 } else if (IS_BROADWELL(dev_priv)) { 3706 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; 3707 } else if (IS_HASWELL(dev_priv)) { 3708 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; 3709 } else if (IS_CHERRYVIEW(dev_priv)) { 3710 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; 3711 } else if (IS_VALLEYVIEW(dev_priv)) { 3712 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; 3713 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 3714 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3715 } else if (IS_IRONLAKE(dev_priv)) { 3716 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; 3717 } else if (IS_GM45(dev_priv)) { 3718 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; 3719 } else if (IS_G45(dev_priv)) { 3720 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3721 } else if (IS_I965GM(dev_priv)) { 3722 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; 3723 } else if (IS_I965G(dev_priv)) { 3724 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3725 } else if (IS_PINEVIEW(dev_priv)) { 3726 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; 3727 } else if (IS_G33(dev_priv)) { 3728 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; 3729 } else if (IS_I945GM(dev_priv)) { 3730 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; 3731 } else if (IS_I945G(dev_priv)) { 3732 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3733 } else if (IS_I915GM(dev_priv)) { 3734 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; 3735 } else if (IS_I915G(dev_priv)) { 3736 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; 3737 } else if (IS_I865G(dev_priv)) { 3738 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; 3739 } else if (IS_I85X(dev_priv)) { 3740 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; 3741 } else if (IS_I845G(dev_priv)) { 3742 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; 3743 } else if (IS_I830(dev_priv)) { 3744 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3745 } 3746 3747 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, 3748 "Unknown platform. Assuming i830\n")) 3749 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; 3750 } 3751