1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/time.h> 26 27 #include <drm/drm_fixed.h> 28 29 #include "soc/intel_dram.h" 30 31 #include "hsw_ips.h" 32 #include "i915_reg.h" 33 #include "intel_atomic.h" 34 #include "intel_atomic_plane.h" 35 #include "intel_audio.h" 36 #include "intel_bw.h" 37 #include "intel_cdclk.h" 38 #include "intel_crtc.h" 39 #include "intel_de.h" 40 #include "intel_dp.h" 41 #include "intel_display_types.h" 42 #include "intel_mchbar_regs.h" 43 #include "intel_pci_config.h" 44 #include "intel_pcode.h" 45 #include "intel_psr.h" 46 #include "intel_vdsc.h" 47 #include "skl_watermark.h" 48 #include "skl_watermark_regs.h" 49 #include "vlv_sideband.h" 50 51 /** 52 * DOC: CDCLK / RAWCLK 53 * 54 * The display engine uses several different clocks to do its work. There 55 * are two main clocks involved that aren't directly related to the actual 56 * pixel clock or any symbol/bit clock of the actual output port. These 57 * are the core display clock (CDCLK) and RAWCLK. 58 * 59 * CDCLK clocks most of the display pipe logic, and thus its frequency 60 * must be high enough to support the rate at which pixels are flowing 61 * through the pipes. Downscaling must also be accounted as that increases 62 * the effective pixel rate. 63 * 64 * On several platforms the CDCLK frequency can be changed dynamically 65 * to minimize power consumption for a given display configuration. 66 * Typically changes to the CDCLK frequency require all the display pipes 67 * to be shut down while the frequency is being changed. 68 * 69 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 70 * DMC will not change the active CDCLK frequency however, so that part 71 * will still be performed by the driver directly. 72 * 73 * There are multiple components involved in the generation of the CDCLK 74 * frequency: 75 * 76 * - We have the CDCLK PLL, which generates an output clock based on a 77 * reference clock and a ratio parameter. 78 * - The CD2X Divider, which divides the output of the PLL based on a 79 * divisor selected from a set of pre-defined choices. 80 * - The CD2X Squasher, which further divides the output based on a 81 * waveform represented as a sequence of bits where each zero 82 * "squashes out" a clock cycle. 83 * - And, finally, a fixed divider that divides the output frequency by 2. 84 * 85 * As such, the resulting CDCLK frequency can be calculated with the 86 * following formula: 87 * 88 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 89 * 90 * , where vco is the frequency generated by the PLL; cd2x_div 91 * represents the CD2X Divider; sq_len and sq_div are the bit length 92 * and the number of high bits for the CD2X Squasher waveform, respectively; 93 * and 2 represents the fixed divider. 94 * 95 * Note that some older platforms do not contain the CD2X Divider 96 * and/or CD2X Squasher, in which case we can ignore their respective 97 * factors in the formula above. 98 * 99 * Several methods exist to change the CDCLK frequency, which ones are 100 * supported depends on the platform: 101 * 102 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 103 * - CD2X divider update. Single pipe can be active as the divider update 104 * can be synchronized with the pipe's start of vblank. 105 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 106 * - Squash waveform update. Pipes can be active. 107 * - Crawl and squash can also be done back to back. Pipes can be active. 108 * 109 * RAWCLK is a fixed frequency clock, often used by various auxiliary 110 * blocks such as AUX CH or backlight PWM. Hence the only thing we 111 * really need to know about RAWCLK is its frequency so that various 112 * dividers can be programmed correctly. 113 */ 114 115 struct intel_cdclk_funcs { 116 void (*get_cdclk)(struct intel_display *display, 117 struct intel_cdclk_config *cdclk_config); 118 void (*set_cdclk)(struct intel_display *display, 119 const struct intel_cdclk_config *cdclk_config, 120 enum pipe pipe); 121 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 122 u8 (*calc_voltage_level)(int cdclk); 123 }; 124 125 void intel_cdclk_get_cdclk(struct intel_display *display, 126 struct intel_cdclk_config *cdclk_config) 127 { 128 display->funcs.cdclk->get_cdclk(display, cdclk_config); 129 } 130 131 static void intel_cdclk_set_cdclk(struct intel_display *display, 132 const struct intel_cdclk_config *cdclk_config, 133 enum pipe pipe) 134 { 135 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); 136 } 137 138 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 139 { 140 struct intel_display *display = to_intel_display(state); 141 142 return display->funcs.cdclk->modeset_calc_cdclk(state); 143 } 144 145 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, 146 int cdclk) 147 { 148 return display->funcs.cdclk->calc_voltage_level(cdclk); 149 } 150 151 static void fixed_133mhz_get_cdclk(struct intel_display *display, 152 struct intel_cdclk_config *cdclk_config) 153 { 154 cdclk_config->cdclk = 133333; 155 } 156 157 static void fixed_200mhz_get_cdclk(struct intel_display *display, 158 struct intel_cdclk_config *cdclk_config) 159 { 160 cdclk_config->cdclk = 200000; 161 } 162 163 static void fixed_266mhz_get_cdclk(struct intel_display *display, 164 struct intel_cdclk_config *cdclk_config) 165 { 166 cdclk_config->cdclk = 266667; 167 } 168 169 static void fixed_333mhz_get_cdclk(struct intel_display *display, 170 struct intel_cdclk_config *cdclk_config) 171 { 172 cdclk_config->cdclk = 333333; 173 } 174 175 static void fixed_400mhz_get_cdclk(struct intel_display *display, 176 struct intel_cdclk_config *cdclk_config) 177 { 178 cdclk_config->cdclk = 400000; 179 } 180 181 static void fixed_450mhz_get_cdclk(struct intel_display *display, 182 struct intel_cdclk_config *cdclk_config) 183 { 184 cdclk_config->cdclk = 450000; 185 } 186 187 static void i85x_get_cdclk(struct intel_display *display, 188 struct intel_cdclk_config *cdclk_config) 189 { 190 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 191 u16 hpllcc = 0; 192 193 /* 194 * 852GM/852GMV only supports 133 MHz and the HPLLCC 195 * encoding is different :( 196 * FIXME is this the right way to detect 852GM/852GMV? 197 */ 198 if (pdev->revision == 0x1) { 199 cdclk_config->cdclk = 133333; 200 return; 201 } 202 203 pci_bus_read_config_word(pdev->bus, 204 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 205 206 /* Assume that the hardware is in the high speed state. This 207 * should be the default. 208 */ 209 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 210 case GC_CLOCK_133_200: 211 case GC_CLOCK_133_200_2: 212 case GC_CLOCK_100_200: 213 cdclk_config->cdclk = 200000; 214 break; 215 case GC_CLOCK_166_250: 216 cdclk_config->cdclk = 250000; 217 break; 218 case GC_CLOCK_100_133: 219 cdclk_config->cdclk = 133333; 220 break; 221 case GC_CLOCK_133_266: 222 case GC_CLOCK_133_266_2: 223 case GC_CLOCK_166_266: 224 cdclk_config->cdclk = 266667; 225 break; 226 } 227 } 228 229 static void i915gm_get_cdclk(struct intel_display *display, 230 struct intel_cdclk_config *cdclk_config) 231 { 232 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 233 u16 gcfgc = 0; 234 235 pci_read_config_word(pdev, GCFGC, &gcfgc); 236 237 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 238 cdclk_config->cdclk = 133333; 239 return; 240 } 241 242 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 243 case GC_DISPLAY_CLOCK_333_320_MHZ: 244 cdclk_config->cdclk = 333333; 245 break; 246 default: 247 case GC_DISPLAY_CLOCK_190_200_MHZ: 248 cdclk_config->cdclk = 190000; 249 break; 250 } 251 } 252 253 static void i945gm_get_cdclk(struct intel_display *display, 254 struct intel_cdclk_config *cdclk_config) 255 { 256 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 257 u16 gcfgc = 0; 258 259 pci_read_config_word(pdev, GCFGC, &gcfgc); 260 261 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 262 cdclk_config->cdclk = 133333; 263 return; 264 } 265 266 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 267 case GC_DISPLAY_CLOCK_333_320_MHZ: 268 cdclk_config->cdclk = 320000; 269 break; 270 default: 271 case GC_DISPLAY_CLOCK_190_200_MHZ: 272 cdclk_config->cdclk = 200000; 273 break; 274 } 275 } 276 277 static unsigned int intel_hpll_vco(struct intel_display *display) 278 { 279 static const unsigned int blb_vco[8] = { 280 [0] = 3200000, 281 [1] = 4000000, 282 [2] = 5333333, 283 [3] = 4800000, 284 [4] = 6400000, 285 }; 286 static const unsigned int pnv_vco[8] = { 287 [0] = 3200000, 288 [1] = 4000000, 289 [2] = 5333333, 290 [3] = 4800000, 291 [4] = 2666667, 292 }; 293 static const unsigned int cl_vco[8] = { 294 [0] = 3200000, 295 [1] = 4000000, 296 [2] = 5333333, 297 [3] = 6400000, 298 [4] = 3333333, 299 [5] = 3566667, 300 [6] = 4266667, 301 }; 302 static const unsigned int elk_vco[8] = { 303 [0] = 3200000, 304 [1] = 4000000, 305 [2] = 5333333, 306 [3] = 4800000, 307 }; 308 static const unsigned int ctg_vco[8] = { 309 [0] = 3200000, 310 [1] = 4000000, 311 [2] = 5333333, 312 [3] = 6400000, 313 [4] = 2666667, 314 [5] = 4266667, 315 }; 316 struct drm_i915_private *dev_priv = to_i915(display->drm); 317 const unsigned int *vco_table; 318 unsigned int vco; 319 u8 tmp = 0; 320 321 /* FIXME other chipsets? */ 322 if (IS_GM45(dev_priv)) 323 vco_table = ctg_vco; 324 else if (IS_G45(dev_priv)) 325 vco_table = elk_vco; 326 else if (IS_I965GM(dev_priv)) 327 vco_table = cl_vco; 328 else if (IS_PINEVIEW(dev_priv)) 329 vco_table = pnv_vco; 330 else if (IS_G33(dev_priv)) 331 vco_table = blb_vco; 332 else 333 return 0; 334 335 tmp = intel_de_read(display, 336 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); 337 338 vco = vco_table[tmp & 0x7]; 339 if (vco == 0) 340 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 341 tmp); 342 else 343 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); 344 345 return vco; 346 } 347 348 static void g33_get_cdclk(struct intel_display *display, 349 struct intel_cdclk_config *cdclk_config) 350 { 351 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 352 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 353 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 354 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 355 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 356 const u8 *div_table; 357 unsigned int cdclk_sel; 358 u16 tmp = 0; 359 360 cdclk_config->vco = intel_hpll_vco(display); 361 362 pci_read_config_word(pdev, GCFGC, &tmp); 363 364 cdclk_sel = (tmp >> 4) & 0x7; 365 366 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 367 goto fail; 368 369 switch (cdclk_config->vco) { 370 case 3200000: 371 div_table = div_3200; 372 break; 373 case 4000000: 374 div_table = div_4000; 375 break; 376 case 4800000: 377 div_table = div_4800; 378 break; 379 case 5333333: 380 div_table = div_5333; 381 break; 382 default: 383 goto fail; 384 } 385 386 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 387 div_table[cdclk_sel]); 388 return; 389 390 fail: 391 drm_err(display->drm, 392 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 393 cdclk_config->vco, tmp); 394 cdclk_config->cdclk = 190476; 395 } 396 397 static void pnv_get_cdclk(struct intel_display *display, 398 struct intel_cdclk_config *cdclk_config) 399 { 400 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 401 u16 gcfgc = 0; 402 403 pci_read_config_word(pdev, GCFGC, &gcfgc); 404 405 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 406 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 407 cdclk_config->cdclk = 266667; 408 break; 409 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 410 cdclk_config->cdclk = 333333; 411 break; 412 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 413 cdclk_config->cdclk = 444444; 414 break; 415 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 416 cdclk_config->cdclk = 200000; 417 break; 418 default: 419 drm_err(display->drm, 420 "Unknown pnv display core clock 0x%04x\n", gcfgc); 421 fallthrough; 422 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 423 cdclk_config->cdclk = 133333; 424 break; 425 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 426 cdclk_config->cdclk = 166667; 427 break; 428 } 429 } 430 431 static void i965gm_get_cdclk(struct intel_display *display, 432 struct intel_cdclk_config *cdclk_config) 433 { 434 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 435 static const u8 div_3200[] = { 16, 10, 8 }; 436 static const u8 div_4000[] = { 20, 12, 10 }; 437 static const u8 div_5333[] = { 24, 16, 14 }; 438 const u8 *div_table; 439 unsigned int cdclk_sel; 440 u16 tmp = 0; 441 442 cdclk_config->vco = intel_hpll_vco(display); 443 444 pci_read_config_word(pdev, GCFGC, &tmp); 445 446 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 447 448 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 449 goto fail; 450 451 switch (cdclk_config->vco) { 452 case 3200000: 453 div_table = div_3200; 454 break; 455 case 4000000: 456 div_table = div_4000; 457 break; 458 case 5333333: 459 div_table = div_5333; 460 break; 461 default: 462 goto fail; 463 } 464 465 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 466 div_table[cdclk_sel]); 467 return; 468 469 fail: 470 drm_err(display->drm, 471 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 472 cdclk_config->vco, tmp); 473 cdclk_config->cdclk = 200000; 474 } 475 476 static void gm45_get_cdclk(struct intel_display *display, 477 struct intel_cdclk_config *cdclk_config) 478 { 479 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 480 unsigned int cdclk_sel; 481 u16 tmp = 0; 482 483 cdclk_config->vco = intel_hpll_vco(display); 484 485 pci_read_config_word(pdev, GCFGC, &tmp); 486 487 cdclk_sel = (tmp >> 12) & 0x1; 488 489 switch (cdclk_config->vco) { 490 case 2666667: 491 case 4000000: 492 case 5333333: 493 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 494 break; 495 case 3200000: 496 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 497 break; 498 default: 499 drm_err(display->drm, 500 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 501 cdclk_config->vco, tmp); 502 cdclk_config->cdclk = 222222; 503 break; 504 } 505 } 506 507 static void hsw_get_cdclk(struct intel_display *display, 508 struct intel_cdclk_config *cdclk_config) 509 { 510 struct drm_i915_private *dev_priv = to_i915(display->drm); 511 u32 lcpll = intel_de_read(display, LCPLL_CTL); 512 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 513 514 if (lcpll & LCPLL_CD_SOURCE_FCLK) 515 cdclk_config->cdclk = 800000; 516 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 517 cdclk_config->cdclk = 450000; 518 else if (freq == LCPLL_CLK_FREQ_450) 519 cdclk_config->cdclk = 450000; 520 else if (IS_HASWELL_ULT(dev_priv)) 521 cdclk_config->cdclk = 337500; 522 else 523 cdclk_config->cdclk = 540000; 524 } 525 526 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) 527 { 528 struct drm_i915_private *dev_priv = to_i915(display->drm); 529 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 530 333333 : 320000; 531 532 /* 533 * We seem to get an unstable or solid color picture at 200MHz. 534 * Not sure what's wrong. For now use 200MHz only when all pipes 535 * are off. 536 */ 537 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) 538 return 400000; 539 else if (min_cdclk > 266667) 540 return freq_320; 541 else if (min_cdclk > 0) 542 return 266667; 543 else 544 return 200000; 545 } 546 547 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 548 { 549 struct drm_i915_private *dev_priv = to_i915(display->drm); 550 551 if (IS_VALLEYVIEW(dev_priv)) { 552 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 553 return 2; 554 else if (cdclk >= 266667) 555 return 1; 556 else 557 return 0; 558 } else { 559 /* 560 * Specs are full of misinformation, but testing on actual 561 * hardware has shown that we just need to write the desired 562 * CCK divider into the Punit register. 563 */ 564 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 565 } 566 } 567 568 static void vlv_get_cdclk(struct intel_display *display, 569 struct intel_cdclk_config *cdclk_config) 570 { 571 struct drm_i915_private *dev_priv = to_i915(display->drm); 572 u32 val; 573 574 vlv_iosf_sb_get(dev_priv, 575 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 576 577 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); 578 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", 579 CCK_DISPLAY_CLOCK_CONTROL, 580 cdclk_config->vco); 581 582 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 583 584 vlv_iosf_sb_put(dev_priv, 585 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 586 587 if (IS_VALLEYVIEW(dev_priv)) 588 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 589 DSPFREQGUAR_SHIFT; 590 else 591 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 592 DSPFREQGUAR_SHIFT_CHV; 593 } 594 595 static void vlv_program_pfi_credits(struct intel_display *display) 596 { 597 struct drm_i915_private *dev_priv = to_i915(display->drm); 598 unsigned int credits, default_credits; 599 600 if (IS_CHERRYVIEW(dev_priv)) 601 default_credits = PFI_CREDIT(12); 602 else 603 default_credits = PFI_CREDIT(8); 604 605 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 606 /* CHV suggested value is 31 or 63 */ 607 if (IS_CHERRYVIEW(dev_priv)) 608 credits = PFI_CREDIT_63; 609 else 610 credits = PFI_CREDIT(15); 611 } else { 612 credits = default_credits; 613 } 614 615 /* 616 * WA - write default credits before re-programming 617 * FIXME: should we also set the resend bit here? 618 */ 619 intel_de_write(display, GCI_CONTROL, 620 VGA_FAST_MODE_DISABLE | default_credits); 621 622 intel_de_write(display, GCI_CONTROL, 623 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 624 625 /* 626 * FIXME is this guaranteed to clear 627 * immediately or should we poll for it? 628 */ 629 drm_WARN_ON(display->drm, 630 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); 631 } 632 633 static void vlv_set_cdclk(struct intel_display *display, 634 const struct intel_cdclk_config *cdclk_config, 635 enum pipe pipe) 636 { 637 struct drm_i915_private *dev_priv = to_i915(display->drm); 638 int cdclk = cdclk_config->cdclk; 639 u32 val, cmd = cdclk_config->voltage_level; 640 intel_wakeref_t wakeref; 641 642 switch (cdclk) { 643 case 400000: 644 case 333333: 645 case 320000: 646 case 266667: 647 case 200000: 648 break; 649 default: 650 MISSING_CASE(cdclk); 651 return; 652 } 653 654 /* There are cases where we can end up here with power domains 655 * off and a CDCLK frequency other than the minimum, like when 656 * issuing a modeset without actually changing any display after 657 * a system suspend. So grab the display core domain, which covers 658 * the HW blocks needed for the following programming. 659 */ 660 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 661 662 vlv_iosf_sb_get(dev_priv, 663 BIT(VLV_IOSF_SB_CCK) | 664 BIT(VLV_IOSF_SB_BUNIT) | 665 BIT(VLV_IOSF_SB_PUNIT)); 666 667 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 668 val &= ~DSPFREQGUAR_MASK; 669 val |= (cmd << DSPFREQGUAR_SHIFT); 670 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 671 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 672 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 673 50)) { 674 drm_err(display->drm, 675 "timed out waiting for CDclk change\n"); 676 } 677 678 if (cdclk == 400000) { 679 u32 divider; 680 681 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 682 cdclk) - 1; 683 684 /* adjust cdclk divider */ 685 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); 686 val &= ~CCK_FREQUENCY_VALUES; 687 val |= divider; 688 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); 689 690 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & 691 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 692 50)) 693 drm_err(display->drm, 694 "timed out waiting for CDclk change\n"); 695 } 696 697 /* adjust self-refresh exit latency value */ 698 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); 699 val &= ~0x7f; 700 701 /* 702 * For high bandwidth configs, we set a higher latency in the bunit 703 * so that the core display fetch happens in time to avoid underruns. 704 */ 705 if (cdclk == 400000) 706 val |= 4500 / 250; /* 4.5 usec */ 707 else 708 val |= 3000 / 250; /* 3.0 usec */ 709 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); 710 711 vlv_iosf_sb_put(dev_priv, 712 BIT(VLV_IOSF_SB_CCK) | 713 BIT(VLV_IOSF_SB_BUNIT) | 714 BIT(VLV_IOSF_SB_PUNIT)); 715 716 intel_update_cdclk(display); 717 718 vlv_program_pfi_credits(display); 719 720 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 721 } 722 723 static void chv_set_cdclk(struct intel_display *display, 724 const struct intel_cdclk_config *cdclk_config, 725 enum pipe pipe) 726 { 727 struct drm_i915_private *dev_priv = to_i915(display->drm); 728 int cdclk = cdclk_config->cdclk; 729 u32 val, cmd = cdclk_config->voltage_level; 730 intel_wakeref_t wakeref; 731 732 switch (cdclk) { 733 case 333333: 734 case 320000: 735 case 266667: 736 case 200000: 737 break; 738 default: 739 MISSING_CASE(cdclk); 740 return; 741 } 742 743 /* There are cases where we can end up here with power domains 744 * off and a CDCLK frequency other than the minimum, like when 745 * issuing a modeset without actually changing any display after 746 * a system suspend. So grab the display core domain, which covers 747 * the HW blocks needed for the following programming. 748 */ 749 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); 750 751 vlv_punit_get(dev_priv); 752 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); 753 val &= ~DSPFREQGUAR_MASK_CHV; 754 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 755 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); 756 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & 757 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 758 50)) { 759 drm_err(display->drm, 760 "timed out waiting for CDclk change\n"); 761 } 762 763 vlv_punit_put(dev_priv); 764 765 intel_update_cdclk(display); 766 767 vlv_program_pfi_credits(display); 768 769 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); 770 } 771 772 static int bdw_calc_cdclk(int min_cdclk) 773 { 774 if (min_cdclk > 540000) 775 return 675000; 776 else if (min_cdclk > 450000) 777 return 540000; 778 else if (min_cdclk > 337500) 779 return 450000; 780 else 781 return 337500; 782 } 783 784 static u8 bdw_calc_voltage_level(int cdclk) 785 { 786 switch (cdclk) { 787 default: 788 case 337500: 789 return 2; 790 case 450000: 791 return 0; 792 case 540000: 793 return 1; 794 case 675000: 795 return 3; 796 } 797 } 798 799 static void bdw_get_cdclk(struct intel_display *display, 800 struct intel_cdclk_config *cdclk_config) 801 { 802 u32 lcpll = intel_de_read(display, LCPLL_CTL); 803 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 804 805 if (lcpll & LCPLL_CD_SOURCE_FCLK) 806 cdclk_config->cdclk = 800000; 807 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 808 cdclk_config->cdclk = 450000; 809 else if (freq == LCPLL_CLK_FREQ_450) 810 cdclk_config->cdclk = 450000; 811 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 812 cdclk_config->cdclk = 540000; 813 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 814 cdclk_config->cdclk = 337500; 815 else 816 cdclk_config->cdclk = 675000; 817 818 /* 819 * Can't read this out :( Let's assume it's 820 * at least what the CDCLK frequency requires. 821 */ 822 cdclk_config->voltage_level = 823 bdw_calc_voltage_level(cdclk_config->cdclk); 824 } 825 826 static u32 bdw_cdclk_freq_sel(int cdclk) 827 { 828 switch (cdclk) { 829 default: 830 MISSING_CASE(cdclk); 831 fallthrough; 832 case 337500: 833 return LCPLL_CLK_FREQ_337_5_BDW; 834 case 450000: 835 return LCPLL_CLK_FREQ_450; 836 case 540000: 837 return LCPLL_CLK_FREQ_54O_BDW; 838 case 675000: 839 return LCPLL_CLK_FREQ_675_BDW; 840 } 841 } 842 843 static void bdw_set_cdclk(struct intel_display *display, 844 const struct intel_cdclk_config *cdclk_config, 845 enum pipe pipe) 846 { 847 struct drm_i915_private *dev_priv = to_i915(display->drm); 848 int cdclk = cdclk_config->cdclk; 849 int ret; 850 851 if (drm_WARN(display->drm, 852 (intel_de_read(display, LCPLL_CTL) & 853 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 854 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 855 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 856 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 857 "trying to change cdclk frequency with cdclk not enabled\n")) 858 return; 859 860 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 861 if (ret) { 862 drm_err(display->drm, 863 "failed to inform pcode about cdclk change\n"); 864 return; 865 } 866 867 intel_de_rmw(display, LCPLL_CTL, 868 0, LCPLL_CD_SOURCE_FCLK); 869 870 /* 871 * According to the spec, it should be enough to poll for this 1 us. 872 * However, extensive testing shows that this can take longer. 873 */ 874 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & 875 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 876 drm_err(display->drm, "Switching to FCLK failed\n"); 877 878 intel_de_rmw(display, LCPLL_CTL, 879 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 880 881 intel_de_rmw(display, LCPLL_CTL, 882 LCPLL_CD_SOURCE_FCLK, 0); 883 884 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & 885 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 886 drm_err(display->drm, "Switching back to LCPLL failed\n"); 887 888 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, 889 cdclk_config->voltage_level); 890 891 intel_de_write(display, CDCLK_FREQ, 892 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 893 894 intel_update_cdclk(display); 895 } 896 897 static int skl_calc_cdclk(int min_cdclk, int vco) 898 { 899 if (vco == 8640000) { 900 if (min_cdclk > 540000) 901 return 617143; 902 else if (min_cdclk > 432000) 903 return 540000; 904 else if (min_cdclk > 308571) 905 return 432000; 906 else 907 return 308571; 908 } else { 909 if (min_cdclk > 540000) 910 return 675000; 911 else if (min_cdclk > 450000) 912 return 540000; 913 else if (min_cdclk > 337500) 914 return 450000; 915 else 916 return 337500; 917 } 918 } 919 920 static u8 skl_calc_voltage_level(int cdclk) 921 { 922 if (cdclk > 540000) 923 return 3; 924 else if (cdclk > 450000) 925 return 2; 926 else if (cdclk > 337500) 927 return 1; 928 else 929 return 0; 930 } 931 932 static void skl_dpll0_update(struct intel_display *display, 933 struct intel_cdclk_config *cdclk_config) 934 { 935 u32 val; 936 937 cdclk_config->ref = 24000; 938 cdclk_config->vco = 0; 939 940 val = intel_de_read(display, LCPLL1_CTL); 941 if ((val & LCPLL_PLL_ENABLE) == 0) 942 return; 943 944 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) 945 return; 946 947 val = intel_de_read(display, DPLL_CTRL1); 948 949 if (drm_WARN_ON(display->drm, 950 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 951 DPLL_CTRL1_SSC(SKL_DPLL0) | 952 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 953 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 954 return; 955 956 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 957 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 958 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 959 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 960 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 961 cdclk_config->vco = 8100000; 962 break; 963 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 964 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 965 cdclk_config->vco = 8640000; 966 break; 967 default: 968 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 969 break; 970 } 971 } 972 973 static void skl_get_cdclk(struct intel_display *display, 974 struct intel_cdclk_config *cdclk_config) 975 { 976 u32 cdctl; 977 978 skl_dpll0_update(display, cdclk_config); 979 980 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 981 982 if (cdclk_config->vco == 0) 983 goto out; 984 985 cdctl = intel_de_read(display, CDCLK_CTL); 986 987 if (cdclk_config->vco == 8640000) { 988 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 989 case CDCLK_FREQ_450_432: 990 cdclk_config->cdclk = 432000; 991 break; 992 case CDCLK_FREQ_337_308: 993 cdclk_config->cdclk = 308571; 994 break; 995 case CDCLK_FREQ_540: 996 cdclk_config->cdclk = 540000; 997 break; 998 case CDCLK_FREQ_675_617: 999 cdclk_config->cdclk = 617143; 1000 break; 1001 default: 1002 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1003 break; 1004 } 1005 } else { 1006 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1007 case CDCLK_FREQ_450_432: 1008 cdclk_config->cdclk = 450000; 1009 break; 1010 case CDCLK_FREQ_337_308: 1011 cdclk_config->cdclk = 337500; 1012 break; 1013 case CDCLK_FREQ_540: 1014 cdclk_config->cdclk = 540000; 1015 break; 1016 case CDCLK_FREQ_675_617: 1017 cdclk_config->cdclk = 675000; 1018 break; 1019 default: 1020 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1021 break; 1022 } 1023 } 1024 1025 out: 1026 /* 1027 * Can't read this out :( Let's assume it's 1028 * at least what the CDCLK frequency requires. 1029 */ 1030 cdclk_config->voltage_level = 1031 skl_calc_voltage_level(cdclk_config->cdclk); 1032 } 1033 1034 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1035 static int skl_cdclk_decimal(int cdclk) 1036 { 1037 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1038 } 1039 1040 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) 1041 { 1042 bool changed = display->cdclk.skl_preferred_vco_freq != vco; 1043 1044 display->cdclk.skl_preferred_vco_freq = vco; 1045 1046 if (changed) 1047 intel_update_max_cdclk(display); 1048 } 1049 1050 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) 1051 { 1052 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 1053 1054 /* 1055 * We always enable DPLL0 with the lowest link rate possible, but still 1056 * taking into account the VCO required to operate the eDP panel at the 1057 * desired frequency. The usual DP link rates operate with a VCO of 1058 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1059 * The modeset code is responsible for the selection of the exact link 1060 * rate later on, with the constraint of choosing a frequency that 1061 * works with vco. 1062 */ 1063 if (vco == 8640000) 1064 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1065 else 1066 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1067 } 1068 1069 static void skl_dpll0_enable(struct intel_display *display, int vco) 1070 { 1071 intel_de_rmw(display, DPLL_CTRL1, 1072 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1073 DPLL_CTRL1_SSC(SKL_DPLL0) | 1074 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1075 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1076 skl_dpll0_link_rate(display, vco)); 1077 intel_de_posting_read(display, DPLL_CTRL1); 1078 1079 intel_de_rmw(display, LCPLL1_CTL, 1080 0, LCPLL_PLL_ENABLE); 1081 1082 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1083 drm_err(display->drm, "DPLL0 not locked\n"); 1084 1085 display->cdclk.hw.vco = vco; 1086 1087 /* We'll want to keep using the current vco from now on. */ 1088 skl_set_preferred_cdclk_vco(display, vco); 1089 } 1090 1091 static void skl_dpll0_disable(struct intel_display *display) 1092 { 1093 intel_de_rmw(display, LCPLL1_CTL, 1094 LCPLL_PLL_ENABLE, 0); 1095 1096 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1097 drm_err(display->drm, "Couldn't disable DPLL0\n"); 1098 1099 display->cdclk.hw.vco = 0; 1100 } 1101 1102 static u32 skl_cdclk_freq_sel(struct intel_display *display, 1103 int cdclk, int vco) 1104 { 1105 switch (cdclk) { 1106 default: 1107 drm_WARN_ON(display->drm, 1108 cdclk != display->cdclk.hw.bypass); 1109 drm_WARN_ON(display->drm, vco != 0); 1110 fallthrough; 1111 case 308571: 1112 case 337500: 1113 return CDCLK_FREQ_337_308; 1114 case 450000: 1115 case 432000: 1116 return CDCLK_FREQ_450_432; 1117 case 540000: 1118 return CDCLK_FREQ_540; 1119 case 617143: 1120 case 675000: 1121 return CDCLK_FREQ_675_617; 1122 } 1123 } 1124 1125 static void skl_set_cdclk(struct intel_display *display, 1126 const struct intel_cdclk_config *cdclk_config, 1127 enum pipe pipe) 1128 { 1129 struct drm_i915_private *dev_priv = to_i915(display->drm); 1130 int cdclk = cdclk_config->cdclk; 1131 int vco = cdclk_config->vco; 1132 u32 freq_select, cdclk_ctl; 1133 int ret; 1134 1135 /* 1136 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1137 * unsupported on SKL. In theory this should never happen since only 1138 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1139 * supported on SKL either, see the above WA. WARN whenever trying to 1140 * use the corresponding VCO freq as that always leads to using the 1141 * minimum 308MHz CDCLK. 1142 */ 1143 drm_WARN_ON_ONCE(display->drm, 1144 IS_SKYLAKE(dev_priv) && vco == 8640000); 1145 1146 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1147 SKL_CDCLK_PREPARE_FOR_CHANGE, 1148 SKL_CDCLK_READY_FOR_CHANGE, 1149 SKL_CDCLK_READY_FOR_CHANGE, 3); 1150 if (ret) { 1151 drm_err(display->drm, 1152 "Failed to inform PCU about cdclk change (%d)\n", ret); 1153 return; 1154 } 1155 1156 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); 1157 1158 if (display->cdclk.hw.vco != 0 && 1159 display->cdclk.hw.vco != vco) 1160 skl_dpll0_disable(display); 1161 1162 cdclk_ctl = intel_de_read(display, CDCLK_CTL); 1163 1164 if (display->cdclk.hw.vco != vco) { 1165 /* Wa Display #1183: skl,kbl,cfl */ 1166 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1167 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1168 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1169 } 1170 1171 /* Wa Display #1183: skl,kbl,cfl */ 1172 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1173 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1174 intel_de_posting_read(display, CDCLK_CTL); 1175 1176 if (display->cdclk.hw.vco != vco) 1177 skl_dpll0_enable(display, vco); 1178 1179 /* Wa Display #1183: skl,kbl,cfl */ 1180 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1181 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1182 1183 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1184 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1185 1186 /* Wa Display #1183: skl,kbl,cfl */ 1187 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1188 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1189 intel_de_posting_read(display, CDCLK_CTL); 1190 1191 /* inform PCU of the change */ 1192 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 1193 cdclk_config->voltage_level); 1194 1195 intel_update_cdclk(display); 1196 } 1197 1198 static void skl_sanitize_cdclk(struct intel_display *display) 1199 { 1200 u32 cdctl, expected; 1201 1202 /* 1203 * check if the pre-os initialized the display 1204 * There is SWF18 scratchpad register defined which is set by the 1205 * pre-os which can be used by the OS drivers to check the status 1206 */ 1207 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1208 goto sanitize; 1209 1210 intel_update_cdclk(display); 1211 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1212 1213 /* Is PLL enabled and locked ? */ 1214 if (display->cdclk.hw.vco == 0 || 1215 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 1216 goto sanitize; 1217 1218 /* DPLL okay; verify the cdclock 1219 * 1220 * Noticed in some instances that the freq selection is correct but 1221 * decimal part is programmed wrong from BIOS where pre-os does not 1222 * enable display. Verify the same as well. 1223 */ 1224 cdctl = intel_de_read(display, CDCLK_CTL); 1225 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1226 skl_cdclk_decimal(display->cdclk.hw.cdclk); 1227 if (cdctl == expected) 1228 /* All well; nothing to sanitize */ 1229 return; 1230 1231 sanitize: 1232 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 1233 1234 /* force cdclk programming */ 1235 display->cdclk.hw.cdclk = 0; 1236 /* force full PLL disable + enable */ 1237 display->cdclk.hw.vco = ~0; 1238 } 1239 1240 static void skl_cdclk_init_hw(struct intel_display *display) 1241 { 1242 struct intel_cdclk_config cdclk_config; 1243 1244 skl_sanitize_cdclk(display); 1245 1246 if (display->cdclk.hw.cdclk != 0 && 1247 display->cdclk.hw.vco != 0) { 1248 /* 1249 * Use the current vco as our initial 1250 * guess as to what the preferred vco is. 1251 */ 1252 if (display->cdclk.skl_preferred_vco_freq == 0) 1253 skl_set_preferred_cdclk_vco(display, 1254 display->cdclk.hw.vco); 1255 return; 1256 } 1257 1258 cdclk_config = display->cdclk.hw; 1259 1260 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; 1261 if (cdclk_config.vco == 0) 1262 cdclk_config.vco = 8100000; 1263 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1264 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1265 1266 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1267 } 1268 1269 static void skl_cdclk_uninit_hw(struct intel_display *display) 1270 { 1271 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 1272 1273 cdclk_config.cdclk = cdclk_config.bypass; 1274 cdclk_config.vco = 0; 1275 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1276 1277 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1278 } 1279 1280 struct intel_cdclk_vals { 1281 u32 cdclk; 1282 u16 refclk; 1283 u16 waveform; 1284 u8 ratio; 1285 }; 1286 1287 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1288 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1289 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1290 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1291 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1292 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1293 {} 1294 }; 1295 1296 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1297 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1298 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1299 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1300 {} 1301 }; 1302 1303 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1304 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1305 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1306 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1307 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1308 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1309 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1310 1311 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1312 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1313 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1314 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1315 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1316 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1317 1318 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1319 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1320 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1321 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1322 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1323 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1324 {} 1325 }; 1326 1327 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1328 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1329 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1330 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1331 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1332 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1333 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1334 1335 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1336 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1337 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1338 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1339 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1340 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1341 1342 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1343 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1344 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1345 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1346 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1347 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1348 {} 1349 }; 1350 1351 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1352 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1353 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1354 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1355 1356 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1357 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1358 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1359 1360 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1361 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1362 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1363 {} 1364 }; 1365 1366 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1367 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1368 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1369 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1370 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1371 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1372 1373 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1374 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1375 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1376 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1377 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1378 1379 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1380 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1381 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1382 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1383 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1384 {} 1385 }; 1386 1387 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1388 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1389 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1390 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1391 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1392 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1393 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1394 1395 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1396 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1397 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1398 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1399 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1400 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1401 1402 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1403 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1404 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1405 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1406 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1407 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1408 {} 1409 }; 1410 1411 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1412 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1413 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1414 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1415 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1416 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1417 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1418 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1419 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1420 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1421 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1422 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1423 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1424 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1425 {} 1426 }; 1427 1428 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1429 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1430 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1431 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1432 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1433 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1434 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1435 {} 1436 }; 1437 1438 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1439 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1440 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1441 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1442 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1443 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1444 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1445 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1446 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1447 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1448 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1449 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1450 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1451 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1452 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1453 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1454 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1455 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1456 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1457 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1458 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1459 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1460 {} 1461 }; 1462 1463 /* 1464 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1465 */ 1466 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1467 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1468 {} 1469 }; 1470 1471 static const int cdclk_squash_len = 16; 1472 1473 static int cdclk_squash_divider(u16 waveform) 1474 { 1475 return hweight16(waveform ?: 0xffff); 1476 } 1477 1478 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1479 { 1480 /* 2 * cd2x divider */ 1481 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1482 cdclk * cdclk_squash_len); 1483 } 1484 1485 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 1486 { 1487 const struct intel_cdclk_vals *table = display->cdclk.table; 1488 int i; 1489 1490 for (i = 0; table[i].refclk; i++) 1491 if (table[i].refclk == display->cdclk.hw.ref && 1492 table[i].cdclk >= min_cdclk) 1493 return table[i].cdclk; 1494 1495 drm_WARN(display->drm, 1, 1496 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1497 min_cdclk, display->cdclk.hw.ref); 1498 return 0; 1499 } 1500 1501 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) 1502 { 1503 const struct intel_cdclk_vals *table = display->cdclk.table; 1504 int i; 1505 1506 if (cdclk == display->cdclk.hw.bypass) 1507 return 0; 1508 1509 for (i = 0; table[i].refclk; i++) 1510 if (table[i].refclk == display->cdclk.hw.ref && 1511 table[i].cdclk == cdclk) 1512 return display->cdclk.hw.ref * table[i].ratio; 1513 1514 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1515 cdclk, display->cdclk.hw.ref); 1516 return 0; 1517 } 1518 1519 static u8 bxt_calc_voltage_level(int cdclk) 1520 { 1521 return DIV_ROUND_UP(cdclk, 25000); 1522 } 1523 1524 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1525 const int voltage_level_max_cdclk[]) 1526 { 1527 int voltage_level; 1528 1529 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1530 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1531 return voltage_level; 1532 } 1533 1534 MISSING_CASE(cdclk); 1535 return num_voltage_levels - 1; 1536 } 1537 1538 static u8 icl_calc_voltage_level(int cdclk) 1539 { 1540 static const int icl_voltage_level_max_cdclk[] = { 1541 [0] = 312000, 1542 [1] = 556800, 1543 [2] = 652800, 1544 }; 1545 1546 return calc_voltage_level(cdclk, 1547 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1548 icl_voltage_level_max_cdclk); 1549 } 1550 1551 static u8 ehl_calc_voltage_level(int cdclk) 1552 { 1553 static const int ehl_voltage_level_max_cdclk[] = { 1554 [0] = 180000, 1555 [1] = 312000, 1556 [2] = 326400, 1557 /* 1558 * Bspec lists the limit as 556.8 MHz, but some JSL 1559 * development boards (at least) boot with 652.8 MHz 1560 */ 1561 [3] = 652800, 1562 }; 1563 1564 return calc_voltage_level(cdclk, 1565 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1566 ehl_voltage_level_max_cdclk); 1567 } 1568 1569 static u8 tgl_calc_voltage_level(int cdclk) 1570 { 1571 static const int tgl_voltage_level_max_cdclk[] = { 1572 [0] = 312000, 1573 [1] = 326400, 1574 [2] = 556800, 1575 [3] = 652800, 1576 }; 1577 1578 return calc_voltage_level(cdclk, 1579 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1580 tgl_voltage_level_max_cdclk); 1581 } 1582 1583 static u8 rplu_calc_voltage_level(int cdclk) 1584 { 1585 static const int rplu_voltage_level_max_cdclk[] = { 1586 [0] = 312000, 1587 [1] = 480000, 1588 [2] = 556800, 1589 [3] = 652800, 1590 }; 1591 1592 return calc_voltage_level(cdclk, 1593 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1594 rplu_voltage_level_max_cdclk); 1595 } 1596 1597 static void icl_readout_refclk(struct intel_display *display, 1598 struct intel_cdclk_config *cdclk_config) 1599 { 1600 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1601 1602 switch (dssm) { 1603 default: 1604 MISSING_CASE(dssm); 1605 fallthrough; 1606 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1607 cdclk_config->ref = 24000; 1608 break; 1609 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1610 cdclk_config->ref = 19200; 1611 break; 1612 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1613 cdclk_config->ref = 38400; 1614 break; 1615 } 1616 } 1617 1618 static void bxt_de_pll_readout(struct intel_display *display, 1619 struct intel_cdclk_config *cdclk_config) 1620 { 1621 struct drm_i915_private *dev_priv = to_i915(display->drm); 1622 u32 val, ratio; 1623 1624 if (IS_DG2(dev_priv)) 1625 cdclk_config->ref = 38400; 1626 else if (DISPLAY_VER(display) >= 11) 1627 icl_readout_refclk(display, cdclk_config); 1628 else 1629 cdclk_config->ref = 19200; 1630 1631 val = intel_de_read(display, BXT_DE_PLL_ENABLE); 1632 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1633 (val & BXT_DE_PLL_LOCK) == 0) { 1634 /* 1635 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1636 * setting it to zero is a way to signal that. 1637 */ 1638 cdclk_config->vco = 0; 1639 return; 1640 } 1641 1642 /* 1643 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1644 * gen9lp had it in a separate PLL control register. 1645 */ 1646 if (DISPLAY_VER(display) >= 11) 1647 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1648 else 1649 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1650 1651 cdclk_config->vco = ratio * cdclk_config->ref; 1652 } 1653 1654 static void bxt_get_cdclk(struct intel_display *display, 1655 struct intel_cdclk_config *cdclk_config) 1656 { 1657 u32 squash_ctl = 0; 1658 u32 divider; 1659 int div; 1660 1661 bxt_de_pll_readout(display, cdclk_config); 1662 1663 if (DISPLAY_VER(display) >= 12) 1664 cdclk_config->bypass = cdclk_config->ref / 2; 1665 else if (DISPLAY_VER(display) >= 11) 1666 cdclk_config->bypass = 50000; 1667 else 1668 cdclk_config->bypass = cdclk_config->ref; 1669 1670 if (cdclk_config->vco == 0) { 1671 cdclk_config->cdclk = cdclk_config->bypass; 1672 goto out; 1673 } 1674 1675 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1676 1677 switch (divider) { 1678 case BXT_CDCLK_CD2X_DIV_SEL_1: 1679 div = 2; 1680 break; 1681 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1682 div = 3; 1683 break; 1684 case BXT_CDCLK_CD2X_DIV_SEL_2: 1685 div = 4; 1686 break; 1687 case BXT_CDCLK_CD2X_DIV_SEL_4: 1688 div = 8; 1689 break; 1690 default: 1691 MISSING_CASE(divider); 1692 return; 1693 } 1694 1695 if (HAS_CDCLK_SQUASH(display)) 1696 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); 1697 1698 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1699 u16 waveform; 1700 int size; 1701 1702 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1703 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1704 1705 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1706 cdclk_config->vco, size * div); 1707 } else { 1708 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1709 } 1710 1711 out: 1712 if (DISPLAY_VER(display) >= 20) 1713 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 1714 /* 1715 * Can't read this out :( Let's assume it's 1716 * at least what the CDCLK frequency requires. 1717 */ 1718 cdclk_config->voltage_level = 1719 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); 1720 } 1721 1722 static void bxt_de_pll_disable(struct intel_display *display) 1723 { 1724 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); 1725 1726 /* Timeout 200us */ 1727 if (intel_de_wait_for_clear(display, 1728 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1729 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); 1730 1731 display->cdclk.hw.vco = 0; 1732 } 1733 1734 static void bxt_de_pll_enable(struct intel_display *display, int vco) 1735 { 1736 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1737 1738 intel_de_rmw(display, BXT_DE_PLL_CTL, 1739 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1740 1741 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1742 1743 /* Timeout 200us */ 1744 if (intel_de_wait_for_set(display, 1745 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1746 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); 1747 1748 display->cdclk.hw.vco = vco; 1749 } 1750 1751 static void icl_cdclk_pll_disable(struct intel_display *display) 1752 { 1753 intel_de_rmw(display, BXT_DE_PLL_ENABLE, 1754 BXT_DE_PLL_PLL_ENABLE, 0); 1755 1756 /* Timeout 200us */ 1757 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1758 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); 1759 1760 display->cdclk.hw.vco = 0; 1761 } 1762 1763 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) 1764 { 1765 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1766 u32 val; 1767 1768 val = ICL_CDCLK_PLL_RATIO(ratio); 1769 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1770 1771 val |= BXT_DE_PLL_PLL_ENABLE; 1772 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1773 1774 /* Timeout 200us */ 1775 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1776 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); 1777 1778 display->cdclk.hw.vco = vco; 1779 } 1780 1781 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) 1782 { 1783 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1784 u32 val; 1785 1786 /* Write PLL ratio without disabling */ 1787 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1788 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1789 1790 /* Submit freq change request */ 1791 val |= BXT_DE_PLL_FREQ_REQ; 1792 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1793 1794 /* Timeout 200us */ 1795 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, 1796 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1797 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); 1798 1799 val &= ~BXT_DE_PLL_FREQ_REQ; 1800 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1801 1802 display->cdclk.hw.vco = vco; 1803 } 1804 1805 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 1806 { 1807 if (DISPLAY_VER(display) >= 12) { 1808 if (pipe == INVALID_PIPE) 1809 return TGL_CDCLK_CD2X_PIPE_NONE; 1810 else 1811 return TGL_CDCLK_CD2X_PIPE(pipe); 1812 } else if (DISPLAY_VER(display) >= 11) { 1813 if (pipe == INVALID_PIPE) 1814 return ICL_CDCLK_CD2X_PIPE_NONE; 1815 else 1816 return ICL_CDCLK_CD2X_PIPE(pipe); 1817 } else { 1818 if (pipe == INVALID_PIPE) 1819 return BXT_CDCLK_CD2X_PIPE_NONE; 1820 else 1821 return BXT_CDCLK_CD2X_PIPE(pipe); 1822 } 1823 } 1824 1825 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 1826 int cdclk, int vco, u16 waveform) 1827 { 1828 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1829 switch (cdclk_divider(cdclk, vco, waveform)) { 1830 default: 1831 drm_WARN_ON(display->drm, 1832 cdclk != display->cdclk.hw.bypass); 1833 drm_WARN_ON(display->drm, vco != 0); 1834 fallthrough; 1835 case 2: 1836 return BXT_CDCLK_CD2X_DIV_SEL_1; 1837 case 3: 1838 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1839 case 4: 1840 return BXT_CDCLK_CD2X_DIV_SEL_2; 1841 case 8: 1842 return BXT_CDCLK_CD2X_DIV_SEL_4; 1843 } 1844 } 1845 1846 static u16 cdclk_squash_waveform(struct intel_display *display, 1847 int cdclk) 1848 { 1849 const struct intel_cdclk_vals *table = display->cdclk.table; 1850 int i; 1851 1852 if (cdclk == display->cdclk.hw.bypass) 1853 return 0; 1854 1855 for (i = 0; table[i].refclk; i++) 1856 if (table[i].refclk == display->cdclk.hw.ref && 1857 table[i].cdclk == cdclk) 1858 return table[i].waveform; 1859 1860 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1861 cdclk, display->cdclk.hw.ref); 1862 1863 return 0xffff; 1864 } 1865 1866 static void icl_cdclk_pll_update(struct intel_display *display, int vco) 1867 { 1868 if (display->cdclk.hw.vco != 0 && 1869 display->cdclk.hw.vco != vco) 1870 icl_cdclk_pll_disable(display); 1871 1872 if (display->cdclk.hw.vco != vco) 1873 icl_cdclk_pll_enable(display, vco); 1874 } 1875 1876 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) 1877 { 1878 if (display->cdclk.hw.vco != 0 && 1879 display->cdclk.hw.vco != vco) 1880 bxt_de_pll_disable(display); 1881 1882 if (display->cdclk.hw.vco != vco) 1883 bxt_de_pll_enable(display, vco); 1884 } 1885 1886 static void dg2_cdclk_squash_program(struct intel_display *display, 1887 u16 waveform) 1888 { 1889 u32 squash_ctl = 0; 1890 1891 if (waveform) 1892 squash_ctl = CDCLK_SQUASH_ENABLE | 1893 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1894 1895 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); 1896 } 1897 1898 static bool cdclk_pll_is_unknown(unsigned int vco) 1899 { 1900 /* 1901 * Ensure driver does not take the crawl path for the 1902 * case when the vco is set to ~0 in the 1903 * sanitize path. 1904 */ 1905 return vco == ~0; 1906 } 1907 1908 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) 1909 { 1910 return DISPLAY_VER(display) >= 20; 1911 } 1912 1913 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) 1914 { 1915 if (mdclk_source_is_cdclk_pll(display)) 1916 return MDCLK_SOURCE_SEL_CDCLK_PLL; 1917 1918 return MDCLK_SOURCE_SEL_CD2XCLK; 1919 } 1920 1921 int intel_mdclk_cdclk_ratio(struct intel_display *display, 1922 const struct intel_cdclk_config *cdclk_config) 1923 { 1924 if (mdclk_source_is_cdclk_pll(display)) 1925 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 1926 1927 /* Otherwise, source for MDCLK is CD2XCLK. */ 1928 return 2; 1929 } 1930 1931 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, 1932 const struct intel_cdclk_config *cdclk_config) 1933 { 1934 struct drm_i915_private *i915 = to_i915(display->drm); 1935 1936 intel_dbuf_mdclk_cdclk_ratio_update(i915, 1937 intel_mdclk_cdclk_ratio(display, cdclk_config), 1938 cdclk_config->joined_mbus); 1939 } 1940 1941 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, 1942 const struct intel_cdclk_config *old_cdclk_config, 1943 const struct intel_cdclk_config *new_cdclk_config, 1944 struct intel_cdclk_config *mid_cdclk_config) 1945 { 1946 u16 old_waveform, new_waveform, mid_waveform; 1947 int old_div, new_div, mid_div; 1948 1949 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 1950 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 1951 return false; 1952 1953 /* Return if both Squash and Crawl are not present */ 1954 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 1955 return false; 1956 1957 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); 1958 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); 1959 1960 /* Return if Squash only or Crawl only is the desired action */ 1961 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 1962 old_cdclk_config->vco == new_cdclk_config->vco || 1963 old_waveform == new_waveform) 1964 return false; 1965 1966 old_div = cdclk_divider(old_cdclk_config->cdclk, 1967 old_cdclk_config->vco, old_waveform); 1968 new_div = cdclk_divider(new_cdclk_config->cdclk, 1969 new_cdclk_config->vco, new_waveform); 1970 1971 /* 1972 * Should not happen currently. We might need more midpoint 1973 * transitions if we need to also change the cd2x divider. 1974 */ 1975 if (drm_WARN_ON(display->drm, old_div != new_div)) 1976 return false; 1977 1978 *mid_cdclk_config = *new_cdclk_config; 1979 1980 /* 1981 * Populate the mid_cdclk_config accordingly. 1982 * - If moving to a higher cdclk, the desired action is squashing. 1983 * The mid cdclk config should have the new (squash) waveform. 1984 * - If moving to a lower cdclk, the desired action is crawling. 1985 * The mid cdclk config should have the new vco. 1986 */ 1987 1988 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 1989 mid_cdclk_config->vco = old_cdclk_config->vco; 1990 mid_div = old_div; 1991 mid_waveform = new_waveform; 1992 } else { 1993 mid_cdclk_config->vco = new_cdclk_config->vco; 1994 mid_div = new_div; 1995 mid_waveform = old_waveform; 1996 } 1997 1998 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 1999 mid_cdclk_config->vco, 2000 cdclk_squash_len * mid_div); 2001 2002 /* make sure the mid clock came out sane */ 2003 2004 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < 2005 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 2006 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > 2007 display->cdclk.max_cdclk_freq); 2008 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != 2009 mid_waveform); 2010 2011 return true; 2012 } 2013 2014 static bool pll_enable_wa_needed(struct intel_display *display) 2015 { 2016 struct drm_i915_private *dev_priv = to_i915(display->drm); 2017 2018 return (DISPLAY_VER_FULL(display) == IP_VER(20, 0) || 2019 DISPLAY_VER_FULL(display) == IP_VER(14, 0) || 2020 IS_DG2(dev_priv)) && 2021 display->cdclk.hw.vco > 0; 2022 } 2023 2024 static u32 bxt_cdclk_ctl(struct intel_display *display, 2025 const struct intel_cdclk_config *cdclk_config, 2026 enum pipe pipe) 2027 { 2028 struct drm_i915_private *i915 = to_i915(display->drm); 2029 int cdclk = cdclk_config->cdclk; 2030 int vco = cdclk_config->vco; 2031 u16 waveform; 2032 u32 val; 2033 2034 waveform = cdclk_squash_waveform(display, cdclk); 2035 2036 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | 2037 bxt_cdclk_cd2x_pipe(display, pipe); 2038 2039 /* 2040 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2041 * enable otherwise. 2042 */ 2043 if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) && 2044 cdclk >= 500000) 2045 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2046 2047 if (DISPLAY_VER(display) >= 20) 2048 val |= xe2lpd_mdclk_source_sel(display); 2049 else 2050 val |= skl_cdclk_decimal(cdclk); 2051 2052 return val; 2053 } 2054 2055 static void _bxt_set_cdclk(struct intel_display *display, 2056 const struct intel_cdclk_config *cdclk_config, 2057 enum pipe pipe) 2058 { 2059 int cdclk = cdclk_config->cdclk; 2060 int vco = cdclk_config->vco; 2061 2062 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && 2063 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { 2064 if (display->cdclk.hw.vco != vco) 2065 adlp_cdclk_pll_crawl(display, vco); 2066 } else if (DISPLAY_VER(display) >= 11) { 2067 /* wa_15010685871: dg2, mtl */ 2068 if (pll_enable_wa_needed(display)) 2069 dg2_cdclk_squash_program(display, 0); 2070 2071 icl_cdclk_pll_update(display, vco); 2072 } else { 2073 bxt_cdclk_pll_update(display, vco); 2074 } 2075 2076 if (HAS_CDCLK_SQUASH(display)) { 2077 u16 waveform = cdclk_squash_waveform(display, cdclk); 2078 2079 dg2_cdclk_squash_program(display, waveform); 2080 } 2081 2082 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); 2083 2084 if (pipe != INVALID_PIPE) 2085 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 2086 } 2087 2088 static void bxt_set_cdclk(struct intel_display *display, 2089 const struct intel_cdclk_config *cdclk_config, 2090 enum pipe pipe) 2091 { 2092 struct drm_i915_private *dev_priv = to_i915(display->drm); 2093 struct intel_cdclk_config mid_cdclk_config; 2094 int cdclk = cdclk_config->cdclk; 2095 int ret = 0; 2096 2097 /* 2098 * Inform power controller of upcoming frequency change. 2099 * Display versions 14 and beyond do not follow the PUnit 2100 * mailbox communication, skip 2101 * this step. 2102 */ 2103 if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv)) 2104 /* NOOP */; 2105 else if (DISPLAY_VER(display) >= 11) 2106 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 2107 SKL_CDCLK_PREPARE_FOR_CHANGE, 2108 SKL_CDCLK_READY_FOR_CHANGE, 2109 SKL_CDCLK_READY_FOR_CHANGE, 3); 2110 else 2111 /* 2112 * BSpec requires us to wait up to 150usec, but that leads to 2113 * timeouts; the 2ms used here is based on experiment. 2114 */ 2115 ret = snb_pcode_write_timeout(&dev_priv->uncore, 2116 HSW_PCODE_DE_WRITE_FREQ_REQ, 2117 0x80000000, 150, 2); 2118 2119 if (ret) { 2120 drm_err(display->drm, 2121 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2122 ret, cdclk); 2123 return; 2124 } 2125 2126 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) 2127 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2128 2129 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, 2130 cdclk_config, &mid_cdclk_config)) { 2131 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); 2132 _bxt_set_cdclk(display, cdclk_config, pipe); 2133 } else { 2134 _bxt_set_cdclk(display, cdclk_config, pipe); 2135 } 2136 2137 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) 2138 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2139 2140 if (DISPLAY_VER(display) >= 14) 2141 /* 2142 * NOOP - No Pcode communication needed for 2143 * Display versions 14 and beyond 2144 */; 2145 else if (DISPLAY_VER(display) >= 11 && !IS_DG2(dev_priv)) 2146 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, 2147 cdclk_config->voltage_level); 2148 if (DISPLAY_VER(display) < 11) { 2149 /* 2150 * The timeout isn't specified, the 2ms used here is based on 2151 * experiment. 2152 * FIXME: Waiting for the request completion could be delayed 2153 * until the next PCODE request based on BSpec. 2154 */ 2155 ret = snb_pcode_write_timeout(&dev_priv->uncore, 2156 HSW_PCODE_DE_WRITE_FREQ_REQ, 2157 cdclk_config->voltage_level, 2158 150, 2); 2159 } 2160 if (ret) { 2161 drm_err(display->drm, 2162 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2163 ret, cdclk); 2164 return; 2165 } 2166 2167 intel_update_cdclk(display); 2168 2169 if (DISPLAY_VER(display) >= 11) 2170 /* 2171 * Can't read out the voltage level :( 2172 * Let's just assume everything is as expected. 2173 */ 2174 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; 2175 } 2176 2177 static void bxt_sanitize_cdclk(struct intel_display *display) 2178 { 2179 u32 cdctl, expected; 2180 int cdclk, vco; 2181 2182 intel_update_cdclk(display); 2183 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 2184 2185 if (display->cdclk.hw.vco == 0 || 2186 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 2187 goto sanitize; 2188 2189 /* Make sure this is a legal cdclk value for the platform */ 2190 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); 2191 if (cdclk != display->cdclk.hw.cdclk) 2192 goto sanitize; 2193 2194 /* Make sure the VCO is correct for the cdclk */ 2195 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 2196 if (vco != display->cdclk.hw.vco) 2197 goto sanitize; 2198 2199 /* 2200 * Some BIOS versions leave an incorrect decimal frequency value and 2201 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2202 * so sanitize this register. 2203 */ 2204 cdctl = intel_de_read(display, CDCLK_CTL); 2205 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); 2206 2207 /* 2208 * Let's ignore the pipe field, since BIOS could have configured the 2209 * dividers both synching to an active pipe, or asynchronously 2210 * (PIPE_NONE). 2211 */ 2212 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2213 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2214 2215 if (cdctl == expected) 2216 /* All well; nothing to sanitize */ 2217 return; 2218 2219 sanitize: 2220 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 2221 2222 /* force cdclk programming */ 2223 display->cdclk.hw.cdclk = 0; 2224 2225 /* force full PLL disable + enable */ 2226 display->cdclk.hw.vco = ~0; 2227 } 2228 2229 static void bxt_cdclk_init_hw(struct intel_display *display) 2230 { 2231 struct intel_cdclk_config cdclk_config; 2232 2233 bxt_sanitize_cdclk(display); 2234 2235 if (display->cdclk.hw.cdclk != 0 && 2236 display->cdclk.hw.vco != 0) 2237 return; 2238 2239 cdclk_config = display->cdclk.hw; 2240 2241 /* 2242 * FIXME: 2243 * - The initial CDCLK needs to be read from VBT. 2244 * Need to make this change after VBT has changes for BXT. 2245 */ 2246 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); 2247 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); 2248 cdclk_config.voltage_level = 2249 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2250 2251 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2252 } 2253 2254 static void bxt_cdclk_uninit_hw(struct intel_display *display) 2255 { 2256 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 2257 2258 cdclk_config.cdclk = cdclk_config.bypass; 2259 cdclk_config.vco = 0; 2260 cdclk_config.voltage_level = 2261 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2262 2263 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2264 } 2265 2266 /** 2267 * intel_cdclk_init_hw - Initialize CDCLK hardware 2268 * @display: display instance 2269 * 2270 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and 2271 * sanitizing the state of the hardware if needed. This is generally done only 2272 * during the display core initialization sequence, after which the DMC will 2273 * take care of turning CDCLK off/on as needed. 2274 */ 2275 void intel_cdclk_init_hw(struct intel_display *display) 2276 { 2277 struct drm_i915_private *i915 = to_i915(display->drm); 2278 2279 if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) 2280 bxt_cdclk_init_hw(display); 2281 else if (DISPLAY_VER(display) == 9) 2282 skl_cdclk_init_hw(display); 2283 } 2284 2285 /** 2286 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2287 * @display: display instance 2288 * 2289 * Uninitialize CDCLK. This is done only during the display core 2290 * uninitialization sequence. 2291 */ 2292 void intel_cdclk_uninit_hw(struct intel_display *display) 2293 { 2294 struct drm_i915_private *i915 = to_i915(display->drm); 2295 2296 if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) 2297 bxt_cdclk_uninit_hw(display); 2298 else if (DISPLAY_VER(display) == 9) 2299 skl_cdclk_uninit_hw(display); 2300 } 2301 2302 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, 2303 const struct intel_cdclk_config *a, 2304 const struct intel_cdclk_config *b) 2305 { 2306 u16 old_waveform; 2307 u16 new_waveform; 2308 2309 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); 2310 2311 if (a->vco == 0 || b->vco == 0) 2312 return false; 2313 2314 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2315 return false; 2316 2317 old_waveform = cdclk_squash_waveform(display, a->cdclk); 2318 new_waveform = cdclk_squash_waveform(display, b->cdclk); 2319 2320 return a->vco != b->vco && 2321 old_waveform != new_waveform; 2322 } 2323 2324 static bool intel_cdclk_can_crawl(struct intel_display *display, 2325 const struct intel_cdclk_config *a, 2326 const struct intel_cdclk_config *b) 2327 { 2328 int a_div, b_div; 2329 2330 if (!HAS_CDCLK_CRAWL(display)) 2331 return false; 2332 2333 /* 2334 * The vco and cd2x divider will change independently 2335 * from each, so we disallow cd2x change when crawling. 2336 */ 2337 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2338 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2339 2340 return a->vco != 0 && b->vco != 0 && 2341 a->vco != b->vco && 2342 a_div == b_div && 2343 a->ref == b->ref; 2344 } 2345 2346 static bool intel_cdclk_can_squash(struct intel_display *display, 2347 const struct intel_cdclk_config *a, 2348 const struct intel_cdclk_config *b) 2349 { 2350 /* 2351 * FIXME should store a bit more state in intel_cdclk_config 2352 * to differentiate squasher vs. cd2x divider properly. For 2353 * the moment all platforms with squasher use a fixed cd2x 2354 * divider. 2355 */ 2356 if (!HAS_CDCLK_SQUASH(display)) 2357 return false; 2358 2359 return a->cdclk != b->cdclk && 2360 a->vco != 0 && 2361 a->vco == b->vco && 2362 a->ref == b->ref; 2363 } 2364 2365 /** 2366 * intel_cdclk_clock_changed - Check whether the clock changed 2367 * @a: first CDCLK configuration 2368 * @b: second CDCLK configuration 2369 * 2370 * Returns: 2371 * True if CDCLK changed in a way that requires re-programming and 2372 * False otherwise. 2373 */ 2374 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2375 const struct intel_cdclk_config *b) 2376 { 2377 return a->cdclk != b->cdclk || 2378 a->vco != b->vco || 2379 a->ref != b->ref; 2380 } 2381 2382 /** 2383 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2384 * configurations requires only a cd2x divider update 2385 * @display: display instance 2386 * @a: first CDCLK configuration 2387 * @b: second CDCLK configuration 2388 * 2389 * Returns: 2390 * True if changing between the two CDCLK configurations 2391 * can be done with just a cd2x divider update, false if not. 2392 */ 2393 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, 2394 const struct intel_cdclk_config *a, 2395 const struct intel_cdclk_config *b) 2396 { 2397 struct drm_i915_private *dev_priv = to_i915(display->drm); 2398 2399 /* Older hw doesn't have the capability */ 2400 if (DISPLAY_VER(display) < 10 && !IS_BROXTON(dev_priv)) 2401 return false; 2402 2403 /* 2404 * FIXME should store a bit more state in intel_cdclk_config 2405 * to differentiate squasher vs. cd2x divider properly. For 2406 * the moment all platforms with squasher use a fixed cd2x 2407 * divider. 2408 */ 2409 if (HAS_CDCLK_SQUASH(display)) 2410 return false; 2411 2412 return a->cdclk != b->cdclk && 2413 a->vco != 0 && 2414 a->vco == b->vco && 2415 a->ref == b->ref; 2416 } 2417 2418 /** 2419 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2420 * @a: first CDCLK configuration 2421 * @b: second CDCLK configuration 2422 * 2423 * Returns: 2424 * True if the CDCLK configurations don't match, false if they do. 2425 */ 2426 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2427 const struct intel_cdclk_config *b) 2428 { 2429 return intel_cdclk_clock_changed(a, b) || 2430 a->voltage_level != b->voltage_level; 2431 } 2432 2433 void intel_cdclk_dump_config(struct intel_display *display, 2434 const struct intel_cdclk_config *cdclk_config, 2435 const char *context) 2436 { 2437 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2438 context, cdclk_config->cdclk, cdclk_config->vco, 2439 cdclk_config->ref, cdclk_config->bypass, 2440 cdclk_config->voltage_level); 2441 } 2442 2443 static void intel_pcode_notify(struct intel_display *display, 2444 u8 voltage_level, 2445 u8 active_pipe_count, 2446 u16 cdclk, 2447 bool cdclk_update_valid, 2448 bool pipe_count_update_valid) 2449 { 2450 struct drm_i915_private *i915 = to_i915(display->drm); 2451 int ret; 2452 u32 update_mask = 0; 2453 2454 if (!IS_DG2(i915)) 2455 return; 2456 2457 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2458 2459 if (cdclk_update_valid) 2460 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2461 2462 if (pipe_count_update_valid) 2463 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2464 2465 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL, 2466 SKL_CDCLK_PREPARE_FOR_CHANGE | 2467 update_mask, 2468 SKL_CDCLK_READY_FOR_CHANGE, 2469 SKL_CDCLK_READY_FOR_CHANGE, 3); 2470 if (ret) 2471 drm_err(display->drm, 2472 "Failed to inform PCU about display config (err %d)\n", 2473 ret); 2474 } 2475 2476 static void intel_set_cdclk(struct intel_display *display, 2477 const struct intel_cdclk_config *cdclk_config, 2478 enum pipe pipe, const char *context) 2479 { 2480 struct drm_i915_private *dev_priv = to_i915(display->drm); 2481 struct intel_encoder *encoder; 2482 2483 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) 2484 return; 2485 2486 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) 2487 return; 2488 2489 intel_cdclk_dump_config(display, cdclk_config, context); 2490 2491 for_each_intel_encoder_with_psr(display->drm, encoder) { 2492 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2493 2494 intel_psr_pause(intel_dp); 2495 } 2496 2497 intel_audio_cdclk_change_pre(dev_priv); 2498 2499 /* 2500 * Lock aux/gmbus while we change cdclk in case those 2501 * functions use cdclk. Not all platforms/ports do, 2502 * but we'll lock them all for simplicity. 2503 */ 2504 mutex_lock(&display->gmbus.mutex); 2505 for_each_intel_dp(display->drm, encoder) { 2506 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2507 2508 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2509 &display->gmbus.mutex); 2510 } 2511 2512 intel_cdclk_set_cdclk(display, cdclk_config, pipe); 2513 2514 for_each_intel_dp(display->drm, encoder) { 2515 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2516 2517 mutex_unlock(&intel_dp->aux.hw_mutex); 2518 } 2519 mutex_unlock(&display->gmbus.mutex); 2520 2521 for_each_intel_encoder_with_psr(display->drm, encoder) { 2522 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2523 2524 intel_psr_resume(intel_dp); 2525 } 2526 2527 intel_audio_cdclk_change_post(dev_priv); 2528 2529 if (drm_WARN(display->drm, 2530 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), 2531 "cdclk state doesn't match!\n")) { 2532 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); 2533 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); 2534 } 2535 } 2536 2537 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2538 { 2539 struct intel_display *display = to_intel_display(state); 2540 const struct intel_cdclk_state *old_cdclk_state = 2541 intel_atomic_get_old_cdclk_state(state); 2542 const struct intel_cdclk_state *new_cdclk_state = 2543 intel_atomic_get_new_cdclk_state(state); 2544 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2545 bool change_cdclk, update_pipe_count; 2546 2547 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2548 &new_cdclk_state->actual) && 2549 new_cdclk_state->active_pipes == 2550 old_cdclk_state->active_pipes) 2551 return; 2552 2553 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2554 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2555 2556 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2557 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > 2558 hweight8(old_cdclk_state->active_pipes); 2559 2560 /* 2561 * According to "Sequence Before Frequency Change", 2562 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2563 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2564 * which basically means we choose the maximum of old and new CDCLK, if we know both 2565 */ 2566 if (change_cdclk) 2567 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2568 2569 /* 2570 * According to "Sequence For Pipe Count Change", 2571 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2572 * (power well is enabled) 2573 * no action if it is decreasing, before the change 2574 */ 2575 if (update_pipe_count) 2576 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2577 2578 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2579 change_cdclk, update_pipe_count); 2580 } 2581 2582 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2583 { 2584 struct intel_display *display = to_intel_display(state); 2585 const struct intel_cdclk_state *new_cdclk_state = 2586 intel_atomic_get_new_cdclk_state(state); 2587 const struct intel_cdclk_state *old_cdclk_state = 2588 intel_atomic_get_old_cdclk_state(state); 2589 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2590 bool update_cdclk, update_pipe_count; 2591 2592 /* According to "Sequence After Frequency Change", set voltage to used level */ 2593 voltage_level = new_cdclk_state->actual.voltage_level; 2594 2595 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2596 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < 2597 hweight8(old_cdclk_state->active_pipes); 2598 2599 /* 2600 * According to "Sequence After Frequency Change", 2601 * set bits 25:16 to current CDCLK 2602 */ 2603 if (update_cdclk) 2604 cdclk = new_cdclk_state->actual.cdclk; 2605 2606 /* 2607 * According to "Sequence For Pipe Count Change", 2608 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2609 * after the change(power well is disabled) 2610 * no action if it is increasing, after the change 2611 */ 2612 if (update_pipe_count) 2613 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2614 2615 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2616 update_cdclk, update_pipe_count); 2617 } 2618 2619 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2620 { 2621 const struct intel_cdclk_state *old_cdclk_state = 2622 intel_atomic_get_old_cdclk_state(state); 2623 const struct intel_cdclk_state *new_cdclk_state = 2624 intel_atomic_get_new_cdclk_state(state); 2625 2626 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2627 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2628 } 2629 2630 /** 2631 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2632 * @state: intel atomic state 2633 * 2634 * Program the hardware before updating the HW plane state based on the 2635 * new CDCLK state, if necessary. 2636 */ 2637 void 2638 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2639 { 2640 struct intel_display *display = to_intel_display(state); 2641 struct drm_i915_private *i915 = to_i915(display->drm); 2642 const struct intel_cdclk_state *old_cdclk_state = 2643 intel_atomic_get_old_cdclk_state(state); 2644 const struct intel_cdclk_state *new_cdclk_state = 2645 intel_atomic_get_new_cdclk_state(state); 2646 struct intel_cdclk_config cdclk_config; 2647 enum pipe pipe; 2648 2649 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2650 &new_cdclk_state->actual)) 2651 return; 2652 2653 if (IS_DG2(i915)) 2654 intel_cdclk_pcode_pre_notify(state); 2655 2656 if (new_cdclk_state->disable_pipes) { 2657 cdclk_config = new_cdclk_state->actual; 2658 pipe = INVALID_PIPE; 2659 } else { 2660 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2661 cdclk_config = new_cdclk_state->actual; 2662 pipe = new_cdclk_state->pipe; 2663 } else { 2664 cdclk_config = old_cdclk_state->actual; 2665 pipe = INVALID_PIPE; 2666 } 2667 2668 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2669 old_cdclk_state->actual.voltage_level); 2670 } 2671 2672 /* 2673 * mbus joining will be changed later by 2674 * intel_dbuf_mbus_{pre,post}_ddb_update() 2675 */ 2676 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2677 2678 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2679 2680 intel_set_cdclk(display, &cdclk_config, pipe, 2681 "Pre changing CDCLK to"); 2682 } 2683 2684 /** 2685 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2686 * @state: intel atomic state 2687 * 2688 * Program the hardware after updating the HW plane state based on the 2689 * new CDCLK state, if necessary. 2690 */ 2691 void 2692 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2693 { 2694 struct intel_display *display = to_intel_display(state); 2695 struct drm_i915_private *i915 = to_i915(display->drm); 2696 const struct intel_cdclk_state *old_cdclk_state = 2697 intel_atomic_get_old_cdclk_state(state); 2698 const struct intel_cdclk_state *new_cdclk_state = 2699 intel_atomic_get_new_cdclk_state(state); 2700 enum pipe pipe; 2701 2702 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2703 &new_cdclk_state->actual)) 2704 return; 2705 2706 if (IS_DG2(i915)) 2707 intel_cdclk_pcode_post_notify(state); 2708 2709 if (!new_cdclk_state->disable_pipes && 2710 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2711 pipe = new_cdclk_state->pipe; 2712 else 2713 pipe = INVALID_PIPE; 2714 2715 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2716 2717 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, 2718 "Post changing CDCLK to"); 2719 } 2720 2721 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2722 { 2723 struct intel_display *display = to_intel_display(crtc_state); 2724 struct drm_i915_private *dev_priv = to_i915(display->drm); 2725 int pixel_rate = crtc_state->pixel_rate; 2726 2727 if (DISPLAY_VER(display) >= 10) 2728 return DIV_ROUND_UP(pixel_rate, 2); 2729 else if (DISPLAY_VER(display) == 9 || 2730 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2731 return pixel_rate; 2732 else if (IS_CHERRYVIEW(dev_priv)) 2733 return DIV_ROUND_UP(pixel_rate * 100, 95); 2734 else if (crtc_state->double_wide) 2735 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2736 else 2737 return DIV_ROUND_UP(pixel_rate * 100, 90); 2738 } 2739 2740 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2741 { 2742 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2743 struct intel_display *display = to_intel_display(crtc); 2744 struct intel_plane *plane; 2745 int min_cdclk = 0; 2746 2747 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2748 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2749 2750 return min_cdclk; 2751 } 2752 2753 static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) 2754 { 2755 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2756 struct intel_display *display = to_intel_display(crtc); 2757 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 2758 int min_cdclk = 0; 2759 2760 /* 2761 * When we decide to use only one VDSC engine, since 2762 * each VDSC operates with 1 ppc throughput, pixel clock 2763 * cannot be higher than the VDSC clock (cdclk) 2764 * If there 2 VDSC engines, then pixel clock can't be higher than 2765 * VDSC clock(cdclk) * 2 and so on. 2766 */ 2767 min_cdclk = max_t(int, min_cdclk, 2768 DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances)); 2769 2770 if (crtc_state->joiner_pipes) { 2771 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); 2772 2773 /* 2774 * According to Bigjoiner bw check: 2775 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock 2776 * 2777 * We have already computed compressed_bpp, so now compute the min CDCLK that 2778 * is required to support this compressed_bpp. 2779 * 2780 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) 2781 * 2782 * Since PPC = 2 with bigjoiner 2783 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits 2784 */ 2785 int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24; 2786 int min_cdclk_bj = 2787 (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * 2788 pixel_clock) / (2 * bigjoiner_interface_bits); 2789 2790 min_cdclk = max(min_cdclk, min_cdclk_bj); 2791 } 2792 2793 return min_cdclk; 2794 } 2795 2796 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2797 { 2798 struct intel_display *display = to_intel_display(crtc_state); 2799 struct drm_i915_private *dev_priv = to_i915(display->drm); 2800 int min_cdclk; 2801 2802 if (!crtc_state->hw.enable) 2803 return 0; 2804 2805 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2806 2807 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2808 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2809 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2810 2811 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2812 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2813 * there may be audio corruption or screen corruption." This cdclk 2814 * restriction for GLK is 316.8 MHz. 2815 */ 2816 if (intel_crtc_has_dp_encoder(crtc_state) && 2817 crtc_state->has_audio && 2818 crtc_state->port_clock >= 540000 && 2819 crtc_state->lane_count == 4) { 2820 if (DISPLAY_VER(display) == 10) { 2821 /* Display WA #1145: glk */ 2822 min_cdclk = max(316800, min_cdclk); 2823 } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) { 2824 /* Display WA #1144: skl,bxt */ 2825 min_cdclk = max(432000, min_cdclk); 2826 } 2827 } 2828 2829 /* 2830 * According to BSpec, "The CD clock frequency must be at least twice 2831 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2832 */ 2833 if (crtc_state->has_audio && DISPLAY_VER(display) >= 9) 2834 min_cdclk = max(2 * 96000, min_cdclk); 2835 2836 /* 2837 * "For DP audio configuration, cdclk frequency shall be set to 2838 * meet the following requirements: 2839 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2840 * 270 | 320 or higher 2841 * 162 | 200 or higher" 2842 */ 2843 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2844 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2845 min_cdclk = max(crtc_state->port_clock, min_cdclk); 2846 2847 /* 2848 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2849 * than 320000KHz. 2850 */ 2851 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2852 IS_VALLEYVIEW(dev_priv)) 2853 min_cdclk = max(320000, min_cdclk); 2854 2855 /* 2856 * On Geminilake once the CDCLK gets as low as 79200 2857 * picture gets unstable, despite that values are 2858 * correct for DSI PLL and DE PLL. 2859 */ 2860 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2861 IS_GEMINILAKE(dev_priv)) 2862 min_cdclk = max(158400, min_cdclk); 2863 2864 /* Account for additional needs from the planes */ 2865 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2866 2867 if (crtc_state->dsc.compression_enable) 2868 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2869 2870 return min_cdclk; 2871 } 2872 2873 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 2874 { 2875 struct intel_display *display = to_intel_display(state); 2876 struct drm_i915_private *dev_priv = to_i915(display->drm); 2877 struct intel_cdclk_state *cdclk_state = 2878 intel_atomic_get_new_cdclk_state(state); 2879 const struct intel_bw_state *bw_state; 2880 struct intel_crtc *crtc; 2881 struct intel_crtc_state *crtc_state; 2882 int min_cdclk, i; 2883 enum pipe pipe; 2884 2885 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2886 int ret; 2887 2888 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2889 if (min_cdclk < 0) 2890 return min_cdclk; 2891 2892 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2893 continue; 2894 2895 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2896 2897 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2898 if (ret) 2899 return ret; 2900 } 2901 2902 bw_state = intel_atomic_get_new_bw_state(state); 2903 if (bw_state) { 2904 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); 2905 2906 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2907 int ret; 2908 2909 cdclk_state->bw_min_cdclk = min_cdclk; 2910 2911 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2912 if (ret) 2913 return ret; 2914 } 2915 } 2916 2917 min_cdclk = max(cdclk_state->force_min_cdclk, 2918 cdclk_state->bw_min_cdclk); 2919 for_each_pipe(display, pipe) 2920 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2921 2922 /* 2923 * Avoid glk_force_audio_cdclk() causing excessive screen 2924 * blinking when multiple pipes are active by making sure 2925 * CDCLK frequency is always high enough for audio. With a 2926 * single active pipe we can always change CDCLK frequency 2927 * by changing the cd2x divider (see glk_cdclk_table[]) and 2928 * thus a full modeset won't be needed then. 2929 */ 2930 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && 2931 !is_power_of_2(cdclk_state->active_pipes)) 2932 min_cdclk = max(2 * 96000, min_cdclk); 2933 2934 if (min_cdclk > display->cdclk.max_cdclk_freq) { 2935 drm_dbg_kms(display->drm, 2936 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2937 min_cdclk, display->cdclk.max_cdclk_freq); 2938 return -EINVAL; 2939 } 2940 2941 return min_cdclk; 2942 } 2943 2944 /* 2945 * Account for port clock min voltage level requirements. 2946 * This only really does something on DISPLA_VER >= 11 but can be 2947 * called on earlier platforms as well. 2948 * 2949 * Note that this functions assumes that 0 is 2950 * the lowest voltage value, and higher values 2951 * correspond to increasingly higher voltages. 2952 * 2953 * Should that relationship no longer hold on 2954 * future platforms this code will need to be 2955 * adjusted. 2956 */ 2957 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 2958 { 2959 struct intel_display *display = to_intel_display(state); 2960 struct intel_cdclk_state *cdclk_state = 2961 intel_atomic_get_new_cdclk_state(state); 2962 struct intel_crtc *crtc; 2963 struct intel_crtc_state *crtc_state; 2964 u8 min_voltage_level; 2965 int i; 2966 enum pipe pipe; 2967 2968 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2969 int ret; 2970 2971 if (crtc_state->hw.enable) 2972 min_voltage_level = crtc_state->min_voltage_level; 2973 else 2974 min_voltage_level = 0; 2975 2976 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2977 continue; 2978 2979 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2980 2981 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2982 if (ret) 2983 return ret; 2984 } 2985 2986 min_voltage_level = 0; 2987 for_each_pipe(display, pipe) 2988 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2989 min_voltage_level); 2990 2991 return min_voltage_level; 2992 } 2993 2994 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 2995 { 2996 struct intel_display *display = to_intel_display(state); 2997 struct intel_cdclk_state *cdclk_state = 2998 intel_atomic_get_new_cdclk_state(state); 2999 int min_cdclk, cdclk; 3000 3001 min_cdclk = intel_compute_min_cdclk(state); 3002 if (min_cdclk < 0) 3003 return min_cdclk; 3004 3005 cdclk = vlv_calc_cdclk(display, min_cdclk); 3006 3007 cdclk_state->logical.cdclk = cdclk; 3008 cdclk_state->logical.voltage_level = 3009 vlv_calc_voltage_level(display, cdclk); 3010 3011 if (!cdclk_state->active_pipes) { 3012 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); 3013 3014 cdclk_state->actual.cdclk = cdclk; 3015 cdclk_state->actual.voltage_level = 3016 vlv_calc_voltage_level(display, cdclk); 3017 } else { 3018 cdclk_state->actual = cdclk_state->logical; 3019 } 3020 3021 return 0; 3022 } 3023 3024 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 3025 { 3026 struct intel_cdclk_state *cdclk_state = 3027 intel_atomic_get_new_cdclk_state(state); 3028 int min_cdclk, cdclk; 3029 3030 min_cdclk = intel_compute_min_cdclk(state); 3031 if (min_cdclk < 0) 3032 return min_cdclk; 3033 3034 cdclk = bdw_calc_cdclk(min_cdclk); 3035 3036 cdclk_state->logical.cdclk = cdclk; 3037 cdclk_state->logical.voltage_level = 3038 bdw_calc_voltage_level(cdclk); 3039 3040 if (!cdclk_state->active_pipes) { 3041 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 3042 3043 cdclk_state->actual.cdclk = cdclk; 3044 cdclk_state->actual.voltage_level = 3045 bdw_calc_voltage_level(cdclk); 3046 } else { 3047 cdclk_state->actual = cdclk_state->logical; 3048 } 3049 3050 return 0; 3051 } 3052 3053 static int skl_dpll0_vco(struct intel_atomic_state *state) 3054 { 3055 struct intel_display *display = to_intel_display(state); 3056 struct intel_cdclk_state *cdclk_state = 3057 intel_atomic_get_new_cdclk_state(state); 3058 struct intel_crtc *crtc; 3059 struct intel_crtc_state *crtc_state; 3060 int vco, i; 3061 3062 vco = cdclk_state->logical.vco; 3063 if (!vco) 3064 vco = display->cdclk.skl_preferred_vco_freq; 3065 3066 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 3067 if (!crtc_state->hw.enable) 3068 continue; 3069 3070 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3071 continue; 3072 3073 /* 3074 * DPLL0 VCO may need to be adjusted to get the correct 3075 * clock for eDP. This will affect cdclk as well. 3076 */ 3077 switch (crtc_state->port_clock / 2) { 3078 case 108000: 3079 case 216000: 3080 vco = 8640000; 3081 break; 3082 default: 3083 vco = 8100000; 3084 break; 3085 } 3086 } 3087 3088 return vco; 3089 } 3090 3091 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3092 { 3093 struct intel_cdclk_state *cdclk_state = 3094 intel_atomic_get_new_cdclk_state(state); 3095 int min_cdclk, cdclk, vco; 3096 3097 min_cdclk = intel_compute_min_cdclk(state); 3098 if (min_cdclk < 0) 3099 return min_cdclk; 3100 3101 vco = skl_dpll0_vco(state); 3102 3103 cdclk = skl_calc_cdclk(min_cdclk, vco); 3104 3105 cdclk_state->logical.vco = vco; 3106 cdclk_state->logical.cdclk = cdclk; 3107 cdclk_state->logical.voltage_level = 3108 skl_calc_voltage_level(cdclk); 3109 3110 if (!cdclk_state->active_pipes) { 3111 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3112 3113 cdclk_state->actual.vco = vco; 3114 cdclk_state->actual.cdclk = cdclk; 3115 cdclk_state->actual.voltage_level = 3116 skl_calc_voltage_level(cdclk); 3117 } else { 3118 cdclk_state->actual = cdclk_state->logical; 3119 } 3120 3121 return 0; 3122 } 3123 3124 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3125 { 3126 struct intel_display *display = to_intel_display(state); 3127 struct intel_cdclk_state *cdclk_state = 3128 intel_atomic_get_new_cdclk_state(state); 3129 int min_cdclk, min_voltage_level, cdclk, vco; 3130 3131 min_cdclk = intel_compute_min_cdclk(state); 3132 if (min_cdclk < 0) 3133 return min_cdclk; 3134 3135 min_voltage_level = bxt_compute_min_voltage_level(state); 3136 if (min_voltage_level < 0) 3137 return min_voltage_level; 3138 3139 cdclk = bxt_calc_cdclk(display, min_cdclk); 3140 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3141 3142 cdclk_state->logical.vco = vco; 3143 cdclk_state->logical.cdclk = cdclk; 3144 cdclk_state->logical.voltage_level = 3145 max_t(int, min_voltage_level, 3146 intel_cdclk_calc_voltage_level(display, cdclk)); 3147 3148 if (!cdclk_state->active_pipes) { 3149 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); 3150 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3151 3152 cdclk_state->actual.vco = vco; 3153 cdclk_state->actual.cdclk = cdclk; 3154 cdclk_state->actual.voltage_level = 3155 intel_cdclk_calc_voltage_level(display, cdclk); 3156 } else { 3157 cdclk_state->actual = cdclk_state->logical; 3158 } 3159 3160 return 0; 3161 } 3162 3163 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3164 { 3165 int min_cdclk; 3166 3167 /* 3168 * We can't change the cdclk frequency, but we still want to 3169 * check that the required minimum frequency doesn't exceed 3170 * the actual cdclk frequency. 3171 */ 3172 min_cdclk = intel_compute_min_cdclk(state); 3173 if (min_cdclk < 0) 3174 return min_cdclk; 3175 3176 return 0; 3177 } 3178 3179 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3180 { 3181 struct intel_cdclk_state *cdclk_state; 3182 3183 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3184 if (!cdclk_state) 3185 return NULL; 3186 3187 cdclk_state->pipe = INVALID_PIPE; 3188 cdclk_state->disable_pipes = false; 3189 3190 return &cdclk_state->base; 3191 } 3192 3193 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3194 struct intel_global_state *state) 3195 { 3196 kfree(state); 3197 } 3198 3199 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3200 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3201 .atomic_destroy_state = intel_cdclk_destroy_state, 3202 }; 3203 3204 struct intel_cdclk_state * 3205 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3206 { 3207 struct intel_display *display = to_intel_display(state); 3208 struct intel_global_state *cdclk_state; 3209 3210 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); 3211 if (IS_ERR(cdclk_state)) 3212 return ERR_CAST(cdclk_state); 3213 3214 return to_intel_cdclk_state(cdclk_state); 3215 } 3216 3217 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 3218 bool *need_cdclk_calc) 3219 { 3220 const struct intel_cdclk_state *old_cdclk_state; 3221 const struct intel_cdclk_state *new_cdclk_state; 3222 struct intel_plane_state __maybe_unused *plane_state; 3223 struct intel_plane *plane; 3224 int ret; 3225 int i; 3226 3227 /* 3228 * active_planes bitmask has been updated, and potentially affected 3229 * planes are part of the state. We can now compute the minimum cdclk 3230 * for each plane. 3231 */ 3232 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 3233 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 3234 if (ret) 3235 return ret; 3236 } 3237 3238 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 3239 if (ret) 3240 return ret; 3241 3242 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3243 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3244 3245 if (new_cdclk_state && 3246 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 3247 *need_cdclk_calc = true; 3248 3249 return 0; 3250 } 3251 3252 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3253 { 3254 struct intel_cdclk_state *cdclk_state; 3255 3256 cdclk_state = intel_atomic_get_cdclk_state(state); 3257 if (IS_ERR(cdclk_state)) 3258 return PTR_ERR(cdclk_state); 3259 3260 cdclk_state->actual.joined_mbus = joined_mbus; 3261 cdclk_state->logical.joined_mbus = joined_mbus; 3262 3263 return intel_atomic_lock_global_state(&cdclk_state->base); 3264 } 3265 3266 int intel_cdclk_init(struct intel_display *display) 3267 { 3268 struct drm_i915_private *dev_priv = to_i915(display->drm); 3269 struct intel_cdclk_state *cdclk_state; 3270 3271 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 3272 if (!cdclk_state) 3273 return -ENOMEM; 3274 3275 intel_atomic_global_obj_init(dev_priv, &display->cdclk.obj, 3276 &cdclk_state->base, &intel_cdclk_funcs); 3277 3278 return 0; 3279 } 3280 3281 static bool intel_cdclk_need_serialize(struct intel_display *display, 3282 const struct intel_cdclk_state *old_cdclk_state, 3283 const struct intel_cdclk_state *new_cdclk_state) 3284 { 3285 struct drm_i915_private *i915 = to_i915(display->drm); 3286 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != 3287 hweight8(new_cdclk_state->active_pipes); 3288 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, 3289 &new_cdclk_state->actual); 3290 /* 3291 * We need to poke hw for gen >= 12, because we notify PCode if 3292 * pipe power well count changes. 3293 */ 3294 return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed); 3295 } 3296 3297 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3298 { 3299 struct intel_display *display = to_intel_display(state); 3300 const struct intel_cdclk_state *old_cdclk_state; 3301 struct intel_cdclk_state *new_cdclk_state; 3302 enum pipe pipe = INVALID_PIPE; 3303 int ret; 3304 3305 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3306 if (IS_ERR(new_cdclk_state)) 3307 return PTR_ERR(new_cdclk_state); 3308 3309 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3310 3311 new_cdclk_state->active_pipes = 3312 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3313 3314 ret = intel_cdclk_modeset_calc_cdclk(state); 3315 if (ret) 3316 return ret; 3317 3318 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { 3319 /* 3320 * Also serialize commits across all crtcs 3321 * if the actual hw needs to be poked. 3322 */ 3323 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3324 if (ret) 3325 return ret; 3326 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 3327 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 3328 intel_cdclk_changed(&old_cdclk_state->logical, 3329 &new_cdclk_state->logical)) { 3330 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3331 if (ret) 3332 return ret; 3333 } else { 3334 return 0; 3335 } 3336 3337 if (is_power_of_2(new_cdclk_state->active_pipes) && 3338 intel_cdclk_can_cd2x_update(display, 3339 &old_cdclk_state->actual, 3340 &new_cdclk_state->actual)) { 3341 struct intel_crtc *crtc; 3342 struct intel_crtc_state *crtc_state; 3343 3344 pipe = ilog2(new_cdclk_state->active_pipes); 3345 crtc = intel_crtc_for_pipe(display, pipe); 3346 3347 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3348 if (IS_ERR(crtc_state)) 3349 return PTR_ERR(crtc_state); 3350 3351 if (intel_crtc_needs_modeset(crtc_state)) 3352 pipe = INVALID_PIPE; 3353 } 3354 3355 if (intel_cdclk_can_crawl_and_squash(display, 3356 &old_cdclk_state->actual, 3357 &new_cdclk_state->actual)) { 3358 drm_dbg_kms(display->drm, 3359 "Can change cdclk via crawling and squashing\n"); 3360 } else if (intel_cdclk_can_squash(display, 3361 &old_cdclk_state->actual, 3362 &new_cdclk_state->actual)) { 3363 drm_dbg_kms(display->drm, 3364 "Can change cdclk via squashing\n"); 3365 } else if (intel_cdclk_can_crawl(display, 3366 &old_cdclk_state->actual, 3367 &new_cdclk_state->actual)) { 3368 drm_dbg_kms(display->drm, 3369 "Can change cdclk via crawling\n"); 3370 } else if (pipe != INVALID_PIPE) { 3371 new_cdclk_state->pipe = pipe; 3372 3373 drm_dbg_kms(display->drm, 3374 "Can change cdclk cd2x divider with pipe %c active\n", 3375 pipe_name(pipe)); 3376 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3377 &new_cdclk_state->actual)) { 3378 /* All pipes must be switched off while we change the cdclk. */ 3379 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3380 if (ret) 3381 return ret; 3382 3383 new_cdclk_state->disable_pipes = true; 3384 3385 drm_dbg_kms(display->drm, 3386 "Modeset required for cdclk change\n"); 3387 } 3388 3389 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != 3390 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { 3391 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); 3392 3393 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3394 if (ret) 3395 return ret; 3396 } 3397 3398 drm_dbg_kms(display->drm, 3399 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3400 new_cdclk_state->logical.cdclk, 3401 new_cdclk_state->actual.cdclk); 3402 drm_dbg_kms(display->drm, 3403 "New voltage level calculated to be logical %u, actual %u\n", 3404 new_cdclk_state->logical.voltage_level, 3405 new_cdclk_state->actual.voltage_level); 3406 3407 return 0; 3408 } 3409 3410 static int intel_compute_max_dotclk(struct intel_display *display) 3411 { 3412 struct drm_i915_private *dev_priv = to_i915(display->drm); 3413 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3414 3415 if (DISPLAY_VER(display) >= 10) 3416 return 2 * max_cdclk_freq; 3417 else if (DISPLAY_VER(display) == 9 || 3418 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3419 return max_cdclk_freq; 3420 else if (IS_CHERRYVIEW(dev_priv)) 3421 return max_cdclk_freq*95/100; 3422 else if (DISPLAY_VER(display) < 4) 3423 return 2*max_cdclk_freq*90/100; 3424 else 3425 return max_cdclk_freq*90/100; 3426 } 3427 3428 /** 3429 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3430 * @display: display instance 3431 * 3432 * Determine the maximum CDCLK frequency the platform supports, and also 3433 * derive the maximum dot clock frequency the maximum CDCLK frequency 3434 * allows. 3435 */ 3436 void intel_update_max_cdclk(struct intel_display *display) 3437 { 3438 struct drm_i915_private *dev_priv = to_i915(display->drm); 3439 3440 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 3441 if (display->cdclk.hw.ref == 24000) 3442 display->cdclk.max_cdclk_freq = 552000; 3443 else 3444 display->cdclk.max_cdclk_freq = 556800; 3445 } else if (DISPLAY_VER(display) >= 11) { 3446 if (display->cdclk.hw.ref == 24000) 3447 display->cdclk.max_cdclk_freq = 648000; 3448 else 3449 display->cdclk.max_cdclk_freq = 652800; 3450 } else if (IS_GEMINILAKE(dev_priv)) { 3451 display->cdclk.max_cdclk_freq = 316800; 3452 } else if (IS_BROXTON(dev_priv)) { 3453 display->cdclk.max_cdclk_freq = 624000; 3454 } else if (DISPLAY_VER(display) == 9) { 3455 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3456 int max_cdclk, vco; 3457 3458 vco = display->cdclk.skl_preferred_vco_freq; 3459 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 3460 3461 /* 3462 * Use the lower (vco 8640) cdclk values as a 3463 * first guess. skl_calc_cdclk() will correct it 3464 * if the preferred vco is 8100 instead. 3465 */ 3466 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3467 max_cdclk = 617143; 3468 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3469 max_cdclk = 540000; 3470 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3471 max_cdclk = 432000; 3472 else 3473 max_cdclk = 308571; 3474 3475 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3476 } else if (IS_BROADWELL(dev_priv)) { 3477 /* 3478 * FIXME with extra cooling we can allow 3479 * 540 MHz for ULX and 675 Mhz for ULT. 3480 * How can we know if extra cooling is 3481 * available? PCI ID, VTB, something else? 3482 */ 3483 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3484 display->cdclk.max_cdclk_freq = 450000; 3485 else if (IS_BROADWELL_ULX(dev_priv)) 3486 display->cdclk.max_cdclk_freq = 450000; 3487 else if (IS_BROADWELL_ULT(dev_priv)) 3488 display->cdclk.max_cdclk_freq = 540000; 3489 else 3490 display->cdclk.max_cdclk_freq = 675000; 3491 } else if (IS_CHERRYVIEW(dev_priv)) { 3492 display->cdclk.max_cdclk_freq = 320000; 3493 } else if (IS_VALLEYVIEW(dev_priv)) { 3494 display->cdclk.max_cdclk_freq = 400000; 3495 } else { 3496 /* otherwise assume cdclk is fixed */ 3497 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; 3498 } 3499 3500 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); 3501 3502 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", 3503 display->cdclk.max_cdclk_freq); 3504 3505 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", 3506 display->cdclk.max_dotclk_freq); 3507 } 3508 3509 /** 3510 * intel_update_cdclk - Determine the current CDCLK frequency 3511 * @display: display instance 3512 * 3513 * Determine the current CDCLK frequency. 3514 */ 3515 void intel_update_cdclk(struct intel_display *display) 3516 { 3517 struct drm_i915_private *dev_priv = to_i915(display->drm); 3518 3519 intel_cdclk_get_cdclk(display, &display->cdclk.hw); 3520 3521 /* 3522 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3523 * Programmng [sic] note: bit[9:2] should be programmed to the number 3524 * of cdclk that generates 4MHz reference clock freq which is used to 3525 * generate GMBus clock. This will vary with the cdclk freq. 3526 */ 3527 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3528 intel_de_write(display, GMBUSFREQ_VLV, 3529 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); 3530 } 3531 3532 static int dg1_rawclk(struct intel_display *display) 3533 { 3534 /* 3535 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3536 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3537 */ 3538 intel_de_write(display, PCH_RAWCLK_FREQ, 3539 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3540 3541 return 38400; 3542 } 3543 3544 static int cnp_rawclk(struct intel_display *display) 3545 { 3546 struct drm_i915_private *dev_priv = to_i915(display->drm); 3547 int divider, fraction; 3548 u32 rawclk; 3549 3550 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3551 /* 24 MHz */ 3552 divider = 24000; 3553 fraction = 0; 3554 } else { 3555 /* 19.2 MHz */ 3556 divider = 19000; 3557 fraction = 200; 3558 } 3559 3560 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3561 if (fraction) { 3562 int numerator = 1; 3563 3564 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3565 fraction) - 1); 3566 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3567 rawclk |= ICP_RAWCLK_NUM(numerator); 3568 } 3569 3570 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); 3571 return divider + fraction; 3572 } 3573 3574 static int pch_rawclk(struct intel_display *display) 3575 { 3576 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3577 } 3578 3579 static int vlv_hrawclk(struct intel_display *display) 3580 { 3581 struct drm_i915_private *dev_priv = to_i915(display->drm); 3582 3583 /* RAWCLK_FREQ_VLV register updated from power well code */ 3584 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", 3585 CCK_DISPLAY_REF_CLOCK_CONTROL); 3586 } 3587 3588 static int i9xx_hrawclk(struct intel_display *display) 3589 { 3590 struct drm_i915_private *i915 = to_i915(display->drm); 3591 3592 /* hrawclock is 1/4 the FSB frequency */ 3593 return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); 3594 } 3595 3596 /** 3597 * intel_read_rawclk - Determine the current RAWCLK frequency 3598 * @display: display instance 3599 * 3600 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3601 * frequency clock so this needs to done only once. 3602 */ 3603 u32 intel_read_rawclk(struct intel_display *display) 3604 { 3605 struct drm_i915_private *dev_priv = to_i915(display->drm); 3606 u32 freq; 3607 3608 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) 3609 /* 3610 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3611 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3612 * not need to be programmed." 3613 */ 3614 freq = 38400; 3615 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 3616 freq = dg1_rawclk(display); 3617 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 3618 freq = cnp_rawclk(display); 3619 else if (HAS_PCH_SPLIT(dev_priv)) 3620 freq = pch_rawclk(display); 3621 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3622 freq = vlv_hrawclk(display); 3623 else if (DISPLAY_VER(display) >= 3) 3624 freq = i9xx_hrawclk(display); 3625 else 3626 /* no rawclk on other platforms, or no need to know it */ 3627 return 0; 3628 3629 return freq; 3630 } 3631 3632 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3633 { 3634 struct intel_display *display = m->private; 3635 3636 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); 3637 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); 3638 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); 3639 3640 return 0; 3641 } 3642 3643 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3644 3645 void intel_cdclk_debugfs_register(struct intel_display *display) 3646 { 3647 struct drm_minor *minor = display->drm->primary; 3648 3649 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, 3650 display, &i915_cdclk_info_fops); 3651 } 3652 3653 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3654 .get_cdclk = bxt_get_cdclk, 3655 .set_cdclk = bxt_set_cdclk, 3656 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3657 .calc_voltage_level = rplu_calc_voltage_level, 3658 }; 3659 3660 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3661 .get_cdclk = bxt_get_cdclk, 3662 .set_cdclk = bxt_set_cdclk, 3663 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3664 .calc_voltage_level = tgl_calc_voltage_level, 3665 }; 3666 3667 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3668 .get_cdclk = bxt_get_cdclk, 3669 .set_cdclk = bxt_set_cdclk, 3670 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3671 .calc_voltage_level = ehl_calc_voltage_level, 3672 }; 3673 3674 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3675 .get_cdclk = bxt_get_cdclk, 3676 .set_cdclk = bxt_set_cdclk, 3677 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3678 .calc_voltage_level = icl_calc_voltage_level, 3679 }; 3680 3681 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3682 .get_cdclk = bxt_get_cdclk, 3683 .set_cdclk = bxt_set_cdclk, 3684 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3685 .calc_voltage_level = bxt_calc_voltage_level, 3686 }; 3687 3688 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3689 .get_cdclk = skl_get_cdclk, 3690 .set_cdclk = skl_set_cdclk, 3691 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3692 }; 3693 3694 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3695 .get_cdclk = bdw_get_cdclk, 3696 .set_cdclk = bdw_set_cdclk, 3697 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3698 }; 3699 3700 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3701 .get_cdclk = vlv_get_cdclk, 3702 .set_cdclk = chv_set_cdclk, 3703 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3704 }; 3705 3706 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3707 .get_cdclk = vlv_get_cdclk, 3708 .set_cdclk = vlv_set_cdclk, 3709 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3710 }; 3711 3712 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3713 .get_cdclk = hsw_get_cdclk, 3714 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3715 }; 3716 3717 /* SNB, IVB, 965G, 945G */ 3718 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3719 .get_cdclk = fixed_400mhz_get_cdclk, 3720 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3721 }; 3722 3723 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3724 .get_cdclk = fixed_450mhz_get_cdclk, 3725 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3726 }; 3727 3728 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3729 .get_cdclk = gm45_get_cdclk, 3730 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3731 }; 3732 3733 /* G45 uses G33 */ 3734 3735 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3736 .get_cdclk = i965gm_get_cdclk, 3737 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3738 }; 3739 3740 /* i965G uses fixed 400 */ 3741 3742 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3743 .get_cdclk = pnv_get_cdclk, 3744 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3745 }; 3746 3747 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3748 .get_cdclk = g33_get_cdclk, 3749 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3750 }; 3751 3752 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3753 .get_cdclk = i945gm_get_cdclk, 3754 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3755 }; 3756 3757 /* i945G uses fixed 400 */ 3758 3759 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3760 .get_cdclk = i915gm_get_cdclk, 3761 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3762 }; 3763 3764 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3765 .get_cdclk = fixed_333mhz_get_cdclk, 3766 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3767 }; 3768 3769 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3770 .get_cdclk = fixed_266mhz_get_cdclk, 3771 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3772 }; 3773 3774 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3775 .get_cdclk = i85x_get_cdclk, 3776 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3777 }; 3778 3779 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3780 .get_cdclk = fixed_200mhz_get_cdclk, 3781 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3782 }; 3783 3784 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3785 .get_cdclk = fixed_133mhz_get_cdclk, 3786 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3787 }; 3788 3789 /** 3790 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3791 * @display: display instance 3792 */ 3793 void intel_init_cdclk_hooks(struct intel_display *display) 3794 { 3795 struct drm_i915_private *dev_priv = to_i915(display->drm); 3796 3797 if (DISPLAY_VER(display) >= 20) { 3798 display->funcs.cdclk = &rplu_cdclk_funcs; 3799 display->cdclk.table = xe2lpd_cdclk_table; 3800 } else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) { 3801 display->funcs.cdclk = &rplu_cdclk_funcs; 3802 display->cdclk.table = xe2hpd_cdclk_table; 3803 } else if (DISPLAY_VER(display) >= 14) { 3804 display->funcs.cdclk = &rplu_cdclk_funcs; 3805 display->cdclk.table = mtl_cdclk_table; 3806 } else if (IS_DG2(dev_priv)) { 3807 display->funcs.cdclk = &tgl_cdclk_funcs; 3808 display->cdclk.table = dg2_cdclk_table; 3809 } else if (IS_ALDERLAKE_P(dev_priv)) { 3810 /* Wa_22011320316:adl-p[a0] */ 3811 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { 3812 display->cdclk.table = adlp_a_step_cdclk_table; 3813 display->funcs.cdclk = &tgl_cdclk_funcs; 3814 } else if (IS_RAPTORLAKE_U(dev_priv)) { 3815 display->cdclk.table = rplu_cdclk_table; 3816 display->funcs.cdclk = &rplu_cdclk_funcs; 3817 } else { 3818 display->cdclk.table = adlp_cdclk_table; 3819 display->funcs.cdclk = &tgl_cdclk_funcs; 3820 } 3821 } else if (IS_ROCKETLAKE(dev_priv)) { 3822 display->funcs.cdclk = &tgl_cdclk_funcs; 3823 display->cdclk.table = rkl_cdclk_table; 3824 } else if (DISPLAY_VER(display) >= 12) { 3825 display->funcs.cdclk = &tgl_cdclk_funcs; 3826 display->cdclk.table = icl_cdclk_table; 3827 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 3828 display->funcs.cdclk = &ehl_cdclk_funcs; 3829 display->cdclk.table = icl_cdclk_table; 3830 } else if (DISPLAY_VER(display) >= 11) { 3831 display->funcs.cdclk = &icl_cdclk_funcs; 3832 display->cdclk.table = icl_cdclk_table; 3833 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 3834 display->funcs.cdclk = &bxt_cdclk_funcs; 3835 if (IS_GEMINILAKE(dev_priv)) 3836 display->cdclk.table = glk_cdclk_table; 3837 else 3838 display->cdclk.table = bxt_cdclk_table; 3839 } else if (DISPLAY_VER(display) == 9) { 3840 display->funcs.cdclk = &skl_cdclk_funcs; 3841 } else if (IS_BROADWELL(dev_priv)) { 3842 display->funcs.cdclk = &bdw_cdclk_funcs; 3843 } else if (IS_HASWELL(dev_priv)) { 3844 display->funcs.cdclk = &hsw_cdclk_funcs; 3845 } else if (IS_CHERRYVIEW(dev_priv)) { 3846 display->funcs.cdclk = &chv_cdclk_funcs; 3847 } else if (IS_VALLEYVIEW(dev_priv)) { 3848 display->funcs.cdclk = &vlv_cdclk_funcs; 3849 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { 3850 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3851 } else if (IS_IRONLAKE(dev_priv)) { 3852 display->funcs.cdclk = &ilk_cdclk_funcs; 3853 } else if (IS_GM45(dev_priv)) { 3854 display->funcs.cdclk = &gm45_cdclk_funcs; 3855 } else if (IS_G45(dev_priv)) { 3856 display->funcs.cdclk = &g33_cdclk_funcs; 3857 } else if (IS_I965GM(dev_priv)) { 3858 display->funcs.cdclk = &i965gm_cdclk_funcs; 3859 } else if (IS_I965G(dev_priv)) { 3860 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3861 } else if (IS_PINEVIEW(dev_priv)) { 3862 display->funcs.cdclk = &pnv_cdclk_funcs; 3863 } else if (IS_G33(dev_priv)) { 3864 display->funcs.cdclk = &g33_cdclk_funcs; 3865 } else if (IS_I945GM(dev_priv)) { 3866 display->funcs.cdclk = &i945gm_cdclk_funcs; 3867 } else if (IS_I945G(dev_priv)) { 3868 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3869 } else if (IS_I915GM(dev_priv)) { 3870 display->funcs.cdclk = &i915gm_cdclk_funcs; 3871 } else if (IS_I915G(dev_priv)) { 3872 display->funcs.cdclk = &i915g_cdclk_funcs; 3873 } else if (IS_I865G(dev_priv)) { 3874 display->funcs.cdclk = &i865g_cdclk_funcs; 3875 } else if (IS_I85X(dev_priv)) { 3876 display->funcs.cdclk = &i85x_cdclk_funcs; 3877 } else if (IS_I845G(dev_priv)) { 3878 display->funcs.cdclk = &i845g_cdclk_funcs; 3879 } else if (IS_I830(dev_priv)) { 3880 display->funcs.cdclk = &i830_cdclk_funcs; 3881 } 3882 3883 if (drm_WARN(display->drm, !display->funcs.cdclk, 3884 "Unknown platform. Assuming i830\n")) 3885 display->funcs.cdclk = &i830_cdclk_funcs; 3886 } 3887