1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/iopoll.h> 26 #include <linux/time.h> 27 28 #include <drm/drm_fixed.h> 29 #include <drm/drm_print.h> 30 31 #include "soc/intel_dram.h" 32 33 #include "hsw_ips.h" 34 #include "i915_drv.h" 35 #include "i915_reg.h" 36 #include "intel_atomic.h" 37 #include "intel_audio.h" 38 #include "intel_cdclk.h" 39 #include "intel_crtc.h" 40 #include "intel_dbuf_bw.h" 41 #include "intel_de.h" 42 #include "intel_display_regs.h" 43 #include "intel_display_types.h" 44 #include "intel_display_utils.h" 45 #include "intel_mchbar_regs.h" 46 #include "intel_pci_config.h" 47 #include "intel_pcode.h" 48 #include "intel_plane.h" 49 #include "intel_psr.h" 50 #include "intel_vdsc.h" 51 #include "skl_watermark.h" 52 #include "skl_watermark_regs.h" 53 #include "vlv_clock.h" 54 #include "vlv_dsi.h" 55 #include "vlv_sideband.h" 56 57 /** 58 * DOC: CDCLK / RAWCLK 59 * 60 * The display engine uses several different clocks to do its work. There 61 * are two main clocks involved that aren't directly related to the actual 62 * pixel clock or any symbol/bit clock of the actual output port. These 63 * are the core display clock (CDCLK) and RAWCLK. 64 * 65 * CDCLK clocks most of the display pipe logic, and thus its frequency 66 * must be high enough to support the rate at which pixels are flowing 67 * through the pipes. Downscaling must also be accounted as that increases 68 * the effective pixel rate. 69 * 70 * On several platforms the CDCLK frequency can be changed dynamically 71 * to minimize power consumption for a given display configuration. 72 * Typically changes to the CDCLK frequency require all the display pipes 73 * to be shut down while the frequency is being changed. 74 * 75 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 76 * DMC will not change the active CDCLK frequency however, so that part 77 * will still be performed by the driver directly. 78 * 79 * There are multiple components involved in the generation of the CDCLK 80 * frequency: 81 * 82 * - We have the CDCLK PLL, which generates an output clock based on a 83 * reference clock and a ratio parameter. 84 * - The CD2X Divider, which divides the output of the PLL based on a 85 * divisor selected from a set of pre-defined choices. 86 * - The CD2X Squasher, which further divides the output based on a 87 * waveform represented as a sequence of bits where each zero 88 * "squashes out" a clock cycle. 89 * - And, finally, a fixed divider that divides the output frequency by 2. 90 * 91 * As such, the resulting CDCLK frequency can be calculated with the 92 * following formula: 93 * 94 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 95 * 96 * , where vco is the frequency generated by the PLL; cd2x_div 97 * represents the CD2X Divider; sq_len and sq_div are the bit length 98 * and the number of high bits for the CD2X Squasher waveform, respectively; 99 * and 2 represents the fixed divider. 100 * 101 * Note that some older platforms do not contain the CD2X Divider 102 * and/or CD2X Squasher, in which case we can ignore their respective 103 * factors in the formula above. 104 * 105 * Several methods exist to change the CDCLK frequency, which ones are 106 * supported depends on the platform: 107 * 108 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 109 * - CD2X divider update. Single pipe can be active as the divider update 110 * can be synchronized with the pipe's start of vblank. 111 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 112 * - Squash waveform update. Pipes can be active. 113 * - Crawl and squash can also be done back to back. Pipes can be active. 114 * 115 * RAWCLK is a fixed frequency clock, often used by various auxiliary 116 * blocks such as AUX CH or backlight PWM. Hence the only thing we 117 * really need to know about RAWCLK is its frequency so that various 118 * dividers can be programmed correctly. 119 */ 120 121 struct intel_cdclk_state { 122 struct intel_global_state base; 123 124 /* 125 * Logical configuration of cdclk (used for all scaling, 126 * watermark, etc. calculations and checks). This is 127 * computed as if all enabled crtcs were active. 128 */ 129 struct intel_cdclk_config logical; 130 131 /* 132 * Actual configuration of cdclk, can be different from the 133 * logical configuration only when all crtc's are DPMS off. 134 */ 135 struct intel_cdclk_config actual; 136 137 /* minimum acceptable cdclk to satisfy DBUF bandwidth requirements */ 138 int dbuf_bw_min_cdclk; 139 /* minimum acceptable cdclk for each pipe */ 140 int min_cdclk[I915_MAX_PIPES]; 141 /* minimum acceptable voltage level for each pipe */ 142 u8 min_voltage_level[I915_MAX_PIPES]; 143 144 /* pipe to which cd2x update is synchronized */ 145 enum pipe pipe; 146 147 /* forced minimum cdclk for glk+ audio w/a */ 148 int force_min_cdclk; 149 150 /* bitmask of enabled pipes */ 151 u8 enabled_pipes; 152 153 /* bitmask of active pipes */ 154 u8 active_pipes; 155 156 /* update cdclk with pipes disabled */ 157 bool disable_pipes; 158 }; 159 160 struct intel_cdclk_funcs { 161 void (*get_cdclk)(struct intel_display *display, 162 struct intel_cdclk_config *cdclk_config); 163 void (*set_cdclk)(struct intel_display *display, 164 const struct intel_cdclk_config *cdclk_config, 165 enum pipe pipe); 166 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 167 u8 (*calc_voltage_level)(int cdclk); 168 }; 169 170 void intel_cdclk_get_cdclk(struct intel_display *display, 171 struct intel_cdclk_config *cdclk_config) 172 { 173 display->funcs.cdclk->get_cdclk(display, cdclk_config); 174 } 175 176 static void intel_cdclk_set_cdclk(struct intel_display *display, 177 const struct intel_cdclk_config *cdclk_config, 178 enum pipe pipe) 179 { 180 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); 181 } 182 183 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 184 { 185 struct intel_display *display = to_intel_display(state); 186 187 return display->funcs.cdclk->modeset_calc_cdclk(state); 188 } 189 190 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, 191 int cdclk) 192 { 193 return display->funcs.cdclk->calc_voltage_level(cdclk); 194 } 195 196 static void fixed_133mhz_get_cdclk(struct intel_display *display, 197 struct intel_cdclk_config *cdclk_config) 198 { 199 cdclk_config->cdclk = 133333; 200 } 201 202 static void fixed_200mhz_get_cdclk(struct intel_display *display, 203 struct intel_cdclk_config *cdclk_config) 204 { 205 cdclk_config->cdclk = 200000; 206 } 207 208 static void fixed_266mhz_get_cdclk(struct intel_display *display, 209 struct intel_cdclk_config *cdclk_config) 210 { 211 cdclk_config->cdclk = 266667; 212 } 213 214 static void fixed_333mhz_get_cdclk(struct intel_display *display, 215 struct intel_cdclk_config *cdclk_config) 216 { 217 cdclk_config->cdclk = 333333; 218 } 219 220 static void fixed_400mhz_get_cdclk(struct intel_display *display, 221 struct intel_cdclk_config *cdclk_config) 222 { 223 cdclk_config->cdclk = 400000; 224 } 225 226 static void fixed_450mhz_get_cdclk(struct intel_display *display, 227 struct intel_cdclk_config *cdclk_config) 228 { 229 cdclk_config->cdclk = 450000; 230 } 231 232 static void i85x_get_cdclk(struct intel_display *display, 233 struct intel_cdclk_config *cdclk_config) 234 { 235 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 236 u16 hpllcc = 0; 237 238 /* 239 * 852GM/852GMV only supports 133 MHz and the HPLLCC 240 * encoding is different :( 241 * FIXME is this the right way to detect 852GM/852GMV? 242 */ 243 if (pdev->revision == 0x1) { 244 cdclk_config->cdclk = 133333; 245 return; 246 } 247 248 pci_bus_read_config_word(pdev->bus, 249 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 250 251 /* Assume that the hardware is in the high speed state. This 252 * should be the default. 253 */ 254 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 255 case GC_CLOCK_133_200: 256 case GC_CLOCK_133_200_2: 257 case GC_CLOCK_100_200: 258 cdclk_config->cdclk = 200000; 259 break; 260 case GC_CLOCK_166_250: 261 cdclk_config->cdclk = 250000; 262 break; 263 case GC_CLOCK_100_133: 264 cdclk_config->cdclk = 133333; 265 break; 266 case GC_CLOCK_133_266: 267 case GC_CLOCK_133_266_2: 268 case GC_CLOCK_166_266: 269 cdclk_config->cdclk = 266667; 270 break; 271 } 272 } 273 274 static void i915gm_get_cdclk(struct intel_display *display, 275 struct intel_cdclk_config *cdclk_config) 276 { 277 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 278 u16 gcfgc = 0; 279 280 pci_read_config_word(pdev, GCFGC, &gcfgc); 281 282 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 283 cdclk_config->cdclk = 133333; 284 return; 285 } 286 287 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 288 case GC_DISPLAY_CLOCK_333_320_MHZ: 289 cdclk_config->cdclk = 333333; 290 break; 291 default: 292 case GC_DISPLAY_CLOCK_190_200_MHZ: 293 cdclk_config->cdclk = 190000; 294 break; 295 } 296 } 297 298 static void i945gm_get_cdclk(struct intel_display *display, 299 struct intel_cdclk_config *cdclk_config) 300 { 301 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 302 u16 gcfgc = 0; 303 304 pci_read_config_word(pdev, GCFGC, &gcfgc); 305 306 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 307 cdclk_config->cdclk = 133333; 308 return; 309 } 310 311 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 312 case GC_DISPLAY_CLOCK_333_320_MHZ: 313 cdclk_config->cdclk = 320000; 314 break; 315 default: 316 case GC_DISPLAY_CLOCK_190_200_MHZ: 317 cdclk_config->cdclk = 200000; 318 break; 319 } 320 } 321 322 static unsigned int intel_hpll_vco(struct intel_display *display) 323 { 324 static const unsigned int blb_vco[8] = { 325 [0] = 3200000, 326 [1] = 4000000, 327 [2] = 5333333, 328 [3] = 4800000, 329 [4] = 6400000, 330 }; 331 static const unsigned int pnv_vco[8] = { 332 [0] = 3200000, 333 [1] = 4000000, 334 [2] = 5333333, 335 [3] = 4800000, 336 [4] = 2666667, 337 }; 338 static const unsigned int cl_vco[8] = { 339 [0] = 3200000, 340 [1] = 4000000, 341 [2] = 5333333, 342 [3] = 6400000, 343 [4] = 3333333, 344 [5] = 3566667, 345 [6] = 4266667, 346 }; 347 static const unsigned int elk_vco[8] = { 348 [0] = 3200000, 349 [1] = 4000000, 350 [2] = 5333333, 351 [3] = 4800000, 352 }; 353 static const unsigned int ctg_vco[8] = { 354 [0] = 3200000, 355 [1] = 4000000, 356 [2] = 5333333, 357 [3] = 6400000, 358 [4] = 2666667, 359 [5] = 4266667, 360 }; 361 const unsigned int *vco_table; 362 unsigned int vco; 363 u8 tmp = 0; 364 365 /* FIXME other chipsets? */ 366 if (display->platform.gm45) 367 vco_table = ctg_vco; 368 else if (display->platform.g45) 369 vco_table = elk_vco; 370 else if (display->platform.i965gm) 371 vco_table = cl_vco; 372 else if (display->platform.pineview) 373 vco_table = pnv_vco; 374 else if (display->platform.g33) 375 vco_table = blb_vco; 376 else 377 return 0; 378 379 tmp = intel_de_read(display, display->platform.pineview || 380 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); 381 382 vco = vco_table[tmp & 0x7]; 383 if (vco == 0) 384 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 385 tmp); 386 else 387 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); 388 389 return vco; 390 } 391 392 static void g33_get_cdclk(struct intel_display *display, 393 struct intel_cdclk_config *cdclk_config) 394 { 395 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 396 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 397 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 398 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 399 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 400 const u8 *div_table; 401 unsigned int cdclk_sel; 402 u16 tmp = 0; 403 404 cdclk_config->vco = intel_hpll_vco(display); 405 406 pci_read_config_word(pdev, GCFGC, &tmp); 407 408 cdclk_sel = (tmp >> 4) & 0x7; 409 410 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 411 goto fail; 412 413 switch (cdclk_config->vco) { 414 case 3200000: 415 div_table = div_3200; 416 break; 417 case 4000000: 418 div_table = div_4000; 419 break; 420 case 4800000: 421 div_table = div_4800; 422 break; 423 case 5333333: 424 div_table = div_5333; 425 break; 426 default: 427 goto fail; 428 } 429 430 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 431 div_table[cdclk_sel]); 432 return; 433 434 fail: 435 drm_err(display->drm, 436 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 437 cdclk_config->vco, tmp); 438 cdclk_config->cdclk = 190476; 439 } 440 441 static void pnv_get_cdclk(struct intel_display *display, 442 struct intel_cdclk_config *cdclk_config) 443 { 444 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 445 u16 gcfgc = 0; 446 447 pci_read_config_word(pdev, GCFGC, &gcfgc); 448 449 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 450 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 451 cdclk_config->cdclk = 266667; 452 break; 453 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 454 cdclk_config->cdclk = 333333; 455 break; 456 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 457 cdclk_config->cdclk = 444444; 458 break; 459 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 460 cdclk_config->cdclk = 200000; 461 break; 462 default: 463 drm_err(display->drm, 464 "Unknown pnv display core clock 0x%04x\n", gcfgc); 465 fallthrough; 466 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 467 cdclk_config->cdclk = 133333; 468 break; 469 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 470 cdclk_config->cdclk = 166667; 471 break; 472 } 473 } 474 475 static void i965gm_get_cdclk(struct intel_display *display, 476 struct intel_cdclk_config *cdclk_config) 477 { 478 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 479 static const u8 div_3200[] = { 16, 10, 8 }; 480 static const u8 div_4000[] = { 20, 12, 10 }; 481 static const u8 div_5333[] = { 24, 16, 14 }; 482 const u8 *div_table; 483 unsigned int cdclk_sel; 484 u16 tmp = 0; 485 486 cdclk_config->vco = intel_hpll_vco(display); 487 488 pci_read_config_word(pdev, GCFGC, &tmp); 489 490 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 491 492 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 493 goto fail; 494 495 switch (cdclk_config->vco) { 496 case 3200000: 497 div_table = div_3200; 498 break; 499 case 4000000: 500 div_table = div_4000; 501 break; 502 case 5333333: 503 div_table = div_5333; 504 break; 505 default: 506 goto fail; 507 } 508 509 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 510 div_table[cdclk_sel]); 511 return; 512 513 fail: 514 drm_err(display->drm, 515 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 516 cdclk_config->vco, tmp); 517 cdclk_config->cdclk = 200000; 518 } 519 520 static void gm45_get_cdclk(struct intel_display *display, 521 struct intel_cdclk_config *cdclk_config) 522 { 523 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 524 unsigned int cdclk_sel; 525 u16 tmp = 0; 526 527 cdclk_config->vco = intel_hpll_vco(display); 528 529 pci_read_config_word(pdev, GCFGC, &tmp); 530 531 cdclk_sel = (tmp >> 12) & 0x1; 532 533 switch (cdclk_config->vco) { 534 case 2666667: 535 case 4000000: 536 case 5333333: 537 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 538 break; 539 case 3200000: 540 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 541 break; 542 default: 543 drm_err(display->drm, 544 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 545 cdclk_config->vco, tmp); 546 cdclk_config->cdclk = 222222; 547 break; 548 } 549 } 550 551 static void hsw_get_cdclk(struct intel_display *display, 552 struct intel_cdclk_config *cdclk_config) 553 { 554 u32 lcpll = intel_de_read(display, LCPLL_CTL); 555 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 556 557 if (lcpll & LCPLL_CD_SOURCE_FCLK) 558 cdclk_config->cdclk = 800000; 559 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 560 cdclk_config->cdclk = 450000; 561 else if (freq == LCPLL_CLK_FREQ_450) 562 cdclk_config->cdclk = 450000; 563 else if (display->platform.haswell_ult) 564 cdclk_config->cdclk = 337500; 565 else 566 cdclk_config->cdclk = 540000; 567 } 568 569 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) 570 { 571 int freq_320 = (vlv_clock_get_hpll_vco(display->drm) << 1) % 320000 != 0 ? 572 333333 : 320000; 573 574 /* 575 * We seem to get an unstable or solid color picture at 200MHz. 576 * Not sure what's wrong. For now use 200MHz only when all pipes 577 * are off. 578 */ 579 if (display->platform.valleyview && min_cdclk > freq_320) 580 return 400000; 581 else if (min_cdclk > 266667) 582 return freq_320; 583 else if (min_cdclk > 0) 584 return 266667; 585 else 586 return 200000; 587 } 588 589 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 590 { 591 if (display->platform.valleyview) { 592 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 593 return 2; 594 else if (cdclk >= 266667) 595 return 1; 596 else 597 return 0; 598 } else { 599 /* 600 * Specs are full of misinformation, but testing on actual 601 * hardware has shown that we just need to write the desired 602 * CCK divider into the Punit register. 603 */ 604 return DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, cdclk) - 1; 605 } 606 } 607 608 static void vlv_get_cdclk(struct intel_display *display, 609 struct intel_cdclk_config *cdclk_config) 610 { 611 u32 val; 612 613 cdclk_config->vco = vlv_clock_get_hpll_vco(display->drm); 614 cdclk_config->cdclk = vlv_clock_get_cdclk(display->drm); 615 616 vlv_punit_get(display->drm); 617 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 618 vlv_punit_put(display->drm); 619 620 if (display->platform.valleyview) 621 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 622 DSPFREQGUAR_SHIFT; 623 else 624 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 625 DSPFREQGUAR_SHIFT_CHV; 626 } 627 628 static void vlv_program_pfi_credits(struct intel_display *display) 629 { 630 unsigned int credits, default_credits; 631 632 if (display->platform.cherryview) 633 default_credits = PFI_CREDIT(12); 634 else 635 default_credits = PFI_CREDIT(8); 636 637 if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(display->drm)) { 638 /* CHV suggested value is 31 or 63 */ 639 if (display->platform.cherryview) 640 credits = PFI_CREDIT_63; 641 else 642 credits = PFI_CREDIT(15); 643 } else { 644 credits = default_credits; 645 } 646 647 /* 648 * WA - write default credits before re-programming 649 * FIXME: should we also set the resend bit here? 650 */ 651 intel_de_write(display, GCI_CONTROL, 652 VGA_FAST_MODE_DISABLE | default_credits); 653 654 intel_de_write(display, GCI_CONTROL, 655 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 656 657 /* 658 * FIXME is this guaranteed to clear 659 * immediately or should we poll for it? 660 */ 661 drm_WARN_ON(display->drm, 662 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); 663 } 664 665 static void vlv_set_cdclk(struct intel_display *display, 666 const struct intel_cdclk_config *cdclk_config, 667 enum pipe pipe) 668 { 669 int cdclk = cdclk_config->cdclk; 670 u32 val, cmd = cdclk_config->voltage_level; 671 intel_wakeref_t wakeref; 672 int ret; 673 674 switch (cdclk) { 675 case 400000: 676 case 333333: 677 case 320000: 678 case 266667: 679 case 200000: 680 break; 681 default: 682 MISSING_CASE(cdclk); 683 return; 684 } 685 686 /* There are cases where we can end up here with power domains 687 * off and a CDCLK frequency other than the minimum, like when 688 * issuing a modeset without actually changing any display after 689 * a system suspend. So grab the display core domain, which covers 690 * the HW blocks needed for the following programming. 691 */ 692 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 693 694 vlv_iosf_sb_get(display->drm, 695 BIT(VLV_IOSF_SB_CCK) | 696 BIT(VLV_IOSF_SB_BUNIT) | 697 BIT(VLV_IOSF_SB_PUNIT)); 698 699 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 700 val &= ~DSPFREQGUAR_MASK; 701 val |= (cmd << DSPFREQGUAR_SHIFT); 702 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); 703 704 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), 705 (val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 706 500, 50 * 1000, false); 707 if (ret) 708 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 709 710 if (cdclk == 400000) { 711 u32 divider; 712 713 divider = DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, 714 cdclk) - 1; 715 716 /* adjust cdclk divider */ 717 val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL); 718 val &= ~CCK_FREQUENCY_VALUES; 719 val |= divider; 720 vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val); 721 722 ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL), 723 (val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 724 500, 50 * 1000, false); 725 if (ret) 726 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 727 } 728 729 /* adjust self-refresh exit latency value */ 730 val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC); 731 val &= ~0x7f; 732 733 /* 734 * For high bandwidth configs, we set a higher latency in the bunit 735 * so that the core display fetch happens in time to avoid underruns. 736 */ 737 if (cdclk == 400000) 738 val |= 4500 / 250; /* 4.5 usec */ 739 else 740 val |= 3000 / 250; /* 3.0 usec */ 741 vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val); 742 743 vlv_iosf_sb_put(display->drm, 744 BIT(VLV_IOSF_SB_CCK) | 745 BIT(VLV_IOSF_SB_BUNIT) | 746 BIT(VLV_IOSF_SB_PUNIT)); 747 748 intel_update_cdclk(display); 749 750 vlv_program_pfi_credits(display); 751 752 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 753 } 754 755 static void chv_set_cdclk(struct intel_display *display, 756 const struct intel_cdclk_config *cdclk_config, 757 enum pipe pipe) 758 { 759 int cdclk = cdclk_config->cdclk; 760 u32 val, cmd = cdclk_config->voltage_level; 761 intel_wakeref_t wakeref; 762 int ret; 763 764 switch (cdclk) { 765 case 333333: 766 case 320000: 767 case 266667: 768 case 200000: 769 break; 770 default: 771 MISSING_CASE(cdclk); 772 return; 773 } 774 775 /* There are cases where we can end up here with power domains 776 * off and a CDCLK frequency other than the minimum, like when 777 * issuing a modeset without actually changing any display after 778 * a system suspend. So grab the display core domain, which covers 779 * the HW blocks needed for the following programming. 780 */ 781 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 782 783 vlv_punit_get(display->drm); 784 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 785 val &= ~DSPFREQGUAR_MASK_CHV; 786 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 787 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); 788 789 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), 790 (val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 791 500, 50 * 1000, false); 792 if (ret) 793 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 794 795 vlv_punit_put(display->drm); 796 797 intel_update_cdclk(display); 798 799 vlv_program_pfi_credits(display); 800 801 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 802 } 803 804 static int bdw_calc_cdclk(int min_cdclk) 805 { 806 if (min_cdclk > 540000) 807 return 675000; 808 else if (min_cdclk > 450000) 809 return 540000; 810 else if (min_cdclk > 337500) 811 return 450000; 812 else 813 return 337500; 814 } 815 816 static u8 bdw_calc_voltage_level(int cdclk) 817 { 818 switch (cdclk) { 819 default: 820 case 337500: 821 return 2; 822 case 450000: 823 return 0; 824 case 540000: 825 return 1; 826 case 675000: 827 return 3; 828 } 829 } 830 831 static void bdw_get_cdclk(struct intel_display *display, 832 struct intel_cdclk_config *cdclk_config) 833 { 834 u32 lcpll = intel_de_read(display, LCPLL_CTL); 835 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 836 837 if (lcpll & LCPLL_CD_SOURCE_FCLK) 838 cdclk_config->cdclk = 800000; 839 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 840 cdclk_config->cdclk = 450000; 841 else if (freq == LCPLL_CLK_FREQ_450) 842 cdclk_config->cdclk = 450000; 843 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 844 cdclk_config->cdclk = 540000; 845 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 846 cdclk_config->cdclk = 337500; 847 else 848 cdclk_config->cdclk = 675000; 849 850 /* 851 * Can't read this out :( Let's assume it's 852 * at least what the CDCLK frequency requires. 853 */ 854 cdclk_config->voltage_level = 855 bdw_calc_voltage_level(cdclk_config->cdclk); 856 } 857 858 static u32 bdw_cdclk_freq_sel(int cdclk) 859 { 860 switch (cdclk) { 861 default: 862 MISSING_CASE(cdclk); 863 fallthrough; 864 case 337500: 865 return LCPLL_CLK_FREQ_337_5_BDW; 866 case 450000: 867 return LCPLL_CLK_FREQ_450; 868 case 540000: 869 return LCPLL_CLK_FREQ_54O_BDW; 870 case 675000: 871 return LCPLL_CLK_FREQ_675_BDW; 872 } 873 } 874 875 static void bdw_set_cdclk(struct intel_display *display, 876 const struct intel_cdclk_config *cdclk_config, 877 enum pipe pipe) 878 { 879 int cdclk = cdclk_config->cdclk; 880 int ret; 881 882 if (drm_WARN(display->drm, 883 (intel_de_read(display, LCPLL_CTL) & 884 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 885 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 886 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 887 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 888 "trying to change cdclk frequency with cdclk not enabled\n")) 889 return; 890 891 ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 892 if (ret) { 893 drm_err(display->drm, 894 "failed to inform pcode about cdclk change\n"); 895 return; 896 } 897 898 intel_de_rmw(display, LCPLL_CTL, 899 0, LCPLL_CD_SOURCE_FCLK); 900 901 /* 902 * According to the spec, it should be enough to poll for this 1 us. 903 * However, extensive testing shows that this can take longer. 904 */ 905 ret = intel_de_wait_custom(display, LCPLL_CTL, 906 LCPLL_CD_SOURCE_FCLK_DONE, LCPLL_CD_SOURCE_FCLK_DONE, 907 100, 0, NULL); 908 if (ret) 909 drm_err(display->drm, "Switching to FCLK failed\n"); 910 911 intel_de_rmw(display, LCPLL_CTL, 912 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 913 914 intel_de_rmw(display, LCPLL_CTL, 915 LCPLL_CD_SOURCE_FCLK, 0); 916 917 ret = intel_de_wait_custom(display, LCPLL_CTL, 918 LCPLL_CD_SOURCE_FCLK_DONE, 0, 919 1, 0, NULL); 920 if (ret) 921 drm_err(display->drm, "Switching back to LCPLL failed\n"); 922 923 intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ, 924 cdclk_config->voltage_level); 925 926 intel_de_write(display, CDCLK_FREQ, 927 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 928 929 intel_update_cdclk(display); 930 } 931 932 static int skl_calc_cdclk(int min_cdclk, int vco) 933 { 934 if (vco == 8640000) { 935 if (min_cdclk > 540000) 936 return 617143; 937 else if (min_cdclk > 432000) 938 return 540000; 939 else if (min_cdclk > 308571) 940 return 432000; 941 else 942 return 308571; 943 } else { 944 if (min_cdclk > 540000) 945 return 675000; 946 else if (min_cdclk > 450000) 947 return 540000; 948 else if (min_cdclk > 337500) 949 return 450000; 950 else 951 return 337500; 952 } 953 } 954 955 static u8 skl_calc_voltage_level(int cdclk) 956 { 957 if (cdclk > 540000) 958 return 3; 959 else if (cdclk > 450000) 960 return 2; 961 else if (cdclk > 337500) 962 return 1; 963 else 964 return 0; 965 } 966 967 static void skl_dpll0_update(struct intel_display *display, 968 struct intel_cdclk_config *cdclk_config) 969 { 970 u32 val; 971 972 cdclk_config->ref = 24000; 973 cdclk_config->vco = 0; 974 975 val = intel_de_read(display, LCPLL1_CTL); 976 if ((val & LCPLL_PLL_ENABLE) == 0) 977 return; 978 979 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) 980 return; 981 982 val = intel_de_read(display, DPLL_CTRL1); 983 984 if (drm_WARN_ON(display->drm, 985 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 986 DPLL_CTRL1_SSC(SKL_DPLL0) | 987 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 988 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 989 return; 990 991 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 992 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 993 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 994 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 995 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 996 cdclk_config->vco = 8100000; 997 break; 998 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 999 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 1000 cdclk_config->vco = 8640000; 1001 break; 1002 default: 1003 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 1004 break; 1005 } 1006 } 1007 1008 static void skl_get_cdclk(struct intel_display *display, 1009 struct intel_cdclk_config *cdclk_config) 1010 { 1011 u32 cdctl; 1012 1013 skl_dpll0_update(display, cdclk_config); 1014 1015 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 1016 1017 if (cdclk_config->vco == 0) 1018 goto out; 1019 1020 cdctl = intel_de_read(display, CDCLK_CTL); 1021 1022 if (cdclk_config->vco == 8640000) { 1023 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1024 case CDCLK_FREQ_450_432: 1025 cdclk_config->cdclk = 432000; 1026 break; 1027 case CDCLK_FREQ_337_308: 1028 cdclk_config->cdclk = 308571; 1029 break; 1030 case CDCLK_FREQ_540: 1031 cdclk_config->cdclk = 540000; 1032 break; 1033 case CDCLK_FREQ_675_617: 1034 cdclk_config->cdclk = 617143; 1035 break; 1036 default: 1037 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1038 break; 1039 } 1040 } else { 1041 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1042 case CDCLK_FREQ_450_432: 1043 cdclk_config->cdclk = 450000; 1044 break; 1045 case CDCLK_FREQ_337_308: 1046 cdclk_config->cdclk = 337500; 1047 break; 1048 case CDCLK_FREQ_540: 1049 cdclk_config->cdclk = 540000; 1050 break; 1051 case CDCLK_FREQ_675_617: 1052 cdclk_config->cdclk = 675000; 1053 break; 1054 default: 1055 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1056 break; 1057 } 1058 } 1059 1060 out: 1061 /* 1062 * Can't read this out :( Let's assume it's 1063 * at least what the CDCLK frequency requires. 1064 */ 1065 cdclk_config->voltage_level = 1066 skl_calc_voltage_level(cdclk_config->cdclk); 1067 } 1068 1069 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1070 static int skl_cdclk_decimal(int cdclk) 1071 { 1072 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1073 } 1074 1075 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) 1076 { 1077 bool changed = display->cdclk.skl_preferred_vco_freq != vco; 1078 1079 display->cdclk.skl_preferred_vco_freq = vco; 1080 1081 if (changed) 1082 intel_update_max_cdclk(display); 1083 } 1084 1085 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) 1086 { 1087 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 1088 1089 /* 1090 * We always enable DPLL0 with the lowest link rate possible, but still 1091 * taking into account the VCO required to operate the eDP panel at the 1092 * desired frequency. The usual DP link rates operate with a VCO of 1093 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1094 * The modeset code is responsible for the selection of the exact link 1095 * rate later on, with the constraint of choosing a frequency that 1096 * works with vco. 1097 */ 1098 if (vco == 8640000) 1099 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1100 else 1101 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1102 } 1103 1104 static void skl_dpll0_enable(struct intel_display *display, int vco) 1105 { 1106 intel_de_rmw(display, DPLL_CTRL1, 1107 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1108 DPLL_CTRL1_SSC(SKL_DPLL0) | 1109 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1110 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1111 skl_dpll0_link_rate(display, vco)); 1112 intel_de_posting_read(display, DPLL_CTRL1); 1113 1114 intel_de_rmw(display, LCPLL1_CTL, 1115 0, LCPLL_PLL_ENABLE); 1116 1117 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1118 drm_err(display->drm, "DPLL0 not locked\n"); 1119 1120 display->cdclk.hw.vco = vco; 1121 1122 /* We'll want to keep using the current vco from now on. */ 1123 skl_set_preferred_cdclk_vco(display, vco); 1124 } 1125 1126 static void skl_dpll0_disable(struct intel_display *display) 1127 { 1128 intel_de_rmw(display, LCPLL1_CTL, 1129 LCPLL_PLL_ENABLE, 0); 1130 1131 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1132 drm_err(display->drm, "Couldn't disable DPLL0\n"); 1133 1134 display->cdclk.hw.vco = 0; 1135 } 1136 1137 static u32 skl_cdclk_freq_sel(struct intel_display *display, 1138 int cdclk, int vco) 1139 { 1140 switch (cdclk) { 1141 default: 1142 drm_WARN_ON(display->drm, 1143 cdclk != display->cdclk.hw.bypass); 1144 drm_WARN_ON(display->drm, vco != 0); 1145 fallthrough; 1146 case 308571: 1147 case 337500: 1148 return CDCLK_FREQ_337_308; 1149 case 450000: 1150 case 432000: 1151 return CDCLK_FREQ_450_432; 1152 case 540000: 1153 return CDCLK_FREQ_540; 1154 case 617143: 1155 case 675000: 1156 return CDCLK_FREQ_675_617; 1157 } 1158 } 1159 1160 static void skl_set_cdclk(struct intel_display *display, 1161 const struct intel_cdclk_config *cdclk_config, 1162 enum pipe pipe) 1163 { 1164 int cdclk = cdclk_config->cdclk; 1165 int vco = cdclk_config->vco; 1166 u32 freq_select, cdclk_ctl; 1167 int ret; 1168 1169 /* 1170 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1171 * unsupported on SKL. In theory this should never happen since only 1172 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1173 * supported on SKL either, see the above WA. WARN whenever trying to 1174 * use the corresponding VCO freq as that always leads to using the 1175 * minimum 308MHz CDCLK. 1176 */ 1177 drm_WARN_ON_ONCE(display->drm, 1178 display->platform.skylake && vco == 8640000); 1179 1180 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 1181 SKL_CDCLK_PREPARE_FOR_CHANGE, 1182 SKL_CDCLK_READY_FOR_CHANGE, 1183 SKL_CDCLK_READY_FOR_CHANGE, 3); 1184 if (ret) { 1185 drm_err(display->drm, 1186 "Failed to inform PCU about cdclk change (%d)\n", ret); 1187 return; 1188 } 1189 1190 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); 1191 1192 if (display->cdclk.hw.vco != 0 && 1193 display->cdclk.hw.vco != vco) 1194 skl_dpll0_disable(display); 1195 1196 cdclk_ctl = intel_de_read(display, CDCLK_CTL); 1197 1198 if (display->cdclk.hw.vco != vco) { 1199 /* Wa Display #1183: skl,kbl,cfl */ 1200 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1201 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1202 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1203 } 1204 1205 /* Wa Display #1183: skl,kbl,cfl */ 1206 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1207 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1208 intel_de_posting_read(display, CDCLK_CTL); 1209 1210 if (display->cdclk.hw.vco != vco) 1211 skl_dpll0_enable(display, vco); 1212 1213 /* Wa Display #1183: skl,kbl,cfl */ 1214 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1215 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1216 1217 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1218 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1219 1220 /* Wa Display #1183: skl,kbl,cfl */ 1221 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1222 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1223 intel_de_posting_read(display, CDCLK_CTL); 1224 1225 /* inform PCU of the change */ 1226 intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, 1227 cdclk_config->voltage_level); 1228 1229 intel_update_cdclk(display); 1230 } 1231 1232 static void skl_sanitize_cdclk(struct intel_display *display) 1233 { 1234 u32 cdctl, expected; 1235 1236 /* 1237 * check if the pre-os initialized the display 1238 * There is SWF18 scratchpad register defined which is set by the 1239 * pre-os which can be used by the OS drivers to check the status 1240 */ 1241 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1242 goto sanitize; 1243 1244 intel_update_cdclk(display); 1245 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1246 1247 /* Is PLL enabled and locked ? */ 1248 if (display->cdclk.hw.vco == 0 || 1249 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 1250 goto sanitize; 1251 1252 /* DPLL okay; verify the cdclock 1253 * 1254 * Noticed in some instances that the freq selection is correct but 1255 * decimal part is programmed wrong from BIOS where pre-os does not 1256 * enable display. Verify the same as well. 1257 */ 1258 cdctl = intel_de_read(display, CDCLK_CTL); 1259 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1260 skl_cdclk_decimal(display->cdclk.hw.cdclk); 1261 if (cdctl == expected) 1262 /* All well; nothing to sanitize */ 1263 return; 1264 1265 sanitize: 1266 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 1267 1268 /* force cdclk programming */ 1269 display->cdclk.hw.cdclk = 0; 1270 /* force full PLL disable + enable */ 1271 display->cdclk.hw.vco = ~0; 1272 } 1273 1274 static void skl_cdclk_init_hw(struct intel_display *display) 1275 { 1276 struct intel_cdclk_config cdclk_config; 1277 1278 skl_sanitize_cdclk(display); 1279 1280 if (display->cdclk.hw.cdclk != 0 && 1281 display->cdclk.hw.vco != 0) { 1282 /* 1283 * Use the current vco as our initial 1284 * guess as to what the preferred vco is. 1285 */ 1286 if (display->cdclk.skl_preferred_vco_freq == 0) 1287 skl_set_preferred_cdclk_vco(display, 1288 display->cdclk.hw.vco); 1289 return; 1290 } 1291 1292 cdclk_config = display->cdclk.hw; 1293 1294 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; 1295 if (cdclk_config.vco == 0) 1296 cdclk_config.vco = 8100000; 1297 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1298 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1299 1300 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1301 } 1302 1303 static void skl_cdclk_uninit_hw(struct intel_display *display) 1304 { 1305 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 1306 1307 cdclk_config.cdclk = cdclk_config.bypass; 1308 cdclk_config.vco = 0; 1309 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1310 1311 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1312 } 1313 1314 struct intel_cdclk_vals { 1315 u32 cdclk; 1316 u16 refclk; 1317 u16 waveform; 1318 u8 ratio; 1319 }; 1320 1321 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1322 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1323 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1324 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1325 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1326 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1327 {} 1328 }; 1329 1330 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1331 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1332 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1333 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1334 {} 1335 }; 1336 1337 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1338 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1339 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1340 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1341 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1342 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1343 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1344 1345 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1346 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1347 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1348 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1349 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1350 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1351 1352 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1353 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1354 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1355 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1356 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1357 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1358 {} 1359 }; 1360 1361 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1362 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1363 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1364 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1365 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1366 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1367 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1368 1369 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1370 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1371 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1372 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1373 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1374 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1375 1376 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1377 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1378 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1379 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1380 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1381 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1382 {} 1383 }; 1384 1385 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1386 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1387 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1388 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1389 1390 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1391 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1392 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1393 1394 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1395 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1396 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1397 {} 1398 }; 1399 1400 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1401 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1402 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1403 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1404 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1405 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1406 1407 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1408 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1409 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1410 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1411 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1412 1413 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1414 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1415 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1416 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1417 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1418 {} 1419 }; 1420 1421 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1422 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1423 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1424 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1425 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1426 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1427 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1428 1429 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1430 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1431 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1432 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1433 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1434 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1435 1436 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1437 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1438 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1439 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1440 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1441 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1442 {} 1443 }; 1444 1445 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1446 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1447 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1448 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1449 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1450 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1451 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1452 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1453 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1454 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1455 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1456 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1457 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1458 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1459 {} 1460 }; 1461 1462 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1463 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1464 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1465 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1466 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1467 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1468 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1469 {} 1470 }; 1471 1472 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1473 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1474 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1475 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1476 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1477 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1478 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1479 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1480 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1481 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1482 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1483 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1484 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1485 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1486 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1487 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1488 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1489 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1490 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1491 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1492 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1493 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1494 {} 1495 }; 1496 1497 /* 1498 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1499 */ 1500 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1501 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1502 {} 1503 }; 1504 1505 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { 1506 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1507 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1508 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1509 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1510 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1511 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1512 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1513 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1514 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1515 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff }, 1516 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff }, 1517 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff }, 1518 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff }, 1519 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1520 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1521 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1522 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1523 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1524 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1525 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1526 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1527 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1528 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1529 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1530 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1531 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1532 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1533 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1534 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1535 {} 1536 }; 1537 1538 static const int cdclk_squash_len = 16; 1539 1540 static int cdclk_squash_divider(u16 waveform) 1541 { 1542 return hweight16(waveform ?: 0xffff); 1543 } 1544 1545 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1546 { 1547 /* 2 * cd2x divider */ 1548 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1549 cdclk * cdclk_squash_len); 1550 } 1551 1552 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 1553 { 1554 const struct intel_cdclk_vals *table = display->cdclk.table; 1555 int i; 1556 1557 for (i = 0; table[i].refclk; i++) 1558 if (table[i].refclk == display->cdclk.hw.ref && 1559 table[i].cdclk >= min_cdclk) 1560 return table[i].cdclk; 1561 1562 drm_WARN(display->drm, 1, 1563 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1564 min_cdclk, display->cdclk.hw.ref); 1565 return display->cdclk.max_cdclk_freq; 1566 } 1567 1568 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) 1569 { 1570 const struct intel_cdclk_vals *table = display->cdclk.table; 1571 int i; 1572 1573 if (cdclk == display->cdclk.hw.bypass) 1574 return 0; 1575 1576 for (i = 0; table[i].refclk; i++) 1577 if (table[i].refclk == display->cdclk.hw.ref && 1578 table[i].cdclk == cdclk) 1579 return display->cdclk.hw.ref * table[i].ratio; 1580 1581 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1582 cdclk, display->cdclk.hw.ref); 1583 return 0; 1584 } 1585 1586 static u8 bxt_calc_voltage_level(int cdclk) 1587 { 1588 return DIV_ROUND_UP(cdclk, 25000); 1589 } 1590 1591 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1592 const int voltage_level_max_cdclk[]) 1593 { 1594 int voltage_level; 1595 1596 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1597 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1598 return voltage_level; 1599 } 1600 1601 MISSING_CASE(cdclk); 1602 return num_voltage_levels - 1; 1603 } 1604 1605 static u8 icl_calc_voltage_level(int cdclk) 1606 { 1607 static const int icl_voltage_level_max_cdclk[] = { 1608 [0] = 312000, 1609 [1] = 556800, 1610 [2] = 652800, 1611 }; 1612 1613 return calc_voltage_level(cdclk, 1614 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1615 icl_voltage_level_max_cdclk); 1616 } 1617 1618 static u8 ehl_calc_voltage_level(int cdclk) 1619 { 1620 static const int ehl_voltage_level_max_cdclk[] = { 1621 [0] = 180000, 1622 [1] = 312000, 1623 [2] = 326400, 1624 /* 1625 * Bspec lists the limit as 556.8 MHz, but some JSL 1626 * development boards (at least) boot with 652.8 MHz 1627 */ 1628 [3] = 652800, 1629 }; 1630 1631 return calc_voltage_level(cdclk, 1632 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1633 ehl_voltage_level_max_cdclk); 1634 } 1635 1636 static u8 tgl_calc_voltage_level(int cdclk) 1637 { 1638 static const int tgl_voltage_level_max_cdclk[] = { 1639 [0] = 312000, 1640 [1] = 326400, 1641 [2] = 556800, 1642 [3] = 652800, 1643 }; 1644 1645 return calc_voltage_level(cdclk, 1646 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1647 tgl_voltage_level_max_cdclk); 1648 } 1649 1650 static u8 rplu_calc_voltage_level(int cdclk) 1651 { 1652 static const int rplu_voltage_level_max_cdclk[] = { 1653 [0] = 312000, 1654 [1] = 480000, 1655 [2] = 556800, 1656 [3] = 652800, 1657 }; 1658 1659 return calc_voltage_level(cdclk, 1660 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1661 rplu_voltage_level_max_cdclk); 1662 } 1663 1664 static u8 xe3lpd_calc_voltage_level(int cdclk) 1665 { 1666 /* 1667 * Starting with xe3lpd power controller does not need the voltage 1668 * index when doing the modeset update. This function is best left 1669 * defined but returning 0 to the mask. 1670 */ 1671 return 0; 1672 } 1673 1674 static void icl_readout_refclk(struct intel_display *display, 1675 struct intel_cdclk_config *cdclk_config) 1676 { 1677 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1678 1679 switch (dssm) { 1680 default: 1681 MISSING_CASE(dssm); 1682 fallthrough; 1683 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1684 cdclk_config->ref = 24000; 1685 break; 1686 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1687 cdclk_config->ref = 19200; 1688 break; 1689 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1690 cdclk_config->ref = 38400; 1691 break; 1692 } 1693 } 1694 1695 static void bxt_de_pll_readout(struct intel_display *display, 1696 struct intel_cdclk_config *cdclk_config) 1697 { 1698 u32 val, ratio; 1699 1700 if (display->platform.dg2) 1701 cdclk_config->ref = 38400; 1702 else if (DISPLAY_VER(display) >= 11) 1703 icl_readout_refclk(display, cdclk_config); 1704 else 1705 cdclk_config->ref = 19200; 1706 1707 val = intel_de_read(display, BXT_DE_PLL_ENABLE); 1708 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1709 (val & BXT_DE_PLL_LOCK) == 0) { 1710 /* 1711 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1712 * setting it to zero is a way to signal that. 1713 */ 1714 cdclk_config->vco = 0; 1715 return; 1716 } 1717 1718 /* 1719 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1720 * gen9lp had it in a separate PLL control register. 1721 */ 1722 if (DISPLAY_VER(display) >= 11) 1723 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1724 else 1725 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1726 1727 cdclk_config->vco = ratio * cdclk_config->ref; 1728 } 1729 1730 static void bxt_get_cdclk(struct intel_display *display, 1731 struct intel_cdclk_config *cdclk_config) 1732 { 1733 u32 squash_ctl = 0; 1734 u32 divider; 1735 int div; 1736 1737 bxt_de_pll_readout(display, cdclk_config); 1738 1739 if (DISPLAY_VER(display) >= 12) 1740 cdclk_config->bypass = cdclk_config->ref / 2; 1741 else if (DISPLAY_VER(display) >= 11) 1742 cdclk_config->bypass = 50000; 1743 else 1744 cdclk_config->bypass = cdclk_config->ref; 1745 1746 if (cdclk_config->vco == 0) { 1747 cdclk_config->cdclk = cdclk_config->bypass; 1748 goto out; 1749 } 1750 1751 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1752 1753 switch (divider) { 1754 case BXT_CDCLK_CD2X_DIV_SEL_1: 1755 div = 2; 1756 break; 1757 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1758 div = 3; 1759 break; 1760 case BXT_CDCLK_CD2X_DIV_SEL_2: 1761 div = 4; 1762 break; 1763 case BXT_CDCLK_CD2X_DIV_SEL_4: 1764 div = 8; 1765 break; 1766 default: 1767 MISSING_CASE(divider); 1768 return; 1769 } 1770 1771 if (HAS_CDCLK_SQUASH(display)) 1772 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); 1773 1774 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1775 u16 waveform; 1776 int size; 1777 1778 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1779 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1780 1781 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1782 cdclk_config->vco, size * div); 1783 } else { 1784 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1785 } 1786 1787 out: 1788 if (DISPLAY_VER(display) >= 20) 1789 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 1790 /* 1791 * Can't read this out :( Let's assume it's 1792 * at least what the CDCLK frequency requires. 1793 */ 1794 cdclk_config->voltage_level = 1795 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); 1796 } 1797 1798 static void bxt_de_pll_disable(struct intel_display *display) 1799 { 1800 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); 1801 1802 /* Timeout 200us */ 1803 if (intel_de_wait_for_clear(display, 1804 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1805 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); 1806 1807 display->cdclk.hw.vco = 0; 1808 } 1809 1810 static void bxt_de_pll_enable(struct intel_display *display, int vco) 1811 { 1812 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1813 1814 intel_de_rmw(display, BXT_DE_PLL_CTL, 1815 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1816 1817 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1818 1819 /* Timeout 200us */ 1820 if (intel_de_wait_for_set(display, 1821 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1822 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); 1823 1824 display->cdclk.hw.vco = vco; 1825 } 1826 1827 static void icl_cdclk_pll_disable(struct intel_display *display) 1828 { 1829 intel_de_rmw(display, BXT_DE_PLL_ENABLE, 1830 BXT_DE_PLL_PLL_ENABLE, 0); 1831 1832 /* Timeout 200us */ 1833 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1834 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); 1835 1836 display->cdclk.hw.vco = 0; 1837 } 1838 1839 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) 1840 { 1841 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1842 u32 val; 1843 1844 val = ICL_CDCLK_PLL_RATIO(ratio); 1845 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1846 1847 val |= BXT_DE_PLL_PLL_ENABLE; 1848 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1849 1850 /* Timeout 200us */ 1851 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1852 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); 1853 1854 display->cdclk.hw.vco = vco; 1855 } 1856 1857 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) 1858 { 1859 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1860 u32 val; 1861 1862 /* Write PLL ratio without disabling */ 1863 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1864 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1865 1866 /* Submit freq change request */ 1867 val |= BXT_DE_PLL_FREQ_REQ; 1868 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1869 1870 /* Timeout 200us */ 1871 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, 1872 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1873 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); 1874 1875 val &= ~BXT_DE_PLL_FREQ_REQ; 1876 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1877 1878 display->cdclk.hw.vco = vco; 1879 } 1880 1881 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 1882 { 1883 if (DISPLAY_VER(display) >= 12) { 1884 if (pipe == INVALID_PIPE) 1885 return TGL_CDCLK_CD2X_PIPE_NONE; 1886 else 1887 return TGL_CDCLK_CD2X_PIPE(pipe); 1888 } else if (DISPLAY_VER(display) >= 11) { 1889 if (pipe == INVALID_PIPE) 1890 return ICL_CDCLK_CD2X_PIPE_NONE; 1891 else 1892 return ICL_CDCLK_CD2X_PIPE(pipe); 1893 } else { 1894 if (pipe == INVALID_PIPE) 1895 return BXT_CDCLK_CD2X_PIPE_NONE; 1896 else 1897 return BXT_CDCLK_CD2X_PIPE(pipe); 1898 } 1899 } 1900 1901 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 1902 int cdclk, int vco, u16 waveform) 1903 { 1904 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1905 switch (cdclk_divider(cdclk, vco, waveform)) { 1906 default: 1907 drm_WARN_ON(display->drm, 1908 cdclk != display->cdclk.hw.bypass); 1909 drm_WARN_ON(display->drm, vco != 0); 1910 fallthrough; 1911 case 2: 1912 return BXT_CDCLK_CD2X_DIV_SEL_1; 1913 case 3: 1914 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1915 case 4: 1916 return BXT_CDCLK_CD2X_DIV_SEL_2; 1917 case 8: 1918 return BXT_CDCLK_CD2X_DIV_SEL_4; 1919 } 1920 } 1921 1922 static u16 cdclk_squash_waveform(struct intel_display *display, 1923 int cdclk) 1924 { 1925 const struct intel_cdclk_vals *table = display->cdclk.table; 1926 int i; 1927 1928 if (cdclk == display->cdclk.hw.bypass) 1929 return 0; 1930 1931 for (i = 0; table[i].refclk; i++) 1932 if (table[i].refclk == display->cdclk.hw.ref && 1933 table[i].cdclk == cdclk) 1934 return table[i].waveform; 1935 1936 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1937 cdclk, display->cdclk.hw.ref); 1938 1939 return 0xffff; 1940 } 1941 1942 static void icl_cdclk_pll_update(struct intel_display *display, int vco) 1943 { 1944 if (display->cdclk.hw.vco != 0 && 1945 display->cdclk.hw.vco != vco) 1946 icl_cdclk_pll_disable(display); 1947 1948 if (display->cdclk.hw.vco != vco) 1949 icl_cdclk_pll_enable(display, vco); 1950 } 1951 1952 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) 1953 { 1954 if (display->cdclk.hw.vco != 0 && 1955 display->cdclk.hw.vco != vco) 1956 bxt_de_pll_disable(display); 1957 1958 if (display->cdclk.hw.vco != vco) 1959 bxt_de_pll_enable(display, vco); 1960 } 1961 1962 static void dg2_cdclk_squash_program(struct intel_display *display, 1963 u16 waveform) 1964 { 1965 u32 squash_ctl = 0; 1966 1967 if (waveform) 1968 squash_ctl = CDCLK_SQUASH_ENABLE | 1969 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1970 1971 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); 1972 } 1973 1974 static bool cdclk_pll_is_unknown(unsigned int vco) 1975 { 1976 /* 1977 * Ensure driver does not take the crawl path for the 1978 * case when the vco is set to ~0 in the 1979 * sanitize path. 1980 */ 1981 return vco == ~0; 1982 } 1983 1984 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) 1985 { 1986 return DISPLAY_VER(display) >= 20; 1987 } 1988 1989 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) 1990 { 1991 if (mdclk_source_is_cdclk_pll(display)) 1992 return MDCLK_SOURCE_SEL_CDCLK_PLL; 1993 1994 return MDCLK_SOURCE_SEL_CD2XCLK; 1995 } 1996 1997 int intel_mdclk_cdclk_ratio(struct intel_display *display, 1998 const struct intel_cdclk_config *cdclk_config) 1999 { 2000 if (mdclk_source_is_cdclk_pll(display)) 2001 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 2002 2003 /* Otherwise, source for MDCLK is CD2XCLK. */ 2004 return 2; 2005 } 2006 2007 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, 2008 const struct intel_cdclk_config *cdclk_config) 2009 { 2010 intel_dbuf_mdclk_cdclk_ratio_update(display, 2011 intel_mdclk_cdclk_ratio(display, cdclk_config), 2012 cdclk_config->joined_mbus); 2013 } 2014 2015 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, 2016 const struct intel_cdclk_config *old_cdclk_config, 2017 const struct intel_cdclk_config *new_cdclk_config, 2018 struct intel_cdclk_config *mid_cdclk_config) 2019 { 2020 u16 old_waveform, new_waveform, mid_waveform; 2021 int old_div, new_div, mid_div; 2022 2023 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 2024 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 2025 return false; 2026 2027 /* Return if both Squash and Crawl are not present */ 2028 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2029 return false; 2030 2031 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); 2032 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); 2033 2034 /* Return if Squash only or Crawl only is the desired action */ 2035 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 2036 old_cdclk_config->vco == new_cdclk_config->vco || 2037 old_waveform == new_waveform) 2038 return false; 2039 2040 old_div = cdclk_divider(old_cdclk_config->cdclk, 2041 old_cdclk_config->vco, old_waveform); 2042 new_div = cdclk_divider(new_cdclk_config->cdclk, 2043 new_cdclk_config->vco, new_waveform); 2044 2045 /* 2046 * Should not happen currently. We might need more midpoint 2047 * transitions if we need to also change the cd2x divider. 2048 */ 2049 if (drm_WARN_ON(display->drm, old_div != new_div)) 2050 return false; 2051 2052 *mid_cdclk_config = *new_cdclk_config; 2053 2054 /* 2055 * Populate the mid_cdclk_config accordingly. 2056 * - If moving to a higher cdclk, the desired action is squashing. 2057 * The mid cdclk config should have the new (squash) waveform. 2058 * - If moving to a lower cdclk, the desired action is crawling. 2059 * The mid cdclk config should have the new vco. 2060 */ 2061 2062 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 2063 mid_cdclk_config->vco = old_cdclk_config->vco; 2064 mid_div = old_div; 2065 mid_waveform = new_waveform; 2066 } else { 2067 mid_cdclk_config->vco = new_cdclk_config->vco; 2068 mid_div = new_div; 2069 mid_waveform = old_waveform; 2070 } 2071 2072 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 2073 mid_cdclk_config->vco, 2074 cdclk_squash_len * mid_div); 2075 2076 /* make sure the mid clock came out sane */ 2077 2078 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < 2079 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 2080 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > 2081 display->cdclk.max_cdclk_freq); 2082 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != 2083 mid_waveform); 2084 2085 return true; 2086 } 2087 2088 static bool pll_enable_wa_needed(struct intel_display *display) 2089 { 2090 return (DISPLAY_VERx100(display) == 2000 || 2091 DISPLAY_VERx100(display) == 1400 || 2092 display->platform.dg2) && 2093 display->cdclk.hw.vco > 0; 2094 } 2095 2096 static u32 bxt_cdclk_ctl(struct intel_display *display, 2097 const struct intel_cdclk_config *cdclk_config, 2098 enum pipe pipe) 2099 { 2100 int cdclk = cdclk_config->cdclk; 2101 int vco = cdclk_config->vco; 2102 u16 waveform; 2103 u32 val; 2104 2105 waveform = cdclk_squash_waveform(display, cdclk); 2106 2107 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | 2108 bxt_cdclk_cd2x_pipe(display, pipe); 2109 2110 /* 2111 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2112 * enable otherwise. 2113 */ 2114 if ((display->platform.geminilake || display->platform.broxton) && 2115 cdclk >= 500000) 2116 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2117 2118 if (DISPLAY_VER(display) >= 20) 2119 val |= xe2lpd_mdclk_source_sel(display); 2120 else 2121 val |= skl_cdclk_decimal(cdclk); 2122 2123 return val; 2124 } 2125 2126 static void _bxt_set_cdclk(struct intel_display *display, 2127 const struct intel_cdclk_config *cdclk_config, 2128 enum pipe pipe) 2129 { 2130 int cdclk = cdclk_config->cdclk; 2131 int vco = cdclk_config->vco; 2132 2133 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && 2134 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { 2135 if (display->cdclk.hw.vco != vco) 2136 adlp_cdclk_pll_crawl(display, vco); 2137 } else if (DISPLAY_VER(display) >= 11) { 2138 /* wa_15010685871: dg2, mtl */ 2139 if (pll_enable_wa_needed(display)) 2140 dg2_cdclk_squash_program(display, 0); 2141 2142 icl_cdclk_pll_update(display, vco); 2143 } else { 2144 bxt_cdclk_pll_update(display, vco); 2145 } 2146 2147 if (HAS_CDCLK_SQUASH(display)) { 2148 u16 waveform = cdclk_squash_waveform(display, cdclk); 2149 2150 dg2_cdclk_squash_program(display, waveform); 2151 } 2152 2153 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); 2154 2155 if (pipe != INVALID_PIPE) 2156 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 2157 } 2158 2159 static void bxt_set_cdclk(struct intel_display *display, 2160 const struct intel_cdclk_config *cdclk_config, 2161 enum pipe pipe) 2162 { 2163 struct intel_cdclk_config mid_cdclk_config; 2164 int cdclk = cdclk_config->cdclk; 2165 int ret = 0; 2166 2167 /* 2168 * Inform power controller of upcoming frequency change. 2169 * Display versions 14 and beyond do not follow the PUnit 2170 * mailbox communication, skip 2171 * this step. 2172 */ 2173 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) 2174 ; /* NOOP */ 2175 else if (DISPLAY_VER(display) >= 11) 2176 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 2177 SKL_CDCLK_PREPARE_FOR_CHANGE, 2178 SKL_CDCLK_READY_FOR_CHANGE, 2179 SKL_CDCLK_READY_FOR_CHANGE, 3); 2180 else 2181 /* 2182 * BSpec requires us to wait up to 150usec, but that leads to 2183 * timeouts; the 2ms used here is based on experiment. 2184 */ 2185 ret = intel_pcode_write_timeout(display->drm, 2186 HSW_PCODE_DE_WRITE_FREQ_REQ, 2187 0x80000000, 2); 2188 2189 if (ret) { 2190 drm_err(display->drm, 2191 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2192 ret, cdclk); 2193 return; 2194 } 2195 2196 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) 2197 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2198 2199 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, 2200 cdclk_config, &mid_cdclk_config)) { 2201 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); 2202 _bxt_set_cdclk(display, cdclk_config, pipe); 2203 } else { 2204 _bxt_set_cdclk(display, cdclk_config, pipe); 2205 } 2206 2207 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) 2208 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2209 2210 if (DISPLAY_VER(display) >= 14) 2211 /* 2212 * NOOP - No Pcode communication needed for 2213 * Display versions 14 and beyond 2214 */; 2215 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) 2216 ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, 2217 cdclk_config->voltage_level); 2218 if (DISPLAY_VER(display) < 11) { 2219 /* 2220 * The timeout isn't specified, the 2ms used here is based on 2221 * experiment. 2222 * FIXME: Waiting for the request completion could be delayed 2223 * until the next PCODE request based on BSpec. 2224 */ 2225 ret = intel_pcode_write_timeout(display->drm, 2226 HSW_PCODE_DE_WRITE_FREQ_REQ, 2227 cdclk_config->voltage_level, 2); 2228 } 2229 if (ret) { 2230 drm_err(display->drm, 2231 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2232 ret, cdclk); 2233 return; 2234 } 2235 2236 intel_update_cdclk(display); 2237 2238 if (DISPLAY_VER(display) >= 11) 2239 /* 2240 * Can't read out the voltage level :( 2241 * Let's just assume everything is as expected. 2242 */ 2243 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; 2244 } 2245 2246 static void bxt_sanitize_cdclk(struct intel_display *display) 2247 { 2248 u32 cdctl, expected; 2249 int cdclk, vco; 2250 2251 intel_update_cdclk(display); 2252 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 2253 2254 if (display->cdclk.hw.vco == 0 || 2255 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 2256 goto sanitize; 2257 2258 /* Make sure this is a legal cdclk value for the platform */ 2259 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); 2260 if (cdclk != display->cdclk.hw.cdclk) 2261 goto sanitize; 2262 2263 /* Make sure the VCO is correct for the cdclk */ 2264 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 2265 if (vco != display->cdclk.hw.vco) 2266 goto sanitize; 2267 2268 /* 2269 * Some BIOS versions leave an incorrect decimal frequency value and 2270 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2271 * so sanitize this register. 2272 */ 2273 cdctl = intel_de_read(display, CDCLK_CTL); 2274 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); 2275 2276 /* 2277 * Let's ignore the pipe field, since BIOS could have configured the 2278 * dividers both syncing to an active pipe, or asynchronously 2279 * (PIPE_NONE). 2280 */ 2281 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2282 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2283 2284 if (cdctl == expected) 2285 /* All well; nothing to sanitize */ 2286 return; 2287 2288 sanitize: 2289 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 2290 2291 /* force cdclk programming */ 2292 display->cdclk.hw.cdclk = 0; 2293 2294 /* force full PLL disable + enable */ 2295 display->cdclk.hw.vco = ~0; 2296 } 2297 2298 static void bxt_cdclk_init_hw(struct intel_display *display) 2299 { 2300 struct intel_cdclk_config cdclk_config; 2301 2302 bxt_sanitize_cdclk(display); 2303 2304 if (display->cdclk.hw.cdclk != 0 && 2305 display->cdclk.hw.vco != 0) 2306 return; 2307 2308 cdclk_config = display->cdclk.hw; 2309 2310 /* 2311 * FIXME: 2312 * - The initial CDCLK needs to be read from VBT. 2313 * Need to make this change after VBT has changes for BXT. 2314 */ 2315 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); 2316 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); 2317 cdclk_config.voltage_level = 2318 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2319 2320 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2321 } 2322 2323 static void bxt_cdclk_uninit_hw(struct intel_display *display) 2324 { 2325 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 2326 2327 cdclk_config.cdclk = cdclk_config.bypass; 2328 cdclk_config.vco = 0; 2329 cdclk_config.voltage_level = 2330 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2331 2332 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2333 } 2334 2335 /** 2336 * intel_cdclk_init_hw - Initialize CDCLK hardware 2337 * @display: display instance 2338 * 2339 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and 2340 * sanitizing the state of the hardware if needed. This is generally done only 2341 * during the display core initialization sequence, after which the DMC will 2342 * take care of turning CDCLK off/on as needed. 2343 */ 2344 void intel_cdclk_init_hw(struct intel_display *display) 2345 { 2346 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2347 bxt_cdclk_init_hw(display); 2348 else if (DISPLAY_VER(display) == 9) 2349 skl_cdclk_init_hw(display); 2350 } 2351 2352 /** 2353 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2354 * @display: display instance 2355 * 2356 * Uninitialize CDCLK. This is done only during the display core 2357 * uninitialization sequence. 2358 */ 2359 void intel_cdclk_uninit_hw(struct intel_display *display) 2360 { 2361 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2362 bxt_cdclk_uninit_hw(display); 2363 else if (DISPLAY_VER(display) == 9) 2364 skl_cdclk_uninit_hw(display); 2365 } 2366 2367 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, 2368 const struct intel_cdclk_config *a, 2369 const struct intel_cdclk_config *b) 2370 { 2371 u16 old_waveform; 2372 u16 new_waveform; 2373 2374 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); 2375 2376 if (a->vco == 0 || b->vco == 0) 2377 return false; 2378 2379 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2380 return false; 2381 2382 old_waveform = cdclk_squash_waveform(display, a->cdclk); 2383 new_waveform = cdclk_squash_waveform(display, b->cdclk); 2384 2385 return a->vco != b->vco && 2386 old_waveform != new_waveform; 2387 } 2388 2389 static bool intel_cdclk_can_crawl(struct intel_display *display, 2390 const struct intel_cdclk_config *a, 2391 const struct intel_cdclk_config *b) 2392 { 2393 int a_div, b_div; 2394 2395 if (!HAS_CDCLK_CRAWL(display)) 2396 return false; 2397 2398 /* 2399 * The vco and cd2x divider will change independently 2400 * from each, so we disallow cd2x change when crawling. 2401 */ 2402 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2403 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2404 2405 return a->vco != 0 && b->vco != 0 && 2406 a->vco != b->vco && 2407 a_div == b_div && 2408 a->ref == b->ref; 2409 } 2410 2411 static bool intel_cdclk_can_squash(struct intel_display *display, 2412 const struct intel_cdclk_config *a, 2413 const struct intel_cdclk_config *b) 2414 { 2415 /* 2416 * FIXME should store a bit more state in intel_cdclk_config 2417 * to differentiate squasher vs. cd2x divider properly. For 2418 * the moment all platforms with squasher use a fixed cd2x 2419 * divider. 2420 */ 2421 if (!HAS_CDCLK_SQUASH(display)) 2422 return false; 2423 2424 return a->cdclk != b->cdclk && 2425 a->vco != 0 && 2426 a->vco == b->vco && 2427 a->ref == b->ref; 2428 } 2429 2430 /** 2431 * intel_cdclk_clock_changed - Check whether the clock changed 2432 * @a: first CDCLK configuration 2433 * @b: second CDCLK configuration 2434 * 2435 * Returns: 2436 * True if CDCLK changed in a way that requires re-programming and 2437 * False otherwise. 2438 */ 2439 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2440 const struct intel_cdclk_config *b) 2441 { 2442 return a->cdclk != b->cdclk || 2443 a->vco != b->vco || 2444 a->ref != b->ref; 2445 } 2446 2447 /** 2448 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2449 * configurations requires only a cd2x divider update 2450 * @display: display instance 2451 * @a: first CDCLK configuration 2452 * @b: second CDCLK configuration 2453 * 2454 * Returns: 2455 * True if changing between the two CDCLK configurations 2456 * can be done with just a cd2x divider update, false if not. 2457 */ 2458 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, 2459 const struct intel_cdclk_config *a, 2460 const struct intel_cdclk_config *b) 2461 { 2462 /* Older hw doesn't have the capability */ 2463 if (DISPLAY_VER(display) < 10 && !display->platform.broxton) 2464 return false; 2465 2466 /* 2467 * FIXME should store a bit more state in intel_cdclk_config 2468 * to differentiate squasher vs. cd2x divider properly. For 2469 * the moment all platforms with squasher use a fixed cd2x 2470 * divider. 2471 */ 2472 if (HAS_CDCLK_SQUASH(display)) 2473 return false; 2474 2475 return a->cdclk != b->cdclk && 2476 a->vco != 0 && 2477 a->vco == b->vco && 2478 a->ref == b->ref; 2479 } 2480 2481 /** 2482 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2483 * @a: first CDCLK configuration 2484 * @b: second CDCLK configuration 2485 * 2486 * Returns: 2487 * True if the CDCLK configurations don't match, false if they do. 2488 */ 2489 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2490 const struct intel_cdclk_config *b) 2491 { 2492 return intel_cdclk_clock_changed(a, b) || 2493 a->voltage_level != b->voltage_level; 2494 } 2495 2496 void intel_cdclk_dump_config(struct intel_display *display, 2497 const struct intel_cdclk_config *cdclk_config, 2498 const char *context) 2499 { 2500 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2501 context, cdclk_config->cdclk, cdclk_config->vco, 2502 cdclk_config->ref, cdclk_config->bypass, 2503 cdclk_config->voltage_level); 2504 } 2505 2506 static void intel_pcode_notify(struct intel_display *display, 2507 u8 voltage_level, 2508 u8 active_pipe_count, 2509 u16 cdclk, 2510 bool cdclk_update_valid, 2511 bool pipe_count_update_valid) 2512 { 2513 int ret; 2514 u32 update_mask = 0; 2515 2516 if (!display->platform.dg2) 2517 return; 2518 2519 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2520 2521 if (cdclk_update_valid) 2522 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2523 2524 if (pipe_count_update_valid) 2525 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2526 2527 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 2528 SKL_CDCLK_PREPARE_FOR_CHANGE | 2529 update_mask, 2530 SKL_CDCLK_READY_FOR_CHANGE, 2531 SKL_CDCLK_READY_FOR_CHANGE, 3); 2532 if (ret) 2533 drm_err(display->drm, 2534 "Failed to inform PCU about display config (err %d)\n", 2535 ret); 2536 } 2537 2538 static void intel_set_cdclk(struct intel_display *display, 2539 const struct intel_cdclk_config *cdclk_config, 2540 enum pipe pipe, const char *context) 2541 { 2542 struct intel_encoder *encoder; 2543 2544 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) 2545 return; 2546 2547 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) 2548 return; 2549 2550 intel_cdclk_dump_config(display, cdclk_config, context); 2551 2552 for_each_intel_encoder_with_psr(display->drm, encoder) { 2553 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2554 2555 intel_psr_pause(intel_dp); 2556 } 2557 2558 intel_audio_cdclk_change_pre(display); 2559 2560 /* 2561 * Lock aux/gmbus while we change cdclk in case those 2562 * functions use cdclk. Not all platforms/ports do, 2563 * but we'll lock them all for simplicity. 2564 */ 2565 mutex_lock(&display->gmbus.mutex); 2566 for_each_intel_dp(display->drm, encoder) { 2567 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2568 2569 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2570 &display->gmbus.mutex); 2571 } 2572 2573 intel_cdclk_set_cdclk(display, cdclk_config, pipe); 2574 2575 for_each_intel_dp(display->drm, encoder) { 2576 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2577 2578 mutex_unlock(&intel_dp->aux.hw_mutex); 2579 } 2580 mutex_unlock(&display->gmbus.mutex); 2581 2582 for_each_intel_encoder_with_psr(display->drm, encoder) { 2583 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2584 2585 intel_psr_resume(intel_dp); 2586 } 2587 2588 intel_audio_cdclk_change_post(display); 2589 2590 if (drm_WARN(display->drm, 2591 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), 2592 "cdclk state doesn't match!\n")) { 2593 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); 2594 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); 2595 } 2596 } 2597 2598 static bool dg2_power_well_count(struct intel_display *display, 2599 const struct intel_cdclk_state *cdclk_state) 2600 { 2601 return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0; 2602 } 2603 2604 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2605 { 2606 struct intel_display *display = to_intel_display(state); 2607 const struct intel_cdclk_state *old_cdclk_state = 2608 intel_atomic_get_old_cdclk_state(state); 2609 const struct intel_cdclk_state *new_cdclk_state = 2610 intel_atomic_get_new_cdclk_state(state); 2611 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2612 bool change_cdclk, update_pipe_count; 2613 2614 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2615 &new_cdclk_state->actual) && 2616 dg2_power_well_count(display, old_cdclk_state) == 2617 dg2_power_well_count(display, new_cdclk_state)) 2618 return; 2619 2620 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2621 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2622 2623 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2624 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) > 2625 dg2_power_well_count(display, old_cdclk_state); 2626 2627 /* 2628 * According to "Sequence Before Frequency Change", 2629 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2630 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2631 * which basically means we choose the maximum of old and new CDCLK, if we know both 2632 */ 2633 if (change_cdclk) 2634 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2635 2636 /* 2637 * According to "Sequence For Pipe Count Change", 2638 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2639 * (power well is enabled) 2640 * no action if it is decreasing, before the change 2641 */ 2642 if (update_pipe_count) 2643 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); 2644 2645 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2646 change_cdclk, update_pipe_count); 2647 } 2648 2649 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2650 { 2651 struct intel_display *display = to_intel_display(state); 2652 const struct intel_cdclk_state *new_cdclk_state = 2653 intel_atomic_get_new_cdclk_state(state); 2654 const struct intel_cdclk_state *old_cdclk_state = 2655 intel_atomic_get_old_cdclk_state(state); 2656 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2657 bool update_cdclk, update_pipe_count; 2658 2659 /* According to "Sequence After Frequency Change", set voltage to used level */ 2660 voltage_level = new_cdclk_state->actual.voltage_level; 2661 2662 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2663 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) < 2664 dg2_power_well_count(display, old_cdclk_state); 2665 2666 /* 2667 * According to "Sequence After Frequency Change", 2668 * set bits 25:16 to current CDCLK 2669 */ 2670 if (update_cdclk) 2671 cdclk = new_cdclk_state->actual.cdclk; 2672 2673 /* 2674 * According to "Sequence For Pipe Count Change", 2675 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2676 * after the change(power well is disabled) 2677 * no action if it is increasing, after the change 2678 */ 2679 if (update_pipe_count) 2680 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); 2681 2682 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2683 update_cdclk, update_pipe_count); 2684 } 2685 2686 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2687 { 2688 const struct intel_cdclk_state *old_cdclk_state = 2689 intel_atomic_get_old_cdclk_state(state); 2690 const struct intel_cdclk_state *new_cdclk_state = 2691 intel_atomic_get_new_cdclk_state(state); 2692 2693 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2694 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2695 } 2696 2697 /** 2698 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2699 * @state: intel atomic state 2700 * 2701 * Program the hardware before updating the HW plane state based on the 2702 * new CDCLK state, if necessary. 2703 */ 2704 void 2705 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2706 { 2707 struct intel_display *display = to_intel_display(state); 2708 const struct intel_cdclk_state *old_cdclk_state = 2709 intel_atomic_get_old_cdclk_state(state); 2710 const struct intel_cdclk_state *new_cdclk_state = 2711 intel_atomic_get_new_cdclk_state(state); 2712 struct intel_cdclk_config cdclk_config; 2713 enum pipe pipe; 2714 2715 if (!new_cdclk_state) 2716 return; 2717 2718 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2719 &new_cdclk_state->actual)) 2720 return; 2721 2722 if (display->platform.dg2) 2723 intel_cdclk_pcode_pre_notify(state); 2724 2725 if (new_cdclk_state->disable_pipes) { 2726 cdclk_config = new_cdclk_state->actual; 2727 pipe = INVALID_PIPE; 2728 } else { 2729 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2730 cdclk_config = new_cdclk_state->actual; 2731 pipe = new_cdclk_state->pipe; 2732 } else { 2733 cdclk_config = old_cdclk_state->actual; 2734 pipe = INVALID_PIPE; 2735 } 2736 2737 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2738 old_cdclk_state->actual.voltage_level); 2739 } 2740 2741 /* 2742 * mbus joining will be changed later by 2743 * intel_dbuf_mbus_{pre,post}_ddb_update() 2744 */ 2745 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2746 2747 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2748 2749 intel_set_cdclk(display, &cdclk_config, pipe, 2750 "Pre changing CDCLK to"); 2751 } 2752 2753 /** 2754 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2755 * @state: intel atomic state 2756 * 2757 * Program the hardware after updating the HW plane state based on the 2758 * new CDCLK state, if necessary. 2759 */ 2760 void 2761 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2762 { 2763 struct intel_display *display = to_intel_display(state); 2764 const struct intel_cdclk_state *old_cdclk_state = 2765 intel_atomic_get_old_cdclk_state(state); 2766 const struct intel_cdclk_state *new_cdclk_state = 2767 intel_atomic_get_new_cdclk_state(state); 2768 enum pipe pipe; 2769 2770 if (!new_cdclk_state) 2771 return; 2772 2773 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2774 &new_cdclk_state->actual)) 2775 return; 2776 2777 if (display->platform.dg2) 2778 intel_cdclk_pcode_post_notify(state); 2779 2780 if (!new_cdclk_state->disable_pipes && 2781 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2782 pipe = new_cdclk_state->pipe; 2783 else 2784 pipe = INVALID_PIPE; 2785 2786 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2787 2788 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, 2789 "Post changing CDCLK to"); 2790 } 2791 2792 /* pixels per CDCLK */ 2793 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) 2794 { 2795 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; 2796 } 2797 2798 /* max pixel rate as % of CDCLK (not accounting for PPC) */ 2799 static int intel_cdclk_guardband(struct intel_display *display) 2800 { 2801 if (DISPLAY_VER(display) >= 9 || 2802 display->platform.broadwell || display->platform.haswell) 2803 return 100; 2804 else if (display->platform.cherryview) 2805 return 95; 2806 else 2807 return 90; 2808 } 2809 2810 static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate) 2811 { 2812 struct intel_display *display = to_intel_display(crtc_state); 2813 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 2814 int guardband = intel_cdclk_guardband(display); 2815 2816 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); 2817 } 2818 2819 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2820 { 2821 return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate); 2822 } 2823 2824 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2825 { 2826 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2827 struct intel_display *display = to_intel_display(crtc); 2828 struct intel_plane *plane; 2829 int min_cdclk = 0; 2830 2831 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2832 min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]); 2833 2834 return min_cdclk; 2835 } 2836 2837 int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state) 2838 { 2839 int min_cdclk; 2840 2841 if (!crtc_state->hw.enable) 2842 return 0; 2843 2844 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2845 min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state)); 2846 min_cdclk = max(min_cdclk, intel_fbc_min_cdclk(crtc_state)); 2847 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state)); 2848 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state)); 2849 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); 2850 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state)); 2851 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2852 2853 return min_cdclk; 2854 } 2855 2856 static int intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state *state, 2857 struct intel_crtc *crtc, 2858 int old_min_cdclk, int new_min_cdclk, 2859 bool *need_cdclk_calc) 2860 { 2861 struct intel_display *display = to_intel_display(state); 2862 struct intel_cdclk_state *cdclk_state; 2863 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state); 2864 int ret; 2865 2866 if (new_min_cdclk == old_min_cdclk) 2867 return 0; 2868 2869 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2870 return 0; 2871 2872 cdclk_state = intel_atomic_get_cdclk_state(state); 2873 if (IS_ERR(cdclk_state)) 2874 return PTR_ERR(cdclk_state); 2875 2876 old_min_cdclk = cdclk_state->min_cdclk[crtc->pipe]; 2877 2878 if (new_min_cdclk == old_min_cdclk) 2879 return 0; 2880 2881 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2882 return 0; 2883 2884 cdclk_state->min_cdclk[crtc->pipe] = new_min_cdclk; 2885 2886 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2887 if (ret) 2888 return ret; 2889 2890 *need_cdclk_calc = true; 2891 2892 drm_dbg_kms(display->drm, 2893 "[CRTC:%d:%s] min cdclk: %d kHz -> %d kHz\n", 2894 crtc->base.base.id, crtc->base.name, 2895 old_min_cdclk, new_min_cdclk); 2896 2897 return 0; 2898 } 2899 2900 int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state, 2901 int old_min_cdclk, int new_min_cdclk, 2902 bool *need_cdclk_calc) 2903 { 2904 struct intel_display *display = to_intel_display(state); 2905 struct intel_cdclk_state *cdclk_state; 2906 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state); 2907 int ret; 2908 2909 if (new_min_cdclk == old_min_cdclk) 2910 return 0; 2911 2912 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2913 return 0; 2914 2915 cdclk_state = intel_atomic_get_cdclk_state(state); 2916 if (IS_ERR(cdclk_state)) 2917 return PTR_ERR(cdclk_state); 2918 2919 old_min_cdclk = cdclk_state->dbuf_bw_min_cdclk; 2920 2921 if (new_min_cdclk == old_min_cdclk) 2922 return 0; 2923 2924 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2925 return 0; 2926 2927 cdclk_state->dbuf_bw_min_cdclk = new_min_cdclk; 2928 2929 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2930 if (ret) 2931 return ret; 2932 2933 *need_cdclk_calc = true; 2934 2935 drm_dbg_kms(display->drm, 2936 "dbuf bandwidth min cdclk: %d kHz -> %d kHz\n", 2937 old_min_cdclk, new_min_cdclk); 2938 2939 return 0; 2940 } 2941 2942 static bool glk_cdclk_audio_wa_needed(struct intel_display *display, 2943 const struct intel_cdclk_state *cdclk_state) 2944 { 2945 return display->platform.geminilake && 2946 cdclk_state->enabled_pipes && 2947 !is_power_of_2(cdclk_state->enabled_pipes); 2948 } 2949 2950 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 2951 { 2952 struct intel_display *display = to_intel_display(state); 2953 struct intel_cdclk_state *cdclk_state = 2954 intel_atomic_get_new_cdclk_state(state); 2955 enum pipe pipe; 2956 int min_cdclk; 2957 2958 min_cdclk = cdclk_state->force_min_cdclk; 2959 min_cdclk = max(min_cdclk, cdclk_state->dbuf_bw_min_cdclk); 2960 for_each_pipe(display, pipe) 2961 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); 2962 2963 /* 2964 * Avoid glk_force_audio_cdclk() causing excessive screen 2965 * blinking when multiple pipes are active by making sure 2966 * CDCLK frequency is always high enough for audio. With a 2967 * single active pipe we can always change CDCLK frequency 2968 * by changing the cd2x divider (see glk_cdclk_table[]) and 2969 * thus a full modeset won't be needed then. 2970 */ 2971 if (glk_cdclk_audio_wa_needed(display, cdclk_state)) 2972 min_cdclk = max(min_cdclk, 2 * 96000); 2973 2974 if (min_cdclk > display->cdclk.max_cdclk_freq) { 2975 drm_dbg_kms(display->drm, 2976 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2977 min_cdclk, display->cdclk.max_cdclk_freq); 2978 return -EINVAL; 2979 } 2980 2981 return min_cdclk; 2982 } 2983 2984 /* 2985 * Account for port clock min voltage level requirements. 2986 * This only really does something on DISPLA_VER >= 11 but can be 2987 * called on earlier platforms as well. 2988 * 2989 * Note that this functions assumes that 0 is 2990 * the lowest voltage value, and higher values 2991 * correspond to increasingly higher voltages. 2992 * 2993 * Should that relationship no longer hold on 2994 * future platforms this code will need to be 2995 * adjusted. 2996 */ 2997 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 2998 { 2999 struct intel_display *display = to_intel_display(state); 3000 struct intel_cdclk_state *cdclk_state = 3001 intel_atomic_get_new_cdclk_state(state); 3002 struct intel_crtc *crtc; 3003 struct intel_crtc_state *crtc_state; 3004 u8 min_voltage_level; 3005 int i; 3006 enum pipe pipe; 3007 3008 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 3009 int ret; 3010 3011 if (crtc_state->hw.enable) 3012 min_voltage_level = crtc_state->min_voltage_level; 3013 else 3014 min_voltage_level = 0; 3015 3016 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 3017 continue; 3018 3019 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 3020 3021 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3022 if (ret) 3023 return ret; 3024 } 3025 3026 min_voltage_level = 0; 3027 for_each_pipe(display, pipe) 3028 min_voltage_level = max(min_voltage_level, 3029 cdclk_state->min_voltage_level[pipe]); 3030 3031 return min_voltage_level; 3032 } 3033 3034 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 3035 { 3036 struct intel_display *display = to_intel_display(state); 3037 struct intel_cdclk_state *cdclk_state = 3038 intel_atomic_get_new_cdclk_state(state); 3039 int min_cdclk, cdclk; 3040 3041 min_cdclk = intel_compute_min_cdclk(state); 3042 if (min_cdclk < 0) 3043 return min_cdclk; 3044 3045 cdclk = vlv_calc_cdclk(display, min_cdclk); 3046 3047 cdclk_state->logical.cdclk = cdclk; 3048 cdclk_state->logical.voltage_level = 3049 vlv_calc_voltage_level(display, cdclk); 3050 3051 if (!cdclk_state->active_pipes) { 3052 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); 3053 3054 cdclk_state->actual.cdclk = cdclk; 3055 cdclk_state->actual.voltage_level = 3056 vlv_calc_voltage_level(display, cdclk); 3057 } else { 3058 cdclk_state->actual = cdclk_state->logical; 3059 } 3060 3061 return 0; 3062 } 3063 3064 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 3065 { 3066 struct intel_cdclk_state *cdclk_state = 3067 intel_atomic_get_new_cdclk_state(state); 3068 int min_cdclk, cdclk; 3069 3070 min_cdclk = intel_compute_min_cdclk(state); 3071 if (min_cdclk < 0) 3072 return min_cdclk; 3073 3074 cdclk = bdw_calc_cdclk(min_cdclk); 3075 3076 cdclk_state->logical.cdclk = cdclk; 3077 cdclk_state->logical.voltage_level = 3078 bdw_calc_voltage_level(cdclk); 3079 3080 if (!cdclk_state->active_pipes) { 3081 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 3082 3083 cdclk_state->actual.cdclk = cdclk; 3084 cdclk_state->actual.voltage_level = 3085 bdw_calc_voltage_level(cdclk); 3086 } else { 3087 cdclk_state->actual = cdclk_state->logical; 3088 } 3089 3090 return 0; 3091 } 3092 3093 static int skl_dpll0_vco(struct intel_atomic_state *state) 3094 { 3095 struct intel_display *display = to_intel_display(state); 3096 struct intel_cdclk_state *cdclk_state = 3097 intel_atomic_get_new_cdclk_state(state); 3098 struct intel_crtc *crtc; 3099 struct intel_crtc_state *crtc_state; 3100 int vco, i; 3101 3102 vco = cdclk_state->logical.vco; 3103 if (!vco) 3104 vco = display->cdclk.skl_preferred_vco_freq; 3105 3106 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 3107 if (!crtc_state->hw.enable) 3108 continue; 3109 3110 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3111 continue; 3112 3113 /* 3114 * DPLL0 VCO may need to be adjusted to get the correct 3115 * clock for eDP. This will affect cdclk as well. 3116 */ 3117 switch (crtc_state->port_clock / 2) { 3118 case 108000: 3119 case 216000: 3120 vco = 8640000; 3121 break; 3122 default: 3123 vco = 8100000; 3124 break; 3125 } 3126 } 3127 3128 return vco; 3129 } 3130 3131 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3132 { 3133 struct intel_cdclk_state *cdclk_state = 3134 intel_atomic_get_new_cdclk_state(state); 3135 int min_cdclk, cdclk, vco; 3136 3137 min_cdclk = intel_compute_min_cdclk(state); 3138 if (min_cdclk < 0) 3139 return min_cdclk; 3140 3141 vco = skl_dpll0_vco(state); 3142 3143 cdclk = skl_calc_cdclk(min_cdclk, vco); 3144 3145 cdclk_state->logical.vco = vco; 3146 cdclk_state->logical.cdclk = cdclk; 3147 cdclk_state->logical.voltage_level = 3148 skl_calc_voltage_level(cdclk); 3149 3150 if (!cdclk_state->active_pipes) { 3151 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3152 3153 cdclk_state->actual.vco = vco; 3154 cdclk_state->actual.cdclk = cdclk; 3155 cdclk_state->actual.voltage_level = 3156 skl_calc_voltage_level(cdclk); 3157 } else { 3158 cdclk_state->actual = cdclk_state->logical; 3159 } 3160 3161 return 0; 3162 } 3163 3164 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3165 { 3166 struct intel_display *display = to_intel_display(state); 3167 struct intel_cdclk_state *cdclk_state = 3168 intel_atomic_get_new_cdclk_state(state); 3169 int min_cdclk, min_voltage_level, cdclk, vco; 3170 3171 min_cdclk = intel_compute_min_cdclk(state); 3172 if (min_cdclk < 0) 3173 return min_cdclk; 3174 3175 min_voltage_level = bxt_compute_min_voltage_level(state); 3176 if (min_voltage_level < 0) 3177 return min_voltage_level; 3178 3179 cdclk = bxt_calc_cdclk(display, min_cdclk); 3180 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3181 3182 cdclk_state->logical.vco = vco; 3183 cdclk_state->logical.cdclk = cdclk; 3184 cdclk_state->logical.voltage_level = 3185 max_t(int, min_voltage_level, 3186 intel_cdclk_calc_voltage_level(display, cdclk)); 3187 3188 if (!cdclk_state->active_pipes) { 3189 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); 3190 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3191 3192 cdclk_state->actual.vco = vco; 3193 cdclk_state->actual.cdclk = cdclk; 3194 cdclk_state->actual.voltage_level = 3195 intel_cdclk_calc_voltage_level(display, cdclk); 3196 } else { 3197 cdclk_state->actual = cdclk_state->logical; 3198 } 3199 3200 return 0; 3201 } 3202 3203 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3204 { 3205 int min_cdclk; 3206 3207 /* 3208 * We can't change the cdclk frequency, but we still want to 3209 * check that the required minimum frequency doesn't exceed 3210 * the actual cdclk frequency. 3211 */ 3212 min_cdclk = intel_compute_min_cdclk(state); 3213 if (min_cdclk < 0) 3214 return min_cdclk; 3215 3216 return 0; 3217 } 3218 3219 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3220 { 3221 struct intel_cdclk_state *cdclk_state; 3222 3223 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3224 if (!cdclk_state) 3225 return NULL; 3226 3227 cdclk_state->pipe = INVALID_PIPE; 3228 cdclk_state->disable_pipes = false; 3229 3230 return &cdclk_state->base; 3231 } 3232 3233 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3234 struct intel_global_state *state) 3235 { 3236 kfree(state); 3237 } 3238 3239 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3240 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3241 .atomic_destroy_state = intel_cdclk_destroy_state, 3242 }; 3243 3244 struct intel_cdclk_state * 3245 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3246 { 3247 struct intel_display *display = to_intel_display(state); 3248 struct intel_global_state *cdclk_state; 3249 3250 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); 3251 if (IS_ERR(cdclk_state)) 3252 return ERR_CAST(cdclk_state); 3253 3254 return to_intel_cdclk_state(cdclk_state); 3255 } 3256 3257 static int intel_cdclk_modeset_checks(struct intel_atomic_state *state, 3258 bool *need_cdclk_calc) 3259 { 3260 struct intel_display *display = to_intel_display(state); 3261 const struct intel_cdclk_state *old_cdclk_state; 3262 struct intel_cdclk_state *new_cdclk_state; 3263 int ret; 3264 3265 if (!intel_any_crtc_enable_changed(state) && 3266 !intel_any_crtc_active_changed(state)) 3267 return 0; 3268 3269 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3270 if (IS_ERR(new_cdclk_state)) 3271 return PTR_ERR(new_cdclk_state); 3272 3273 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3274 3275 new_cdclk_state->enabled_pipes = 3276 intel_calc_enabled_pipes(state, old_cdclk_state->enabled_pipes); 3277 3278 new_cdclk_state->active_pipes = 3279 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3280 3281 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3282 if (ret) 3283 return ret; 3284 3285 if (!old_cdclk_state->active_pipes != !new_cdclk_state->active_pipes) 3286 *need_cdclk_calc = true; 3287 3288 if (glk_cdclk_audio_wa_needed(display, old_cdclk_state) != 3289 glk_cdclk_audio_wa_needed(display, new_cdclk_state)) 3290 *need_cdclk_calc = true; 3291 3292 if (dg2_power_well_count(display, old_cdclk_state) != 3293 dg2_power_well_count(display, new_cdclk_state)) 3294 *need_cdclk_calc = true; 3295 3296 return 0; 3297 } 3298 3299 static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state, 3300 bool *need_cdclk_calc) 3301 { 3302 const struct intel_crtc_state *old_crtc_state; 3303 const struct intel_crtc_state *new_crtc_state; 3304 struct intel_crtc *crtc; 3305 int i, ret; 3306 3307 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 3308 new_crtc_state, i) { 3309 ret = intel_cdclk_update_crtc_min_cdclk(state, crtc, 3310 old_crtc_state->min_cdclk, 3311 new_crtc_state->min_cdclk, 3312 need_cdclk_calc); 3313 if (ret) 3314 return ret; 3315 } 3316 3317 return 0; 3318 } 3319 3320 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3321 { 3322 struct intel_cdclk_state *cdclk_state; 3323 3324 cdclk_state = intel_atomic_get_cdclk_state(state); 3325 if (IS_ERR(cdclk_state)) 3326 return PTR_ERR(cdclk_state); 3327 3328 cdclk_state->actual.joined_mbus = joined_mbus; 3329 cdclk_state->logical.joined_mbus = joined_mbus; 3330 3331 return intel_atomic_lock_global_state(&cdclk_state->base); 3332 } 3333 3334 int intel_cdclk_init(struct intel_display *display) 3335 { 3336 struct intel_cdclk_state *cdclk_state; 3337 3338 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 3339 if (!cdclk_state) 3340 return -ENOMEM; 3341 3342 intel_atomic_global_obj_init(display, &display->cdclk.obj, 3343 &cdclk_state->base, &intel_cdclk_funcs); 3344 3345 return 0; 3346 } 3347 3348 static bool intel_cdclk_need_serialize(struct intel_display *display, 3349 const struct intel_cdclk_state *old_cdclk_state, 3350 const struct intel_cdclk_state *new_cdclk_state) 3351 { 3352 /* 3353 * We need to poke hw for DG2, because we notify PCode if 3354 * pipe power well count changes. 3355 */ 3356 return intel_cdclk_changed(&old_cdclk_state->actual, 3357 &new_cdclk_state->actual) || 3358 dg2_power_well_count(display, old_cdclk_state) != 3359 dg2_power_well_count(display, new_cdclk_state); 3360 } 3361 3362 static int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3363 { 3364 struct intel_display *display = to_intel_display(state); 3365 const struct intel_cdclk_state *old_cdclk_state; 3366 struct intel_cdclk_state *new_cdclk_state; 3367 enum pipe pipe = INVALID_PIPE; 3368 int ret; 3369 3370 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3371 if (IS_ERR(new_cdclk_state)) 3372 return PTR_ERR(new_cdclk_state); 3373 3374 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3375 3376 ret = intel_cdclk_modeset_calc_cdclk(state); 3377 if (ret) 3378 return ret; 3379 3380 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { 3381 /* 3382 * Also serialize commits across all crtcs 3383 * if the actual hw needs to be poked. 3384 */ 3385 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3386 if (ret) 3387 return ret; 3388 } else if (intel_cdclk_changed(&old_cdclk_state->logical, 3389 &new_cdclk_state->logical)) { 3390 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3391 if (ret) 3392 return ret; 3393 } else { 3394 return 0; 3395 } 3396 3397 if (is_power_of_2(new_cdclk_state->active_pipes) && 3398 intel_cdclk_can_cd2x_update(display, 3399 &old_cdclk_state->actual, 3400 &new_cdclk_state->actual)) { 3401 struct intel_crtc *crtc; 3402 struct intel_crtc_state *crtc_state; 3403 3404 pipe = ilog2(new_cdclk_state->active_pipes); 3405 crtc = intel_crtc_for_pipe(display, pipe); 3406 3407 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3408 if (IS_ERR(crtc_state)) 3409 return PTR_ERR(crtc_state); 3410 3411 if (intel_crtc_needs_modeset(crtc_state)) 3412 pipe = INVALID_PIPE; 3413 } 3414 3415 if (intel_cdclk_can_crawl_and_squash(display, 3416 &old_cdclk_state->actual, 3417 &new_cdclk_state->actual)) { 3418 drm_dbg_kms(display->drm, 3419 "Can change cdclk via crawling and squashing\n"); 3420 } else if (intel_cdclk_can_squash(display, 3421 &old_cdclk_state->actual, 3422 &new_cdclk_state->actual)) { 3423 drm_dbg_kms(display->drm, 3424 "Can change cdclk via squashing\n"); 3425 } else if (intel_cdclk_can_crawl(display, 3426 &old_cdclk_state->actual, 3427 &new_cdclk_state->actual)) { 3428 drm_dbg_kms(display->drm, 3429 "Can change cdclk via crawling\n"); 3430 } else if (pipe != INVALID_PIPE) { 3431 new_cdclk_state->pipe = pipe; 3432 3433 drm_dbg_kms(display->drm, 3434 "Can change cdclk cd2x divider with pipe %c active\n", 3435 pipe_name(pipe)); 3436 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3437 &new_cdclk_state->actual)) { 3438 /* All pipes must be switched off while we change the cdclk. */ 3439 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3440 if (ret) 3441 return ret; 3442 3443 new_cdclk_state->disable_pipes = true; 3444 3445 drm_dbg_kms(display->drm, 3446 "Modeset required for cdclk change\n"); 3447 } 3448 3449 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != 3450 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { 3451 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); 3452 3453 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3454 if (ret) 3455 return ret; 3456 } 3457 3458 drm_dbg_kms(display->drm, 3459 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3460 new_cdclk_state->logical.cdclk, 3461 new_cdclk_state->actual.cdclk); 3462 drm_dbg_kms(display->drm, 3463 "New voltage level calculated to be logical %u, actual %u\n", 3464 new_cdclk_state->logical.voltage_level, 3465 new_cdclk_state->actual.voltage_level); 3466 3467 return 0; 3468 } 3469 3470 int intel_cdclk_atomic_check(struct intel_atomic_state *state) 3471 { 3472 const struct intel_cdclk_state *old_cdclk_state; 3473 struct intel_cdclk_state *new_cdclk_state; 3474 bool need_cdclk_calc = false; 3475 int ret; 3476 3477 ret = intel_cdclk_modeset_checks(state, &need_cdclk_calc); 3478 if (ret) 3479 return ret; 3480 3481 ret = intel_crtcs_calc_min_cdclk(state, &need_cdclk_calc); 3482 if (ret) 3483 return ret; 3484 3485 ret = intel_dbuf_bw_calc_min_cdclk(state, &need_cdclk_calc); 3486 if (ret) 3487 return ret; 3488 3489 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3490 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3491 3492 if (new_cdclk_state && 3493 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) { 3494 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3495 if (ret) 3496 return ret; 3497 3498 need_cdclk_calc = true; 3499 } 3500 3501 if (need_cdclk_calc) { 3502 ret = intel_modeset_calc_cdclk(state); 3503 if (ret) 3504 return ret; 3505 } 3506 3507 return 0; 3508 } 3509 3510 void intel_cdclk_update_hw_state(struct intel_display *display) 3511 { 3512 const struct intel_dbuf_bw_state *dbuf_bw_state = 3513 to_intel_dbuf_bw_state(display->dbuf_bw.obj.state); 3514 struct intel_cdclk_state *cdclk_state = 3515 to_intel_cdclk_state(display->cdclk.obj.state); 3516 struct intel_crtc *crtc; 3517 3518 cdclk_state->enabled_pipes = 0; 3519 cdclk_state->active_pipes = 0; 3520 3521 for_each_intel_crtc(display->drm, crtc) { 3522 const struct intel_crtc_state *crtc_state = 3523 to_intel_crtc_state(crtc->base.state); 3524 enum pipe pipe = crtc->pipe; 3525 3526 if (crtc_state->hw.enable) 3527 cdclk_state->enabled_pipes |= BIT(pipe); 3528 if (crtc_state->hw.active) 3529 cdclk_state->active_pipes |= BIT(pipe); 3530 3531 cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk; 3532 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level; 3533 } 3534 3535 cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display, dbuf_bw_state); 3536 } 3537 3538 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc) 3539 { 3540 struct intel_display *display = to_intel_display(crtc); 3541 3542 intel_cdclk_update_hw_state(display); 3543 } 3544 3545 static int intel_compute_max_dotclk(struct intel_display *display) 3546 { 3547 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); 3548 int guardband = intel_cdclk_guardband(display); 3549 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3550 3551 return ppc * max_cdclk_freq * guardband / 100; 3552 } 3553 3554 /** 3555 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3556 * @display: display instance 3557 * 3558 * Determine the maximum CDCLK frequency the platform supports, and also 3559 * derive the maximum dot clock frequency the maximum CDCLK frequency 3560 * allows. 3561 */ 3562 void intel_update_max_cdclk(struct intel_display *display) 3563 { 3564 if (DISPLAY_VERx100(display) >= 3002) { 3565 display->cdclk.max_cdclk_freq = 480000; 3566 } else if (DISPLAY_VER(display) >= 30) { 3567 display->cdclk.max_cdclk_freq = 691200; 3568 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3569 if (display->cdclk.hw.ref == 24000) 3570 display->cdclk.max_cdclk_freq = 552000; 3571 else 3572 display->cdclk.max_cdclk_freq = 556800; 3573 } else if (DISPLAY_VER(display) >= 11) { 3574 if (display->cdclk.hw.ref == 24000) 3575 display->cdclk.max_cdclk_freq = 648000; 3576 else 3577 display->cdclk.max_cdclk_freq = 652800; 3578 } else if (display->platform.geminilake) { 3579 display->cdclk.max_cdclk_freq = 316800; 3580 } else if (display->platform.broxton) { 3581 display->cdclk.max_cdclk_freq = 624000; 3582 } else if (DISPLAY_VER(display) == 9) { 3583 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3584 int max_cdclk, vco; 3585 3586 vco = display->cdclk.skl_preferred_vco_freq; 3587 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 3588 3589 /* 3590 * Use the lower (vco 8640) cdclk values as a 3591 * first guess. skl_calc_cdclk() will correct it 3592 * if the preferred vco is 8100 instead. 3593 */ 3594 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3595 max_cdclk = 617143; 3596 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3597 max_cdclk = 540000; 3598 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3599 max_cdclk = 432000; 3600 else 3601 max_cdclk = 308571; 3602 3603 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3604 } else if (display->platform.broadwell) { 3605 /* 3606 * FIXME with extra cooling we can allow 3607 * 540 MHz for ULX and 675 Mhz for ULT. 3608 * How can we know if extra cooling is 3609 * available? PCI ID, VTB, something else? 3610 */ 3611 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3612 display->cdclk.max_cdclk_freq = 450000; 3613 else if (display->platform.broadwell_ulx) 3614 display->cdclk.max_cdclk_freq = 450000; 3615 else if (display->platform.broadwell_ult) 3616 display->cdclk.max_cdclk_freq = 540000; 3617 else 3618 display->cdclk.max_cdclk_freq = 675000; 3619 } else if (display->platform.cherryview) { 3620 display->cdclk.max_cdclk_freq = 320000; 3621 } else if (display->platform.valleyview) { 3622 display->cdclk.max_cdclk_freq = 400000; 3623 } else { 3624 /* otherwise assume cdclk is fixed */ 3625 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; 3626 } 3627 3628 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); 3629 3630 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", 3631 display->cdclk.max_cdclk_freq); 3632 3633 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", 3634 display->cdclk.max_dotclk_freq); 3635 } 3636 3637 /** 3638 * intel_update_cdclk - Determine the current CDCLK frequency 3639 * @display: display instance 3640 * 3641 * Determine the current CDCLK frequency. 3642 */ 3643 void intel_update_cdclk(struct intel_display *display) 3644 { 3645 intel_cdclk_get_cdclk(display, &display->cdclk.hw); 3646 3647 /* 3648 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3649 * Programmng [sic] note: bit[9:2] should be programmed to the number 3650 * of cdclk that generates 4MHz reference clock freq which is used to 3651 * generate GMBus clock. This will vary with the cdclk freq. 3652 */ 3653 if (display->platform.valleyview || display->platform.cherryview) 3654 intel_de_write(display, GMBUSFREQ_VLV, 3655 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); 3656 } 3657 3658 static int dg1_rawclk(struct intel_display *display) 3659 { 3660 /* 3661 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3662 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3663 */ 3664 intel_de_write(display, PCH_RAWCLK_FREQ, 3665 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3666 3667 return 38400; 3668 } 3669 3670 static int cnp_rawclk(struct intel_display *display) 3671 { 3672 int divider, fraction; 3673 u32 rawclk; 3674 3675 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3676 /* 24 MHz */ 3677 divider = 24000; 3678 fraction = 0; 3679 } else { 3680 /* 19.2 MHz */ 3681 divider = 19000; 3682 fraction = 200; 3683 } 3684 3685 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3686 if (fraction) { 3687 int numerator = 1; 3688 3689 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3690 fraction) - 1); 3691 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 3692 rawclk |= ICP_RAWCLK_NUM(numerator); 3693 } 3694 3695 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); 3696 return divider + fraction; 3697 } 3698 3699 static int pch_rawclk(struct intel_display *display) 3700 { 3701 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3702 } 3703 3704 static int i9xx_hrawclk(struct intel_display *display) 3705 { 3706 struct drm_i915_private *i915 = to_i915(display->drm); 3707 3708 /* hrawclock is 1/4 the FSB frequency */ 3709 return DIV_ROUND_CLOSEST(intel_fsb_freq(i915), 4); 3710 } 3711 3712 /** 3713 * intel_read_rawclk - Determine the current RAWCLK frequency 3714 * @display: display instance 3715 * 3716 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3717 * frequency clock so this needs to done only once. 3718 */ 3719 u32 intel_read_rawclk(struct intel_display *display) 3720 { 3721 u32 freq; 3722 3723 if (INTEL_PCH_TYPE(display) >= PCH_MTL) 3724 /* 3725 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3726 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3727 * not need to be programmed." 3728 */ 3729 freq = 38400; 3730 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 3731 freq = dg1_rawclk(display); 3732 else if (INTEL_PCH_TYPE(display) >= PCH_CNP) 3733 freq = cnp_rawclk(display); 3734 else if (HAS_PCH_SPLIT(display)) 3735 freq = pch_rawclk(display); 3736 else if (display->platform.valleyview || display->platform.cherryview) 3737 freq = vlv_clock_get_hrawclk(display->drm); 3738 else if (DISPLAY_VER(display) >= 3) 3739 freq = i9xx_hrawclk(display); 3740 else 3741 /* no rawclk on other platforms, or no need to know it */ 3742 return 0; 3743 3744 return freq; 3745 } 3746 3747 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3748 { 3749 struct intel_display *display = m->private; 3750 3751 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); 3752 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); 3753 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); 3754 3755 return 0; 3756 } 3757 3758 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3759 3760 void intel_cdclk_debugfs_register(struct intel_display *display) 3761 { 3762 debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root, 3763 display, &i915_cdclk_info_fops); 3764 } 3765 3766 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { 3767 .get_cdclk = bxt_get_cdclk, 3768 .set_cdclk = bxt_set_cdclk, 3769 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3770 .calc_voltage_level = xe3lpd_calc_voltage_level, 3771 }; 3772 3773 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3774 .get_cdclk = bxt_get_cdclk, 3775 .set_cdclk = bxt_set_cdclk, 3776 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3777 .calc_voltage_level = rplu_calc_voltage_level, 3778 }; 3779 3780 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3781 .get_cdclk = bxt_get_cdclk, 3782 .set_cdclk = bxt_set_cdclk, 3783 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3784 .calc_voltage_level = tgl_calc_voltage_level, 3785 }; 3786 3787 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3788 .get_cdclk = bxt_get_cdclk, 3789 .set_cdclk = bxt_set_cdclk, 3790 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3791 .calc_voltage_level = ehl_calc_voltage_level, 3792 }; 3793 3794 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3795 .get_cdclk = bxt_get_cdclk, 3796 .set_cdclk = bxt_set_cdclk, 3797 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3798 .calc_voltage_level = icl_calc_voltage_level, 3799 }; 3800 3801 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3802 .get_cdclk = bxt_get_cdclk, 3803 .set_cdclk = bxt_set_cdclk, 3804 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3805 .calc_voltage_level = bxt_calc_voltage_level, 3806 }; 3807 3808 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3809 .get_cdclk = skl_get_cdclk, 3810 .set_cdclk = skl_set_cdclk, 3811 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3812 }; 3813 3814 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3815 .get_cdclk = bdw_get_cdclk, 3816 .set_cdclk = bdw_set_cdclk, 3817 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3818 }; 3819 3820 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3821 .get_cdclk = vlv_get_cdclk, 3822 .set_cdclk = chv_set_cdclk, 3823 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3824 }; 3825 3826 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3827 .get_cdclk = vlv_get_cdclk, 3828 .set_cdclk = vlv_set_cdclk, 3829 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3830 }; 3831 3832 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3833 .get_cdclk = hsw_get_cdclk, 3834 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3835 }; 3836 3837 /* SNB, IVB, 965G, 945G */ 3838 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3839 .get_cdclk = fixed_400mhz_get_cdclk, 3840 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3841 }; 3842 3843 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3844 .get_cdclk = fixed_450mhz_get_cdclk, 3845 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3846 }; 3847 3848 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3849 .get_cdclk = gm45_get_cdclk, 3850 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3851 }; 3852 3853 /* G45 uses G33 */ 3854 3855 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3856 .get_cdclk = i965gm_get_cdclk, 3857 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3858 }; 3859 3860 /* i965G uses fixed 400 */ 3861 3862 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3863 .get_cdclk = pnv_get_cdclk, 3864 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3865 }; 3866 3867 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3868 .get_cdclk = g33_get_cdclk, 3869 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3870 }; 3871 3872 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3873 .get_cdclk = i945gm_get_cdclk, 3874 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3875 }; 3876 3877 /* i945G uses fixed 400 */ 3878 3879 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3880 .get_cdclk = i915gm_get_cdclk, 3881 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3882 }; 3883 3884 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3885 .get_cdclk = fixed_333mhz_get_cdclk, 3886 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3887 }; 3888 3889 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3890 .get_cdclk = fixed_266mhz_get_cdclk, 3891 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3892 }; 3893 3894 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3895 .get_cdclk = i85x_get_cdclk, 3896 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3897 }; 3898 3899 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3900 .get_cdclk = fixed_200mhz_get_cdclk, 3901 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3902 }; 3903 3904 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3905 .get_cdclk = fixed_133mhz_get_cdclk, 3906 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3907 }; 3908 3909 /** 3910 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3911 * @display: display instance 3912 */ 3913 void intel_init_cdclk_hooks(struct intel_display *display) 3914 { 3915 if (DISPLAY_VER(display) >= 30) { 3916 display->funcs.cdclk = &xe3lpd_cdclk_funcs; 3917 display->cdclk.table = xe3lpd_cdclk_table; 3918 } else if (DISPLAY_VER(display) >= 20) { 3919 display->funcs.cdclk = &rplu_cdclk_funcs; 3920 display->cdclk.table = xe2lpd_cdclk_table; 3921 } else if (DISPLAY_VERx100(display) >= 1401) { 3922 display->funcs.cdclk = &rplu_cdclk_funcs; 3923 display->cdclk.table = xe2hpd_cdclk_table; 3924 } else if (DISPLAY_VER(display) >= 14) { 3925 display->funcs.cdclk = &rplu_cdclk_funcs; 3926 display->cdclk.table = mtl_cdclk_table; 3927 } else if (display->platform.dg2) { 3928 display->funcs.cdclk = &tgl_cdclk_funcs; 3929 display->cdclk.table = dg2_cdclk_table; 3930 } else if (display->platform.alderlake_p) { 3931 /* Wa_22011320316:adl-p[a0] */ 3932 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 3933 display->cdclk.table = adlp_a_step_cdclk_table; 3934 display->funcs.cdclk = &tgl_cdclk_funcs; 3935 } else if (display->platform.alderlake_p_raptorlake_u) { 3936 display->cdclk.table = rplu_cdclk_table; 3937 display->funcs.cdclk = &rplu_cdclk_funcs; 3938 } else { 3939 display->cdclk.table = adlp_cdclk_table; 3940 display->funcs.cdclk = &tgl_cdclk_funcs; 3941 } 3942 } else if (display->platform.rocketlake) { 3943 display->funcs.cdclk = &tgl_cdclk_funcs; 3944 display->cdclk.table = rkl_cdclk_table; 3945 } else if (DISPLAY_VER(display) >= 12) { 3946 display->funcs.cdclk = &tgl_cdclk_funcs; 3947 display->cdclk.table = icl_cdclk_table; 3948 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3949 display->funcs.cdclk = &ehl_cdclk_funcs; 3950 display->cdclk.table = icl_cdclk_table; 3951 } else if (DISPLAY_VER(display) >= 11) { 3952 display->funcs.cdclk = &icl_cdclk_funcs; 3953 display->cdclk.table = icl_cdclk_table; 3954 } else if (display->platform.geminilake || display->platform.broxton) { 3955 display->funcs.cdclk = &bxt_cdclk_funcs; 3956 if (display->platform.geminilake) 3957 display->cdclk.table = glk_cdclk_table; 3958 else 3959 display->cdclk.table = bxt_cdclk_table; 3960 } else if (DISPLAY_VER(display) == 9) { 3961 display->funcs.cdclk = &skl_cdclk_funcs; 3962 } else if (display->platform.broadwell) { 3963 display->funcs.cdclk = &bdw_cdclk_funcs; 3964 } else if (display->platform.haswell) { 3965 display->funcs.cdclk = &hsw_cdclk_funcs; 3966 } else if (display->platform.cherryview) { 3967 display->funcs.cdclk = &chv_cdclk_funcs; 3968 } else if (display->platform.valleyview) { 3969 display->funcs.cdclk = &vlv_cdclk_funcs; 3970 } else if (display->platform.sandybridge || display->platform.ivybridge) { 3971 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3972 } else if (display->platform.ironlake) { 3973 display->funcs.cdclk = &ilk_cdclk_funcs; 3974 } else if (display->platform.gm45) { 3975 display->funcs.cdclk = &gm45_cdclk_funcs; 3976 } else if (display->platform.g45) { 3977 display->funcs.cdclk = &g33_cdclk_funcs; 3978 } else if (display->platform.i965gm) { 3979 display->funcs.cdclk = &i965gm_cdclk_funcs; 3980 } else if (display->platform.i965g) { 3981 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3982 } else if (display->platform.pineview) { 3983 display->funcs.cdclk = &pnv_cdclk_funcs; 3984 } else if (display->platform.g33) { 3985 display->funcs.cdclk = &g33_cdclk_funcs; 3986 } else if (display->platform.i945gm) { 3987 display->funcs.cdclk = &i945gm_cdclk_funcs; 3988 } else if (display->platform.i945g) { 3989 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3990 } else if (display->platform.i915gm) { 3991 display->funcs.cdclk = &i915gm_cdclk_funcs; 3992 } else if (display->platform.i915g) { 3993 display->funcs.cdclk = &i915g_cdclk_funcs; 3994 } else if (display->platform.i865g) { 3995 display->funcs.cdclk = &i865g_cdclk_funcs; 3996 } else if (display->platform.i85x) { 3997 display->funcs.cdclk = &i85x_cdclk_funcs; 3998 } else if (display->platform.i845g) { 3999 display->funcs.cdclk = &i845g_cdclk_funcs; 4000 } else if (display->platform.i830) { 4001 display->funcs.cdclk = &i830_cdclk_funcs; 4002 } 4003 4004 if (drm_WARN(display->drm, !display->funcs.cdclk, 4005 "Unknown platform. Assuming i830\n")) 4006 display->funcs.cdclk = &i830_cdclk_funcs; 4007 } 4008 4009 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state) 4010 { 4011 return cdclk_state->logical.cdclk; 4012 } 4013 4014 int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state) 4015 { 4016 return cdclk_state->actual.cdclk; 4017 } 4018 4019 int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state) 4020 { 4021 return cdclk_state->actual.voltage_level; 4022 } 4023 4024 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe) 4025 { 4026 return cdclk_state->min_cdclk[pipe]; 4027 } 4028 4029 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state) 4030 { 4031 const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state; 4032 4033 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 4034 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 4035 4036 if (new_cdclk_state && 4037 (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk || 4038 new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level)) 4039 return true; 4040 4041 return false; 4042 } 4043 4044 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk) 4045 { 4046 cdclk_state->force_min_cdclk = force_min_cdclk; 4047 } 4048 4049 void intel_cdclk_read_hw(struct intel_display *display) 4050 { 4051 struct intel_cdclk_state *cdclk_state; 4052 4053 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); 4054 4055 intel_update_cdclk(display); 4056 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 4057 cdclk_state->actual = display->cdclk.hw; 4058 cdclk_state->logical = display->cdclk.hw; 4059 } 4060 4061 static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk) 4062 { 4063 struct intel_display *display = to_intel_display(crtc_state); 4064 4065 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) { 4066 return bxt_calc_cdclk(display, min_cdclk); 4067 } else if (DISPLAY_VER(display) == 9) { 4068 int vco; 4069 4070 vco = display->cdclk.skl_preferred_vco_freq; 4071 if (vco == 0) 4072 vco = 8100000; 4073 4074 return skl_calc_cdclk(min_cdclk, vco); 4075 } else if (display->platform.broadwell) { 4076 return bdw_calc_cdclk(min_cdclk); 4077 } else if (display->platform.cherryview || display->platform.valleyview) { 4078 return vlv_calc_cdclk(display, min_cdclk); 4079 } else { 4080 return display->cdclk.max_cdclk_freq; 4081 } 4082 } 4083 4084 static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc_state, 4085 int clock, int min_cdclk) 4086 { 4087 struct intel_display *display = to_intel_display(crtc_state); 4088 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 4089 int cdclk = calc_cdclk(crtc_state, min_cdclk); 4090 4091 return min(0x10000, DIV_ROUND_UP_ULL((u64)clock << 16, ppc * cdclk)); 4092 } 4093 4094 unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) 4095 { 4096 /* FIXME use the actual min_cdclk for the pipe here */ 4097 return intel_cdclk_prefill_adjustment_worst(crtc_state); 4098 } 4099 4100 unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state) 4101 { 4102 int clock = crtc_state->hw.pipe_mode.crtc_clock; 4103 int min_cdclk; 4104 4105 /* 4106 * FIXME could perhaps consider a few more of the factors 4107 * that go the per-crtc min_cdclk. Namely anything that 4108 * only changes during full modesets. 4109 * 4110 * FIXME this assumes 1:1 scaling, but the other _worst() stuff 4111 * assumes max downscaling, so the final result will be 4112 * unrealistically bad. Figure out where the actual maximum value 4113 * lies and use that to compute a more realistic worst case 4114 * estimate... 4115 */ 4116 min_cdclk = _intel_pixel_rate_to_cdclk(crtc_state, clock); 4117 4118 return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk); 4119 } 4120 4121 int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state, 4122 unsigned int prefill_lines_unadjusted, 4123 unsigned int prefill_lines_available) 4124 { 4125 struct intel_display *display = to_intel_display(crtc_state); 4126 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 4127 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 4128 4129 return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted), 4130 ppc * prefill_lines_available); 4131 } 4132