1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/iopoll.h> 26 #include <linux/time.h> 27 28 #include <drm/drm_fixed.h> 29 #include <drm/drm_print.h> 30 31 #include "hsw_ips.h" 32 #include "i915_reg.h" 33 #include "intel_atomic.h" 34 #include "intel_audio.h" 35 #include "intel_cdclk.h" 36 #include "intel_crtc.h" 37 #include "intel_dbuf_bw.h" 38 #include "intel_de.h" 39 #include "intel_display_regs.h" 40 #include "intel_display_types.h" 41 #include "intel_display_utils.h" 42 #include "intel_dram.h" 43 #include "intel_mchbar_regs.h" 44 #include "intel_pci_config.h" 45 #include "intel_pcode.h" 46 #include "intel_plane.h" 47 #include "intel_psr.h" 48 #include "intel_step.h" 49 #include "intel_vdsc.h" 50 #include "skl_watermark.h" 51 #include "skl_watermark_regs.h" 52 #include "vlv_clock.h" 53 #include "vlv_dsi.h" 54 #include "vlv_sideband.h" 55 56 /** 57 * DOC: CDCLK / RAWCLK 58 * 59 * The display engine uses several different clocks to do its work. There 60 * are two main clocks involved that aren't directly related to the actual 61 * pixel clock or any symbol/bit clock of the actual output port. These 62 * are the core display clock (CDCLK) and RAWCLK. 63 * 64 * CDCLK clocks most of the display pipe logic, and thus its frequency 65 * must be high enough to support the rate at which pixels are flowing 66 * through the pipes. Downscaling must also be accounted as that increases 67 * the effective pixel rate. 68 * 69 * On several platforms the CDCLK frequency can be changed dynamically 70 * to minimize power consumption for a given display configuration. 71 * Typically changes to the CDCLK frequency require all the display pipes 72 * to be shut down while the frequency is being changed. 73 * 74 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 75 * DMC will not change the active CDCLK frequency however, so that part 76 * will still be performed by the driver directly. 77 * 78 * There are multiple components involved in the generation of the CDCLK 79 * frequency: 80 * 81 * - We have the CDCLK PLL, which generates an output clock based on a 82 * reference clock and a ratio parameter. 83 * - The CD2X Divider, which divides the output of the PLL based on a 84 * divisor selected from a set of pre-defined choices. 85 * - The CD2X Squasher, which further divides the output based on a 86 * waveform represented as a sequence of bits where each zero 87 * "squashes out" a clock cycle. 88 * - And, finally, a fixed divider that divides the output frequency by 2. 89 * 90 * As such, the resulting CDCLK frequency can be calculated with the 91 * following formula: 92 * 93 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 94 * 95 * , where vco is the frequency generated by the PLL; cd2x_div 96 * represents the CD2X Divider; sq_len and sq_div are the bit length 97 * and the number of high bits for the CD2X Squasher waveform, respectively; 98 * and 2 represents the fixed divider. 99 * 100 * Note that some older platforms do not contain the CD2X Divider 101 * and/or CD2X Squasher, in which case we can ignore their respective 102 * factors in the formula above. 103 * 104 * Several methods exist to change the CDCLK frequency, which ones are 105 * supported depends on the platform: 106 * 107 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 108 * - CD2X divider update. Single pipe can be active as the divider update 109 * can be synchronized with the pipe's start of vblank. 110 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 111 * - Squash waveform update. Pipes can be active. 112 * - Crawl and squash can also be done back to back. Pipes can be active. 113 * 114 * RAWCLK is a fixed frequency clock, often used by various auxiliary 115 * blocks such as AUX CH or backlight PWM. Hence the only thing we 116 * really need to know about RAWCLK is its frequency so that various 117 * dividers can be programmed correctly. 118 */ 119 120 struct intel_cdclk_state { 121 struct intel_global_state base; 122 123 /* 124 * Logical configuration of cdclk (used for all scaling, 125 * watermark, etc. calculations and checks). This is 126 * computed as if all enabled crtcs were active. 127 */ 128 struct intel_cdclk_config logical; 129 130 /* 131 * Actual configuration of cdclk, can be different from the 132 * logical configuration only when all crtc's are DPMS off. 133 */ 134 struct intel_cdclk_config actual; 135 136 /* minimum acceptable cdclk to satisfy DBUF bandwidth requirements */ 137 int dbuf_bw_min_cdclk; 138 /* minimum acceptable cdclk for each pipe */ 139 int min_cdclk[I915_MAX_PIPES]; 140 /* minimum acceptable voltage level for each pipe */ 141 u8 min_voltage_level[I915_MAX_PIPES]; 142 143 /* pipe to which cd2x update is synchronized */ 144 enum pipe pipe; 145 146 /* forced minimum cdclk for glk+ audio w/a */ 147 int force_min_cdclk; 148 149 /* bitmask of enabled pipes */ 150 u8 enabled_pipes; 151 152 /* bitmask of active pipes */ 153 u8 active_pipes; 154 155 /* update cdclk with pipes disabled */ 156 bool disable_pipes; 157 }; 158 159 struct intel_cdclk_funcs { 160 void (*get_cdclk)(struct intel_display *display, 161 struct intel_cdclk_config *cdclk_config); 162 void (*set_cdclk)(struct intel_display *display, 163 const struct intel_cdclk_config *cdclk_config, 164 enum pipe pipe); 165 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 166 u8 (*calc_voltage_level)(int cdclk); 167 }; 168 169 void intel_cdclk_get_cdclk(struct intel_display *display, 170 struct intel_cdclk_config *cdclk_config) 171 { 172 display->funcs.cdclk->get_cdclk(display, cdclk_config); 173 } 174 175 static void intel_cdclk_set_cdclk(struct intel_display *display, 176 const struct intel_cdclk_config *cdclk_config, 177 enum pipe pipe) 178 { 179 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); 180 } 181 182 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 183 { 184 struct intel_display *display = to_intel_display(state); 185 186 return display->funcs.cdclk->modeset_calc_cdclk(state); 187 } 188 189 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, 190 int cdclk) 191 { 192 return display->funcs.cdclk->calc_voltage_level(cdclk); 193 } 194 195 static void fixed_133mhz_get_cdclk(struct intel_display *display, 196 struct intel_cdclk_config *cdclk_config) 197 { 198 cdclk_config->cdclk = 133333; 199 } 200 201 static void fixed_200mhz_get_cdclk(struct intel_display *display, 202 struct intel_cdclk_config *cdclk_config) 203 { 204 cdclk_config->cdclk = 200000; 205 } 206 207 static void fixed_266mhz_get_cdclk(struct intel_display *display, 208 struct intel_cdclk_config *cdclk_config) 209 { 210 cdclk_config->cdclk = 266667; 211 } 212 213 static void fixed_333mhz_get_cdclk(struct intel_display *display, 214 struct intel_cdclk_config *cdclk_config) 215 { 216 cdclk_config->cdclk = 333333; 217 } 218 219 static void fixed_400mhz_get_cdclk(struct intel_display *display, 220 struct intel_cdclk_config *cdclk_config) 221 { 222 cdclk_config->cdclk = 400000; 223 } 224 225 static void fixed_450mhz_get_cdclk(struct intel_display *display, 226 struct intel_cdclk_config *cdclk_config) 227 { 228 cdclk_config->cdclk = 450000; 229 } 230 231 static void i85x_get_cdclk(struct intel_display *display, 232 struct intel_cdclk_config *cdclk_config) 233 { 234 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 235 u16 hpllcc = 0; 236 237 /* 238 * 852GM/852GMV only supports 133 MHz and the HPLLCC 239 * encoding is different :( 240 * FIXME is this the right way to detect 852GM/852GMV? 241 */ 242 if (pdev->revision == 0x1) { 243 cdclk_config->cdclk = 133333; 244 return; 245 } 246 247 pci_bus_read_config_word(pdev->bus, 248 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 249 250 /* Assume that the hardware is in the high speed state. This 251 * should be the default. 252 */ 253 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 254 case GC_CLOCK_133_200: 255 case GC_CLOCK_133_200_2: 256 case GC_CLOCK_100_200: 257 cdclk_config->cdclk = 200000; 258 break; 259 case GC_CLOCK_166_250: 260 cdclk_config->cdclk = 250000; 261 break; 262 case GC_CLOCK_100_133: 263 cdclk_config->cdclk = 133333; 264 break; 265 case GC_CLOCK_133_266: 266 case GC_CLOCK_133_266_2: 267 case GC_CLOCK_166_266: 268 cdclk_config->cdclk = 266667; 269 break; 270 } 271 } 272 273 static void i915gm_get_cdclk(struct intel_display *display, 274 struct intel_cdclk_config *cdclk_config) 275 { 276 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 277 u16 gcfgc = 0; 278 279 pci_read_config_word(pdev, GCFGC, &gcfgc); 280 281 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 282 cdclk_config->cdclk = 133333; 283 return; 284 } 285 286 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 287 case GC_DISPLAY_CLOCK_333_320_MHZ: 288 cdclk_config->cdclk = 333333; 289 break; 290 default: 291 case GC_DISPLAY_CLOCK_190_200_MHZ: 292 cdclk_config->cdclk = 190000; 293 break; 294 } 295 } 296 297 static void i945gm_get_cdclk(struct intel_display *display, 298 struct intel_cdclk_config *cdclk_config) 299 { 300 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 301 u16 gcfgc = 0; 302 303 pci_read_config_word(pdev, GCFGC, &gcfgc); 304 305 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 306 cdclk_config->cdclk = 133333; 307 return; 308 } 309 310 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 311 case GC_DISPLAY_CLOCK_333_320_MHZ: 312 cdclk_config->cdclk = 320000; 313 break; 314 default: 315 case GC_DISPLAY_CLOCK_190_200_MHZ: 316 cdclk_config->cdclk = 200000; 317 break; 318 } 319 } 320 321 static unsigned int intel_hpll_vco(struct intel_display *display) 322 { 323 static const unsigned int blb_vco[8] = { 324 [0] = 3200000, 325 [1] = 4000000, 326 [2] = 5333333, 327 [3] = 4800000, 328 [4] = 6400000, 329 }; 330 static const unsigned int pnv_vco[8] = { 331 [0] = 3200000, 332 [1] = 4000000, 333 [2] = 5333333, 334 [3] = 4800000, 335 [4] = 2666667, 336 }; 337 static const unsigned int cl_vco[8] = { 338 [0] = 3200000, 339 [1] = 4000000, 340 [2] = 5333333, 341 [3] = 6400000, 342 [4] = 3333333, 343 [5] = 3566667, 344 [6] = 4266667, 345 }; 346 static const unsigned int elk_vco[8] = { 347 [0] = 3200000, 348 [1] = 4000000, 349 [2] = 5333333, 350 [3] = 4800000, 351 }; 352 static const unsigned int ctg_vco[8] = { 353 [0] = 3200000, 354 [1] = 4000000, 355 [2] = 5333333, 356 [3] = 6400000, 357 [4] = 2666667, 358 [5] = 4266667, 359 }; 360 const unsigned int *vco_table; 361 unsigned int vco; 362 u8 tmp = 0; 363 364 /* FIXME other chipsets? */ 365 if (display->platform.gm45) 366 vco_table = ctg_vco; 367 else if (display->platform.g45) 368 vco_table = elk_vco; 369 else if (display->platform.i965gm) 370 vco_table = cl_vco; 371 else if (display->platform.pineview) 372 vco_table = pnv_vco; 373 else if (display->platform.g33) 374 vco_table = blb_vco; 375 else 376 return 0; 377 378 tmp = intel_de_read(display, display->platform.pineview || 379 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); 380 381 vco = vco_table[tmp & 0x7]; 382 if (vco == 0) 383 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 384 tmp); 385 else 386 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); 387 388 return vco; 389 } 390 391 static void g33_get_cdclk(struct intel_display *display, 392 struct intel_cdclk_config *cdclk_config) 393 { 394 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 395 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 396 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 397 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 398 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 399 const u8 *div_table; 400 unsigned int cdclk_sel; 401 u16 tmp = 0; 402 403 cdclk_config->vco = intel_hpll_vco(display); 404 405 pci_read_config_word(pdev, GCFGC, &tmp); 406 407 cdclk_sel = (tmp >> 4) & 0x7; 408 409 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 410 goto fail; 411 412 switch (cdclk_config->vco) { 413 case 3200000: 414 div_table = div_3200; 415 break; 416 case 4000000: 417 div_table = div_4000; 418 break; 419 case 4800000: 420 div_table = div_4800; 421 break; 422 case 5333333: 423 div_table = div_5333; 424 break; 425 default: 426 goto fail; 427 } 428 429 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 430 div_table[cdclk_sel]); 431 return; 432 433 fail: 434 drm_err(display->drm, 435 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 436 cdclk_config->vco, tmp); 437 cdclk_config->cdclk = 190476; 438 } 439 440 static void pnv_get_cdclk(struct intel_display *display, 441 struct intel_cdclk_config *cdclk_config) 442 { 443 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 444 u16 gcfgc = 0; 445 446 pci_read_config_word(pdev, GCFGC, &gcfgc); 447 448 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 449 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 450 cdclk_config->cdclk = 266667; 451 break; 452 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 453 cdclk_config->cdclk = 333333; 454 break; 455 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 456 cdclk_config->cdclk = 444444; 457 break; 458 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 459 cdclk_config->cdclk = 200000; 460 break; 461 default: 462 drm_err(display->drm, 463 "Unknown pnv display core clock 0x%04x\n", gcfgc); 464 fallthrough; 465 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 466 cdclk_config->cdclk = 133333; 467 break; 468 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 469 cdclk_config->cdclk = 166667; 470 break; 471 } 472 } 473 474 static void i965gm_get_cdclk(struct intel_display *display, 475 struct intel_cdclk_config *cdclk_config) 476 { 477 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 478 static const u8 div_3200[] = { 16, 10, 8 }; 479 static const u8 div_4000[] = { 20, 12, 10 }; 480 static const u8 div_5333[] = { 24, 16, 14 }; 481 const u8 *div_table; 482 unsigned int cdclk_sel; 483 u16 tmp = 0; 484 485 cdclk_config->vco = intel_hpll_vco(display); 486 487 pci_read_config_word(pdev, GCFGC, &tmp); 488 489 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 490 491 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 492 goto fail; 493 494 switch (cdclk_config->vco) { 495 case 3200000: 496 div_table = div_3200; 497 break; 498 case 4000000: 499 div_table = div_4000; 500 break; 501 case 5333333: 502 div_table = div_5333; 503 break; 504 default: 505 goto fail; 506 } 507 508 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 509 div_table[cdclk_sel]); 510 return; 511 512 fail: 513 drm_err(display->drm, 514 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 515 cdclk_config->vco, tmp); 516 cdclk_config->cdclk = 200000; 517 } 518 519 static void gm45_get_cdclk(struct intel_display *display, 520 struct intel_cdclk_config *cdclk_config) 521 { 522 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 523 unsigned int cdclk_sel; 524 u16 tmp = 0; 525 526 cdclk_config->vco = intel_hpll_vco(display); 527 528 pci_read_config_word(pdev, GCFGC, &tmp); 529 530 cdclk_sel = (tmp >> 12) & 0x1; 531 532 switch (cdclk_config->vco) { 533 case 2666667: 534 case 4000000: 535 case 5333333: 536 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 537 break; 538 case 3200000: 539 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 540 break; 541 default: 542 drm_err(display->drm, 543 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 544 cdclk_config->vco, tmp); 545 cdclk_config->cdclk = 222222; 546 break; 547 } 548 } 549 550 static void hsw_get_cdclk(struct intel_display *display, 551 struct intel_cdclk_config *cdclk_config) 552 { 553 u32 lcpll = intel_de_read(display, LCPLL_CTL); 554 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 555 556 if (lcpll & LCPLL_CD_SOURCE_FCLK) 557 cdclk_config->cdclk = 800000; 558 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 559 cdclk_config->cdclk = 450000; 560 else if (freq == LCPLL_CLK_FREQ_450) 561 cdclk_config->cdclk = 450000; 562 else if (display->platform.haswell_ult) 563 cdclk_config->cdclk = 337500; 564 else 565 cdclk_config->cdclk = 540000; 566 } 567 568 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) 569 { 570 int freq_320 = (vlv_clock_get_hpll_vco(display->drm) << 1) % 320000 != 0 ? 571 333333 : 320000; 572 573 /* 574 * We seem to get an unstable or solid color picture at 200MHz. 575 * Not sure what's wrong. For now use 200MHz only when all pipes 576 * are off. 577 */ 578 if (display->platform.valleyview && min_cdclk > freq_320) 579 return 400000; 580 else if (min_cdclk > 266667) 581 return freq_320; 582 else if (min_cdclk > 0) 583 return 266667; 584 else 585 return 200000; 586 } 587 588 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 589 { 590 if (display->platform.valleyview) { 591 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 592 return 2; 593 else if (cdclk >= 266667) 594 return 1; 595 else 596 return 0; 597 } else { 598 /* 599 * Specs are full of misinformation, but testing on actual 600 * hardware has shown that we just need to write the desired 601 * CCK divider into the Punit register. 602 */ 603 return DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, cdclk) - 1; 604 } 605 } 606 607 static void vlv_get_cdclk(struct intel_display *display, 608 struct intel_cdclk_config *cdclk_config) 609 { 610 u32 val; 611 612 cdclk_config->vco = vlv_clock_get_hpll_vco(display->drm); 613 cdclk_config->cdclk = vlv_clock_get_cdclk(display->drm); 614 615 vlv_punit_get(display->drm); 616 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 617 vlv_punit_put(display->drm); 618 619 if (display->platform.valleyview) 620 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 621 DSPFREQGUAR_SHIFT; 622 else 623 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 624 DSPFREQGUAR_SHIFT_CHV; 625 } 626 627 static void vlv_program_pfi_credits(struct intel_display *display) 628 { 629 unsigned int credits, default_credits; 630 631 if (display->platform.cherryview) 632 default_credits = PFI_CREDIT(12); 633 else 634 default_credits = PFI_CREDIT(8); 635 636 if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(display->drm)) { 637 /* CHV suggested value is 31 or 63 */ 638 if (display->platform.cherryview) 639 credits = PFI_CREDIT_63; 640 else 641 credits = PFI_CREDIT(15); 642 } else { 643 credits = default_credits; 644 } 645 646 /* 647 * WA - write default credits before re-programming 648 * FIXME: should we also set the resend bit here? 649 */ 650 intel_de_write(display, GCI_CONTROL, 651 VGA_FAST_MODE_DISABLE | default_credits); 652 653 intel_de_write(display, GCI_CONTROL, 654 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 655 656 /* 657 * FIXME is this guaranteed to clear 658 * immediately or should we poll for it? 659 */ 660 drm_WARN_ON(display->drm, 661 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); 662 } 663 664 static void vlv_set_cdclk(struct intel_display *display, 665 const struct intel_cdclk_config *cdclk_config, 666 enum pipe pipe) 667 { 668 int cdclk = cdclk_config->cdclk; 669 u32 val, cmd = cdclk_config->voltage_level; 670 intel_wakeref_t wakeref; 671 int ret; 672 673 switch (cdclk) { 674 case 400000: 675 case 333333: 676 case 320000: 677 case 266667: 678 case 200000: 679 break; 680 default: 681 MISSING_CASE(cdclk); 682 return; 683 } 684 685 /* There are cases where we can end up here with power domains 686 * off and a CDCLK frequency other than the minimum, like when 687 * issuing a modeset without actually changing any display after 688 * a system suspend. So grab the display core domain, which covers 689 * the HW blocks needed for the following programming. 690 */ 691 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 692 693 vlv_iosf_sb_get(display->drm, 694 BIT(VLV_IOSF_SB_CCK) | 695 BIT(VLV_IOSF_SB_BUNIT) | 696 BIT(VLV_IOSF_SB_PUNIT)); 697 698 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 699 val &= ~DSPFREQGUAR_MASK; 700 val |= (cmd << DSPFREQGUAR_SHIFT); 701 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); 702 703 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), 704 (val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 705 500, 50 * 1000, false); 706 if (ret) 707 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 708 709 if (cdclk == 400000) { 710 u32 divider; 711 712 divider = DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, 713 cdclk) - 1; 714 715 /* adjust cdclk divider */ 716 val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL); 717 val &= ~CCK_FREQUENCY_VALUES; 718 val |= divider; 719 vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val); 720 721 ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL), 722 (val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 723 500, 50 * 1000, false); 724 if (ret) 725 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 726 } 727 728 /* adjust self-refresh exit latency value */ 729 val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC); 730 val &= ~0x7f; 731 732 /* 733 * For high bandwidth configs, we set a higher latency in the bunit 734 * so that the core display fetch happens in time to avoid underruns. 735 */ 736 if (cdclk == 400000) 737 val |= 4500 / 250; /* 4.5 usec */ 738 else 739 val |= 3000 / 250; /* 3.0 usec */ 740 vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val); 741 742 vlv_iosf_sb_put(display->drm, 743 BIT(VLV_IOSF_SB_CCK) | 744 BIT(VLV_IOSF_SB_BUNIT) | 745 BIT(VLV_IOSF_SB_PUNIT)); 746 747 intel_update_cdclk(display); 748 749 vlv_program_pfi_credits(display); 750 751 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 752 } 753 754 static void chv_set_cdclk(struct intel_display *display, 755 const struct intel_cdclk_config *cdclk_config, 756 enum pipe pipe) 757 { 758 int cdclk = cdclk_config->cdclk; 759 u32 val, cmd = cdclk_config->voltage_level; 760 intel_wakeref_t wakeref; 761 int ret; 762 763 switch (cdclk) { 764 case 333333: 765 case 320000: 766 case 266667: 767 case 200000: 768 break; 769 default: 770 MISSING_CASE(cdclk); 771 return; 772 } 773 774 /* There are cases where we can end up here with power domains 775 * off and a CDCLK frequency other than the minimum, like when 776 * issuing a modeset without actually changing any display after 777 * a system suspend. So grab the display core domain, which covers 778 * the HW blocks needed for the following programming. 779 */ 780 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 781 782 vlv_punit_get(display->drm); 783 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 784 val &= ~DSPFREQGUAR_MASK_CHV; 785 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 786 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); 787 788 ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM), 789 (val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 790 500, 50 * 1000, false); 791 if (ret) 792 drm_err(display->drm, "timed out waiting for CDCLK change\n"); 793 794 vlv_punit_put(display->drm); 795 796 intel_update_cdclk(display); 797 798 vlv_program_pfi_credits(display); 799 800 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 801 } 802 803 static int bdw_calc_cdclk(int min_cdclk) 804 { 805 if (min_cdclk > 540000) 806 return 675000; 807 else if (min_cdclk > 450000) 808 return 540000; 809 else if (min_cdclk > 337500) 810 return 450000; 811 else 812 return 337500; 813 } 814 815 static u8 bdw_calc_voltage_level(int cdclk) 816 { 817 switch (cdclk) { 818 default: 819 case 337500: 820 return 2; 821 case 450000: 822 return 0; 823 case 540000: 824 return 1; 825 case 675000: 826 return 3; 827 } 828 } 829 830 static void bdw_get_cdclk(struct intel_display *display, 831 struct intel_cdclk_config *cdclk_config) 832 { 833 u32 lcpll = intel_de_read(display, LCPLL_CTL); 834 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 835 836 if (lcpll & LCPLL_CD_SOURCE_FCLK) 837 cdclk_config->cdclk = 800000; 838 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 839 cdclk_config->cdclk = 450000; 840 else if (freq == LCPLL_CLK_FREQ_450) 841 cdclk_config->cdclk = 450000; 842 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 843 cdclk_config->cdclk = 540000; 844 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 845 cdclk_config->cdclk = 337500; 846 else 847 cdclk_config->cdclk = 675000; 848 849 /* 850 * Can't read this out :( Let's assume it's 851 * at least what the CDCLK frequency requires. 852 */ 853 cdclk_config->voltage_level = 854 bdw_calc_voltage_level(cdclk_config->cdclk); 855 } 856 857 static u32 bdw_cdclk_freq_sel(int cdclk) 858 { 859 switch (cdclk) { 860 default: 861 MISSING_CASE(cdclk); 862 fallthrough; 863 case 337500: 864 return LCPLL_CLK_FREQ_337_5_BDW; 865 case 450000: 866 return LCPLL_CLK_FREQ_450; 867 case 540000: 868 return LCPLL_CLK_FREQ_54O_BDW; 869 case 675000: 870 return LCPLL_CLK_FREQ_675_BDW; 871 } 872 } 873 874 static void bdw_set_cdclk(struct intel_display *display, 875 const struct intel_cdclk_config *cdclk_config, 876 enum pipe pipe) 877 { 878 int cdclk = cdclk_config->cdclk; 879 int ret; 880 881 if (drm_WARN(display->drm, 882 (intel_de_read(display, LCPLL_CTL) & 883 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 884 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 885 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 886 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 887 "trying to change cdclk frequency with cdclk not enabled\n")) 888 return; 889 890 ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 891 if (ret) { 892 drm_err(display->drm, 893 "failed to inform pcode about cdclk change\n"); 894 return; 895 } 896 897 intel_de_rmw(display, LCPLL_CTL, 898 0, LCPLL_CD_SOURCE_FCLK); 899 900 /* 901 * According to the spec, it should be enough to poll for this 1 us. 902 * However, extensive testing shows that this can take longer. 903 */ 904 ret = intel_de_wait_for_set_us(display, LCPLL_CTL, 905 LCPLL_CD_SOURCE_FCLK_DONE, 100); 906 if (ret) 907 drm_err(display->drm, "Switching to FCLK failed\n"); 908 909 intel_de_rmw(display, LCPLL_CTL, 910 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 911 912 intel_de_rmw(display, LCPLL_CTL, 913 LCPLL_CD_SOURCE_FCLK, 0); 914 915 ret = intel_de_wait_for_clear_us(display, LCPLL_CTL, 916 LCPLL_CD_SOURCE_FCLK_DONE, 1); 917 if (ret) 918 drm_err(display->drm, "Switching back to LCPLL failed\n"); 919 920 intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ, 921 cdclk_config->voltage_level); 922 923 intel_de_write(display, CDCLK_FREQ, 924 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 925 926 intel_update_cdclk(display); 927 } 928 929 static int skl_calc_cdclk(int min_cdclk, int vco) 930 { 931 if (vco == 8640000) { 932 if (min_cdclk > 540000) 933 return 617143; 934 else if (min_cdclk > 432000) 935 return 540000; 936 else if (min_cdclk > 308571) 937 return 432000; 938 else 939 return 308571; 940 } else { 941 if (min_cdclk > 540000) 942 return 675000; 943 else if (min_cdclk > 450000) 944 return 540000; 945 else if (min_cdclk > 337500) 946 return 450000; 947 else 948 return 337500; 949 } 950 } 951 952 static u8 skl_calc_voltage_level(int cdclk) 953 { 954 if (cdclk > 540000) 955 return 3; 956 else if (cdclk > 450000) 957 return 2; 958 else if (cdclk > 337500) 959 return 1; 960 else 961 return 0; 962 } 963 964 static void skl_dpll0_update(struct intel_display *display, 965 struct intel_cdclk_config *cdclk_config) 966 { 967 u32 val; 968 969 cdclk_config->ref = 24000; 970 cdclk_config->vco = 0; 971 972 val = intel_de_read(display, LCPLL1_CTL); 973 if ((val & LCPLL_PLL_ENABLE) == 0) 974 return; 975 976 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) 977 return; 978 979 val = intel_de_read(display, DPLL_CTRL1); 980 981 if (drm_WARN_ON(display->drm, 982 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 983 DPLL_CTRL1_SSC(SKL_DPLL0) | 984 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 985 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 986 return; 987 988 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 989 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 990 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 991 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 992 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 993 cdclk_config->vco = 8100000; 994 break; 995 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 996 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 997 cdclk_config->vco = 8640000; 998 break; 999 default: 1000 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 1001 break; 1002 } 1003 } 1004 1005 static void skl_get_cdclk(struct intel_display *display, 1006 struct intel_cdclk_config *cdclk_config) 1007 { 1008 u32 cdctl; 1009 1010 skl_dpll0_update(display, cdclk_config); 1011 1012 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 1013 1014 if (cdclk_config->vco == 0) 1015 goto out; 1016 1017 cdctl = intel_de_read(display, CDCLK_CTL); 1018 1019 if (cdclk_config->vco == 8640000) { 1020 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1021 case CDCLK_FREQ_450_432: 1022 cdclk_config->cdclk = 432000; 1023 break; 1024 case CDCLK_FREQ_337_308: 1025 cdclk_config->cdclk = 308571; 1026 break; 1027 case CDCLK_FREQ_540: 1028 cdclk_config->cdclk = 540000; 1029 break; 1030 case CDCLK_FREQ_675_617: 1031 cdclk_config->cdclk = 617143; 1032 break; 1033 default: 1034 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1035 break; 1036 } 1037 } else { 1038 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1039 case CDCLK_FREQ_450_432: 1040 cdclk_config->cdclk = 450000; 1041 break; 1042 case CDCLK_FREQ_337_308: 1043 cdclk_config->cdclk = 337500; 1044 break; 1045 case CDCLK_FREQ_540: 1046 cdclk_config->cdclk = 540000; 1047 break; 1048 case CDCLK_FREQ_675_617: 1049 cdclk_config->cdclk = 675000; 1050 break; 1051 default: 1052 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1053 break; 1054 } 1055 } 1056 1057 out: 1058 /* 1059 * Can't read this out :( Let's assume it's 1060 * at least what the CDCLK frequency requires. 1061 */ 1062 cdclk_config->voltage_level = 1063 skl_calc_voltage_level(cdclk_config->cdclk); 1064 } 1065 1066 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1067 static int skl_cdclk_decimal(int cdclk) 1068 { 1069 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1070 } 1071 1072 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) 1073 { 1074 bool changed = display->cdclk.skl_preferred_vco_freq != vco; 1075 1076 display->cdclk.skl_preferred_vco_freq = vco; 1077 1078 if (changed) 1079 intel_update_max_cdclk(display); 1080 } 1081 1082 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) 1083 { 1084 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 1085 1086 /* 1087 * We always enable DPLL0 with the lowest link rate possible, but still 1088 * taking into account the VCO required to operate the eDP panel at the 1089 * desired frequency. The usual DP link rates operate with a VCO of 1090 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1091 * The modeset code is responsible for the selection of the exact link 1092 * rate later on, with the constraint of choosing a frequency that 1093 * works with vco. 1094 */ 1095 if (vco == 8640000) 1096 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1097 else 1098 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1099 } 1100 1101 static void skl_dpll0_enable(struct intel_display *display, int vco) 1102 { 1103 intel_de_rmw(display, DPLL_CTRL1, 1104 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1105 DPLL_CTRL1_SSC(SKL_DPLL0) | 1106 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1107 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1108 skl_dpll0_link_rate(display, vco)); 1109 intel_de_posting_read(display, DPLL_CTRL1); 1110 1111 intel_de_rmw(display, LCPLL1_CTL, 1112 0, LCPLL_PLL_ENABLE); 1113 1114 if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1115 drm_err(display->drm, "DPLL0 not locked\n"); 1116 1117 display->cdclk.hw.vco = vco; 1118 1119 /* We'll want to keep using the current vco from now on. */ 1120 skl_set_preferred_cdclk_vco(display, vco); 1121 } 1122 1123 static void skl_dpll0_disable(struct intel_display *display) 1124 { 1125 intel_de_rmw(display, LCPLL1_CTL, 1126 LCPLL_PLL_ENABLE, 0); 1127 1128 if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1129 drm_err(display->drm, "Couldn't disable DPLL0\n"); 1130 1131 display->cdclk.hw.vco = 0; 1132 } 1133 1134 static u32 skl_cdclk_freq_sel(struct intel_display *display, 1135 int cdclk, int vco) 1136 { 1137 switch (cdclk) { 1138 default: 1139 drm_WARN_ON(display->drm, 1140 cdclk != display->cdclk.hw.bypass); 1141 drm_WARN_ON(display->drm, vco != 0); 1142 fallthrough; 1143 case 308571: 1144 case 337500: 1145 return CDCLK_FREQ_337_308; 1146 case 450000: 1147 case 432000: 1148 return CDCLK_FREQ_450_432; 1149 case 540000: 1150 return CDCLK_FREQ_540; 1151 case 617143: 1152 case 675000: 1153 return CDCLK_FREQ_675_617; 1154 } 1155 } 1156 1157 static void skl_set_cdclk(struct intel_display *display, 1158 const struct intel_cdclk_config *cdclk_config, 1159 enum pipe pipe) 1160 { 1161 int cdclk = cdclk_config->cdclk; 1162 int vco = cdclk_config->vco; 1163 u32 freq_select, cdclk_ctl; 1164 int ret; 1165 1166 /* 1167 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1168 * unsupported on SKL. In theory this should never happen since only 1169 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1170 * supported on SKL either, see the above WA. WARN whenever trying to 1171 * use the corresponding VCO freq as that always leads to using the 1172 * minimum 308MHz CDCLK. 1173 */ 1174 drm_WARN_ON_ONCE(display->drm, 1175 display->platform.skylake && vco == 8640000); 1176 1177 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 1178 SKL_CDCLK_PREPARE_FOR_CHANGE, 1179 SKL_CDCLK_READY_FOR_CHANGE, 1180 SKL_CDCLK_READY_FOR_CHANGE, 3); 1181 if (ret) { 1182 drm_err(display->drm, 1183 "Failed to inform PCU about cdclk change (%d)\n", ret); 1184 return; 1185 } 1186 1187 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); 1188 1189 if (display->cdclk.hw.vco != 0 && 1190 display->cdclk.hw.vco != vco) 1191 skl_dpll0_disable(display); 1192 1193 cdclk_ctl = intel_de_read(display, CDCLK_CTL); 1194 1195 if (display->cdclk.hw.vco != vco) { 1196 /* Wa Display #1183: skl,kbl,cfl */ 1197 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1198 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1199 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1200 } 1201 1202 /* Wa Display #1183: skl,kbl,cfl */ 1203 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1204 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1205 intel_de_posting_read(display, CDCLK_CTL); 1206 1207 if (display->cdclk.hw.vco != vco) 1208 skl_dpll0_enable(display, vco); 1209 1210 /* Wa Display #1183: skl,kbl,cfl */ 1211 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1212 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1213 1214 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1215 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1216 1217 /* Wa Display #1183: skl,kbl,cfl */ 1218 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1219 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1220 intel_de_posting_read(display, CDCLK_CTL); 1221 1222 /* inform PCU of the change */ 1223 intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, 1224 cdclk_config->voltage_level); 1225 1226 intel_update_cdclk(display); 1227 } 1228 1229 static void skl_sanitize_cdclk(struct intel_display *display) 1230 { 1231 u32 cdctl, expected; 1232 1233 /* 1234 * check if the pre-os initialized the display 1235 * There is SWF18 scratchpad register defined which is set by the 1236 * pre-os which can be used by the OS drivers to check the status 1237 */ 1238 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1239 goto sanitize; 1240 1241 intel_update_cdclk(display); 1242 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1243 1244 /* Is PLL enabled and locked ? */ 1245 if (display->cdclk.hw.vco == 0 || 1246 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 1247 goto sanitize; 1248 1249 /* DPLL okay; verify the cdclock 1250 * 1251 * Noticed in some instances that the freq selection is correct but 1252 * decimal part is programmed wrong from BIOS where pre-os does not 1253 * enable display. Verify the same as well. 1254 */ 1255 cdctl = intel_de_read(display, CDCLK_CTL); 1256 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1257 skl_cdclk_decimal(display->cdclk.hw.cdclk); 1258 if (cdctl == expected) 1259 /* All well; nothing to sanitize */ 1260 return; 1261 1262 sanitize: 1263 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 1264 1265 /* force cdclk programming */ 1266 display->cdclk.hw.cdclk = 0; 1267 /* force full PLL disable + enable */ 1268 display->cdclk.hw.vco = ~0; 1269 } 1270 1271 static void skl_cdclk_init_hw(struct intel_display *display) 1272 { 1273 struct intel_cdclk_config cdclk_config; 1274 1275 skl_sanitize_cdclk(display); 1276 1277 if (display->cdclk.hw.cdclk != 0 && 1278 display->cdclk.hw.vco != 0) { 1279 /* 1280 * Use the current vco as our initial 1281 * guess as to what the preferred vco is. 1282 */ 1283 if (display->cdclk.skl_preferred_vco_freq == 0) 1284 skl_set_preferred_cdclk_vco(display, 1285 display->cdclk.hw.vco); 1286 return; 1287 } 1288 1289 cdclk_config = display->cdclk.hw; 1290 1291 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; 1292 if (cdclk_config.vco == 0) 1293 cdclk_config.vco = 8100000; 1294 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1295 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1296 1297 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1298 } 1299 1300 static void skl_cdclk_uninit_hw(struct intel_display *display) 1301 { 1302 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 1303 1304 cdclk_config.cdclk = cdclk_config.bypass; 1305 cdclk_config.vco = 0; 1306 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1307 1308 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1309 } 1310 1311 struct intel_cdclk_vals { 1312 u32 cdclk; 1313 u16 refclk; 1314 u16 waveform; 1315 u8 ratio; 1316 }; 1317 1318 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1319 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1320 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1321 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1322 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1323 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1324 {} 1325 }; 1326 1327 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1328 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1329 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1330 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1331 {} 1332 }; 1333 1334 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1335 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1336 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1337 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1338 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1339 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1340 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1341 1342 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1343 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1344 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1345 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1346 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1347 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1348 1349 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1350 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1351 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1352 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1353 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1354 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1355 {} 1356 }; 1357 1358 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1359 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1360 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1361 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1362 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1363 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1364 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1365 1366 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1367 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1368 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1369 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1370 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1371 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1372 1373 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1374 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1375 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1376 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1377 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1378 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1379 {} 1380 }; 1381 1382 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1383 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1384 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1385 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1386 1387 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1388 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1389 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1390 1391 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1392 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1393 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1394 {} 1395 }; 1396 1397 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1398 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1399 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1400 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1401 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1402 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1403 1404 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1405 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1406 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1407 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1408 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1409 1410 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1411 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1412 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1413 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1414 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1415 {} 1416 }; 1417 1418 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1419 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1420 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1421 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1422 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1423 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1424 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1425 1426 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1427 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1428 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1429 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1430 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1431 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1432 1433 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1434 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1435 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1436 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1437 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1438 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1439 {} 1440 }; 1441 1442 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1443 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1444 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1445 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1446 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1447 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1448 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1449 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1450 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1451 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1452 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1453 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1454 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1455 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1456 {} 1457 }; 1458 1459 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1460 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1461 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1462 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1463 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1464 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1465 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1466 {} 1467 }; 1468 1469 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1470 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1471 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1472 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1473 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1474 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1475 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1476 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1477 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1478 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1479 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1480 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1481 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1482 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1483 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1484 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1485 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1486 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1487 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1488 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1489 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1490 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1491 {} 1492 }; 1493 1494 /* 1495 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1496 */ 1497 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1498 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1499 {} 1500 }; 1501 1502 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { 1503 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1504 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1505 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1506 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1507 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1508 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1509 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1510 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1511 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1512 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff }, 1513 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff }, 1514 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff }, 1515 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff }, 1516 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1517 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1518 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1519 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1520 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1521 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1522 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1523 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1524 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1525 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1526 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1527 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1528 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1529 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1530 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1531 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1532 {} 1533 }; 1534 1535 static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = { 1536 { .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 }, 1537 { .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 }, 1538 { .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa }, 1539 { .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a }, 1540 { .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 }, 1541 { .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 }, 1542 { .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee }, 1543 { .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de }, 1544 { .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe }, 1545 { .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe }, 1546 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1547 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1548 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1549 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1550 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1551 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1552 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1553 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1554 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1555 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1556 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1557 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1558 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1559 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1560 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1561 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1562 { .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff }, 1563 { .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff }, 1564 { .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff }, 1565 { .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff }, 1566 { .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff }, 1567 {} 1568 }; 1569 1570 static const int cdclk_squash_len = 16; 1571 1572 static int cdclk_squash_divider(u16 waveform) 1573 { 1574 return hweight16(waveform ?: 0xffff); 1575 } 1576 1577 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1578 { 1579 /* 2 * cd2x divider */ 1580 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1581 cdclk * cdclk_squash_len); 1582 } 1583 1584 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 1585 { 1586 const struct intel_cdclk_vals *table = display->cdclk.table; 1587 int i; 1588 1589 for (i = 0; table[i].refclk; i++) 1590 if (table[i].refclk == display->cdclk.hw.ref && 1591 table[i].cdclk >= min_cdclk) 1592 return table[i].cdclk; 1593 1594 drm_WARN(display->drm, 1, 1595 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1596 min_cdclk, display->cdclk.hw.ref); 1597 return display->cdclk.max_cdclk_freq; 1598 } 1599 1600 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) 1601 { 1602 const struct intel_cdclk_vals *table = display->cdclk.table; 1603 int i; 1604 1605 if (cdclk == display->cdclk.hw.bypass) 1606 return 0; 1607 1608 for (i = 0; table[i].refclk; i++) 1609 if (table[i].refclk == display->cdclk.hw.ref && 1610 table[i].cdclk == cdclk) 1611 return display->cdclk.hw.ref * table[i].ratio; 1612 1613 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1614 cdclk, display->cdclk.hw.ref); 1615 return 0; 1616 } 1617 1618 static u8 bxt_calc_voltage_level(int cdclk) 1619 { 1620 return DIV_ROUND_UP(cdclk, 25000); 1621 } 1622 1623 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1624 const int voltage_level_max_cdclk[]) 1625 { 1626 int voltage_level; 1627 1628 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1629 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1630 return voltage_level; 1631 } 1632 1633 MISSING_CASE(cdclk); 1634 return num_voltage_levels - 1; 1635 } 1636 1637 static u8 icl_calc_voltage_level(int cdclk) 1638 { 1639 static const int icl_voltage_level_max_cdclk[] = { 1640 [0] = 312000, 1641 [1] = 556800, 1642 [2] = 652800, 1643 }; 1644 1645 return calc_voltage_level(cdclk, 1646 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1647 icl_voltage_level_max_cdclk); 1648 } 1649 1650 static u8 ehl_calc_voltage_level(int cdclk) 1651 { 1652 static const int ehl_voltage_level_max_cdclk[] = { 1653 [0] = 180000, 1654 [1] = 312000, 1655 [2] = 326400, 1656 /* 1657 * Bspec lists the limit as 556.8 MHz, but some JSL 1658 * development boards (at least) boot with 652.8 MHz 1659 */ 1660 [3] = 652800, 1661 }; 1662 1663 return calc_voltage_level(cdclk, 1664 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1665 ehl_voltage_level_max_cdclk); 1666 } 1667 1668 static u8 tgl_calc_voltage_level(int cdclk) 1669 { 1670 static const int tgl_voltage_level_max_cdclk[] = { 1671 [0] = 312000, 1672 [1] = 326400, 1673 [2] = 556800, 1674 [3] = 652800, 1675 }; 1676 1677 return calc_voltage_level(cdclk, 1678 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1679 tgl_voltage_level_max_cdclk); 1680 } 1681 1682 static u8 rplu_calc_voltage_level(int cdclk) 1683 { 1684 static const int rplu_voltage_level_max_cdclk[] = { 1685 [0] = 312000, 1686 [1] = 480000, 1687 [2] = 556800, 1688 [3] = 652800, 1689 }; 1690 1691 return calc_voltage_level(cdclk, 1692 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1693 rplu_voltage_level_max_cdclk); 1694 } 1695 1696 static u8 xe3lpd_calc_voltage_level(int cdclk) 1697 { 1698 /* 1699 * Starting with xe3lpd power controller does not need the voltage 1700 * index when doing the modeset update. This function is best left 1701 * defined but returning 0 to the mask. 1702 */ 1703 return 0; 1704 } 1705 1706 static void icl_readout_refclk(struct intel_display *display, 1707 struct intel_cdclk_config *cdclk_config) 1708 { 1709 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1710 1711 switch (dssm) { 1712 default: 1713 MISSING_CASE(dssm); 1714 fallthrough; 1715 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1716 cdclk_config->ref = 24000; 1717 break; 1718 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1719 cdclk_config->ref = 19200; 1720 break; 1721 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1722 cdclk_config->ref = 38400; 1723 break; 1724 } 1725 } 1726 1727 static void bxt_de_pll_readout(struct intel_display *display, 1728 struct intel_cdclk_config *cdclk_config) 1729 { 1730 u32 val, ratio; 1731 1732 if (display->platform.dg2) 1733 cdclk_config->ref = 38400; 1734 else if (DISPLAY_VER(display) >= 11) 1735 icl_readout_refclk(display, cdclk_config); 1736 else 1737 cdclk_config->ref = 19200; 1738 1739 val = intel_de_read(display, BXT_DE_PLL_ENABLE); 1740 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1741 (val & BXT_DE_PLL_LOCK) == 0) { 1742 /* 1743 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1744 * setting it to zero is a way to signal that. 1745 */ 1746 cdclk_config->vco = 0; 1747 return; 1748 } 1749 1750 /* 1751 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1752 * gen9lp had it in a separate PLL control register. 1753 */ 1754 if (DISPLAY_VER(display) >= 11) 1755 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1756 else 1757 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1758 1759 cdclk_config->vco = ratio * cdclk_config->ref; 1760 } 1761 1762 static void bxt_get_cdclk(struct intel_display *display, 1763 struct intel_cdclk_config *cdclk_config) 1764 { 1765 u32 squash_ctl = 0; 1766 u32 divider; 1767 int div; 1768 1769 bxt_de_pll_readout(display, cdclk_config); 1770 1771 if (DISPLAY_VER(display) >= 12) 1772 cdclk_config->bypass = cdclk_config->ref / 2; 1773 else if (DISPLAY_VER(display) >= 11) 1774 cdclk_config->bypass = 50000; 1775 else 1776 cdclk_config->bypass = cdclk_config->ref; 1777 1778 if (cdclk_config->vco == 0) { 1779 cdclk_config->cdclk = cdclk_config->bypass; 1780 goto out; 1781 } 1782 1783 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1784 1785 switch (divider) { 1786 case BXT_CDCLK_CD2X_DIV_SEL_1: 1787 div = 2; 1788 break; 1789 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1790 div = 3; 1791 break; 1792 case BXT_CDCLK_CD2X_DIV_SEL_2: 1793 div = 4; 1794 break; 1795 case BXT_CDCLK_CD2X_DIV_SEL_4: 1796 div = 8; 1797 break; 1798 default: 1799 MISSING_CASE(divider); 1800 return; 1801 } 1802 1803 if (HAS_CDCLK_SQUASH(display)) 1804 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); 1805 1806 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1807 u16 waveform; 1808 int size; 1809 1810 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1811 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1812 1813 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1814 cdclk_config->vco, size * div); 1815 } else { 1816 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1817 } 1818 1819 out: 1820 if (DISPLAY_VER(display) >= 20) 1821 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 1822 /* 1823 * Can't read this out :( Let's assume it's 1824 * at least what the CDCLK frequency requires. 1825 */ 1826 cdclk_config->voltage_level = 1827 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); 1828 } 1829 1830 static void bxt_de_pll_disable(struct intel_display *display) 1831 { 1832 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); 1833 1834 /* Timeout 200us */ 1835 if (intel_de_wait_for_clear_ms(display, 1836 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1837 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); 1838 1839 display->cdclk.hw.vco = 0; 1840 } 1841 1842 static void bxt_de_pll_enable(struct intel_display *display, int vco) 1843 { 1844 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1845 1846 intel_de_rmw(display, BXT_DE_PLL_CTL, 1847 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1848 1849 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1850 1851 /* Timeout 200us */ 1852 if (intel_de_wait_for_set_ms(display, 1853 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1854 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); 1855 1856 display->cdclk.hw.vco = vco; 1857 } 1858 1859 static void icl_cdclk_pll_disable(struct intel_display *display) 1860 { 1861 intel_de_rmw(display, BXT_DE_PLL_ENABLE, 1862 BXT_DE_PLL_PLL_ENABLE, 0); 1863 1864 /* Timeout 200us */ 1865 if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1866 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); 1867 1868 display->cdclk.hw.vco = 0; 1869 } 1870 1871 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) 1872 { 1873 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1874 u32 val; 1875 1876 val = ICL_CDCLK_PLL_RATIO(ratio); 1877 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1878 1879 val |= BXT_DE_PLL_PLL_ENABLE; 1880 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1881 1882 /* Timeout 200us */ 1883 if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1884 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); 1885 1886 display->cdclk.hw.vco = vco; 1887 } 1888 1889 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) 1890 { 1891 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1892 u32 val; 1893 1894 /* Write PLL ratio without disabling */ 1895 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1896 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1897 1898 /* Submit freq change request */ 1899 val |= BXT_DE_PLL_FREQ_REQ; 1900 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1901 1902 /* Timeout 200us */ 1903 if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, 1904 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1905 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); 1906 1907 val &= ~BXT_DE_PLL_FREQ_REQ; 1908 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1909 1910 display->cdclk.hw.vco = vco; 1911 } 1912 1913 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 1914 { 1915 if (DISPLAY_VER(display) >= 12) { 1916 if (pipe == INVALID_PIPE) 1917 return TGL_CDCLK_CD2X_PIPE_NONE; 1918 else 1919 return TGL_CDCLK_CD2X_PIPE(pipe); 1920 } else if (DISPLAY_VER(display) >= 11) { 1921 if (pipe == INVALID_PIPE) 1922 return ICL_CDCLK_CD2X_PIPE_NONE; 1923 else 1924 return ICL_CDCLK_CD2X_PIPE(pipe); 1925 } else { 1926 if (pipe == INVALID_PIPE) 1927 return BXT_CDCLK_CD2X_PIPE_NONE; 1928 else 1929 return BXT_CDCLK_CD2X_PIPE(pipe); 1930 } 1931 } 1932 1933 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 1934 int cdclk, int vco, u16 waveform) 1935 { 1936 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1937 switch (cdclk_divider(cdclk, vco, waveform)) { 1938 default: 1939 drm_WARN_ON(display->drm, 1940 cdclk != display->cdclk.hw.bypass); 1941 drm_WARN_ON(display->drm, vco != 0); 1942 fallthrough; 1943 case 2: 1944 return BXT_CDCLK_CD2X_DIV_SEL_1; 1945 case 3: 1946 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1947 case 4: 1948 return BXT_CDCLK_CD2X_DIV_SEL_2; 1949 case 8: 1950 return BXT_CDCLK_CD2X_DIV_SEL_4; 1951 } 1952 } 1953 1954 static u16 cdclk_squash_waveform(struct intel_display *display, 1955 int cdclk) 1956 { 1957 const struct intel_cdclk_vals *table = display->cdclk.table; 1958 int i; 1959 1960 if (cdclk == display->cdclk.hw.bypass) 1961 return 0; 1962 1963 for (i = 0; table[i].refclk; i++) 1964 if (table[i].refclk == display->cdclk.hw.ref && 1965 table[i].cdclk == cdclk) 1966 return table[i].waveform; 1967 1968 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1969 cdclk, display->cdclk.hw.ref); 1970 1971 return 0xffff; 1972 } 1973 1974 static void icl_cdclk_pll_update(struct intel_display *display, int vco) 1975 { 1976 if (display->cdclk.hw.vco != 0 && 1977 display->cdclk.hw.vco != vco) 1978 icl_cdclk_pll_disable(display); 1979 1980 if (display->cdclk.hw.vco != vco) 1981 icl_cdclk_pll_enable(display, vco); 1982 } 1983 1984 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) 1985 { 1986 if (display->cdclk.hw.vco != 0 && 1987 display->cdclk.hw.vco != vco) 1988 bxt_de_pll_disable(display); 1989 1990 if (display->cdclk.hw.vco != vco) 1991 bxt_de_pll_enable(display, vco); 1992 } 1993 1994 static void dg2_cdclk_squash_program(struct intel_display *display, 1995 u16 waveform) 1996 { 1997 u32 squash_ctl = 0; 1998 1999 if (waveform) 2000 squash_ctl = CDCLK_SQUASH_ENABLE | 2001 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 2002 2003 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); 2004 } 2005 2006 static bool cdclk_pll_is_unknown(unsigned int vco) 2007 { 2008 /* 2009 * Ensure driver does not take the crawl path for the 2010 * case when the vco is set to ~0 in the 2011 * sanitize path. 2012 */ 2013 return vco == ~0; 2014 } 2015 2016 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) 2017 { 2018 return DISPLAY_VER(display) >= 20; 2019 } 2020 2021 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) 2022 { 2023 if (mdclk_source_is_cdclk_pll(display)) 2024 return MDCLK_SOURCE_SEL_CDCLK_PLL; 2025 2026 return MDCLK_SOURCE_SEL_CD2XCLK; 2027 } 2028 2029 int intel_mdclk_cdclk_ratio(struct intel_display *display, 2030 const struct intel_cdclk_config *cdclk_config) 2031 { 2032 if (mdclk_source_is_cdclk_pll(display)) 2033 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 2034 2035 /* Otherwise, source for MDCLK is CD2XCLK. */ 2036 return 2; 2037 } 2038 2039 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, 2040 const struct intel_cdclk_config *cdclk_config) 2041 { 2042 intel_dbuf_mdclk_cdclk_ratio_update(display, 2043 intel_mdclk_cdclk_ratio(display, cdclk_config), 2044 cdclk_config->joined_mbus); 2045 } 2046 2047 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, 2048 const struct intel_cdclk_config *old_cdclk_config, 2049 const struct intel_cdclk_config *new_cdclk_config, 2050 struct intel_cdclk_config *mid_cdclk_config) 2051 { 2052 u16 old_waveform, new_waveform, mid_waveform; 2053 int old_div, new_div, mid_div; 2054 2055 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 2056 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 2057 return false; 2058 2059 /* Return if both Squash and Crawl are not present */ 2060 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2061 return false; 2062 2063 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); 2064 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); 2065 2066 /* Return if Squash only or Crawl only is the desired action */ 2067 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 2068 old_cdclk_config->vco == new_cdclk_config->vco || 2069 old_waveform == new_waveform) 2070 return false; 2071 2072 old_div = cdclk_divider(old_cdclk_config->cdclk, 2073 old_cdclk_config->vco, old_waveform); 2074 new_div = cdclk_divider(new_cdclk_config->cdclk, 2075 new_cdclk_config->vco, new_waveform); 2076 2077 /* 2078 * Should not happen currently. We might need more midpoint 2079 * transitions if we need to also change the cd2x divider. 2080 */ 2081 if (drm_WARN_ON(display->drm, old_div != new_div)) 2082 return false; 2083 2084 *mid_cdclk_config = *new_cdclk_config; 2085 2086 /* 2087 * Populate the mid_cdclk_config accordingly. 2088 * - If moving to a higher cdclk, the desired action is squashing. 2089 * The mid cdclk config should have the new (squash) waveform. 2090 * - If moving to a lower cdclk, the desired action is crawling. 2091 * The mid cdclk config should have the new vco. 2092 */ 2093 2094 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 2095 mid_cdclk_config->vco = old_cdclk_config->vco; 2096 mid_div = old_div; 2097 mid_waveform = new_waveform; 2098 } else { 2099 mid_cdclk_config->vco = new_cdclk_config->vco; 2100 mid_div = new_div; 2101 mid_waveform = old_waveform; 2102 } 2103 2104 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 2105 mid_cdclk_config->vco, 2106 cdclk_squash_len * mid_div); 2107 2108 /* make sure the mid clock came out sane */ 2109 2110 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < 2111 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 2112 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > 2113 display->cdclk.max_cdclk_freq); 2114 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != 2115 mid_waveform); 2116 2117 return true; 2118 } 2119 2120 static bool pll_enable_wa_needed(struct intel_display *display) 2121 { 2122 return (DISPLAY_VERx100(display) == 2000 || 2123 DISPLAY_VERx100(display) == 1400 || 2124 display->platform.dg2) && 2125 display->cdclk.hw.vco > 0; 2126 } 2127 2128 static u32 bxt_cdclk_ctl(struct intel_display *display, 2129 const struct intel_cdclk_config *cdclk_config, 2130 enum pipe pipe) 2131 { 2132 int cdclk = cdclk_config->cdclk; 2133 int vco = cdclk_config->vco; 2134 u16 waveform; 2135 u32 val; 2136 2137 waveform = cdclk_squash_waveform(display, cdclk); 2138 2139 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | 2140 bxt_cdclk_cd2x_pipe(display, pipe); 2141 2142 /* 2143 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2144 * enable otherwise. 2145 */ 2146 if ((display->platform.geminilake || display->platform.broxton) && 2147 cdclk >= 500000) 2148 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2149 2150 if (DISPLAY_VER(display) >= 20) 2151 val |= xe2lpd_mdclk_source_sel(display); 2152 else 2153 val |= skl_cdclk_decimal(cdclk); 2154 2155 return val; 2156 } 2157 2158 static void _bxt_set_cdclk(struct intel_display *display, 2159 const struct intel_cdclk_config *cdclk_config, 2160 enum pipe pipe) 2161 { 2162 int cdclk = cdclk_config->cdclk; 2163 int vco = cdclk_config->vco; 2164 2165 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && 2166 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { 2167 if (display->cdclk.hw.vco != vco) 2168 adlp_cdclk_pll_crawl(display, vco); 2169 } else if (DISPLAY_VER(display) >= 11) { 2170 /* wa_15010685871: dg2, mtl */ 2171 if (pll_enable_wa_needed(display)) 2172 dg2_cdclk_squash_program(display, 0); 2173 2174 icl_cdclk_pll_update(display, vco); 2175 } else { 2176 bxt_cdclk_pll_update(display, vco); 2177 } 2178 2179 if (HAS_CDCLK_SQUASH(display)) { 2180 u16 waveform = cdclk_squash_waveform(display, cdclk); 2181 2182 dg2_cdclk_squash_program(display, waveform); 2183 } 2184 2185 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); 2186 2187 if (pipe != INVALID_PIPE) 2188 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 2189 } 2190 2191 static void bxt_set_cdclk(struct intel_display *display, 2192 const struct intel_cdclk_config *cdclk_config, 2193 enum pipe pipe) 2194 { 2195 struct intel_cdclk_config mid_cdclk_config; 2196 int cdclk = cdclk_config->cdclk; 2197 int ret = 0; 2198 2199 /* 2200 * Inform power controller of upcoming frequency change. 2201 * Display versions 14 and beyond do not follow the PUnit 2202 * mailbox communication, skip 2203 * this step. 2204 */ 2205 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) 2206 ; /* NOOP */ 2207 else if (DISPLAY_VER(display) >= 11) 2208 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 2209 SKL_CDCLK_PREPARE_FOR_CHANGE, 2210 SKL_CDCLK_READY_FOR_CHANGE, 2211 SKL_CDCLK_READY_FOR_CHANGE, 3); 2212 else 2213 /* 2214 * BSpec requires us to wait up to 150usec, but that leads to 2215 * timeouts; the 2ms used here is based on experiment. 2216 */ 2217 ret = intel_pcode_write_timeout(display->drm, 2218 HSW_PCODE_DE_WRITE_FREQ_REQ, 2219 0x80000000, 2); 2220 2221 if (ret) { 2222 drm_err(display->drm, 2223 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2224 ret, cdclk); 2225 return; 2226 } 2227 2228 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) 2229 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2230 2231 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, 2232 cdclk_config, &mid_cdclk_config)) { 2233 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); 2234 _bxt_set_cdclk(display, cdclk_config, pipe); 2235 } else { 2236 _bxt_set_cdclk(display, cdclk_config, pipe); 2237 } 2238 2239 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) 2240 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2241 2242 if (DISPLAY_VER(display) >= 14) 2243 /* 2244 * NOOP - No Pcode communication needed for 2245 * Display versions 14 and beyond 2246 */; 2247 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) 2248 ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, 2249 cdclk_config->voltage_level); 2250 if (DISPLAY_VER(display) < 11) { 2251 /* 2252 * The timeout isn't specified, the 2ms used here is based on 2253 * experiment. 2254 * FIXME: Waiting for the request completion could be delayed 2255 * until the next PCODE request based on BSpec. 2256 */ 2257 ret = intel_pcode_write_timeout(display->drm, 2258 HSW_PCODE_DE_WRITE_FREQ_REQ, 2259 cdclk_config->voltage_level, 2); 2260 } 2261 if (ret) { 2262 drm_err(display->drm, 2263 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2264 ret, cdclk); 2265 return; 2266 } 2267 2268 intel_update_cdclk(display); 2269 2270 if (DISPLAY_VER(display) >= 11) 2271 /* 2272 * Can't read out the voltage level :( 2273 * Let's just assume everything is as expected. 2274 */ 2275 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; 2276 } 2277 2278 static void bxt_sanitize_cdclk(struct intel_display *display) 2279 { 2280 u32 cdctl, expected; 2281 int cdclk, vco; 2282 2283 intel_update_cdclk(display); 2284 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 2285 2286 if (display->cdclk.hw.vco == 0 || 2287 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 2288 goto sanitize; 2289 2290 /* Make sure this is a legal cdclk value for the platform */ 2291 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); 2292 if (cdclk != display->cdclk.hw.cdclk) 2293 goto sanitize; 2294 2295 /* Make sure the VCO is correct for the cdclk */ 2296 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 2297 if (vco != display->cdclk.hw.vco) 2298 goto sanitize; 2299 2300 /* 2301 * Some BIOS versions leave an incorrect decimal frequency value and 2302 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2303 * so sanitize this register. 2304 */ 2305 cdctl = intel_de_read(display, CDCLK_CTL); 2306 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); 2307 2308 /* 2309 * Let's ignore the pipe field, since BIOS could have configured the 2310 * dividers both syncing to an active pipe, or asynchronously 2311 * (PIPE_NONE). 2312 */ 2313 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2314 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2315 2316 if (cdctl == expected) 2317 /* All well; nothing to sanitize */ 2318 return; 2319 2320 sanitize: 2321 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 2322 2323 /* force cdclk programming */ 2324 display->cdclk.hw.cdclk = 0; 2325 2326 /* force full PLL disable + enable */ 2327 display->cdclk.hw.vco = ~0; 2328 } 2329 2330 static void bxt_cdclk_init_hw(struct intel_display *display) 2331 { 2332 struct intel_cdclk_config cdclk_config; 2333 2334 bxt_sanitize_cdclk(display); 2335 2336 if (display->cdclk.hw.cdclk != 0 && 2337 display->cdclk.hw.vco != 0) 2338 return; 2339 2340 cdclk_config = display->cdclk.hw; 2341 2342 /* 2343 * FIXME: 2344 * - The initial CDCLK needs to be read from VBT. 2345 * Need to make this change after VBT has changes for BXT. 2346 */ 2347 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); 2348 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); 2349 cdclk_config.voltage_level = 2350 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2351 2352 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2353 } 2354 2355 static void bxt_cdclk_uninit_hw(struct intel_display *display) 2356 { 2357 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 2358 2359 cdclk_config.cdclk = cdclk_config.bypass; 2360 cdclk_config.vco = 0; 2361 cdclk_config.voltage_level = 2362 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2363 2364 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2365 } 2366 2367 /** 2368 * intel_cdclk_init_hw - Initialize CDCLK hardware 2369 * @display: display instance 2370 * 2371 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and 2372 * sanitizing the state of the hardware if needed. This is generally done only 2373 * during the display core initialization sequence, after which the DMC will 2374 * take care of turning CDCLK off/on as needed. 2375 */ 2376 void intel_cdclk_init_hw(struct intel_display *display) 2377 { 2378 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2379 bxt_cdclk_init_hw(display); 2380 else if (DISPLAY_VER(display) == 9) 2381 skl_cdclk_init_hw(display); 2382 } 2383 2384 /** 2385 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2386 * @display: display instance 2387 * 2388 * Uninitialize CDCLK. This is done only during the display core 2389 * uninitialization sequence. 2390 */ 2391 void intel_cdclk_uninit_hw(struct intel_display *display) 2392 { 2393 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2394 bxt_cdclk_uninit_hw(display); 2395 else if (DISPLAY_VER(display) == 9) 2396 skl_cdclk_uninit_hw(display); 2397 } 2398 2399 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, 2400 const struct intel_cdclk_config *a, 2401 const struct intel_cdclk_config *b) 2402 { 2403 u16 old_waveform; 2404 u16 new_waveform; 2405 2406 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); 2407 2408 if (a->vco == 0 || b->vco == 0) 2409 return false; 2410 2411 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2412 return false; 2413 2414 old_waveform = cdclk_squash_waveform(display, a->cdclk); 2415 new_waveform = cdclk_squash_waveform(display, b->cdclk); 2416 2417 return a->vco != b->vco && 2418 old_waveform != new_waveform; 2419 } 2420 2421 static bool intel_cdclk_can_crawl(struct intel_display *display, 2422 const struct intel_cdclk_config *a, 2423 const struct intel_cdclk_config *b) 2424 { 2425 int a_div, b_div; 2426 2427 if (!HAS_CDCLK_CRAWL(display)) 2428 return false; 2429 2430 /* 2431 * The vco and cd2x divider will change independently 2432 * from each, so we disallow cd2x change when crawling. 2433 */ 2434 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2435 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2436 2437 return a->vco != 0 && b->vco != 0 && 2438 a->vco != b->vco && 2439 a_div == b_div && 2440 a->ref == b->ref; 2441 } 2442 2443 static bool intel_cdclk_can_squash(struct intel_display *display, 2444 const struct intel_cdclk_config *a, 2445 const struct intel_cdclk_config *b) 2446 { 2447 /* 2448 * FIXME should store a bit more state in intel_cdclk_config 2449 * to differentiate squasher vs. cd2x divider properly. For 2450 * the moment all platforms with squasher use a fixed cd2x 2451 * divider. 2452 */ 2453 if (!HAS_CDCLK_SQUASH(display)) 2454 return false; 2455 2456 return a->cdclk != b->cdclk && 2457 a->vco != 0 && 2458 a->vco == b->vco && 2459 a->ref == b->ref; 2460 } 2461 2462 /** 2463 * intel_cdclk_clock_changed - Check whether the clock changed 2464 * @a: first CDCLK configuration 2465 * @b: second CDCLK configuration 2466 * 2467 * Returns: 2468 * True if CDCLK changed in a way that requires re-programming and 2469 * False otherwise. 2470 */ 2471 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2472 const struct intel_cdclk_config *b) 2473 { 2474 return a->cdclk != b->cdclk || 2475 a->vco != b->vco || 2476 a->ref != b->ref; 2477 } 2478 2479 /** 2480 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2481 * configurations requires only a cd2x divider update 2482 * @display: display instance 2483 * @a: first CDCLK configuration 2484 * @b: second CDCLK configuration 2485 * 2486 * Returns: 2487 * True if changing between the two CDCLK configurations 2488 * can be done with just a cd2x divider update, false if not. 2489 */ 2490 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, 2491 const struct intel_cdclk_config *a, 2492 const struct intel_cdclk_config *b) 2493 { 2494 /* Older hw doesn't have the capability */ 2495 if (DISPLAY_VER(display) < 10 && !display->platform.broxton) 2496 return false; 2497 2498 /* 2499 * FIXME should store a bit more state in intel_cdclk_config 2500 * to differentiate squasher vs. cd2x divider properly. For 2501 * the moment all platforms with squasher use a fixed cd2x 2502 * divider. 2503 */ 2504 if (HAS_CDCLK_SQUASH(display)) 2505 return false; 2506 2507 return a->cdclk != b->cdclk && 2508 a->vco != 0 && 2509 a->vco == b->vco && 2510 a->ref == b->ref; 2511 } 2512 2513 /** 2514 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2515 * @a: first CDCLK configuration 2516 * @b: second CDCLK configuration 2517 * 2518 * Returns: 2519 * True if the CDCLK configurations don't match, false if they do. 2520 */ 2521 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2522 const struct intel_cdclk_config *b) 2523 { 2524 return intel_cdclk_clock_changed(a, b) || 2525 a->voltage_level != b->voltage_level; 2526 } 2527 2528 void intel_cdclk_dump_config(struct intel_display *display, 2529 const struct intel_cdclk_config *cdclk_config, 2530 const char *context) 2531 { 2532 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2533 context, cdclk_config->cdclk, cdclk_config->vco, 2534 cdclk_config->ref, cdclk_config->bypass, 2535 cdclk_config->voltage_level); 2536 } 2537 2538 static void intel_pcode_notify(struct intel_display *display, 2539 u8 voltage_level, 2540 u8 active_pipe_count, 2541 u16 cdclk, 2542 bool cdclk_update_valid, 2543 bool pipe_count_update_valid) 2544 { 2545 int ret; 2546 u32 update_mask = 0; 2547 2548 if (!display->platform.dg2) 2549 return; 2550 2551 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2552 2553 if (cdclk_update_valid) 2554 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2555 2556 if (pipe_count_update_valid) 2557 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2558 2559 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 2560 SKL_CDCLK_PREPARE_FOR_CHANGE | 2561 update_mask, 2562 SKL_CDCLK_READY_FOR_CHANGE, 2563 SKL_CDCLK_READY_FOR_CHANGE, 3); 2564 if (ret) 2565 drm_err(display->drm, 2566 "Failed to inform PCU about display config (err %d)\n", 2567 ret); 2568 } 2569 2570 static void intel_set_cdclk(struct intel_display *display, 2571 const struct intel_cdclk_config *cdclk_config, 2572 enum pipe pipe, const char *context) 2573 { 2574 struct intel_encoder *encoder; 2575 2576 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) 2577 return; 2578 2579 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) 2580 return; 2581 2582 intel_cdclk_dump_config(display, cdclk_config, context); 2583 2584 for_each_intel_encoder_with_psr(display->drm, encoder) { 2585 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2586 2587 intel_psr_pause(intel_dp); 2588 } 2589 2590 intel_audio_cdclk_change_pre(display); 2591 2592 /* 2593 * Lock aux/gmbus while we change cdclk in case those 2594 * functions use cdclk. Not all platforms/ports do, 2595 * but we'll lock them all for simplicity. 2596 */ 2597 mutex_lock(&display->gmbus.mutex); 2598 for_each_intel_dp(display->drm, encoder) { 2599 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2600 2601 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2602 &display->gmbus.mutex); 2603 } 2604 2605 intel_cdclk_set_cdclk(display, cdclk_config, pipe); 2606 2607 for_each_intel_dp(display->drm, encoder) { 2608 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2609 2610 mutex_unlock(&intel_dp->aux.hw_mutex); 2611 } 2612 mutex_unlock(&display->gmbus.mutex); 2613 2614 for_each_intel_encoder_with_psr(display->drm, encoder) { 2615 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2616 2617 intel_psr_resume(intel_dp); 2618 } 2619 2620 intel_audio_cdclk_change_post(display); 2621 2622 if (drm_WARN(display->drm, 2623 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), 2624 "cdclk state doesn't match!\n")) { 2625 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); 2626 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); 2627 } 2628 } 2629 2630 static bool dg2_power_well_count(struct intel_display *display, 2631 const struct intel_cdclk_state *cdclk_state) 2632 { 2633 return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0; 2634 } 2635 2636 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2637 { 2638 struct intel_display *display = to_intel_display(state); 2639 const struct intel_cdclk_state *old_cdclk_state = 2640 intel_atomic_get_old_cdclk_state(state); 2641 const struct intel_cdclk_state *new_cdclk_state = 2642 intel_atomic_get_new_cdclk_state(state); 2643 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2644 bool change_cdclk, update_pipe_count; 2645 2646 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2647 &new_cdclk_state->actual) && 2648 dg2_power_well_count(display, old_cdclk_state) == 2649 dg2_power_well_count(display, new_cdclk_state)) 2650 return; 2651 2652 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2653 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2654 2655 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2656 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) > 2657 dg2_power_well_count(display, old_cdclk_state); 2658 2659 /* 2660 * According to "Sequence Before Frequency Change", 2661 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2662 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2663 * which basically means we choose the maximum of old and new CDCLK, if we know both 2664 */ 2665 if (change_cdclk) 2666 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2667 2668 /* 2669 * According to "Sequence For Pipe Count Change", 2670 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2671 * (power well is enabled) 2672 * no action if it is decreasing, before the change 2673 */ 2674 if (update_pipe_count) 2675 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); 2676 2677 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2678 change_cdclk, update_pipe_count); 2679 } 2680 2681 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2682 { 2683 struct intel_display *display = to_intel_display(state); 2684 const struct intel_cdclk_state *new_cdclk_state = 2685 intel_atomic_get_new_cdclk_state(state); 2686 const struct intel_cdclk_state *old_cdclk_state = 2687 intel_atomic_get_old_cdclk_state(state); 2688 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2689 bool update_cdclk, update_pipe_count; 2690 2691 /* According to "Sequence After Frequency Change", set voltage to used level */ 2692 voltage_level = new_cdclk_state->actual.voltage_level; 2693 2694 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2695 update_pipe_count = dg2_power_well_count(display, new_cdclk_state) < 2696 dg2_power_well_count(display, old_cdclk_state); 2697 2698 /* 2699 * According to "Sequence After Frequency Change", 2700 * set bits 25:16 to current CDCLK 2701 */ 2702 if (update_cdclk) 2703 cdclk = new_cdclk_state->actual.cdclk; 2704 2705 /* 2706 * According to "Sequence For Pipe Count Change", 2707 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2708 * after the change(power well is disabled) 2709 * no action if it is increasing, after the change 2710 */ 2711 if (update_pipe_count) 2712 num_active_pipes = dg2_power_well_count(display, new_cdclk_state); 2713 2714 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2715 update_cdclk, update_pipe_count); 2716 } 2717 2718 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2719 { 2720 const struct intel_cdclk_state *old_cdclk_state = 2721 intel_atomic_get_old_cdclk_state(state); 2722 const struct intel_cdclk_state *new_cdclk_state = 2723 intel_atomic_get_new_cdclk_state(state); 2724 2725 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2726 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2727 } 2728 2729 /** 2730 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2731 * @state: intel atomic state 2732 * 2733 * Program the hardware before updating the HW plane state based on the 2734 * new CDCLK state, if necessary. 2735 */ 2736 void 2737 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2738 { 2739 struct intel_display *display = to_intel_display(state); 2740 const struct intel_cdclk_state *old_cdclk_state = 2741 intel_atomic_get_old_cdclk_state(state); 2742 const struct intel_cdclk_state *new_cdclk_state = 2743 intel_atomic_get_new_cdclk_state(state); 2744 struct intel_cdclk_config cdclk_config; 2745 enum pipe pipe; 2746 2747 if (!new_cdclk_state) 2748 return; 2749 2750 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2751 &new_cdclk_state->actual)) 2752 return; 2753 2754 if (display->platform.dg2) 2755 intel_cdclk_pcode_pre_notify(state); 2756 2757 if (new_cdclk_state->disable_pipes) { 2758 cdclk_config = new_cdclk_state->actual; 2759 pipe = INVALID_PIPE; 2760 } else { 2761 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2762 cdclk_config = new_cdclk_state->actual; 2763 pipe = new_cdclk_state->pipe; 2764 } else { 2765 cdclk_config = old_cdclk_state->actual; 2766 pipe = INVALID_PIPE; 2767 } 2768 2769 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2770 old_cdclk_state->actual.voltage_level); 2771 } 2772 2773 /* 2774 * mbus joining will be changed later by 2775 * intel_dbuf_mbus_{pre,post}_ddb_update() 2776 */ 2777 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2778 2779 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2780 2781 intel_set_cdclk(display, &cdclk_config, pipe, 2782 "Pre changing CDCLK to"); 2783 } 2784 2785 /** 2786 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2787 * @state: intel atomic state 2788 * 2789 * Program the hardware after updating the HW plane state based on the 2790 * new CDCLK state, if necessary. 2791 */ 2792 void 2793 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2794 { 2795 struct intel_display *display = to_intel_display(state); 2796 const struct intel_cdclk_state *old_cdclk_state = 2797 intel_atomic_get_old_cdclk_state(state); 2798 const struct intel_cdclk_state *new_cdclk_state = 2799 intel_atomic_get_new_cdclk_state(state); 2800 enum pipe pipe; 2801 2802 if (!new_cdclk_state) 2803 return; 2804 2805 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2806 &new_cdclk_state->actual)) 2807 return; 2808 2809 if (display->platform.dg2) 2810 intel_cdclk_pcode_post_notify(state); 2811 2812 if (!new_cdclk_state->disable_pipes && 2813 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2814 pipe = new_cdclk_state->pipe; 2815 else 2816 pipe = INVALID_PIPE; 2817 2818 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2819 2820 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, 2821 "Post changing CDCLK to"); 2822 } 2823 2824 /* pixels per CDCLK */ 2825 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) 2826 { 2827 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; 2828 } 2829 2830 /* max pixel rate as % of CDCLK (not accounting for PPC) */ 2831 static int intel_cdclk_guardband(struct intel_display *display) 2832 { 2833 if (DISPLAY_VER(display) >= 9 || 2834 display->platform.broadwell || display->platform.haswell) 2835 return 100; 2836 else if (display->platform.cherryview) 2837 return 95; 2838 else 2839 return 90; 2840 } 2841 2842 static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate) 2843 { 2844 struct intel_display *display = to_intel_display(crtc_state); 2845 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 2846 int guardband = intel_cdclk_guardband(display); 2847 2848 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); 2849 } 2850 2851 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2852 { 2853 return _intel_pixel_rate_to_cdclk(crtc_state, crtc_state->pixel_rate); 2854 } 2855 2856 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2857 { 2858 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2859 struct intel_display *display = to_intel_display(crtc); 2860 struct intel_plane *plane; 2861 int min_cdclk = 0; 2862 2863 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2864 min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]); 2865 2866 return min_cdclk; 2867 } 2868 2869 int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state) 2870 { 2871 int min_cdclk; 2872 2873 if (!crtc_state->hw.enable) 2874 return 0; 2875 2876 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2877 min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state)); 2878 min_cdclk = max(min_cdclk, intel_fbc_min_cdclk(crtc_state)); 2879 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state)); 2880 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state)); 2881 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); 2882 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state)); 2883 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2884 2885 return min_cdclk; 2886 } 2887 2888 static int intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state *state, 2889 struct intel_crtc *crtc, 2890 int old_min_cdclk, int new_min_cdclk, 2891 bool *need_cdclk_calc) 2892 { 2893 struct intel_display *display = to_intel_display(state); 2894 struct intel_cdclk_state *cdclk_state; 2895 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state); 2896 int ret; 2897 2898 if (new_min_cdclk == old_min_cdclk) 2899 return 0; 2900 2901 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2902 return 0; 2903 2904 cdclk_state = intel_atomic_get_cdclk_state(state); 2905 if (IS_ERR(cdclk_state)) 2906 return PTR_ERR(cdclk_state); 2907 2908 old_min_cdclk = cdclk_state->min_cdclk[crtc->pipe]; 2909 2910 if (new_min_cdclk == old_min_cdclk) 2911 return 0; 2912 2913 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2914 return 0; 2915 2916 cdclk_state->min_cdclk[crtc->pipe] = new_min_cdclk; 2917 2918 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2919 if (ret) 2920 return ret; 2921 2922 *need_cdclk_calc = true; 2923 2924 drm_dbg_kms(display->drm, 2925 "[CRTC:%d:%s] min cdclk: %d kHz -> %d kHz\n", 2926 crtc->base.base.id, crtc->base.name, 2927 old_min_cdclk, new_min_cdclk); 2928 2929 return 0; 2930 } 2931 2932 int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state, 2933 int old_min_cdclk, int new_min_cdclk, 2934 bool *need_cdclk_calc) 2935 { 2936 struct intel_display *display = to_intel_display(state); 2937 struct intel_cdclk_state *cdclk_state; 2938 bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state); 2939 int ret; 2940 2941 if (new_min_cdclk == old_min_cdclk) 2942 return 0; 2943 2944 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2945 return 0; 2946 2947 cdclk_state = intel_atomic_get_cdclk_state(state); 2948 if (IS_ERR(cdclk_state)) 2949 return PTR_ERR(cdclk_state); 2950 2951 old_min_cdclk = cdclk_state->dbuf_bw_min_cdclk; 2952 2953 if (new_min_cdclk == old_min_cdclk) 2954 return 0; 2955 2956 if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk) 2957 return 0; 2958 2959 cdclk_state->dbuf_bw_min_cdclk = new_min_cdclk; 2960 2961 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2962 if (ret) 2963 return ret; 2964 2965 *need_cdclk_calc = true; 2966 2967 drm_dbg_kms(display->drm, 2968 "dbuf bandwidth min cdclk: %d kHz -> %d kHz\n", 2969 old_min_cdclk, new_min_cdclk); 2970 2971 return 0; 2972 } 2973 2974 static bool glk_cdclk_audio_wa_needed(struct intel_display *display, 2975 const struct intel_cdclk_state *cdclk_state) 2976 { 2977 return display->platform.geminilake && 2978 cdclk_state->enabled_pipes && 2979 !is_power_of_2(cdclk_state->enabled_pipes); 2980 } 2981 2982 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 2983 { 2984 struct intel_display *display = to_intel_display(state); 2985 struct intel_cdclk_state *cdclk_state = 2986 intel_atomic_get_new_cdclk_state(state); 2987 enum pipe pipe; 2988 int min_cdclk; 2989 2990 min_cdclk = cdclk_state->force_min_cdclk; 2991 min_cdclk = max(min_cdclk, cdclk_state->dbuf_bw_min_cdclk); 2992 for_each_pipe(display, pipe) 2993 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); 2994 2995 /* 2996 * Avoid glk_force_audio_cdclk() causing excessive screen 2997 * blinking when multiple pipes are active by making sure 2998 * CDCLK frequency is always high enough for audio. With a 2999 * single active pipe we can always change CDCLK frequency 3000 * by changing the cd2x divider (see glk_cdclk_table[]) and 3001 * thus a full modeset won't be needed then. 3002 */ 3003 if (glk_cdclk_audio_wa_needed(display, cdclk_state)) 3004 min_cdclk = max(min_cdclk, 2 * 96000); 3005 3006 if (min_cdclk > display->cdclk.max_cdclk_freq) { 3007 drm_dbg_kms(display->drm, 3008 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 3009 min_cdclk, display->cdclk.max_cdclk_freq); 3010 return -EINVAL; 3011 } 3012 3013 return min_cdclk; 3014 } 3015 3016 /* 3017 * Account for port clock min voltage level requirements. 3018 * This only really does something on DISPLA_VER >= 11 but can be 3019 * called on earlier platforms as well. 3020 * 3021 * Note that this functions assumes that 0 is 3022 * the lowest voltage value, and higher values 3023 * correspond to increasingly higher voltages. 3024 * 3025 * Should that relationship no longer hold on 3026 * future platforms this code will need to be 3027 * adjusted. 3028 */ 3029 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 3030 { 3031 struct intel_display *display = to_intel_display(state); 3032 struct intel_cdclk_state *cdclk_state = 3033 intel_atomic_get_new_cdclk_state(state); 3034 struct intel_crtc *crtc; 3035 struct intel_crtc_state *crtc_state; 3036 u8 min_voltage_level; 3037 int i; 3038 enum pipe pipe; 3039 3040 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 3041 int ret; 3042 3043 if (crtc_state->hw.enable) 3044 min_voltage_level = crtc_state->min_voltage_level; 3045 else 3046 min_voltage_level = 0; 3047 3048 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 3049 continue; 3050 3051 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 3052 3053 ret = intel_atomic_lock_global_state(&cdclk_state->base); 3054 if (ret) 3055 return ret; 3056 } 3057 3058 min_voltage_level = 0; 3059 for_each_pipe(display, pipe) 3060 min_voltage_level = max(min_voltage_level, 3061 cdclk_state->min_voltage_level[pipe]); 3062 3063 return min_voltage_level; 3064 } 3065 3066 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 3067 { 3068 struct intel_display *display = to_intel_display(state); 3069 struct intel_cdclk_state *cdclk_state = 3070 intel_atomic_get_new_cdclk_state(state); 3071 int min_cdclk, cdclk; 3072 3073 min_cdclk = intel_compute_min_cdclk(state); 3074 if (min_cdclk < 0) 3075 return min_cdclk; 3076 3077 cdclk = vlv_calc_cdclk(display, min_cdclk); 3078 3079 cdclk_state->logical.cdclk = cdclk; 3080 cdclk_state->logical.voltage_level = 3081 vlv_calc_voltage_level(display, cdclk); 3082 3083 if (!cdclk_state->active_pipes) { 3084 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); 3085 3086 cdclk_state->actual.cdclk = cdclk; 3087 cdclk_state->actual.voltage_level = 3088 vlv_calc_voltage_level(display, cdclk); 3089 } else { 3090 cdclk_state->actual = cdclk_state->logical; 3091 } 3092 3093 return 0; 3094 } 3095 3096 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 3097 { 3098 struct intel_cdclk_state *cdclk_state = 3099 intel_atomic_get_new_cdclk_state(state); 3100 int min_cdclk, cdclk; 3101 3102 min_cdclk = intel_compute_min_cdclk(state); 3103 if (min_cdclk < 0) 3104 return min_cdclk; 3105 3106 cdclk = bdw_calc_cdclk(min_cdclk); 3107 3108 cdclk_state->logical.cdclk = cdclk; 3109 cdclk_state->logical.voltage_level = 3110 bdw_calc_voltage_level(cdclk); 3111 3112 if (!cdclk_state->active_pipes) { 3113 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 3114 3115 cdclk_state->actual.cdclk = cdclk; 3116 cdclk_state->actual.voltage_level = 3117 bdw_calc_voltage_level(cdclk); 3118 } else { 3119 cdclk_state->actual = cdclk_state->logical; 3120 } 3121 3122 return 0; 3123 } 3124 3125 static int skl_dpll0_vco(struct intel_atomic_state *state) 3126 { 3127 struct intel_display *display = to_intel_display(state); 3128 struct intel_cdclk_state *cdclk_state = 3129 intel_atomic_get_new_cdclk_state(state); 3130 struct intel_crtc *crtc; 3131 struct intel_crtc_state *crtc_state; 3132 int vco, i; 3133 3134 vco = cdclk_state->logical.vco; 3135 if (!vco) 3136 vco = display->cdclk.skl_preferred_vco_freq; 3137 3138 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 3139 if (!crtc_state->hw.enable) 3140 continue; 3141 3142 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3143 continue; 3144 3145 /* 3146 * DPLL0 VCO may need to be adjusted to get the correct 3147 * clock for eDP. This will affect cdclk as well. 3148 */ 3149 switch (crtc_state->port_clock / 2) { 3150 case 108000: 3151 case 216000: 3152 vco = 8640000; 3153 break; 3154 default: 3155 vco = 8100000; 3156 break; 3157 } 3158 } 3159 3160 return vco; 3161 } 3162 3163 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3164 { 3165 struct intel_cdclk_state *cdclk_state = 3166 intel_atomic_get_new_cdclk_state(state); 3167 int min_cdclk, cdclk, vco; 3168 3169 min_cdclk = intel_compute_min_cdclk(state); 3170 if (min_cdclk < 0) 3171 return min_cdclk; 3172 3173 vco = skl_dpll0_vco(state); 3174 3175 cdclk = skl_calc_cdclk(min_cdclk, vco); 3176 3177 cdclk_state->logical.vco = vco; 3178 cdclk_state->logical.cdclk = cdclk; 3179 cdclk_state->logical.voltage_level = 3180 skl_calc_voltage_level(cdclk); 3181 3182 if (!cdclk_state->active_pipes) { 3183 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3184 3185 cdclk_state->actual.vco = vco; 3186 cdclk_state->actual.cdclk = cdclk; 3187 cdclk_state->actual.voltage_level = 3188 skl_calc_voltage_level(cdclk); 3189 } else { 3190 cdclk_state->actual = cdclk_state->logical; 3191 } 3192 3193 return 0; 3194 } 3195 3196 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3197 { 3198 struct intel_display *display = to_intel_display(state); 3199 struct intel_cdclk_state *cdclk_state = 3200 intel_atomic_get_new_cdclk_state(state); 3201 int min_cdclk, min_voltage_level, cdclk, vco; 3202 3203 min_cdclk = intel_compute_min_cdclk(state); 3204 if (min_cdclk < 0) 3205 return min_cdclk; 3206 3207 min_voltage_level = bxt_compute_min_voltage_level(state); 3208 if (min_voltage_level < 0) 3209 return min_voltage_level; 3210 3211 cdclk = bxt_calc_cdclk(display, min_cdclk); 3212 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3213 3214 cdclk_state->logical.vco = vco; 3215 cdclk_state->logical.cdclk = cdclk; 3216 cdclk_state->logical.voltage_level = 3217 max_t(int, min_voltage_level, 3218 intel_cdclk_calc_voltage_level(display, cdclk)); 3219 3220 if (!cdclk_state->active_pipes) { 3221 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); 3222 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3223 3224 cdclk_state->actual.vco = vco; 3225 cdclk_state->actual.cdclk = cdclk; 3226 cdclk_state->actual.voltage_level = 3227 intel_cdclk_calc_voltage_level(display, cdclk); 3228 } else { 3229 cdclk_state->actual = cdclk_state->logical; 3230 } 3231 3232 return 0; 3233 } 3234 3235 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3236 { 3237 int min_cdclk; 3238 3239 /* 3240 * We can't change the cdclk frequency, but we still want to 3241 * check that the required minimum frequency doesn't exceed 3242 * the actual cdclk frequency. 3243 */ 3244 min_cdclk = intel_compute_min_cdclk(state); 3245 if (min_cdclk < 0) 3246 return min_cdclk; 3247 3248 return 0; 3249 } 3250 3251 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3252 { 3253 struct intel_cdclk_state *cdclk_state; 3254 3255 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3256 if (!cdclk_state) 3257 return NULL; 3258 3259 cdclk_state->pipe = INVALID_PIPE; 3260 cdclk_state->disable_pipes = false; 3261 3262 return &cdclk_state->base; 3263 } 3264 3265 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3266 struct intel_global_state *state) 3267 { 3268 kfree(state); 3269 } 3270 3271 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3272 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3273 .atomic_destroy_state = intel_cdclk_destroy_state, 3274 }; 3275 3276 struct intel_cdclk_state * 3277 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3278 { 3279 struct intel_display *display = to_intel_display(state); 3280 struct intel_global_state *cdclk_state; 3281 3282 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); 3283 if (IS_ERR(cdclk_state)) 3284 return ERR_CAST(cdclk_state); 3285 3286 return to_intel_cdclk_state(cdclk_state); 3287 } 3288 3289 static int intel_cdclk_modeset_checks(struct intel_atomic_state *state, 3290 bool *need_cdclk_calc) 3291 { 3292 struct intel_display *display = to_intel_display(state); 3293 const struct intel_cdclk_state *old_cdclk_state; 3294 struct intel_cdclk_state *new_cdclk_state; 3295 int ret; 3296 3297 if (!intel_any_crtc_enable_changed(state) && 3298 !intel_any_crtc_active_changed(state)) 3299 return 0; 3300 3301 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3302 if (IS_ERR(new_cdclk_state)) 3303 return PTR_ERR(new_cdclk_state); 3304 3305 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3306 3307 new_cdclk_state->enabled_pipes = 3308 intel_calc_enabled_pipes(state, old_cdclk_state->enabled_pipes); 3309 3310 new_cdclk_state->active_pipes = 3311 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3312 3313 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3314 if (ret) 3315 return ret; 3316 3317 if (!old_cdclk_state->active_pipes != !new_cdclk_state->active_pipes) 3318 *need_cdclk_calc = true; 3319 3320 if (glk_cdclk_audio_wa_needed(display, old_cdclk_state) != 3321 glk_cdclk_audio_wa_needed(display, new_cdclk_state)) 3322 *need_cdclk_calc = true; 3323 3324 if (dg2_power_well_count(display, old_cdclk_state) != 3325 dg2_power_well_count(display, new_cdclk_state)) 3326 *need_cdclk_calc = true; 3327 3328 return 0; 3329 } 3330 3331 static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state, 3332 bool *need_cdclk_calc) 3333 { 3334 const struct intel_crtc_state *old_crtc_state; 3335 const struct intel_crtc_state *new_crtc_state; 3336 struct intel_crtc *crtc; 3337 int i, ret; 3338 3339 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 3340 new_crtc_state, i) { 3341 ret = intel_cdclk_update_crtc_min_cdclk(state, crtc, 3342 old_crtc_state->min_cdclk, 3343 new_crtc_state->min_cdclk, 3344 need_cdclk_calc); 3345 if (ret) 3346 return ret; 3347 } 3348 3349 return 0; 3350 } 3351 3352 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3353 { 3354 struct intel_cdclk_state *cdclk_state; 3355 3356 cdclk_state = intel_atomic_get_cdclk_state(state); 3357 if (IS_ERR(cdclk_state)) 3358 return PTR_ERR(cdclk_state); 3359 3360 cdclk_state->actual.joined_mbus = joined_mbus; 3361 cdclk_state->logical.joined_mbus = joined_mbus; 3362 3363 return intel_atomic_lock_global_state(&cdclk_state->base); 3364 } 3365 3366 int intel_cdclk_init(struct intel_display *display) 3367 { 3368 struct intel_cdclk_state *cdclk_state; 3369 3370 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 3371 if (!cdclk_state) 3372 return -ENOMEM; 3373 3374 intel_atomic_global_obj_init(display, &display->cdclk.obj, 3375 &cdclk_state->base, &intel_cdclk_funcs); 3376 3377 return 0; 3378 } 3379 3380 static bool intel_cdclk_need_serialize(struct intel_display *display, 3381 const struct intel_cdclk_state *old_cdclk_state, 3382 const struct intel_cdclk_state *new_cdclk_state) 3383 { 3384 /* 3385 * We need to poke hw for DG2, because we notify PCode if 3386 * pipe power well count changes. 3387 */ 3388 return intel_cdclk_changed(&old_cdclk_state->actual, 3389 &new_cdclk_state->actual) || 3390 dg2_power_well_count(display, old_cdclk_state) != 3391 dg2_power_well_count(display, new_cdclk_state); 3392 } 3393 3394 static int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3395 { 3396 struct intel_display *display = to_intel_display(state); 3397 const struct intel_cdclk_state *old_cdclk_state; 3398 struct intel_cdclk_state *new_cdclk_state; 3399 enum pipe pipe = INVALID_PIPE; 3400 int ret; 3401 3402 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3403 if (IS_ERR(new_cdclk_state)) 3404 return PTR_ERR(new_cdclk_state); 3405 3406 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3407 3408 ret = intel_cdclk_modeset_calc_cdclk(state); 3409 if (ret) 3410 return ret; 3411 3412 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { 3413 /* 3414 * Also serialize commits across all crtcs 3415 * if the actual hw needs to be poked. 3416 */ 3417 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3418 if (ret) 3419 return ret; 3420 } else if (intel_cdclk_changed(&old_cdclk_state->logical, 3421 &new_cdclk_state->logical)) { 3422 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3423 if (ret) 3424 return ret; 3425 } else { 3426 return 0; 3427 } 3428 3429 if (is_power_of_2(new_cdclk_state->active_pipes) && 3430 intel_cdclk_can_cd2x_update(display, 3431 &old_cdclk_state->actual, 3432 &new_cdclk_state->actual)) { 3433 struct intel_crtc *crtc; 3434 struct intel_crtc_state *crtc_state; 3435 3436 pipe = ilog2(new_cdclk_state->active_pipes); 3437 crtc = intel_crtc_for_pipe(display, pipe); 3438 3439 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3440 if (IS_ERR(crtc_state)) 3441 return PTR_ERR(crtc_state); 3442 3443 if (intel_crtc_needs_modeset(crtc_state)) 3444 pipe = INVALID_PIPE; 3445 } 3446 3447 if (intel_cdclk_can_crawl_and_squash(display, 3448 &old_cdclk_state->actual, 3449 &new_cdclk_state->actual)) { 3450 drm_dbg_kms(display->drm, 3451 "Can change cdclk via crawling and squashing\n"); 3452 } else if (intel_cdclk_can_squash(display, 3453 &old_cdclk_state->actual, 3454 &new_cdclk_state->actual)) { 3455 drm_dbg_kms(display->drm, 3456 "Can change cdclk via squashing\n"); 3457 } else if (intel_cdclk_can_crawl(display, 3458 &old_cdclk_state->actual, 3459 &new_cdclk_state->actual)) { 3460 drm_dbg_kms(display->drm, 3461 "Can change cdclk via crawling\n"); 3462 } else if (pipe != INVALID_PIPE) { 3463 new_cdclk_state->pipe = pipe; 3464 3465 drm_dbg_kms(display->drm, 3466 "Can change cdclk cd2x divider with pipe %c active\n", 3467 pipe_name(pipe)); 3468 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3469 &new_cdclk_state->actual)) { 3470 /* All pipes must be switched off while we change the cdclk. */ 3471 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3472 if (ret) 3473 return ret; 3474 3475 new_cdclk_state->disable_pipes = true; 3476 3477 drm_dbg_kms(display->drm, 3478 "Modeset required for cdclk change\n"); 3479 } 3480 3481 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != 3482 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { 3483 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); 3484 3485 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3486 if (ret) 3487 return ret; 3488 } 3489 3490 drm_dbg_kms(display->drm, 3491 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3492 new_cdclk_state->logical.cdclk, 3493 new_cdclk_state->actual.cdclk); 3494 drm_dbg_kms(display->drm, 3495 "New voltage level calculated to be logical %u, actual %u\n", 3496 new_cdclk_state->logical.voltage_level, 3497 new_cdclk_state->actual.voltage_level); 3498 3499 return 0; 3500 } 3501 3502 int intel_cdclk_atomic_check(struct intel_atomic_state *state) 3503 { 3504 const struct intel_cdclk_state *old_cdclk_state; 3505 struct intel_cdclk_state *new_cdclk_state; 3506 bool need_cdclk_calc = false; 3507 int ret; 3508 3509 ret = intel_cdclk_modeset_checks(state, &need_cdclk_calc); 3510 if (ret) 3511 return ret; 3512 3513 ret = intel_crtcs_calc_min_cdclk(state, &need_cdclk_calc); 3514 if (ret) 3515 return ret; 3516 3517 ret = intel_dbuf_bw_calc_min_cdclk(state, &need_cdclk_calc); 3518 if (ret) 3519 return ret; 3520 3521 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3522 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3523 3524 if (new_cdclk_state && 3525 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) { 3526 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3527 if (ret) 3528 return ret; 3529 3530 need_cdclk_calc = true; 3531 } 3532 3533 if (need_cdclk_calc) { 3534 ret = intel_modeset_calc_cdclk(state); 3535 if (ret) 3536 return ret; 3537 } 3538 3539 return 0; 3540 } 3541 3542 void intel_cdclk_update_hw_state(struct intel_display *display) 3543 { 3544 const struct intel_dbuf_bw_state *dbuf_bw_state = 3545 to_intel_dbuf_bw_state(display->dbuf_bw.obj.state); 3546 struct intel_cdclk_state *cdclk_state = 3547 to_intel_cdclk_state(display->cdclk.obj.state); 3548 struct intel_crtc *crtc; 3549 3550 cdclk_state->enabled_pipes = 0; 3551 cdclk_state->active_pipes = 0; 3552 3553 for_each_intel_crtc(display->drm, crtc) { 3554 const struct intel_crtc_state *crtc_state = 3555 to_intel_crtc_state(crtc->base.state); 3556 enum pipe pipe = crtc->pipe; 3557 3558 if (crtc_state->hw.enable) 3559 cdclk_state->enabled_pipes |= BIT(pipe); 3560 if (crtc_state->hw.active) 3561 cdclk_state->active_pipes |= BIT(pipe); 3562 3563 cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk; 3564 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level; 3565 } 3566 3567 cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display, dbuf_bw_state); 3568 } 3569 3570 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc) 3571 { 3572 struct intel_display *display = to_intel_display(crtc); 3573 3574 intel_cdclk_update_hw_state(display); 3575 } 3576 3577 static int intel_compute_max_dotclk(struct intel_display *display) 3578 { 3579 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); 3580 int guardband = intel_cdclk_guardband(display); 3581 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3582 3583 return ppc * max_cdclk_freq * guardband / 100; 3584 } 3585 3586 /** 3587 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3588 * @display: display instance 3589 * 3590 * Determine the maximum CDCLK frequency the platform supports, and also 3591 * derive the maximum dot clock frequency the maximum CDCLK frequency 3592 * allows. 3593 */ 3594 void intel_update_max_cdclk(struct intel_display *display) 3595 { 3596 if (DISPLAY_VER(display) >= 35) { 3597 display->cdclk.max_cdclk_freq = 787200; 3598 } else if (DISPLAY_VERx100(display) >= 3002) { 3599 display->cdclk.max_cdclk_freq = 480000; 3600 } else if (DISPLAY_VER(display) >= 30) { 3601 display->cdclk.max_cdclk_freq = 691200; 3602 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3603 if (display->cdclk.hw.ref == 24000) 3604 display->cdclk.max_cdclk_freq = 552000; 3605 else 3606 display->cdclk.max_cdclk_freq = 556800; 3607 } else if (DISPLAY_VER(display) >= 11) { 3608 if (display->cdclk.hw.ref == 24000) 3609 display->cdclk.max_cdclk_freq = 648000; 3610 else 3611 display->cdclk.max_cdclk_freq = 652800; 3612 } else if (display->platform.geminilake) { 3613 display->cdclk.max_cdclk_freq = 316800; 3614 } else if (display->platform.broxton) { 3615 display->cdclk.max_cdclk_freq = 624000; 3616 } else if (DISPLAY_VER(display) == 9) { 3617 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3618 int max_cdclk, vco; 3619 3620 vco = display->cdclk.skl_preferred_vco_freq; 3621 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 3622 3623 /* 3624 * Use the lower (vco 8640) cdclk values as a 3625 * first guess. skl_calc_cdclk() will correct it 3626 * if the preferred vco is 8100 instead. 3627 */ 3628 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3629 max_cdclk = 617143; 3630 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3631 max_cdclk = 540000; 3632 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3633 max_cdclk = 432000; 3634 else 3635 max_cdclk = 308571; 3636 3637 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3638 } else if (display->platform.broadwell) { 3639 /* 3640 * FIXME with extra cooling we can allow 3641 * 540 MHz for ULX and 675 Mhz for ULT. 3642 * How can we know if extra cooling is 3643 * available? PCI ID, VTB, something else? 3644 */ 3645 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3646 display->cdclk.max_cdclk_freq = 450000; 3647 else if (display->platform.broadwell_ulx) 3648 display->cdclk.max_cdclk_freq = 450000; 3649 else if (display->platform.broadwell_ult) 3650 display->cdclk.max_cdclk_freq = 540000; 3651 else 3652 display->cdclk.max_cdclk_freq = 675000; 3653 } else if (display->platform.cherryview) { 3654 display->cdclk.max_cdclk_freq = 320000; 3655 } else if (display->platform.valleyview) { 3656 display->cdclk.max_cdclk_freq = 400000; 3657 } else { 3658 /* otherwise assume cdclk is fixed */ 3659 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; 3660 } 3661 3662 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); 3663 3664 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", 3665 display->cdclk.max_cdclk_freq); 3666 3667 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", 3668 display->cdclk.max_dotclk_freq); 3669 } 3670 3671 /** 3672 * intel_update_cdclk - Determine the current CDCLK frequency 3673 * @display: display instance 3674 * 3675 * Determine the current CDCLK frequency. 3676 */ 3677 void intel_update_cdclk(struct intel_display *display) 3678 { 3679 intel_cdclk_get_cdclk(display, &display->cdclk.hw); 3680 3681 /* 3682 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3683 * Programmng [sic] note: bit[9:2] should be programmed to the number 3684 * of cdclk that generates 4MHz reference clock freq which is used to 3685 * generate GMBus clock. This will vary with the cdclk freq. 3686 */ 3687 if (display->platform.valleyview || display->platform.cherryview) 3688 intel_de_write(display, GMBUSFREQ_VLV, 3689 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); 3690 } 3691 3692 static int dg1_rawclk(struct intel_display *display) 3693 { 3694 /* 3695 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3696 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3697 */ 3698 intel_de_write(display, PCH_RAWCLK_FREQ, 3699 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3700 3701 return 38400; 3702 } 3703 3704 static int cnp_rawclk(struct intel_display *display) 3705 { 3706 int divider, fraction; 3707 u32 rawclk; 3708 3709 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3710 /* 24 MHz */ 3711 divider = 24000; 3712 fraction = 0; 3713 } else { 3714 /* 19.2 MHz */ 3715 divider = 19000; 3716 fraction = 200; 3717 } 3718 3719 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3720 if (fraction) { 3721 int numerator = 1; 3722 3723 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3724 fraction) - 1); 3725 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 3726 rawclk |= ICP_RAWCLK_NUM(numerator); 3727 } 3728 3729 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); 3730 return divider + fraction; 3731 } 3732 3733 static int pch_rawclk(struct intel_display *display) 3734 { 3735 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3736 } 3737 3738 static int i9xx_hrawclk(struct intel_display *display) 3739 { 3740 /* hrawclock is 1/4 the FSB frequency */ 3741 return DIV_ROUND_CLOSEST(intel_fsb_freq(display), 4); 3742 } 3743 3744 /** 3745 * intel_read_rawclk - Determine the current RAWCLK frequency 3746 * @display: display instance 3747 * 3748 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3749 * frequency clock so this needs to done only once. 3750 */ 3751 u32 intel_read_rawclk(struct intel_display *display) 3752 { 3753 u32 freq; 3754 3755 if (INTEL_PCH_TYPE(display) >= PCH_MTL) 3756 /* 3757 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3758 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3759 * not need to be programmed." 3760 */ 3761 freq = 38400; 3762 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 3763 freq = dg1_rawclk(display); 3764 else if (INTEL_PCH_TYPE(display) >= PCH_CNP) 3765 freq = cnp_rawclk(display); 3766 else if (HAS_PCH_SPLIT(display)) 3767 freq = pch_rawclk(display); 3768 else if (display->platform.valleyview || display->platform.cherryview) 3769 freq = vlv_clock_get_hrawclk(display->drm); 3770 else if (DISPLAY_VER(display) >= 3) 3771 freq = i9xx_hrawclk(display); 3772 else 3773 /* no rawclk on other platforms, or no need to know it */ 3774 return 0; 3775 3776 return freq; 3777 } 3778 3779 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3780 { 3781 struct intel_display *display = m->private; 3782 3783 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); 3784 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); 3785 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); 3786 3787 return 0; 3788 } 3789 3790 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3791 3792 void intel_cdclk_debugfs_register(struct intel_display *display) 3793 { 3794 debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root, 3795 display, &i915_cdclk_info_fops); 3796 } 3797 3798 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { 3799 .get_cdclk = bxt_get_cdclk, 3800 .set_cdclk = bxt_set_cdclk, 3801 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3802 .calc_voltage_level = xe3lpd_calc_voltage_level, 3803 }; 3804 3805 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3806 .get_cdclk = bxt_get_cdclk, 3807 .set_cdclk = bxt_set_cdclk, 3808 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3809 .calc_voltage_level = rplu_calc_voltage_level, 3810 }; 3811 3812 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3813 .get_cdclk = bxt_get_cdclk, 3814 .set_cdclk = bxt_set_cdclk, 3815 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3816 .calc_voltage_level = tgl_calc_voltage_level, 3817 }; 3818 3819 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3820 .get_cdclk = bxt_get_cdclk, 3821 .set_cdclk = bxt_set_cdclk, 3822 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3823 .calc_voltage_level = ehl_calc_voltage_level, 3824 }; 3825 3826 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3827 .get_cdclk = bxt_get_cdclk, 3828 .set_cdclk = bxt_set_cdclk, 3829 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3830 .calc_voltage_level = icl_calc_voltage_level, 3831 }; 3832 3833 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3834 .get_cdclk = bxt_get_cdclk, 3835 .set_cdclk = bxt_set_cdclk, 3836 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3837 .calc_voltage_level = bxt_calc_voltage_level, 3838 }; 3839 3840 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3841 .get_cdclk = skl_get_cdclk, 3842 .set_cdclk = skl_set_cdclk, 3843 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3844 }; 3845 3846 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3847 .get_cdclk = bdw_get_cdclk, 3848 .set_cdclk = bdw_set_cdclk, 3849 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3850 }; 3851 3852 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3853 .get_cdclk = vlv_get_cdclk, 3854 .set_cdclk = chv_set_cdclk, 3855 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3856 }; 3857 3858 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3859 .get_cdclk = vlv_get_cdclk, 3860 .set_cdclk = vlv_set_cdclk, 3861 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3862 }; 3863 3864 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3865 .get_cdclk = hsw_get_cdclk, 3866 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3867 }; 3868 3869 /* SNB, IVB, 965G, 945G */ 3870 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3871 .get_cdclk = fixed_400mhz_get_cdclk, 3872 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3873 }; 3874 3875 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3876 .get_cdclk = fixed_450mhz_get_cdclk, 3877 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3878 }; 3879 3880 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3881 .get_cdclk = gm45_get_cdclk, 3882 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3883 }; 3884 3885 /* G45 uses G33 */ 3886 3887 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3888 .get_cdclk = i965gm_get_cdclk, 3889 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3890 }; 3891 3892 /* i965G uses fixed 400 */ 3893 3894 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3895 .get_cdclk = pnv_get_cdclk, 3896 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3897 }; 3898 3899 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3900 .get_cdclk = g33_get_cdclk, 3901 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3902 }; 3903 3904 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3905 .get_cdclk = i945gm_get_cdclk, 3906 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3907 }; 3908 3909 /* i945G uses fixed 400 */ 3910 3911 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3912 .get_cdclk = i915gm_get_cdclk, 3913 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3914 }; 3915 3916 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3917 .get_cdclk = fixed_333mhz_get_cdclk, 3918 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3919 }; 3920 3921 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3922 .get_cdclk = fixed_266mhz_get_cdclk, 3923 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3924 }; 3925 3926 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3927 .get_cdclk = i85x_get_cdclk, 3928 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3929 }; 3930 3931 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3932 .get_cdclk = fixed_200mhz_get_cdclk, 3933 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3934 }; 3935 3936 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3937 .get_cdclk = fixed_133mhz_get_cdclk, 3938 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3939 }; 3940 3941 /** 3942 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3943 * @display: display instance 3944 */ 3945 void intel_init_cdclk_hooks(struct intel_display *display) 3946 { 3947 if (DISPLAY_VER(display) >= 35) { 3948 display->funcs.cdclk = &xe3lpd_cdclk_funcs; 3949 display->cdclk.table = xe3p_lpd_cdclk_table; 3950 } else if (DISPLAY_VER(display) >= 30) { 3951 display->funcs.cdclk = &xe3lpd_cdclk_funcs; 3952 display->cdclk.table = xe3lpd_cdclk_table; 3953 } else if (DISPLAY_VER(display) >= 20) { 3954 display->funcs.cdclk = &rplu_cdclk_funcs; 3955 display->cdclk.table = xe2lpd_cdclk_table; 3956 } else if (DISPLAY_VERx100(display) >= 1401) { 3957 display->funcs.cdclk = &rplu_cdclk_funcs; 3958 display->cdclk.table = xe2hpd_cdclk_table; 3959 } else if (DISPLAY_VER(display) >= 14) { 3960 display->funcs.cdclk = &rplu_cdclk_funcs; 3961 display->cdclk.table = mtl_cdclk_table; 3962 } else if (display->platform.dg2) { 3963 display->funcs.cdclk = &tgl_cdclk_funcs; 3964 display->cdclk.table = dg2_cdclk_table; 3965 } else if (display->platform.alderlake_p) { 3966 /* Wa_22011320316:adl-p[a0] */ 3967 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 3968 display->cdclk.table = adlp_a_step_cdclk_table; 3969 display->funcs.cdclk = &tgl_cdclk_funcs; 3970 } else if (display->platform.alderlake_p_raptorlake_u) { 3971 display->cdclk.table = rplu_cdclk_table; 3972 display->funcs.cdclk = &rplu_cdclk_funcs; 3973 } else { 3974 display->cdclk.table = adlp_cdclk_table; 3975 display->funcs.cdclk = &tgl_cdclk_funcs; 3976 } 3977 } else if (display->platform.rocketlake) { 3978 display->funcs.cdclk = &tgl_cdclk_funcs; 3979 display->cdclk.table = rkl_cdclk_table; 3980 } else if (DISPLAY_VER(display) >= 12) { 3981 display->funcs.cdclk = &tgl_cdclk_funcs; 3982 display->cdclk.table = icl_cdclk_table; 3983 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3984 display->funcs.cdclk = &ehl_cdclk_funcs; 3985 display->cdclk.table = icl_cdclk_table; 3986 } else if (DISPLAY_VER(display) >= 11) { 3987 display->funcs.cdclk = &icl_cdclk_funcs; 3988 display->cdclk.table = icl_cdclk_table; 3989 } else if (display->platform.geminilake || display->platform.broxton) { 3990 display->funcs.cdclk = &bxt_cdclk_funcs; 3991 if (display->platform.geminilake) 3992 display->cdclk.table = glk_cdclk_table; 3993 else 3994 display->cdclk.table = bxt_cdclk_table; 3995 } else if (DISPLAY_VER(display) == 9) { 3996 display->funcs.cdclk = &skl_cdclk_funcs; 3997 } else if (display->platform.broadwell) { 3998 display->funcs.cdclk = &bdw_cdclk_funcs; 3999 } else if (display->platform.haswell) { 4000 display->funcs.cdclk = &hsw_cdclk_funcs; 4001 } else if (display->platform.cherryview) { 4002 display->funcs.cdclk = &chv_cdclk_funcs; 4003 } else if (display->platform.valleyview) { 4004 display->funcs.cdclk = &vlv_cdclk_funcs; 4005 } else if (display->platform.sandybridge || display->platform.ivybridge) { 4006 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 4007 } else if (display->platform.ironlake) { 4008 display->funcs.cdclk = &ilk_cdclk_funcs; 4009 } else if (display->platform.gm45) { 4010 display->funcs.cdclk = &gm45_cdclk_funcs; 4011 } else if (display->platform.g45) { 4012 display->funcs.cdclk = &g33_cdclk_funcs; 4013 } else if (display->platform.i965gm) { 4014 display->funcs.cdclk = &i965gm_cdclk_funcs; 4015 } else if (display->platform.i965g) { 4016 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 4017 } else if (display->platform.pineview) { 4018 display->funcs.cdclk = &pnv_cdclk_funcs; 4019 } else if (display->platform.g33) { 4020 display->funcs.cdclk = &g33_cdclk_funcs; 4021 } else if (display->platform.i945gm) { 4022 display->funcs.cdclk = &i945gm_cdclk_funcs; 4023 } else if (display->platform.i945g) { 4024 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 4025 } else if (display->platform.i915gm) { 4026 display->funcs.cdclk = &i915gm_cdclk_funcs; 4027 } else if (display->platform.i915g) { 4028 display->funcs.cdclk = &i915g_cdclk_funcs; 4029 } else if (display->platform.i865g) { 4030 display->funcs.cdclk = &i865g_cdclk_funcs; 4031 } else if (display->platform.i85x) { 4032 display->funcs.cdclk = &i85x_cdclk_funcs; 4033 } else if (display->platform.i845g) { 4034 display->funcs.cdclk = &i845g_cdclk_funcs; 4035 } else if (display->platform.i830) { 4036 display->funcs.cdclk = &i830_cdclk_funcs; 4037 } 4038 4039 if (drm_WARN(display->drm, !display->funcs.cdclk, 4040 "Unknown platform. Assuming i830\n")) 4041 display->funcs.cdclk = &i830_cdclk_funcs; 4042 } 4043 4044 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state) 4045 { 4046 return cdclk_state->logical.cdclk; 4047 } 4048 4049 int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state) 4050 { 4051 return cdclk_state->actual.cdclk; 4052 } 4053 4054 int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state) 4055 { 4056 return cdclk_state->actual.voltage_level; 4057 } 4058 4059 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe) 4060 { 4061 return cdclk_state->min_cdclk[pipe]; 4062 } 4063 4064 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state) 4065 { 4066 const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state; 4067 4068 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 4069 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 4070 4071 if (new_cdclk_state && 4072 (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk || 4073 new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level)) 4074 return true; 4075 4076 return false; 4077 } 4078 4079 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk) 4080 { 4081 cdclk_state->force_min_cdclk = force_min_cdclk; 4082 } 4083 4084 void intel_cdclk_read_hw(struct intel_display *display) 4085 { 4086 struct intel_cdclk_state *cdclk_state; 4087 4088 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); 4089 4090 intel_update_cdclk(display); 4091 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 4092 cdclk_state->actual = display->cdclk.hw; 4093 cdclk_state->logical = display->cdclk.hw; 4094 } 4095 4096 static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk) 4097 { 4098 struct intel_display *display = to_intel_display(crtc_state); 4099 4100 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) { 4101 return bxt_calc_cdclk(display, min_cdclk); 4102 } else if (DISPLAY_VER(display) == 9) { 4103 int vco; 4104 4105 vco = display->cdclk.skl_preferred_vco_freq; 4106 if (vco == 0) 4107 vco = 8100000; 4108 4109 return skl_calc_cdclk(min_cdclk, vco); 4110 } else if (display->platform.broadwell) { 4111 return bdw_calc_cdclk(min_cdclk); 4112 } else if (display->platform.cherryview || display->platform.valleyview) { 4113 return vlv_calc_cdclk(display, min_cdclk); 4114 } else { 4115 return display->cdclk.max_cdclk_freq; 4116 } 4117 } 4118 4119 static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc_state, 4120 int clock, int min_cdclk) 4121 { 4122 struct intel_display *display = to_intel_display(crtc_state); 4123 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 4124 int cdclk = calc_cdclk(crtc_state, min_cdclk); 4125 4126 return min(0x10000, DIV_ROUND_UP_ULL((u64)clock << 16, ppc * cdclk)); 4127 } 4128 4129 unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) 4130 { 4131 /* FIXME use the actual min_cdclk for the pipe here */ 4132 return intel_cdclk_prefill_adjustment_worst(crtc_state); 4133 } 4134 4135 unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state) 4136 { 4137 int clock = crtc_state->hw.pipe_mode.crtc_clock; 4138 int min_cdclk; 4139 4140 /* 4141 * FIXME could perhaps consider a few more of the factors 4142 * that go the per-crtc min_cdclk. Namely anything that 4143 * only changes during full modesets. 4144 * 4145 * FIXME this assumes 1:1 scaling, but the other _worst() stuff 4146 * assumes max downscaling, so the final result will be 4147 * unrealistically bad. Figure out where the actual maximum value 4148 * lies and use that to compute a more realistic worst case 4149 * estimate... 4150 */ 4151 min_cdclk = _intel_pixel_rate_to_cdclk(crtc_state, clock); 4152 4153 return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk); 4154 } 4155 4156 int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state, 4157 unsigned int prefill_lines_unadjusted, 4158 unsigned int prefill_lines_available) 4159 { 4160 struct intel_display *display = to_intel_display(crtc_state); 4161 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 4162 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 4163 4164 return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted), 4165 ppc * prefill_lines_available); 4166 } 4167