1 /* 2 * Copyright © 2006-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/debugfs.h> 25 #include <linux/time.h> 26 27 #include <drm/drm_fixed.h> 28 29 #include "soc/intel_dram.h" 30 31 #include "hsw_ips.h" 32 #include "i915_drv.h" 33 #include "i915_reg.h" 34 #include "intel_atomic.h" 35 #include "intel_audio.h" 36 #include "intel_bw.h" 37 #include "intel_cdclk.h" 38 #include "intel_crtc.h" 39 #include "intel_de.h" 40 #include "intel_display_regs.h" 41 #include "intel_display_types.h" 42 #include "intel_mchbar_regs.h" 43 #include "intel_pci_config.h" 44 #include "intel_pcode.h" 45 #include "intel_plane.h" 46 #include "intel_psr.h" 47 #include "intel_vdsc.h" 48 #include "skl_watermark.h" 49 #include "skl_watermark_regs.h" 50 #include "vlv_dsi.h" 51 #include "vlv_sideband.h" 52 53 /** 54 * DOC: CDCLK / RAWCLK 55 * 56 * The display engine uses several different clocks to do its work. There 57 * are two main clocks involved that aren't directly related to the actual 58 * pixel clock or any symbol/bit clock of the actual output port. These 59 * are the core display clock (CDCLK) and RAWCLK. 60 * 61 * CDCLK clocks most of the display pipe logic, and thus its frequency 62 * must be high enough to support the rate at which pixels are flowing 63 * through the pipes. Downscaling must also be accounted as that increases 64 * the effective pixel rate. 65 * 66 * On several platforms the CDCLK frequency can be changed dynamically 67 * to minimize power consumption for a given display configuration. 68 * Typically changes to the CDCLK frequency require all the display pipes 69 * to be shut down while the frequency is being changed. 70 * 71 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit. 72 * DMC will not change the active CDCLK frequency however, so that part 73 * will still be performed by the driver directly. 74 * 75 * There are multiple components involved in the generation of the CDCLK 76 * frequency: 77 * 78 * - We have the CDCLK PLL, which generates an output clock based on a 79 * reference clock and a ratio parameter. 80 * - The CD2X Divider, which divides the output of the PLL based on a 81 * divisor selected from a set of pre-defined choices. 82 * - The CD2X Squasher, which further divides the output based on a 83 * waveform represented as a sequence of bits where each zero 84 * "squashes out" a clock cycle. 85 * - And, finally, a fixed divider that divides the output frequency by 2. 86 * 87 * As such, the resulting CDCLK frequency can be calculated with the 88 * following formula: 89 * 90 * cdclk = vco / cd2x_div / (sq_len / sq_div) / 2 91 * 92 * , where vco is the frequency generated by the PLL; cd2x_div 93 * represents the CD2X Divider; sq_len and sq_div are the bit length 94 * and the number of high bits for the CD2X Squasher waveform, respectively; 95 * and 2 represents the fixed divider. 96 * 97 * Note that some older platforms do not contain the CD2X Divider 98 * and/or CD2X Squasher, in which case we can ignore their respective 99 * factors in the formula above. 100 * 101 * Several methods exist to change the CDCLK frequency, which ones are 102 * supported depends on the platform: 103 * 104 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive. 105 * - CD2X divider update. Single pipe can be active as the divider update 106 * can be synchronized with the pipe's start of vblank. 107 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active. 108 * - Squash waveform update. Pipes can be active. 109 * - Crawl and squash can also be done back to back. Pipes can be active. 110 * 111 * RAWCLK is a fixed frequency clock, often used by various auxiliary 112 * blocks such as AUX CH or backlight PWM. Hence the only thing we 113 * really need to know about RAWCLK is its frequency so that various 114 * dividers can be programmed correctly. 115 */ 116 117 struct intel_cdclk_state { 118 struct intel_global_state base; 119 120 /* 121 * Logical configuration of cdclk (used for all scaling, 122 * watermark, etc. calculations and checks). This is 123 * computed as if all enabled crtcs were active. 124 */ 125 struct intel_cdclk_config logical; 126 127 /* 128 * Actual configuration of cdclk, can be different from the 129 * logical configuration only when all crtc's are DPMS off. 130 */ 131 struct intel_cdclk_config actual; 132 133 /* minimum acceptable cdclk to satisfy bandwidth requirements */ 134 int bw_min_cdclk; 135 /* minimum acceptable cdclk for each pipe */ 136 int min_cdclk[I915_MAX_PIPES]; 137 /* minimum acceptable voltage level for each pipe */ 138 u8 min_voltage_level[I915_MAX_PIPES]; 139 140 /* pipe to which cd2x update is synchronized */ 141 enum pipe pipe; 142 143 /* forced minimum cdclk for glk+ audio w/a */ 144 int force_min_cdclk; 145 146 /* bitmask of active pipes */ 147 u8 active_pipes; 148 149 /* update cdclk with pipes disabled */ 150 bool disable_pipes; 151 }; 152 153 struct intel_cdclk_funcs { 154 void (*get_cdclk)(struct intel_display *display, 155 struct intel_cdclk_config *cdclk_config); 156 void (*set_cdclk)(struct intel_display *display, 157 const struct intel_cdclk_config *cdclk_config, 158 enum pipe pipe); 159 int (*modeset_calc_cdclk)(struct intel_atomic_state *state); 160 u8 (*calc_voltage_level)(int cdclk); 161 }; 162 163 void intel_cdclk_get_cdclk(struct intel_display *display, 164 struct intel_cdclk_config *cdclk_config) 165 { 166 display->funcs.cdclk->get_cdclk(display, cdclk_config); 167 } 168 169 static void intel_cdclk_set_cdclk(struct intel_display *display, 170 const struct intel_cdclk_config *cdclk_config, 171 enum pipe pipe) 172 { 173 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); 174 } 175 176 static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) 177 { 178 struct intel_display *display = to_intel_display(state); 179 180 return display->funcs.cdclk->modeset_calc_cdclk(state); 181 } 182 183 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, 184 int cdclk) 185 { 186 return display->funcs.cdclk->calc_voltage_level(cdclk); 187 } 188 189 static void fixed_133mhz_get_cdclk(struct intel_display *display, 190 struct intel_cdclk_config *cdclk_config) 191 { 192 cdclk_config->cdclk = 133333; 193 } 194 195 static void fixed_200mhz_get_cdclk(struct intel_display *display, 196 struct intel_cdclk_config *cdclk_config) 197 { 198 cdclk_config->cdclk = 200000; 199 } 200 201 static void fixed_266mhz_get_cdclk(struct intel_display *display, 202 struct intel_cdclk_config *cdclk_config) 203 { 204 cdclk_config->cdclk = 266667; 205 } 206 207 static void fixed_333mhz_get_cdclk(struct intel_display *display, 208 struct intel_cdclk_config *cdclk_config) 209 { 210 cdclk_config->cdclk = 333333; 211 } 212 213 static void fixed_400mhz_get_cdclk(struct intel_display *display, 214 struct intel_cdclk_config *cdclk_config) 215 { 216 cdclk_config->cdclk = 400000; 217 } 218 219 static void fixed_450mhz_get_cdclk(struct intel_display *display, 220 struct intel_cdclk_config *cdclk_config) 221 { 222 cdclk_config->cdclk = 450000; 223 } 224 225 static void i85x_get_cdclk(struct intel_display *display, 226 struct intel_cdclk_config *cdclk_config) 227 { 228 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 229 u16 hpllcc = 0; 230 231 /* 232 * 852GM/852GMV only supports 133 MHz and the HPLLCC 233 * encoding is different :( 234 * FIXME is this the right way to detect 852GM/852GMV? 235 */ 236 if (pdev->revision == 0x1) { 237 cdclk_config->cdclk = 133333; 238 return; 239 } 240 241 pci_bus_read_config_word(pdev->bus, 242 PCI_DEVFN(0, 3), HPLLCC, &hpllcc); 243 244 /* Assume that the hardware is in the high speed state. This 245 * should be the default. 246 */ 247 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 248 case GC_CLOCK_133_200: 249 case GC_CLOCK_133_200_2: 250 case GC_CLOCK_100_200: 251 cdclk_config->cdclk = 200000; 252 break; 253 case GC_CLOCK_166_250: 254 cdclk_config->cdclk = 250000; 255 break; 256 case GC_CLOCK_100_133: 257 cdclk_config->cdclk = 133333; 258 break; 259 case GC_CLOCK_133_266: 260 case GC_CLOCK_133_266_2: 261 case GC_CLOCK_166_266: 262 cdclk_config->cdclk = 266667; 263 break; 264 } 265 } 266 267 static void i915gm_get_cdclk(struct intel_display *display, 268 struct intel_cdclk_config *cdclk_config) 269 { 270 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 271 u16 gcfgc = 0; 272 273 pci_read_config_word(pdev, GCFGC, &gcfgc); 274 275 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 276 cdclk_config->cdclk = 133333; 277 return; 278 } 279 280 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 281 case GC_DISPLAY_CLOCK_333_320_MHZ: 282 cdclk_config->cdclk = 333333; 283 break; 284 default: 285 case GC_DISPLAY_CLOCK_190_200_MHZ: 286 cdclk_config->cdclk = 190000; 287 break; 288 } 289 } 290 291 static void i945gm_get_cdclk(struct intel_display *display, 292 struct intel_cdclk_config *cdclk_config) 293 { 294 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 295 u16 gcfgc = 0; 296 297 pci_read_config_word(pdev, GCFGC, &gcfgc); 298 299 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { 300 cdclk_config->cdclk = 133333; 301 return; 302 } 303 304 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 305 case GC_DISPLAY_CLOCK_333_320_MHZ: 306 cdclk_config->cdclk = 320000; 307 break; 308 default: 309 case GC_DISPLAY_CLOCK_190_200_MHZ: 310 cdclk_config->cdclk = 200000; 311 break; 312 } 313 } 314 315 static unsigned int intel_hpll_vco(struct intel_display *display) 316 { 317 static const unsigned int blb_vco[8] = { 318 [0] = 3200000, 319 [1] = 4000000, 320 [2] = 5333333, 321 [3] = 4800000, 322 [4] = 6400000, 323 }; 324 static const unsigned int pnv_vco[8] = { 325 [0] = 3200000, 326 [1] = 4000000, 327 [2] = 5333333, 328 [3] = 4800000, 329 [4] = 2666667, 330 }; 331 static const unsigned int cl_vco[8] = { 332 [0] = 3200000, 333 [1] = 4000000, 334 [2] = 5333333, 335 [3] = 6400000, 336 [4] = 3333333, 337 [5] = 3566667, 338 [6] = 4266667, 339 }; 340 static const unsigned int elk_vco[8] = { 341 [0] = 3200000, 342 [1] = 4000000, 343 [2] = 5333333, 344 [3] = 4800000, 345 }; 346 static const unsigned int ctg_vco[8] = { 347 [0] = 3200000, 348 [1] = 4000000, 349 [2] = 5333333, 350 [3] = 6400000, 351 [4] = 2666667, 352 [5] = 4266667, 353 }; 354 const unsigned int *vco_table; 355 unsigned int vco; 356 u8 tmp = 0; 357 358 /* FIXME other chipsets? */ 359 if (display->platform.gm45) 360 vco_table = ctg_vco; 361 else if (display->platform.g45) 362 vco_table = elk_vco; 363 else if (display->platform.i965gm) 364 vco_table = cl_vco; 365 else if (display->platform.pineview) 366 vco_table = pnv_vco; 367 else if (display->platform.g33) 368 vco_table = blb_vco; 369 else 370 return 0; 371 372 tmp = intel_de_read(display, display->platform.pineview || 373 display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); 374 375 vco = vco_table[tmp & 0x7]; 376 if (vco == 0) 377 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", 378 tmp); 379 else 380 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); 381 382 return vco; 383 } 384 385 static void g33_get_cdclk(struct intel_display *display, 386 struct intel_cdclk_config *cdclk_config) 387 { 388 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 389 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; 390 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; 391 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; 392 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 }; 393 const u8 *div_table; 394 unsigned int cdclk_sel; 395 u16 tmp = 0; 396 397 cdclk_config->vco = intel_hpll_vco(display); 398 399 pci_read_config_word(pdev, GCFGC, &tmp); 400 401 cdclk_sel = (tmp >> 4) & 0x7; 402 403 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 404 goto fail; 405 406 switch (cdclk_config->vco) { 407 case 3200000: 408 div_table = div_3200; 409 break; 410 case 4000000: 411 div_table = div_4000; 412 break; 413 case 4800000: 414 div_table = div_4800; 415 break; 416 case 5333333: 417 div_table = div_5333; 418 break; 419 default: 420 goto fail; 421 } 422 423 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 424 div_table[cdclk_sel]); 425 return; 426 427 fail: 428 drm_err(display->drm, 429 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", 430 cdclk_config->vco, tmp); 431 cdclk_config->cdclk = 190476; 432 } 433 434 static void pnv_get_cdclk(struct intel_display *display, 435 struct intel_cdclk_config *cdclk_config) 436 { 437 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 438 u16 gcfgc = 0; 439 440 pci_read_config_word(pdev, GCFGC, &gcfgc); 441 442 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 443 case GC_DISPLAY_CLOCK_267_MHZ_PNV: 444 cdclk_config->cdclk = 266667; 445 break; 446 case GC_DISPLAY_CLOCK_333_MHZ_PNV: 447 cdclk_config->cdclk = 333333; 448 break; 449 case GC_DISPLAY_CLOCK_444_MHZ_PNV: 450 cdclk_config->cdclk = 444444; 451 break; 452 case GC_DISPLAY_CLOCK_200_MHZ_PNV: 453 cdclk_config->cdclk = 200000; 454 break; 455 default: 456 drm_err(display->drm, 457 "Unknown pnv display core clock 0x%04x\n", gcfgc); 458 fallthrough; 459 case GC_DISPLAY_CLOCK_133_MHZ_PNV: 460 cdclk_config->cdclk = 133333; 461 break; 462 case GC_DISPLAY_CLOCK_167_MHZ_PNV: 463 cdclk_config->cdclk = 166667; 464 break; 465 } 466 } 467 468 static void i965gm_get_cdclk(struct intel_display *display, 469 struct intel_cdclk_config *cdclk_config) 470 { 471 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 472 static const u8 div_3200[] = { 16, 10, 8 }; 473 static const u8 div_4000[] = { 20, 12, 10 }; 474 static const u8 div_5333[] = { 24, 16, 14 }; 475 const u8 *div_table; 476 unsigned int cdclk_sel; 477 u16 tmp = 0; 478 479 cdclk_config->vco = intel_hpll_vco(display); 480 481 pci_read_config_word(pdev, GCFGC, &tmp); 482 483 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; 484 485 if (cdclk_sel >= ARRAY_SIZE(div_3200)) 486 goto fail; 487 488 switch (cdclk_config->vco) { 489 case 3200000: 490 div_table = div_3200; 491 break; 492 case 4000000: 493 div_table = div_4000; 494 break; 495 case 5333333: 496 div_table = div_5333; 497 break; 498 default: 499 goto fail; 500 } 501 502 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, 503 div_table[cdclk_sel]); 504 return; 505 506 fail: 507 drm_err(display->drm, 508 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", 509 cdclk_config->vco, tmp); 510 cdclk_config->cdclk = 200000; 511 } 512 513 static void gm45_get_cdclk(struct intel_display *display, 514 struct intel_cdclk_config *cdclk_config) 515 { 516 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 517 unsigned int cdclk_sel; 518 u16 tmp = 0; 519 520 cdclk_config->vco = intel_hpll_vco(display); 521 522 pci_read_config_word(pdev, GCFGC, &tmp); 523 524 cdclk_sel = (tmp >> 12) & 0x1; 525 526 switch (cdclk_config->vco) { 527 case 2666667: 528 case 4000000: 529 case 5333333: 530 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; 531 break; 532 case 3200000: 533 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; 534 break; 535 default: 536 drm_err(display->drm, 537 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", 538 cdclk_config->vco, tmp); 539 cdclk_config->cdclk = 222222; 540 break; 541 } 542 } 543 544 static void hsw_get_cdclk(struct intel_display *display, 545 struct intel_cdclk_config *cdclk_config) 546 { 547 u32 lcpll = intel_de_read(display, LCPLL_CTL); 548 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 549 550 if (lcpll & LCPLL_CD_SOURCE_FCLK) 551 cdclk_config->cdclk = 800000; 552 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 553 cdclk_config->cdclk = 450000; 554 else if (freq == LCPLL_CLK_FREQ_450) 555 cdclk_config->cdclk = 450000; 556 else if (display->platform.haswell_ult) 557 cdclk_config->cdclk = 337500; 558 else 559 cdclk_config->cdclk = 540000; 560 } 561 562 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) 563 { 564 struct drm_i915_private *dev_priv = to_i915(display->drm); 565 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 566 333333 : 320000; 567 568 /* 569 * We seem to get an unstable or solid color picture at 200MHz. 570 * Not sure what's wrong. For now use 200MHz only when all pipes 571 * are off. 572 */ 573 if (display->platform.valleyview && min_cdclk > freq_320) 574 return 400000; 575 else if (min_cdclk > 266667) 576 return freq_320; 577 else if (min_cdclk > 0) 578 return 266667; 579 else 580 return 200000; 581 } 582 583 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) 584 { 585 struct drm_i915_private *dev_priv = to_i915(display->drm); 586 587 if (display->platform.valleyview) { 588 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ 589 return 2; 590 else if (cdclk >= 266667) 591 return 1; 592 else 593 return 0; 594 } else { 595 /* 596 * Specs are full of misinformation, but testing on actual 597 * hardware has shown that we just need to write the desired 598 * CCK divider into the Punit register. 599 */ 600 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; 601 } 602 } 603 604 static void vlv_get_cdclk(struct intel_display *display, 605 struct intel_cdclk_config *cdclk_config) 606 { 607 u32 val; 608 609 vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 610 611 cdclk_config->vco = vlv_get_hpll_vco(display->drm); 612 cdclk_config->cdclk = vlv_get_cck_clock(display->drm, "cdclk", 613 CCK_DISPLAY_CLOCK_CONTROL, 614 cdclk_config->vco); 615 616 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 617 618 vlv_iosf_sb_put(display->drm, 619 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); 620 621 if (display->platform.valleyview) 622 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> 623 DSPFREQGUAR_SHIFT; 624 else 625 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> 626 DSPFREQGUAR_SHIFT_CHV; 627 } 628 629 static void vlv_program_pfi_credits(struct intel_display *display) 630 { 631 struct drm_i915_private *dev_priv = to_i915(display->drm); 632 unsigned int credits, default_credits; 633 634 if (display->platform.cherryview) 635 default_credits = PFI_CREDIT(12); 636 else 637 default_credits = PFI_CREDIT(8); 638 639 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { 640 /* CHV suggested value is 31 or 63 */ 641 if (display->platform.cherryview) 642 credits = PFI_CREDIT_63; 643 else 644 credits = PFI_CREDIT(15); 645 } else { 646 credits = default_credits; 647 } 648 649 /* 650 * WA - write default credits before re-programming 651 * FIXME: should we also set the resend bit here? 652 */ 653 intel_de_write(display, GCI_CONTROL, 654 VGA_FAST_MODE_DISABLE | default_credits); 655 656 intel_de_write(display, GCI_CONTROL, 657 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); 658 659 /* 660 * FIXME is this guaranteed to clear 661 * immediately or should we poll for it? 662 */ 663 drm_WARN_ON(display->drm, 664 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); 665 } 666 667 static void vlv_set_cdclk(struct intel_display *display, 668 const struct intel_cdclk_config *cdclk_config, 669 enum pipe pipe) 670 { 671 struct drm_i915_private *dev_priv = to_i915(display->drm); 672 int cdclk = cdclk_config->cdclk; 673 u32 val, cmd = cdclk_config->voltage_level; 674 intel_wakeref_t wakeref; 675 676 switch (cdclk) { 677 case 400000: 678 case 333333: 679 case 320000: 680 case 266667: 681 case 200000: 682 break; 683 default: 684 MISSING_CASE(cdclk); 685 return; 686 } 687 688 /* There are cases where we can end up here with power domains 689 * off and a CDCLK frequency other than the minimum, like when 690 * issuing a modeset without actually changing any display after 691 * a system suspend. So grab the display core domain, which covers 692 * the HW blocks needed for the following programming. 693 */ 694 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 695 696 vlv_iosf_sb_get(display->drm, 697 BIT(VLV_IOSF_SB_CCK) | 698 BIT(VLV_IOSF_SB_BUNIT) | 699 BIT(VLV_IOSF_SB_PUNIT)); 700 701 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 702 val &= ~DSPFREQGUAR_MASK; 703 val |= (cmd << DSPFREQGUAR_SHIFT); 704 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); 705 if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & 706 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 707 50)) { 708 drm_err(display->drm, 709 "timed out waiting for CDclk change\n"); 710 } 711 712 if (cdclk == 400000) { 713 u32 divider; 714 715 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, 716 cdclk) - 1; 717 718 /* adjust cdclk divider */ 719 val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL); 720 val &= ~CCK_FREQUENCY_VALUES; 721 val |= divider; 722 vlv_cck_write(display->drm, CCK_DISPLAY_CLOCK_CONTROL, val); 723 724 if (wait_for((vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL) & 725 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 726 50)) 727 drm_err(display->drm, 728 "timed out waiting for CDclk change\n"); 729 } 730 731 /* adjust self-refresh exit latency value */ 732 val = vlv_bunit_read(display->drm, BUNIT_REG_BISOC); 733 val &= ~0x7f; 734 735 /* 736 * For high bandwidth configs, we set a higher latency in the bunit 737 * so that the core display fetch happens in time to avoid underruns. 738 */ 739 if (cdclk == 400000) 740 val |= 4500 / 250; /* 4.5 usec */ 741 else 742 val |= 3000 / 250; /* 3.0 usec */ 743 vlv_bunit_write(display->drm, BUNIT_REG_BISOC, val); 744 745 vlv_iosf_sb_put(display->drm, 746 BIT(VLV_IOSF_SB_CCK) | 747 BIT(VLV_IOSF_SB_BUNIT) | 748 BIT(VLV_IOSF_SB_PUNIT)); 749 750 intel_update_cdclk(display); 751 752 vlv_program_pfi_credits(display); 753 754 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 755 } 756 757 static void chv_set_cdclk(struct intel_display *display, 758 const struct intel_cdclk_config *cdclk_config, 759 enum pipe pipe) 760 { 761 int cdclk = cdclk_config->cdclk; 762 u32 val, cmd = cdclk_config->voltage_level; 763 intel_wakeref_t wakeref; 764 765 switch (cdclk) { 766 case 333333: 767 case 320000: 768 case 266667: 769 case 200000: 770 break; 771 default: 772 MISSING_CASE(cdclk); 773 return; 774 } 775 776 /* There are cases where we can end up here with power domains 777 * off and a CDCLK frequency other than the minimum, like when 778 * issuing a modeset without actually changing any display after 779 * a system suspend. So grab the display core domain, which covers 780 * the HW blocks needed for the following programming. 781 */ 782 wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); 783 784 vlv_punit_get(display->drm); 785 val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM); 786 val &= ~DSPFREQGUAR_MASK_CHV; 787 val |= (cmd << DSPFREQGUAR_SHIFT_CHV); 788 vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, val); 789 if (wait_for((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & 790 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 791 50)) { 792 drm_err(display->drm, 793 "timed out waiting for CDclk change\n"); 794 } 795 796 vlv_punit_put(display->drm); 797 798 intel_update_cdclk(display); 799 800 vlv_program_pfi_credits(display); 801 802 intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); 803 } 804 805 static int bdw_calc_cdclk(int min_cdclk) 806 { 807 if (min_cdclk > 540000) 808 return 675000; 809 else if (min_cdclk > 450000) 810 return 540000; 811 else if (min_cdclk > 337500) 812 return 450000; 813 else 814 return 337500; 815 } 816 817 static u8 bdw_calc_voltage_level(int cdclk) 818 { 819 switch (cdclk) { 820 default: 821 case 337500: 822 return 2; 823 case 450000: 824 return 0; 825 case 540000: 826 return 1; 827 case 675000: 828 return 3; 829 } 830 } 831 832 static void bdw_get_cdclk(struct intel_display *display, 833 struct intel_cdclk_config *cdclk_config) 834 { 835 u32 lcpll = intel_de_read(display, LCPLL_CTL); 836 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; 837 838 if (lcpll & LCPLL_CD_SOURCE_FCLK) 839 cdclk_config->cdclk = 800000; 840 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 841 cdclk_config->cdclk = 450000; 842 else if (freq == LCPLL_CLK_FREQ_450) 843 cdclk_config->cdclk = 450000; 844 else if (freq == LCPLL_CLK_FREQ_54O_BDW) 845 cdclk_config->cdclk = 540000; 846 else if (freq == LCPLL_CLK_FREQ_337_5_BDW) 847 cdclk_config->cdclk = 337500; 848 else 849 cdclk_config->cdclk = 675000; 850 851 /* 852 * Can't read this out :( Let's assume it's 853 * at least what the CDCLK frequency requires. 854 */ 855 cdclk_config->voltage_level = 856 bdw_calc_voltage_level(cdclk_config->cdclk); 857 } 858 859 static u32 bdw_cdclk_freq_sel(int cdclk) 860 { 861 switch (cdclk) { 862 default: 863 MISSING_CASE(cdclk); 864 fallthrough; 865 case 337500: 866 return LCPLL_CLK_FREQ_337_5_BDW; 867 case 450000: 868 return LCPLL_CLK_FREQ_450; 869 case 540000: 870 return LCPLL_CLK_FREQ_54O_BDW; 871 case 675000: 872 return LCPLL_CLK_FREQ_675_BDW; 873 } 874 } 875 876 static void bdw_set_cdclk(struct intel_display *display, 877 const struct intel_cdclk_config *cdclk_config, 878 enum pipe pipe) 879 { 880 int cdclk = cdclk_config->cdclk; 881 int ret; 882 883 if (drm_WARN(display->drm, 884 (intel_de_read(display, LCPLL_CTL) & 885 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | 886 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | 887 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | 888 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, 889 "trying to change cdclk frequency with cdclk not enabled\n")) 890 return; 891 892 ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); 893 if (ret) { 894 drm_err(display->drm, 895 "failed to inform pcode about cdclk change\n"); 896 return; 897 } 898 899 intel_de_rmw(display, LCPLL_CTL, 900 0, LCPLL_CD_SOURCE_FCLK); 901 902 /* 903 * According to the spec, it should be enough to poll for this 1 us. 904 * However, extensive testing shows that this can take longer. 905 */ 906 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & 907 LCPLL_CD_SOURCE_FCLK_DONE, 100)) 908 drm_err(display->drm, "Switching to FCLK failed\n"); 909 910 intel_de_rmw(display, LCPLL_CTL, 911 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); 912 913 intel_de_rmw(display, LCPLL_CTL, 914 LCPLL_CD_SOURCE_FCLK, 0); 915 916 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & 917 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 918 drm_err(display->drm, "Switching back to LCPLL failed\n"); 919 920 intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ, 921 cdclk_config->voltage_level); 922 923 intel_de_write(display, CDCLK_FREQ, 924 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); 925 926 intel_update_cdclk(display); 927 } 928 929 static int skl_calc_cdclk(int min_cdclk, int vco) 930 { 931 if (vco == 8640000) { 932 if (min_cdclk > 540000) 933 return 617143; 934 else if (min_cdclk > 432000) 935 return 540000; 936 else if (min_cdclk > 308571) 937 return 432000; 938 else 939 return 308571; 940 } else { 941 if (min_cdclk > 540000) 942 return 675000; 943 else if (min_cdclk > 450000) 944 return 540000; 945 else if (min_cdclk > 337500) 946 return 450000; 947 else 948 return 337500; 949 } 950 } 951 952 static u8 skl_calc_voltage_level(int cdclk) 953 { 954 if (cdclk > 540000) 955 return 3; 956 else if (cdclk > 450000) 957 return 2; 958 else if (cdclk > 337500) 959 return 1; 960 else 961 return 0; 962 } 963 964 static void skl_dpll0_update(struct intel_display *display, 965 struct intel_cdclk_config *cdclk_config) 966 { 967 u32 val; 968 969 cdclk_config->ref = 24000; 970 cdclk_config->vco = 0; 971 972 val = intel_de_read(display, LCPLL1_CTL); 973 if ((val & LCPLL_PLL_ENABLE) == 0) 974 return; 975 976 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) 977 return; 978 979 val = intel_de_read(display, DPLL_CTRL1); 980 981 if (drm_WARN_ON(display->drm, 982 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 983 DPLL_CTRL1_SSC(SKL_DPLL0) | 984 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != 985 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) 986 return; 987 988 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { 989 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): 990 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): 991 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): 992 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): 993 cdclk_config->vco = 8100000; 994 break; 995 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): 996 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): 997 cdclk_config->vco = 8640000; 998 break; 999 default: 1000 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); 1001 break; 1002 } 1003 } 1004 1005 static void skl_get_cdclk(struct intel_display *display, 1006 struct intel_cdclk_config *cdclk_config) 1007 { 1008 u32 cdctl; 1009 1010 skl_dpll0_update(display, cdclk_config); 1011 1012 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; 1013 1014 if (cdclk_config->vco == 0) 1015 goto out; 1016 1017 cdctl = intel_de_read(display, CDCLK_CTL); 1018 1019 if (cdclk_config->vco == 8640000) { 1020 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1021 case CDCLK_FREQ_450_432: 1022 cdclk_config->cdclk = 432000; 1023 break; 1024 case CDCLK_FREQ_337_308: 1025 cdclk_config->cdclk = 308571; 1026 break; 1027 case CDCLK_FREQ_540: 1028 cdclk_config->cdclk = 540000; 1029 break; 1030 case CDCLK_FREQ_675_617: 1031 cdclk_config->cdclk = 617143; 1032 break; 1033 default: 1034 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1035 break; 1036 } 1037 } else { 1038 switch (cdctl & CDCLK_FREQ_SEL_MASK) { 1039 case CDCLK_FREQ_450_432: 1040 cdclk_config->cdclk = 450000; 1041 break; 1042 case CDCLK_FREQ_337_308: 1043 cdclk_config->cdclk = 337500; 1044 break; 1045 case CDCLK_FREQ_540: 1046 cdclk_config->cdclk = 540000; 1047 break; 1048 case CDCLK_FREQ_675_617: 1049 cdclk_config->cdclk = 675000; 1050 break; 1051 default: 1052 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); 1053 break; 1054 } 1055 } 1056 1057 out: 1058 /* 1059 * Can't read this out :( Let's assume it's 1060 * at least what the CDCLK frequency requires. 1061 */ 1062 cdclk_config->voltage_level = 1063 skl_calc_voltage_level(cdclk_config->cdclk); 1064 } 1065 1066 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ 1067 static int skl_cdclk_decimal(int cdclk) 1068 { 1069 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); 1070 } 1071 1072 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) 1073 { 1074 bool changed = display->cdclk.skl_preferred_vco_freq != vco; 1075 1076 display->cdclk.skl_preferred_vco_freq = vco; 1077 1078 if (changed) 1079 intel_update_max_cdclk(display); 1080 } 1081 1082 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) 1083 { 1084 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 1085 1086 /* 1087 * We always enable DPLL0 with the lowest link rate possible, but still 1088 * taking into account the VCO required to operate the eDP panel at the 1089 * desired frequency. The usual DP link rates operate with a VCO of 1090 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. 1091 * The modeset code is responsible for the selection of the exact link 1092 * rate later on, with the constraint of choosing a frequency that 1093 * works with vco. 1094 */ 1095 if (vco == 8640000) 1096 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0); 1097 else 1098 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); 1099 } 1100 1101 static void skl_dpll0_enable(struct intel_display *display, int vco) 1102 { 1103 intel_de_rmw(display, DPLL_CTRL1, 1104 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | 1105 DPLL_CTRL1_SSC(SKL_DPLL0) | 1106 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), 1107 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | 1108 skl_dpll0_link_rate(display, vco)); 1109 intel_de_posting_read(display, DPLL_CTRL1); 1110 1111 intel_de_rmw(display, LCPLL1_CTL, 1112 0, LCPLL_PLL_ENABLE); 1113 1114 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) 1115 drm_err(display->drm, "DPLL0 not locked\n"); 1116 1117 display->cdclk.hw.vco = vco; 1118 1119 /* We'll want to keep using the current vco from now on. */ 1120 skl_set_preferred_cdclk_vco(display, vco); 1121 } 1122 1123 static void skl_dpll0_disable(struct intel_display *display) 1124 { 1125 intel_de_rmw(display, LCPLL1_CTL, 1126 LCPLL_PLL_ENABLE, 0); 1127 1128 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) 1129 drm_err(display->drm, "Couldn't disable DPLL0\n"); 1130 1131 display->cdclk.hw.vco = 0; 1132 } 1133 1134 static u32 skl_cdclk_freq_sel(struct intel_display *display, 1135 int cdclk, int vco) 1136 { 1137 switch (cdclk) { 1138 default: 1139 drm_WARN_ON(display->drm, 1140 cdclk != display->cdclk.hw.bypass); 1141 drm_WARN_ON(display->drm, vco != 0); 1142 fallthrough; 1143 case 308571: 1144 case 337500: 1145 return CDCLK_FREQ_337_308; 1146 case 450000: 1147 case 432000: 1148 return CDCLK_FREQ_450_432; 1149 case 540000: 1150 return CDCLK_FREQ_540; 1151 case 617143: 1152 case 675000: 1153 return CDCLK_FREQ_675_617; 1154 } 1155 } 1156 1157 static void skl_set_cdclk(struct intel_display *display, 1158 const struct intel_cdclk_config *cdclk_config, 1159 enum pipe pipe) 1160 { 1161 int cdclk = cdclk_config->cdclk; 1162 int vco = cdclk_config->vco; 1163 u32 freq_select, cdclk_ctl; 1164 int ret; 1165 1166 /* 1167 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are 1168 * unsupported on SKL. In theory this should never happen since only 1169 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not 1170 * supported on SKL either, see the above WA. WARN whenever trying to 1171 * use the corresponding VCO freq as that always leads to using the 1172 * minimum 308MHz CDCLK. 1173 */ 1174 drm_WARN_ON_ONCE(display->drm, 1175 display->platform.skylake && vco == 8640000); 1176 1177 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 1178 SKL_CDCLK_PREPARE_FOR_CHANGE, 1179 SKL_CDCLK_READY_FOR_CHANGE, 1180 SKL_CDCLK_READY_FOR_CHANGE, 3); 1181 if (ret) { 1182 drm_err(display->drm, 1183 "Failed to inform PCU about cdclk change (%d)\n", ret); 1184 return; 1185 } 1186 1187 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); 1188 1189 if (display->cdclk.hw.vco != 0 && 1190 display->cdclk.hw.vco != vco) 1191 skl_dpll0_disable(display); 1192 1193 cdclk_ctl = intel_de_read(display, CDCLK_CTL); 1194 1195 if (display->cdclk.hw.vco != vco) { 1196 /* Wa Display #1183: skl,kbl,cfl */ 1197 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1198 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1199 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1200 } 1201 1202 /* Wa Display #1183: skl,kbl,cfl */ 1203 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; 1204 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1205 intel_de_posting_read(display, CDCLK_CTL); 1206 1207 if (display->cdclk.hw.vco != vco) 1208 skl_dpll0_enable(display, vco); 1209 1210 /* Wa Display #1183: skl,kbl,cfl */ 1211 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); 1212 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1213 1214 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); 1215 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1216 1217 /* Wa Display #1183: skl,kbl,cfl */ 1218 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; 1219 intel_de_write(display, CDCLK_CTL, cdclk_ctl); 1220 intel_de_posting_read(display, CDCLK_CTL); 1221 1222 /* inform PCU of the change */ 1223 intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, 1224 cdclk_config->voltage_level); 1225 1226 intel_update_cdclk(display); 1227 } 1228 1229 static void skl_sanitize_cdclk(struct intel_display *display) 1230 { 1231 u32 cdctl, expected; 1232 1233 /* 1234 * check if the pre-os initialized the display 1235 * There is SWF18 scratchpad register defined which is set by the 1236 * pre-os which can be used by the OS drivers to check the status 1237 */ 1238 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) 1239 goto sanitize; 1240 1241 intel_update_cdclk(display); 1242 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 1243 1244 /* Is PLL enabled and locked ? */ 1245 if (display->cdclk.hw.vco == 0 || 1246 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 1247 goto sanitize; 1248 1249 /* DPLL okay; verify the cdclock 1250 * 1251 * Noticed in some instances that the freq selection is correct but 1252 * decimal part is programmed wrong from BIOS where pre-os does not 1253 * enable display. Verify the same as well. 1254 */ 1255 cdctl = intel_de_read(display, CDCLK_CTL); 1256 expected = (cdctl & CDCLK_FREQ_SEL_MASK) | 1257 skl_cdclk_decimal(display->cdclk.hw.cdclk); 1258 if (cdctl == expected) 1259 /* All well; nothing to sanitize */ 1260 return; 1261 1262 sanitize: 1263 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 1264 1265 /* force cdclk programming */ 1266 display->cdclk.hw.cdclk = 0; 1267 /* force full PLL disable + enable */ 1268 display->cdclk.hw.vco = ~0; 1269 } 1270 1271 static void skl_cdclk_init_hw(struct intel_display *display) 1272 { 1273 struct intel_cdclk_config cdclk_config; 1274 1275 skl_sanitize_cdclk(display); 1276 1277 if (display->cdclk.hw.cdclk != 0 && 1278 display->cdclk.hw.vco != 0) { 1279 /* 1280 * Use the current vco as our initial 1281 * guess as to what the preferred vco is. 1282 */ 1283 if (display->cdclk.skl_preferred_vco_freq == 0) 1284 skl_set_preferred_cdclk_vco(display, 1285 display->cdclk.hw.vco); 1286 return; 1287 } 1288 1289 cdclk_config = display->cdclk.hw; 1290 1291 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; 1292 if (cdclk_config.vco == 0) 1293 cdclk_config.vco = 8100000; 1294 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); 1295 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1296 1297 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1298 } 1299 1300 static void skl_cdclk_uninit_hw(struct intel_display *display) 1301 { 1302 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 1303 1304 cdclk_config.cdclk = cdclk_config.bypass; 1305 cdclk_config.vco = 0; 1306 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); 1307 1308 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); 1309 } 1310 1311 struct intel_cdclk_vals { 1312 u32 cdclk; 1313 u16 refclk; 1314 u16 waveform; 1315 u8 ratio; 1316 }; 1317 1318 static const struct intel_cdclk_vals bxt_cdclk_table[] = { 1319 { .refclk = 19200, .cdclk = 144000, .ratio = 60 }, 1320 { .refclk = 19200, .cdclk = 288000, .ratio = 60 }, 1321 { .refclk = 19200, .cdclk = 384000, .ratio = 60 }, 1322 { .refclk = 19200, .cdclk = 576000, .ratio = 60 }, 1323 { .refclk = 19200, .cdclk = 624000, .ratio = 65 }, 1324 {} 1325 }; 1326 1327 static const struct intel_cdclk_vals glk_cdclk_table[] = { 1328 { .refclk = 19200, .cdclk = 79200, .ratio = 33 }, 1329 { .refclk = 19200, .cdclk = 158400, .ratio = 33 }, 1330 { .refclk = 19200, .cdclk = 316800, .ratio = 33 }, 1331 {} 1332 }; 1333 1334 static const struct intel_cdclk_vals icl_cdclk_table[] = { 1335 { .refclk = 19200, .cdclk = 172800, .ratio = 18 }, 1336 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1337 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1338 { .refclk = 19200, .cdclk = 326400, .ratio = 68 }, 1339 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1340 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1341 1342 { .refclk = 24000, .cdclk = 180000, .ratio = 15 }, 1343 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1344 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1345 { .refclk = 24000, .cdclk = 324000, .ratio = 54 }, 1346 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1347 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1348 1349 { .refclk = 38400, .cdclk = 172800, .ratio = 9 }, 1350 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1351 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1352 { .refclk = 38400, .cdclk = 326400, .ratio = 34 }, 1353 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1354 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1355 {} 1356 }; 1357 1358 static const struct intel_cdclk_vals rkl_cdclk_table[] = { 1359 { .refclk = 19200, .cdclk = 172800, .ratio = 36 }, 1360 { .refclk = 19200, .cdclk = 192000, .ratio = 40 }, 1361 { .refclk = 19200, .cdclk = 307200, .ratio = 64 }, 1362 { .refclk = 19200, .cdclk = 326400, .ratio = 136 }, 1363 { .refclk = 19200, .cdclk = 556800, .ratio = 116 }, 1364 { .refclk = 19200, .cdclk = 652800, .ratio = 136 }, 1365 1366 { .refclk = 24000, .cdclk = 180000, .ratio = 30 }, 1367 { .refclk = 24000, .cdclk = 192000, .ratio = 32 }, 1368 { .refclk = 24000, .cdclk = 312000, .ratio = 52 }, 1369 { .refclk = 24000, .cdclk = 324000, .ratio = 108 }, 1370 { .refclk = 24000, .cdclk = 552000, .ratio = 92 }, 1371 { .refclk = 24000, .cdclk = 648000, .ratio = 108 }, 1372 1373 { .refclk = 38400, .cdclk = 172800, .ratio = 18 }, 1374 { .refclk = 38400, .cdclk = 192000, .ratio = 20 }, 1375 { .refclk = 38400, .cdclk = 307200, .ratio = 32 }, 1376 { .refclk = 38400, .cdclk = 326400, .ratio = 68 }, 1377 { .refclk = 38400, .cdclk = 556800, .ratio = 58 }, 1378 { .refclk = 38400, .cdclk = 652800, .ratio = 68 }, 1379 {} 1380 }; 1381 1382 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = { 1383 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1384 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1385 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1386 1387 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1388 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1389 { .refclk = 24400, .cdclk = 648000, .ratio = 54 }, 1390 1391 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1392 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1393 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1394 {} 1395 }; 1396 1397 static const struct intel_cdclk_vals adlp_cdclk_table[] = { 1398 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1399 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1400 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1401 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1402 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1403 1404 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1405 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1406 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1407 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1408 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1409 1410 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1411 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1412 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1413 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1414 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1415 {} 1416 }; 1417 1418 static const struct intel_cdclk_vals rplu_cdclk_table[] = { 1419 { .refclk = 19200, .cdclk = 172800, .ratio = 27 }, 1420 { .refclk = 19200, .cdclk = 192000, .ratio = 20 }, 1421 { .refclk = 19200, .cdclk = 307200, .ratio = 32 }, 1422 { .refclk = 19200, .cdclk = 480000, .ratio = 50 }, 1423 { .refclk = 19200, .cdclk = 556800, .ratio = 58 }, 1424 { .refclk = 19200, .cdclk = 652800, .ratio = 68 }, 1425 1426 { .refclk = 24000, .cdclk = 176000, .ratio = 22 }, 1427 { .refclk = 24000, .cdclk = 192000, .ratio = 16 }, 1428 { .refclk = 24000, .cdclk = 312000, .ratio = 26 }, 1429 { .refclk = 24000, .cdclk = 480000, .ratio = 40 }, 1430 { .refclk = 24000, .cdclk = 552000, .ratio = 46 }, 1431 { .refclk = 24000, .cdclk = 648000, .ratio = 54 }, 1432 1433 { .refclk = 38400, .cdclk = 179200, .ratio = 14 }, 1434 { .refclk = 38400, .cdclk = 192000, .ratio = 10 }, 1435 { .refclk = 38400, .cdclk = 307200, .ratio = 16 }, 1436 { .refclk = 38400, .cdclk = 480000, .ratio = 25 }, 1437 { .refclk = 38400, .cdclk = 556800, .ratio = 29 }, 1438 { .refclk = 38400, .cdclk = 652800, .ratio = 34 }, 1439 {} 1440 }; 1441 1442 static const struct intel_cdclk_vals dg2_cdclk_table[] = { 1443 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 }, 1444 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 }, 1445 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 }, 1446 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a }, 1447 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa }, 1448 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a }, 1449 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 }, 1450 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 }, 1451 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee }, 1452 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de }, 1453 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1454 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1455 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1456 {} 1457 }; 1458 1459 static const struct intel_cdclk_vals mtl_cdclk_table[] = { 1460 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1461 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1462 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 }, 1463 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 }, 1464 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 }, 1465 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 }, 1466 {} 1467 }; 1468 1469 static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { 1470 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1471 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1472 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1473 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1474 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1475 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1476 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1477 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1478 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1479 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 }, 1480 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee }, 1481 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de }, 1482 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe }, 1483 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe }, 1484 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1485 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe }, 1486 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe }, 1487 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1488 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe }, 1489 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe }, 1490 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1491 {} 1492 }; 1493 1494 /* 1495 * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 1496 */ 1497 static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { 1498 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1499 {} 1500 }; 1501 1502 static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = { 1503 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa }, 1504 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a }, 1505 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 }, 1506 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 }, 1507 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee }, 1508 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de }, 1509 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe }, 1510 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe }, 1511 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff }, 1512 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff }, 1513 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff }, 1514 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff }, 1515 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff }, 1516 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, 1517 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, 1518 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, 1519 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, 1520 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, 1521 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, 1522 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, 1523 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, 1524 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, 1525 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, 1526 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, 1527 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, 1528 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, 1529 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, 1530 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, 1531 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, 1532 {} 1533 }; 1534 1535 static const int cdclk_squash_len = 16; 1536 1537 static int cdclk_squash_divider(u16 waveform) 1538 { 1539 return hweight16(waveform ?: 0xffff); 1540 } 1541 1542 static int cdclk_divider(int cdclk, int vco, u16 waveform) 1543 { 1544 /* 2 * cd2x divider */ 1545 return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform), 1546 cdclk * cdclk_squash_len); 1547 } 1548 1549 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) 1550 { 1551 const struct intel_cdclk_vals *table = display->cdclk.table; 1552 int i; 1553 1554 for (i = 0; table[i].refclk; i++) 1555 if (table[i].refclk == display->cdclk.hw.ref && 1556 table[i].cdclk >= min_cdclk) 1557 return table[i].cdclk; 1558 1559 drm_WARN(display->drm, 1, 1560 "Cannot satisfy minimum cdclk %d with refclk %u\n", 1561 min_cdclk, display->cdclk.hw.ref); 1562 return 0; 1563 } 1564 1565 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) 1566 { 1567 const struct intel_cdclk_vals *table = display->cdclk.table; 1568 int i; 1569 1570 if (cdclk == display->cdclk.hw.bypass) 1571 return 0; 1572 1573 for (i = 0; table[i].refclk; i++) 1574 if (table[i].refclk == display->cdclk.hw.ref && 1575 table[i].cdclk == cdclk) 1576 return display->cdclk.hw.ref * table[i].ratio; 1577 1578 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1579 cdclk, display->cdclk.hw.ref); 1580 return 0; 1581 } 1582 1583 static u8 bxt_calc_voltage_level(int cdclk) 1584 { 1585 return DIV_ROUND_UP(cdclk, 25000); 1586 } 1587 1588 static u8 calc_voltage_level(int cdclk, int num_voltage_levels, 1589 const int voltage_level_max_cdclk[]) 1590 { 1591 int voltage_level; 1592 1593 for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) { 1594 if (cdclk <= voltage_level_max_cdclk[voltage_level]) 1595 return voltage_level; 1596 } 1597 1598 MISSING_CASE(cdclk); 1599 return num_voltage_levels - 1; 1600 } 1601 1602 static u8 icl_calc_voltage_level(int cdclk) 1603 { 1604 static const int icl_voltage_level_max_cdclk[] = { 1605 [0] = 312000, 1606 [1] = 556800, 1607 [2] = 652800, 1608 }; 1609 1610 return calc_voltage_level(cdclk, 1611 ARRAY_SIZE(icl_voltage_level_max_cdclk), 1612 icl_voltage_level_max_cdclk); 1613 } 1614 1615 static u8 ehl_calc_voltage_level(int cdclk) 1616 { 1617 static const int ehl_voltage_level_max_cdclk[] = { 1618 [0] = 180000, 1619 [1] = 312000, 1620 [2] = 326400, 1621 /* 1622 * Bspec lists the limit as 556.8 MHz, but some JSL 1623 * development boards (at least) boot with 652.8 MHz 1624 */ 1625 [3] = 652800, 1626 }; 1627 1628 return calc_voltage_level(cdclk, 1629 ARRAY_SIZE(ehl_voltage_level_max_cdclk), 1630 ehl_voltage_level_max_cdclk); 1631 } 1632 1633 static u8 tgl_calc_voltage_level(int cdclk) 1634 { 1635 static const int tgl_voltage_level_max_cdclk[] = { 1636 [0] = 312000, 1637 [1] = 326400, 1638 [2] = 556800, 1639 [3] = 652800, 1640 }; 1641 1642 return calc_voltage_level(cdclk, 1643 ARRAY_SIZE(tgl_voltage_level_max_cdclk), 1644 tgl_voltage_level_max_cdclk); 1645 } 1646 1647 static u8 rplu_calc_voltage_level(int cdclk) 1648 { 1649 static const int rplu_voltage_level_max_cdclk[] = { 1650 [0] = 312000, 1651 [1] = 480000, 1652 [2] = 556800, 1653 [3] = 652800, 1654 }; 1655 1656 return calc_voltage_level(cdclk, 1657 ARRAY_SIZE(rplu_voltage_level_max_cdclk), 1658 rplu_voltage_level_max_cdclk); 1659 } 1660 1661 static u8 xe3lpd_calc_voltage_level(int cdclk) 1662 { 1663 /* 1664 * Starting with xe3lpd power controller does not need the voltage 1665 * index when doing the modeset update. This function is best left 1666 * defined but returning 0 to the mask. 1667 */ 1668 return 0; 1669 } 1670 1671 static void icl_readout_refclk(struct intel_display *display, 1672 struct intel_cdclk_config *cdclk_config) 1673 { 1674 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; 1675 1676 switch (dssm) { 1677 default: 1678 MISSING_CASE(dssm); 1679 fallthrough; 1680 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: 1681 cdclk_config->ref = 24000; 1682 break; 1683 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: 1684 cdclk_config->ref = 19200; 1685 break; 1686 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: 1687 cdclk_config->ref = 38400; 1688 break; 1689 } 1690 } 1691 1692 static void bxt_de_pll_readout(struct intel_display *display, 1693 struct intel_cdclk_config *cdclk_config) 1694 { 1695 u32 val, ratio; 1696 1697 if (display->platform.dg2) 1698 cdclk_config->ref = 38400; 1699 else if (DISPLAY_VER(display) >= 11) 1700 icl_readout_refclk(display, cdclk_config); 1701 else 1702 cdclk_config->ref = 19200; 1703 1704 val = intel_de_read(display, BXT_DE_PLL_ENABLE); 1705 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || 1706 (val & BXT_DE_PLL_LOCK) == 0) { 1707 /* 1708 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but 1709 * setting it to zero is a way to signal that. 1710 */ 1711 cdclk_config->vco = 0; 1712 return; 1713 } 1714 1715 /* 1716 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, 1717 * gen9lp had it in a separate PLL control register. 1718 */ 1719 if (DISPLAY_VER(display) >= 11) 1720 ratio = val & ICL_CDCLK_PLL_RATIO_MASK; 1721 else 1722 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; 1723 1724 cdclk_config->vco = ratio * cdclk_config->ref; 1725 } 1726 1727 static void bxt_get_cdclk(struct intel_display *display, 1728 struct intel_cdclk_config *cdclk_config) 1729 { 1730 u32 squash_ctl = 0; 1731 u32 divider; 1732 int div; 1733 1734 bxt_de_pll_readout(display, cdclk_config); 1735 1736 if (DISPLAY_VER(display) >= 12) 1737 cdclk_config->bypass = cdclk_config->ref / 2; 1738 else if (DISPLAY_VER(display) >= 11) 1739 cdclk_config->bypass = 50000; 1740 else 1741 cdclk_config->bypass = cdclk_config->ref; 1742 1743 if (cdclk_config->vco == 0) { 1744 cdclk_config->cdclk = cdclk_config->bypass; 1745 goto out; 1746 } 1747 1748 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; 1749 1750 switch (divider) { 1751 case BXT_CDCLK_CD2X_DIV_SEL_1: 1752 div = 2; 1753 break; 1754 case BXT_CDCLK_CD2X_DIV_SEL_1_5: 1755 div = 3; 1756 break; 1757 case BXT_CDCLK_CD2X_DIV_SEL_2: 1758 div = 4; 1759 break; 1760 case BXT_CDCLK_CD2X_DIV_SEL_4: 1761 div = 8; 1762 break; 1763 default: 1764 MISSING_CASE(divider); 1765 return; 1766 } 1767 1768 if (HAS_CDCLK_SQUASH(display)) 1769 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); 1770 1771 if (squash_ctl & CDCLK_SQUASH_ENABLE) { 1772 u16 waveform; 1773 int size; 1774 1775 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1; 1776 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); 1777 1778 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * 1779 cdclk_config->vco, size * div); 1780 } else { 1781 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); 1782 } 1783 1784 out: 1785 if (DISPLAY_VER(display) >= 20) 1786 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; 1787 /* 1788 * Can't read this out :( Let's assume it's 1789 * at least what the CDCLK frequency requires. 1790 */ 1791 cdclk_config->voltage_level = 1792 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); 1793 } 1794 1795 static void bxt_de_pll_disable(struct intel_display *display) 1796 { 1797 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); 1798 1799 /* Timeout 200us */ 1800 if (intel_de_wait_for_clear(display, 1801 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1802 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); 1803 1804 display->cdclk.hw.vco = 0; 1805 } 1806 1807 static void bxt_de_pll_enable(struct intel_display *display, int vco) 1808 { 1809 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1810 1811 intel_de_rmw(display, BXT_DE_PLL_CTL, 1812 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); 1813 1814 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); 1815 1816 /* Timeout 200us */ 1817 if (intel_de_wait_for_set(display, 1818 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1819 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); 1820 1821 display->cdclk.hw.vco = vco; 1822 } 1823 1824 static void icl_cdclk_pll_disable(struct intel_display *display) 1825 { 1826 intel_de_rmw(display, BXT_DE_PLL_ENABLE, 1827 BXT_DE_PLL_PLL_ENABLE, 0); 1828 1829 /* Timeout 200us */ 1830 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1831 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); 1832 1833 display->cdclk.hw.vco = 0; 1834 } 1835 1836 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) 1837 { 1838 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1839 u32 val; 1840 1841 val = ICL_CDCLK_PLL_RATIO(ratio); 1842 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1843 1844 val |= BXT_DE_PLL_PLL_ENABLE; 1845 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1846 1847 /* Timeout 200us */ 1848 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) 1849 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); 1850 1851 display->cdclk.hw.vco = vco; 1852 } 1853 1854 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) 1855 { 1856 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); 1857 u32 val; 1858 1859 /* Write PLL ratio without disabling */ 1860 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; 1861 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1862 1863 /* Submit freq change request */ 1864 val |= BXT_DE_PLL_FREQ_REQ; 1865 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1866 1867 /* Timeout 200us */ 1868 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, 1869 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) 1870 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); 1871 1872 val &= ~BXT_DE_PLL_FREQ_REQ; 1873 intel_de_write(display, BXT_DE_PLL_ENABLE, val); 1874 1875 display->cdclk.hw.vco = vco; 1876 } 1877 1878 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) 1879 { 1880 if (DISPLAY_VER(display) >= 12) { 1881 if (pipe == INVALID_PIPE) 1882 return TGL_CDCLK_CD2X_PIPE_NONE; 1883 else 1884 return TGL_CDCLK_CD2X_PIPE(pipe); 1885 } else if (DISPLAY_VER(display) >= 11) { 1886 if (pipe == INVALID_PIPE) 1887 return ICL_CDCLK_CD2X_PIPE_NONE; 1888 else 1889 return ICL_CDCLK_CD2X_PIPE(pipe); 1890 } else { 1891 if (pipe == INVALID_PIPE) 1892 return BXT_CDCLK_CD2X_PIPE_NONE; 1893 else 1894 return BXT_CDCLK_CD2X_PIPE(pipe); 1895 } 1896 } 1897 1898 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, 1899 int cdclk, int vco, u16 waveform) 1900 { 1901 /* cdclk = vco / 2 / div{1,1.5,2,4} */ 1902 switch (cdclk_divider(cdclk, vco, waveform)) { 1903 default: 1904 drm_WARN_ON(display->drm, 1905 cdclk != display->cdclk.hw.bypass); 1906 drm_WARN_ON(display->drm, vco != 0); 1907 fallthrough; 1908 case 2: 1909 return BXT_CDCLK_CD2X_DIV_SEL_1; 1910 case 3: 1911 return BXT_CDCLK_CD2X_DIV_SEL_1_5; 1912 case 4: 1913 return BXT_CDCLK_CD2X_DIV_SEL_2; 1914 case 8: 1915 return BXT_CDCLK_CD2X_DIV_SEL_4; 1916 } 1917 } 1918 1919 static u16 cdclk_squash_waveform(struct intel_display *display, 1920 int cdclk) 1921 { 1922 const struct intel_cdclk_vals *table = display->cdclk.table; 1923 int i; 1924 1925 if (cdclk == display->cdclk.hw.bypass) 1926 return 0; 1927 1928 for (i = 0; table[i].refclk; i++) 1929 if (table[i].refclk == display->cdclk.hw.ref && 1930 table[i].cdclk == cdclk) 1931 return table[i].waveform; 1932 1933 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", 1934 cdclk, display->cdclk.hw.ref); 1935 1936 return 0xffff; 1937 } 1938 1939 static void icl_cdclk_pll_update(struct intel_display *display, int vco) 1940 { 1941 if (display->cdclk.hw.vco != 0 && 1942 display->cdclk.hw.vco != vco) 1943 icl_cdclk_pll_disable(display); 1944 1945 if (display->cdclk.hw.vco != vco) 1946 icl_cdclk_pll_enable(display, vco); 1947 } 1948 1949 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) 1950 { 1951 if (display->cdclk.hw.vco != 0 && 1952 display->cdclk.hw.vco != vco) 1953 bxt_de_pll_disable(display); 1954 1955 if (display->cdclk.hw.vco != vco) 1956 bxt_de_pll_enable(display, vco); 1957 } 1958 1959 static void dg2_cdclk_squash_program(struct intel_display *display, 1960 u16 waveform) 1961 { 1962 u32 squash_ctl = 0; 1963 1964 if (waveform) 1965 squash_ctl = CDCLK_SQUASH_ENABLE | 1966 CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; 1967 1968 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); 1969 } 1970 1971 static bool cdclk_pll_is_unknown(unsigned int vco) 1972 { 1973 /* 1974 * Ensure driver does not take the crawl path for the 1975 * case when the vco is set to ~0 in the 1976 * sanitize path. 1977 */ 1978 return vco == ~0; 1979 } 1980 1981 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) 1982 { 1983 return DISPLAY_VER(display) >= 20; 1984 } 1985 1986 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) 1987 { 1988 if (mdclk_source_is_cdclk_pll(display)) 1989 return MDCLK_SOURCE_SEL_CDCLK_PLL; 1990 1991 return MDCLK_SOURCE_SEL_CD2XCLK; 1992 } 1993 1994 int intel_mdclk_cdclk_ratio(struct intel_display *display, 1995 const struct intel_cdclk_config *cdclk_config) 1996 { 1997 if (mdclk_source_is_cdclk_pll(display)) 1998 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); 1999 2000 /* Otherwise, source for MDCLK is CD2XCLK. */ 2001 return 2; 2002 } 2003 2004 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, 2005 const struct intel_cdclk_config *cdclk_config) 2006 { 2007 intel_dbuf_mdclk_cdclk_ratio_update(display, 2008 intel_mdclk_cdclk_ratio(display, cdclk_config), 2009 cdclk_config->joined_mbus); 2010 } 2011 2012 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, 2013 const struct intel_cdclk_config *old_cdclk_config, 2014 const struct intel_cdclk_config *new_cdclk_config, 2015 struct intel_cdclk_config *mid_cdclk_config) 2016 { 2017 u16 old_waveform, new_waveform, mid_waveform; 2018 int old_div, new_div, mid_div; 2019 2020 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ 2021 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) 2022 return false; 2023 2024 /* Return if both Squash and Crawl are not present */ 2025 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2026 return false; 2027 2028 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); 2029 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); 2030 2031 /* Return if Squash only or Crawl only is the desired action */ 2032 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || 2033 old_cdclk_config->vco == new_cdclk_config->vco || 2034 old_waveform == new_waveform) 2035 return false; 2036 2037 old_div = cdclk_divider(old_cdclk_config->cdclk, 2038 old_cdclk_config->vco, old_waveform); 2039 new_div = cdclk_divider(new_cdclk_config->cdclk, 2040 new_cdclk_config->vco, new_waveform); 2041 2042 /* 2043 * Should not happen currently. We might need more midpoint 2044 * transitions if we need to also change the cd2x divider. 2045 */ 2046 if (drm_WARN_ON(display->drm, old_div != new_div)) 2047 return false; 2048 2049 *mid_cdclk_config = *new_cdclk_config; 2050 2051 /* 2052 * Populate the mid_cdclk_config accordingly. 2053 * - If moving to a higher cdclk, the desired action is squashing. 2054 * The mid cdclk config should have the new (squash) waveform. 2055 * - If moving to a lower cdclk, the desired action is crawling. 2056 * The mid cdclk config should have the new vco. 2057 */ 2058 2059 if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) { 2060 mid_cdclk_config->vco = old_cdclk_config->vco; 2061 mid_div = old_div; 2062 mid_waveform = new_waveform; 2063 } else { 2064 mid_cdclk_config->vco = new_cdclk_config->vco; 2065 mid_div = new_div; 2066 mid_waveform = old_waveform; 2067 } 2068 2069 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * 2070 mid_cdclk_config->vco, 2071 cdclk_squash_len * mid_div); 2072 2073 /* make sure the mid clock came out sane */ 2074 2075 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < 2076 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); 2077 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > 2078 display->cdclk.max_cdclk_freq); 2079 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != 2080 mid_waveform); 2081 2082 return true; 2083 } 2084 2085 static bool pll_enable_wa_needed(struct intel_display *display) 2086 { 2087 return (DISPLAY_VERx100(display) == 2000 || 2088 DISPLAY_VERx100(display) == 1400 || 2089 display->platform.dg2) && 2090 display->cdclk.hw.vco > 0; 2091 } 2092 2093 static u32 bxt_cdclk_ctl(struct intel_display *display, 2094 const struct intel_cdclk_config *cdclk_config, 2095 enum pipe pipe) 2096 { 2097 int cdclk = cdclk_config->cdclk; 2098 int vco = cdclk_config->vco; 2099 u16 waveform; 2100 u32 val; 2101 2102 waveform = cdclk_squash_waveform(display, cdclk); 2103 2104 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | 2105 bxt_cdclk_cd2x_pipe(display, pipe); 2106 2107 /* 2108 * Disable SSA Precharge when CD clock frequency < 500 MHz, 2109 * enable otherwise. 2110 */ 2111 if ((display->platform.geminilake || display->platform.broxton) && 2112 cdclk >= 500000) 2113 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; 2114 2115 if (DISPLAY_VER(display) >= 20) 2116 val |= xe2lpd_mdclk_source_sel(display); 2117 else 2118 val |= skl_cdclk_decimal(cdclk); 2119 2120 return val; 2121 } 2122 2123 static void _bxt_set_cdclk(struct intel_display *display, 2124 const struct intel_cdclk_config *cdclk_config, 2125 enum pipe pipe) 2126 { 2127 int cdclk = cdclk_config->cdclk; 2128 int vco = cdclk_config->vco; 2129 2130 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && 2131 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { 2132 if (display->cdclk.hw.vco != vco) 2133 adlp_cdclk_pll_crawl(display, vco); 2134 } else if (DISPLAY_VER(display) >= 11) { 2135 /* wa_15010685871: dg2, mtl */ 2136 if (pll_enable_wa_needed(display)) 2137 dg2_cdclk_squash_program(display, 0); 2138 2139 icl_cdclk_pll_update(display, vco); 2140 } else { 2141 bxt_cdclk_pll_update(display, vco); 2142 } 2143 2144 if (HAS_CDCLK_SQUASH(display)) { 2145 u16 waveform = cdclk_squash_waveform(display, cdclk); 2146 2147 dg2_cdclk_squash_program(display, waveform); 2148 } 2149 2150 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); 2151 2152 if (pipe != INVALID_PIPE) 2153 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); 2154 } 2155 2156 static void bxt_set_cdclk(struct intel_display *display, 2157 const struct intel_cdclk_config *cdclk_config, 2158 enum pipe pipe) 2159 { 2160 struct intel_cdclk_config mid_cdclk_config; 2161 int cdclk = cdclk_config->cdclk; 2162 int ret = 0; 2163 2164 /* 2165 * Inform power controller of upcoming frequency change. 2166 * Display versions 14 and beyond do not follow the PUnit 2167 * mailbox communication, skip 2168 * this step. 2169 */ 2170 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) 2171 ; /* NOOP */ 2172 else if (DISPLAY_VER(display) >= 11) 2173 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 2174 SKL_CDCLK_PREPARE_FOR_CHANGE, 2175 SKL_CDCLK_READY_FOR_CHANGE, 2176 SKL_CDCLK_READY_FOR_CHANGE, 3); 2177 else 2178 /* 2179 * BSpec requires us to wait up to 150usec, but that leads to 2180 * timeouts; the 2ms used here is based on experiment. 2181 */ 2182 ret = intel_pcode_write_timeout(display->drm, 2183 HSW_PCODE_DE_WRITE_FREQ_REQ, 2184 0x80000000, 2); 2185 2186 if (ret) { 2187 drm_err(display->drm, 2188 "Failed to inform PCU about cdclk change (err %d, freq %d)\n", 2189 ret, cdclk); 2190 return; 2191 } 2192 2193 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) 2194 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2195 2196 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, 2197 cdclk_config, &mid_cdclk_config)) { 2198 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); 2199 _bxt_set_cdclk(display, cdclk_config, pipe); 2200 } else { 2201 _bxt_set_cdclk(display, cdclk_config, pipe); 2202 } 2203 2204 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) 2205 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); 2206 2207 if (DISPLAY_VER(display) >= 14) 2208 /* 2209 * NOOP - No Pcode communication needed for 2210 * Display versions 14 and beyond 2211 */; 2212 else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) 2213 ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, 2214 cdclk_config->voltage_level); 2215 if (DISPLAY_VER(display) < 11) { 2216 /* 2217 * The timeout isn't specified, the 2ms used here is based on 2218 * experiment. 2219 * FIXME: Waiting for the request completion could be delayed 2220 * until the next PCODE request based on BSpec. 2221 */ 2222 ret = intel_pcode_write_timeout(display->drm, 2223 HSW_PCODE_DE_WRITE_FREQ_REQ, 2224 cdclk_config->voltage_level, 2); 2225 } 2226 if (ret) { 2227 drm_err(display->drm, 2228 "PCode CDCLK freq set failed, (err %d, freq %d)\n", 2229 ret, cdclk); 2230 return; 2231 } 2232 2233 intel_update_cdclk(display); 2234 2235 if (DISPLAY_VER(display) >= 11) 2236 /* 2237 * Can't read out the voltage level :( 2238 * Let's just assume everything is as expected. 2239 */ 2240 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; 2241 } 2242 2243 static void bxt_sanitize_cdclk(struct intel_display *display) 2244 { 2245 u32 cdctl, expected; 2246 int cdclk, vco; 2247 2248 intel_update_cdclk(display); 2249 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 2250 2251 if (display->cdclk.hw.vco == 0 || 2252 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) 2253 goto sanitize; 2254 2255 /* Make sure this is a legal cdclk value for the platform */ 2256 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); 2257 if (cdclk != display->cdclk.hw.cdclk) 2258 goto sanitize; 2259 2260 /* Make sure the VCO is correct for the cdclk */ 2261 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 2262 if (vco != display->cdclk.hw.vco) 2263 goto sanitize; 2264 2265 /* 2266 * Some BIOS versions leave an incorrect decimal frequency value and 2267 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, 2268 * so sanitize this register. 2269 */ 2270 cdctl = intel_de_read(display, CDCLK_CTL); 2271 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); 2272 2273 /* 2274 * Let's ignore the pipe field, since BIOS could have configured the 2275 * dividers both syncing to an active pipe, or asynchronously 2276 * (PIPE_NONE). 2277 */ 2278 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2279 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); 2280 2281 if (cdctl == expected) 2282 /* All well; nothing to sanitize */ 2283 return; 2284 2285 sanitize: 2286 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); 2287 2288 /* force cdclk programming */ 2289 display->cdclk.hw.cdclk = 0; 2290 2291 /* force full PLL disable + enable */ 2292 display->cdclk.hw.vco = ~0; 2293 } 2294 2295 static void bxt_cdclk_init_hw(struct intel_display *display) 2296 { 2297 struct intel_cdclk_config cdclk_config; 2298 2299 bxt_sanitize_cdclk(display); 2300 2301 if (display->cdclk.hw.cdclk != 0 && 2302 display->cdclk.hw.vco != 0) 2303 return; 2304 2305 cdclk_config = display->cdclk.hw; 2306 2307 /* 2308 * FIXME: 2309 * - The initial CDCLK needs to be read from VBT. 2310 * Need to make this change after VBT has changes for BXT. 2311 */ 2312 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); 2313 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); 2314 cdclk_config.voltage_level = 2315 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2316 2317 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2318 } 2319 2320 static void bxt_cdclk_uninit_hw(struct intel_display *display) 2321 { 2322 struct intel_cdclk_config cdclk_config = display->cdclk.hw; 2323 2324 cdclk_config.cdclk = cdclk_config.bypass; 2325 cdclk_config.vco = 0; 2326 cdclk_config.voltage_level = 2327 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); 2328 2329 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); 2330 } 2331 2332 /** 2333 * intel_cdclk_init_hw - Initialize CDCLK hardware 2334 * @display: display instance 2335 * 2336 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and 2337 * sanitizing the state of the hardware if needed. This is generally done only 2338 * during the display core initialization sequence, after which the DMC will 2339 * take care of turning CDCLK off/on as needed. 2340 */ 2341 void intel_cdclk_init_hw(struct intel_display *display) 2342 { 2343 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2344 bxt_cdclk_init_hw(display); 2345 else if (DISPLAY_VER(display) == 9) 2346 skl_cdclk_init_hw(display); 2347 } 2348 2349 /** 2350 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware 2351 * @display: display instance 2352 * 2353 * Uninitialize CDCLK. This is done only during the display core 2354 * uninitialization sequence. 2355 */ 2356 void intel_cdclk_uninit_hw(struct intel_display *display) 2357 { 2358 if (DISPLAY_VER(display) >= 10 || display->platform.broxton) 2359 bxt_cdclk_uninit_hw(display); 2360 else if (DISPLAY_VER(display) == 9) 2361 skl_cdclk_uninit_hw(display); 2362 } 2363 2364 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, 2365 const struct intel_cdclk_config *a, 2366 const struct intel_cdclk_config *b) 2367 { 2368 u16 old_waveform; 2369 u16 new_waveform; 2370 2371 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); 2372 2373 if (a->vco == 0 || b->vco == 0) 2374 return false; 2375 2376 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) 2377 return false; 2378 2379 old_waveform = cdclk_squash_waveform(display, a->cdclk); 2380 new_waveform = cdclk_squash_waveform(display, b->cdclk); 2381 2382 return a->vco != b->vco && 2383 old_waveform != new_waveform; 2384 } 2385 2386 static bool intel_cdclk_can_crawl(struct intel_display *display, 2387 const struct intel_cdclk_config *a, 2388 const struct intel_cdclk_config *b) 2389 { 2390 int a_div, b_div; 2391 2392 if (!HAS_CDCLK_CRAWL(display)) 2393 return false; 2394 2395 /* 2396 * The vco and cd2x divider will change independently 2397 * from each, so we disallow cd2x change when crawling. 2398 */ 2399 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); 2400 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); 2401 2402 return a->vco != 0 && b->vco != 0 && 2403 a->vco != b->vco && 2404 a_div == b_div && 2405 a->ref == b->ref; 2406 } 2407 2408 static bool intel_cdclk_can_squash(struct intel_display *display, 2409 const struct intel_cdclk_config *a, 2410 const struct intel_cdclk_config *b) 2411 { 2412 /* 2413 * FIXME should store a bit more state in intel_cdclk_config 2414 * to differentiate squasher vs. cd2x divider properly. For 2415 * the moment all platforms with squasher use a fixed cd2x 2416 * divider. 2417 */ 2418 if (!HAS_CDCLK_SQUASH(display)) 2419 return false; 2420 2421 return a->cdclk != b->cdclk && 2422 a->vco != 0 && 2423 a->vco == b->vco && 2424 a->ref == b->ref; 2425 } 2426 2427 /** 2428 * intel_cdclk_clock_changed - Check whether the clock changed 2429 * @a: first CDCLK configuration 2430 * @b: second CDCLK configuration 2431 * 2432 * Returns: 2433 * True if CDCLK changed in a way that requires re-programming and 2434 * False otherwise. 2435 */ 2436 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, 2437 const struct intel_cdclk_config *b) 2438 { 2439 return a->cdclk != b->cdclk || 2440 a->vco != b->vco || 2441 a->ref != b->ref; 2442 } 2443 2444 /** 2445 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK 2446 * configurations requires only a cd2x divider update 2447 * @display: display instance 2448 * @a: first CDCLK configuration 2449 * @b: second CDCLK configuration 2450 * 2451 * Returns: 2452 * True if changing between the two CDCLK configurations 2453 * can be done with just a cd2x divider update, false if not. 2454 */ 2455 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, 2456 const struct intel_cdclk_config *a, 2457 const struct intel_cdclk_config *b) 2458 { 2459 /* Older hw doesn't have the capability */ 2460 if (DISPLAY_VER(display) < 10 && !display->platform.broxton) 2461 return false; 2462 2463 /* 2464 * FIXME should store a bit more state in intel_cdclk_config 2465 * to differentiate squasher vs. cd2x divider properly. For 2466 * the moment all platforms with squasher use a fixed cd2x 2467 * divider. 2468 */ 2469 if (HAS_CDCLK_SQUASH(display)) 2470 return false; 2471 2472 return a->cdclk != b->cdclk && 2473 a->vco != 0 && 2474 a->vco == b->vco && 2475 a->ref == b->ref; 2476 } 2477 2478 /** 2479 * intel_cdclk_changed - Determine if two CDCLK configurations are different 2480 * @a: first CDCLK configuration 2481 * @b: second CDCLK configuration 2482 * 2483 * Returns: 2484 * True if the CDCLK configurations don't match, false if they do. 2485 */ 2486 static bool intel_cdclk_changed(const struct intel_cdclk_config *a, 2487 const struct intel_cdclk_config *b) 2488 { 2489 return intel_cdclk_clock_changed(a, b) || 2490 a->voltage_level != b->voltage_level; 2491 } 2492 2493 void intel_cdclk_dump_config(struct intel_display *display, 2494 const struct intel_cdclk_config *cdclk_config, 2495 const char *context) 2496 { 2497 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", 2498 context, cdclk_config->cdclk, cdclk_config->vco, 2499 cdclk_config->ref, cdclk_config->bypass, 2500 cdclk_config->voltage_level); 2501 } 2502 2503 static void intel_pcode_notify(struct intel_display *display, 2504 u8 voltage_level, 2505 u8 active_pipe_count, 2506 u16 cdclk, 2507 bool cdclk_update_valid, 2508 bool pipe_count_update_valid) 2509 { 2510 int ret; 2511 u32 update_mask = 0; 2512 2513 if (!display->platform.dg2) 2514 return; 2515 2516 update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); 2517 2518 if (cdclk_update_valid) 2519 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID; 2520 2521 if (pipe_count_update_valid) 2522 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID; 2523 2524 ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL, 2525 SKL_CDCLK_PREPARE_FOR_CHANGE | 2526 update_mask, 2527 SKL_CDCLK_READY_FOR_CHANGE, 2528 SKL_CDCLK_READY_FOR_CHANGE, 3); 2529 if (ret) 2530 drm_err(display->drm, 2531 "Failed to inform PCU about display config (err %d)\n", 2532 ret); 2533 } 2534 2535 static void intel_set_cdclk(struct intel_display *display, 2536 const struct intel_cdclk_config *cdclk_config, 2537 enum pipe pipe, const char *context) 2538 { 2539 struct intel_encoder *encoder; 2540 2541 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) 2542 return; 2543 2544 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) 2545 return; 2546 2547 intel_cdclk_dump_config(display, cdclk_config, context); 2548 2549 for_each_intel_encoder_with_psr(display->drm, encoder) { 2550 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2551 2552 intel_psr_pause(intel_dp); 2553 } 2554 2555 intel_audio_cdclk_change_pre(display); 2556 2557 /* 2558 * Lock aux/gmbus while we change cdclk in case those 2559 * functions use cdclk. Not all platforms/ports do, 2560 * but we'll lock them all for simplicity. 2561 */ 2562 mutex_lock(&display->gmbus.mutex); 2563 for_each_intel_dp(display->drm, encoder) { 2564 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2565 2566 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, 2567 &display->gmbus.mutex); 2568 } 2569 2570 intel_cdclk_set_cdclk(display, cdclk_config, pipe); 2571 2572 for_each_intel_dp(display->drm, encoder) { 2573 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2574 2575 mutex_unlock(&intel_dp->aux.hw_mutex); 2576 } 2577 mutex_unlock(&display->gmbus.mutex); 2578 2579 for_each_intel_encoder_with_psr(display->drm, encoder) { 2580 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2581 2582 intel_psr_resume(intel_dp); 2583 } 2584 2585 intel_audio_cdclk_change_post(display); 2586 2587 if (drm_WARN(display->drm, 2588 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), 2589 "cdclk state doesn't match!\n")) { 2590 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); 2591 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); 2592 } 2593 } 2594 2595 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) 2596 { 2597 struct intel_display *display = to_intel_display(state); 2598 const struct intel_cdclk_state *old_cdclk_state = 2599 intel_atomic_get_old_cdclk_state(state); 2600 const struct intel_cdclk_state *new_cdclk_state = 2601 intel_atomic_get_new_cdclk_state(state); 2602 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2603 bool change_cdclk, update_pipe_count; 2604 2605 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2606 &new_cdclk_state->actual) && 2607 new_cdclk_state->active_pipes == 2608 old_cdclk_state->active_pipes) 2609 return; 2610 2611 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ 2612 voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX; 2613 2614 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2615 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > 2616 hweight8(old_cdclk_state->active_pipes); 2617 2618 /* 2619 * According to "Sequence Before Frequency Change", 2620 * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK, 2621 * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, 2622 * which basically means we choose the maximum of old and new CDCLK, if we know both 2623 */ 2624 if (change_cdclk) 2625 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); 2626 2627 /* 2628 * According to "Sequence For Pipe Count Change", 2629 * if pipe count is increasing, set bits 25:16 to upcoming pipe count 2630 * (power well is enabled) 2631 * no action if it is decreasing, before the change 2632 */ 2633 if (update_pipe_count) 2634 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2635 2636 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2637 change_cdclk, update_pipe_count); 2638 } 2639 2640 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) 2641 { 2642 struct intel_display *display = to_intel_display(state); 2643 const struct intel_cdclk_state *new_cdclk_state = 2644 intel_atomic_get_new_cdclk_state(state); 2645 const struct intel_cdclk_state *old_cdclk_state = 2646 intel_atomic_get_old_cdclk_state(state); 2647 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; 2648 bool update_cdclk, update_pipe_count; 2649 2650 /* According to "Sequence After Frequency Change", set voltage to used level */ 2651 voltage_level = new_cdclk_state->actual.voltage_level; 2652 2653 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; 2654 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < 2655 hweight8(old_cdclk_state->active_pipes); 2656 2657 /* 2658 * According to "Sequence After Frequency Change", 2659 * set bits 25:16 to current CDCLK 2660 */ 2661 if (update_cdclk) 2662 cdclk = new_cdclk_state->actual.cdclk; 2663 2664 /* 2665 * According to "Sequence For Pipe Count Change", 2666 * if pipe count is decreasing, set bits 25:16 to current pipe count, 2667 * after the change(power well is disabled) 2668 * no action if it is increasing, after the change 2669 */ 2670 if (update_pipe_count) 2671 num_active_pipes = hweight8(new_cdclk_state->active_pipes); 2672 2673 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, 2674 update_cdclk, update_pipe_count); 2675 } 2676 2677 bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) 2678 { 2679 const struct intel_cdclk_state *old_cdclk_state = 2680 intel_atomic_get_old_cdclk_state(state); 2681 const struct intel_cdclk_state *new_cdclk_state = 2682 intel_atomic_get_new_cdclk_state(state); 2683 2684 return new_cdclk_state && !new_cdclk_state->disable_pipes && 2685 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; 2686 } 2687 2688 /** 2689 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware 2690 * @state: intel atomic state 2691 * 2692 * Program the hardware before updating the HW plane state based on the 2693 * new CDCLK state, if necessary. 2694 */ 2695 void 2696 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) 2697 { 2698 struct intel_display *display = to_intel_display(state); 2699 const struct intel_cdclk_state *old_cdclk_state = 2700 intel_atomic_get_old_cdclk_state(state); 2701 const struct intel_cdclk_state *new_cdclk_state = 2702 intel_atomic_get_new_cdclk_state(state); 2703 struct intel_cdclk_config cdclk_config; 2704 enum pipe pipe; 2705 2706 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2707 &new_cdclk_state->actual)) 2708 return; 2709 2710 if (display->platform.dg2) 2711 intel_cdclk_pcode_pre_notify(state); 2712 2713 if (new_cdclk_state->disable_pipes) { 2714 cdclk_config = new_cdclk_state->actual; 2715 pipe = INVALID_PIPE; 2716 } else { 2717 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { 2718 cdclk_config = new_cdclk_state->actual; 2719 pipe = new_cdclk_state->pipe; 2720 } else { 2721 cdclk_config = old_cdclk_state->actual; 2722 pipe = INVALID_PIPE; 2723 } 2724 2725 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, 2726 old_cdclk_state->actual.voltage_level); 2727 } 2728 2729 /* 2730 * mbus joining will be changed later by 2731 * intel_dbuf_mbus_{pre,post}_ddb_update() 2732 */ 2733 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; 2734 2735 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2736 2737 intel_set_cdclk(display, &cdclk_config, pipe, 2738 "Pre changing CDCLK to"); 2739 } 2740 2741 /** 2742 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware 2743 * @state: intel atomic state 2744 * 2745 * Program the hardware after updating the HW plane state based on the 2746 * new CDCLK state, if necessary. 2747 */ 2748 void 2749 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) 2750 { 2751 struct intel_display *display = to_intel_display(state); 2752 const struct intel_cdclk_state *old_cdclk_state = 2753 intel_atomic_get_old_cdclk_state(state); 2754 const struct intel_cdclk_state *new_cdclk_state = 2755 intel_atomic_get_new_cdclk_state(state); 2756 enum pipe pipe; 2757 2758 if (!intel_cdclk_changed(&old_cdclk_state->actual, 2759 &new_cdclk_state->actual)) 2760 return; 2761 2762 if (display->platform.dg2) 2763 intel_cdclk_pcode_post_notify(state); 2764 2765 if (!new_cdclk_state->disable_pipes && 2766 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) 2767 pipe = new_cdclk_state->pipe; 2768 else 2769 pipe = INVALID_PIPE; 2770 2771 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); 2772 2773 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, 2774 "Post changing CDCLK to"); 2775 } 2776 2777 /* pixels per CDCLK */ 2778 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) 2779 { 2780 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; 2781 } 2782 2783 /* max pixel rate as % of CDCLK (not accounting for PPC) */ 2784 static int intel_cdclk_guardband(struct intel_display *display) 2785 { 2786 if (DISPLAY_VER(display) >= 9 || 2787 display->platform.broadwell || display->platform.haswell) 2788 return 100; 2789 else if (display->platform.cherryview) 2790 return 95; 2791 else 2792 return 90; 2793 } 2794 2795 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2796 { 2797 struct intel_display *display = to_intel_display(crtc_state); 2798 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 2799 int guardband = intel_cdclk_guardband(display); 2800 int pixel_rate = crtc_state->pixel_rate; 2801 2802 return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); 2803 } 2804 2805 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) 2806 { 2807 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2808 struct intel_display *display = to_intel_display(crtc); 2809 struct intel_plane *plane; 2810 int min_cdclk = 0; 2811 2812 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2813 min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]); 2814 2815 return min_cdclk; 2816 } 2817 2818 static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2819 { 2820 int min_cdclk; 2821 2822 if (!crtc_state->hw.enable) 2823 return 0; 2824 2825 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2826 min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state)); 2827 min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state)); 2828 min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); 2829 min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state)); 2830 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2831 2832 return min_cdclk; 2833 } 2834 2835 static int intel_compute_min_cdclk(struct intel_atomic_state *state) 2836 { 2837 struct intel_display *display = to_intel_display(state); 2838 struct intel_cdclk_state *cdclk_state = 2839 intel_atomic_get_new_cdclk_state(state); 2840 const struct intel_bw_state *bw_state; 2841 struct intel_crtc *crtc; 2842 struct intel_crtc_state *crtc_state; 2843 int min_cdclk, i; 2844 enum pipe pipe; 2845 2846 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2847 int ret; 2848 2849 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); 2850 if (min_cdclk < 0) 2851 return min_cdclk; 2852 2853 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) 2854 continue; 2855 2856 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; 2857 2858 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2859 if (ret) 2860 return ret; 2861 } 2862 2863 bw_state = intel_atomic_get_new_bw_state(state); 2864 if (bw_state) { 2865 min_cdclk = intel_bw_min_cdclk(display, bw_state); 2866 2867 if (cdclk_state->bw_min_cdclk != min_cdclk) { 2868 int ret; 2869 2870 cdclk_state->bw_min_cdclk = min_cdclk; 2871 2872 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2873 if (ret) 2874 return ret; 2875 } 2876 } 2877 2878 min_cdclk = max(cdclk_state->force_min_cdclk, 2879 cdclk_state->bw_min_cdclk); 2880 for_each_pipe(display, pipe) 2881 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); 2882 2883 /* 2884 * Avoid glk_force_audio_cdclk() causing excessive screen 2885 * blinking when multiple pipes are active by making sure 2886 * CDCLK frequency is always high enough for audio. With a 2887 * single active pipe we can always change CDCLK frequency 2888 * by changing the cd2x divider (see glk_cdclk_table[]) and 2889 * thus a full modeset won't be needed then. 2890 */ 2891 if (display->platform.geminilake && cdclk_state->active_pipes && 2892 !is_power_of_2(cdclk_state->active_pipes)) 2893 min_cdclk = max(min_cdclk, 2 * 96000); 2894 2895 if (min_cdclk > display->cdclk.max_cdclk_freq) { 2896 drm_dbg_kms(display->drm, 2897 "required cdclk (%d kHz) exceeds max (%d kHz)\n", 2898 min_cdclk, display->cdclk.max_cdclk_freq); 2899 return -EINVAL; 2900 } 2901 2902 return min_cdclk; 2903 } 2904 2905 /* 2906 * Account for port clock min voltage level requirements. 2907 * This only really does something on DISPLA_VER >= 11 but can be 2908 * called on earlier platforms as well. 2909 * 2910 * Note that this functions assumes that 0 is 2911 * the lowest voltage value, and higher values 2912 * correspond to increasingly higher voltages. 2913 * 2914 * Should that relationship no longer hold on 2915 * future platforms this code will need to be 2916 * adjusted. 2917 */ 2918 static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 2919 { 2920 struct intel_display *display = to_intel_display(state); 2921 struct intel_cdclk_state *cdclk_state = 2922 intel_atomic_get_new_cdclk_state(state); 2923 struct intel_crtc *crtc; 2924 struct intel_crtc_state *crtc_state; 2925 u8 min_voltage_level; 2926 int i; 2927 enum pipe pipe; 2928 2929 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 2930 int ret; 2931 2932 if (crtc_state->hw.enable) 2933 min_voltage_level = crtc_state->min_voltage_level; 2934 else 2935 min_voltage_level = 0; 2936 2937 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) 2938 continue; 2939 2940 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; 2941 2942 ret = intel_atomic_lock_global_state(&cdclk_state->base); 2943 if (ret) 2944 return ret; 2945 } 2946 2947 min_voltage_level = 0; 2948 for_each_pipe(display, pipe) 2949 min_voltage_level = max(min_voltage_level, 2950 cdclk_state->min_voltage_level[pipe]); 2951 2952 return min_voltage_level; 2953 } 2954 2955 static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) 2956 { 2957 struct intel_display *display = to_intel_display(state); 2958 struct intel_cdclk_state *cdclk_state = 2959 intel_atomic_get_new_cdclk_state(state); 2960 int min_cdclk, cdclk; 2961 2962 min_cdclk = intel_compute_min_cdclk(state); 2963 if (min_cdclk < 0) 2964 return min_cdclk; 2965 2966 cdclk = vlv_calc_cdclk(display, min_cdclk); 2967 2968 cdclk_state->logical.cdclk = cdclk; 2969 cdclk_state->logical.voltage_level = 2970 vlv_calc_voltage_level(display, cdclk); 2971 2972 if (!cdclk_state->active_pipes) { 2973 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); 2974 2975 cdclk_state->actual.cdclk = cdclk; 2976 cdclk_state->actual.voltage_level = 2977 vlv_calc_voltage_level(display, cdclk); 2978 } else { 2979 cdclk_state->actual = cdclk_state->logical; 2980 } 2981 2982 return 0; 2983 } 2984 2985 static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) 2986 { 2987 struct intel_cdclk_state *cdclk_state = 2988 intel_atomic_get_new_cdclk_state(state); 2989 int min_cdclk, cdclk; 2990 2991 min_cdclk = intel_compute_min_cdclk(state); 2992 if (min_cdclk < 0) 2993 return min_cdclk; 2994 2995 cdclk = bdw_calc_cdclk(min_cdclk); 2996 2997 cdclk_state->logical.cdclk = cdclk; 2998 cdclk_state->logical.voltage_level = 2999 bdw_calc_voltage_level(cdclk); 3000 3001 if (!cdclk_state->active_pipes) { 3002 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); 3003 3004 cdclk_state->actual.cdclk = cdclk; 3005 cdclk_state->actual.voltage_level = 3006 bdw_calc_voltage_level(cdclk); 3007 } else { 3008 cdclk_state->actual = cdclk_state->logical; 3009 } 3010 3011 return 0; 3012 } 3013 3014 static int skl_dpll0_vco(struct intel_atomic_state *state) 3015 { 3016 struct intel_display *display = to_intel_display(state); 3017 struct intel_cdclk_state *cdclk_state = 3018 intel_atomic_get_new_cdclk_state(state); 3019 struct intel_crtc *crtc; 3020 struct intel_crtc_state *crtc_state; 3021 int vco, i; 3022 3023 vco = cdclk_state->logical.vco; 3024 if (!vco) 3025 vco = display->cdclk.skl_preferred_vco_freq; 3026 3027 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 3028 if (!crtc_state->hw.enable) 3029 continue; 3030 3031 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 3032 continue; 3033 3034 /* 3035 * DPLL0 VCO may need to be adjusted to get the correct 3036 * clock for eDP. This will affect cdclk as well. 3037 */ 3038 switch (crtc_state->port_clock / 2) { 3039 case 108000: 3040 case 216000: 3041 vco = 8640000; 3042 break; 3043 default: 3044 vco = 8100000; 3045 break; 3046 } 3047 } 3048 3049 return vco; 3050 } 3051 3052 static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) 3053 { 3054 struct intel_cdclk_state *cdclk_state = 3055 intel_atomic_get_new_cdclk_state(state); 3056 int min_cdclk, cdclk, vco; 3057 3058 min_cdclk = intel_compute_min_cdclk(state); 3059 if (min_cdclk < 0) 3060 return min_cdclk; 3061 3062 vco = skl_dpll0_vco(state); 3063 3064 cdclk = skl_calc_cdclk(min_cdclk, vco); 3065 3066 cdclk_state->logical.vco = vco; 3067 cdclk_state->logical.cdclk = cdclk; 3068 cdclk_state->logical.voltage_level = 3069 skl_calc_voltage_level(cdclk); 3070 3071 if (!cdclk_state->active_pipes) { 3072 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); 3073 3074 cdclk_state->actual.vco = vco; 3075 cdclk_state->actual.cdclk = cdclk; 3076 cdclk_state->actual.voltage_level = 3077 skl_calc_voltage_level(cdclk); 3078 } else { 3079 cdclk_state->actual = cdclk_state->logical; 3080 } 3081 3082 return 0; 3083 } 3084 3085 static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) 3086 { 3087 struct intel_display *display = to_intel_display(state); 3088 struct intel_cdclk_state *cdclk_state = 3089 intel_atomic_get_new_cdclk_state(state); 3090 int min_cdclk, min_voltage_level, cdclk, vco; 3091 3092 min_cdclk = intel_compute_min_cdclk(state); 3093 if (min_cdclk < 0) 3094 return min_cdclk; 3095 3096 min_voltage_level = bxt_compute_min_voltage_level(state); 3097 if (min_voltage_level < 0) 3098 return min_voltage_level; 3099 3100 cdclk = bxt_calc_cdclk(display, min_cdclk); 3101 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3102 3103 cdclk_state->logical.vco = vco; 3104 cdclk_state->logical.cdclk = cdclk; 3105 cdclk_state->logical.voltage_level = 3106 max_t(int, min_voltage_level, 3107 intel_cdclk_calc_voltage_level(display, cdclk)); 3108 3109 if (!cdclk_state->active_pipes) { 3110 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); 3111 vco = bxt_calc_cdclk_pll_vco(display, cdclk); 3112 3113 cdclk_state->actual.vco = vco; 3114 cdclk_state->actual.cdclk = cdclk; 3115 cdclk_state->actual.voltage_level = 3116 intel_cdclk_calc_voltage_level(display, cdclk); 3117 } else { 3118 cdclk_state->actual = cdclk_state->logical; 3119 } 3120 3121 return 0; 3122 } 3123 3124 static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) 3125 { 3126 int min_cdclk; 3127 3128 /* 3129 * We can't change the cdclk frequency, but we still want to 3130 * check that the required minimum frequency doesn't exceed 3131 * the actual cdclk frequency. 3132 */ 3133 min_cdclk = intel_compute_min_cdclk(state); 3134 if (min_cdclk < 0) 3135 return min_cdclk; 3136 3137 return 0; 3138 } 3139 3140 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) 3141 { 3142 struct intel_cdclk_state *cdclk_state; 3143 3144 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); 3145 if (!cdclk_state) 3146 return NULL; 3147 3148 cdclk_state->pipe = INVALID_PIPE; 3149 cdclk_state->disable_pipes = false; 3150 3151 return &cdclk_state->base; 3152 } 3153 3154 static void intel_cdclk_destroy_state(struct intel_global_obj *obj, 3155 struct intel_global_state *state) 3156 { 3157 kfree(state); 3158 } 3159 3160 static const struct intel_global_state_funcs intel_cdclk_funcs = { 3161 .atomic_duplicate_state = intel_cdclk_duplicate_state, 3162 .atomic_destroy_state = intel_cdclk_destroy_state, 3163 }; 3164 3165 struct intel_cdclk_state * 3166 intel_atomic_get_cdclk_state(struct intel_atomic_state *state) 3167 { 3168 struct intel_display *display = to_intel_display(state); 3169 struct intel_global_state *cdclk_state; 3170 3171 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); 3172 if (IS_ERR(cdclk_state)) 3173 return ERR_CAST(cdclk_state); 3174 3175 return to_intel_cdclk_state(cdclk_state); 3176 } 3177 3178 int intel_cdclk_atomic_check(struct intel_atomic_state *state, 3179 bool *need_cdclk_calc) 3180 { 3181 const struct intel_cdclk_state *old_cdclk_state; 3182 const struct intel_cdclk_state *new_cdclk_state; 3183 struct intel_plane_state __maybe_unused *plane_state; 3184 struct intel_plane *plane; 3185 int ret; 3186 int i; 3187 3188 /* 3189 * active_planes bitmask has been updated, and potentially affected 3190 * planes are part of the state. We can now compute the minimum cdclk 3191 * for each plane. 3192 */ 3193 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 3194 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); 3195 if (ret) 3196 return ret; 3197 } 3198 3199 ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc); 3200 if (ret) 3201 return ret; 3202 3203 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3204 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3205 3206 if (new_cdclk_state && 3207 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) 3208 *need_cdclk_calc = true; 3209 3210 return 0; 3211 } 3212 3213 int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus) 3214 { 3215 struct intel_cdclk_state *cdclk_state; 3216 3217 cdclk_state = intel_atomic_get_cdclk_state(state); 3218 if (IS_ERR(cdclk_state)) 3219 return PTR_ERR(cdclk_state); 3220 3221 cdclk_state->actual.joined_mbus = joined_mbus; 3222 cdclk_state->logical.joined_mbus = joined_mbus; 3223 3224 return intel_atomic_lock_global_state(&cdclk_state->base); 3225 } 3226 3227 int intel_cdclk_init(struct intel_display *display) 3228 { 3229 struct intel_cdclk_state *cdclk_state; 3230 3231 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); 3232 if (!cdclk_state) 3233 return -ENOMEM; 3234 3235 intel_atomic_global_obj_init(display, &display->cdclk.obj, 3236 &cdclk_state->base, &intel_cdclk_funcs); 3237 3238 return 0; 3239 } 3240 3241 static bool intel_cdclk_need_serialize(struct intel_display *display, 3242 const struct intel_cdclk_state *old_cdclk_state, 3243 const struct intel_cdclk_state *new_cdclk_state) 3244 { 3245 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != 3246 hweight8(new_cdclk_state->active_pipes); 3247 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, 3248 &new_cdclk_state->actual); 3249 /* 3250 * We need to poke hw for gen >= 12, because we notify PCode if 3251 * pipe power well count changes. 3252 */ 3253 return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed); 3254 } 3255 3256 int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 3257 { 3258 struct intel_display *display = to_intel_display(state); 3259 const struct intel_cdclk_state *old_cdclk_state; 3260 struct intel_cdclk_state *new_cdclk_state; 3261 enum pipe pipe = INVALID_PIPE; 3262 int ret; 3263 3264 new_cdclk_state = intel_atomic_get_cdclk_state(state); 3265 if (IS_ERR(new_cdclk_state)) 3266 return PTR_ERR(new_cdclk_state); 3267 3268 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3269 3270 new_cdclk_state->active_pipes = 3271 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); 3272 3273 ret = intel_cdclk_modeset_calc_cdclk(state); 3274 if (ret) 3275 return ret; 3276 3277 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { 3278 /* 3279 * Also serialize commits across all crtcs 3280 * if the actual hw needs to be poked. 3281 */ 3282 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); 3283 if (ret) 3284 return ret; 3285 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || 3286 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || 3287 intel_cdclk_changed(&old_cdclk_state->logical, 3288 &new_cdclk_state->logical)) { 3289 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); 3290 if (ret) 3291 return ret; 3292 } else { 3293 return 0; 3294 } 3295 3296 if (is_power_of_2(new_cdclk_state->active_pipes) && 3297 intel_cdclk_can_cd2x_update(display, 3298 &old_cdclk_state->actual, 3299 &new_cdclk_state->actual)) { 3300 struct intel_crtc *crtc; 3301 struct intel_crtc_state *crtc_state; 3302 3303 pipe = ilog2(new_cdclk_state->active_pipes); 3304 crtc = intel_crtc_for_pipe(display, pipe); 3305 3306 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 3307 if (IS_ERR(crtc_state)) 3308 return PTR_ERR(crtc_state); 3309 3310 if (intel_crtc_needs_modeset(crtc_state)) 3311 pipe = INVALID_PIPE; 3312 } 3313 3314 if (intel_cdclk_can_crawl_and_squash(display, 3315 &old_cdclk_state->actual, 3316 &new_cdclk_state->actual)) { 3317 drm_dbg_kms(display->drm, 3318 "Can change cdclk via crawling and squashing\n"); 3319 } else if (intel_cdclk_can_squash(display, 3320 &old_cdclk_state->actual, 3321 &new_cdclk_state->actual)) { 3322 drm_dbg_kms(display->drm, 3323 "Can change cdclk via squashing\n"); 3324 } else if (intel_cdclk_can_crawl(display, 3325 &old_cdclk_state->actual, 3326 &new_cdclk_state->actual)) { 3327 drm_dbg_kms(display->drm, 3328 "Can change cdclk via crawling\n"); 3329 } else if (pipe != INVALID_PIPE) { 3330 new_cdclk_state->pipe = pipe; 3331 3332 drm_dbg_kms(display->drm, 3333 "Can change cdclk cd2x divider with pipe %c active\n", 3334 pipe_name(pipe)); 3335 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, 3336 &new_cdclk_state->actual)) { 3337 /* All pipes must be switched off while we change the cdclk. */ 3338 ret = intel_modeset_all_pipes_late(state, "CDCLK change"); 3339 if (ret) 3340 return ret; 3341 3342 new_cdclk_state->disable_pipes = true; 3343 3344 drm_dbg_kms(display->drm, 3345 "Modeset required for cdclk change\n"); 3346 } 3347 3348 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != 3349 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { 3350 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); 3351 3352 ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); 3353 if (ret) 3354 return ret; 3355 } 3356 3357 drm_dbg_kms(display->drm, 3358 "New cdclk calculated to be logical %u kHz, actual %u kHz\n", 3359 new_cdclk_state->logical.cdclk, 3360 new_cdclk_state->actual.cdclk); 3361 drm_dbg_kms(display->drm, 3362 "New voltage level calculated to be logical %u, actual %u\n", 3363 new_cdclk_state->logical.voltage_level, 3364 new_cdclk_state->actual.voltage_level); 3365 3366 return 0; 3367 } 3368 3369 void intel_cdclk_update_hw_state(struct intel_display *display) 3370 { 3371 const struct intel_bw_state *bw_state = 3372 to_intel_bw_state(display->bw.obj.state); 3373 struct intel_cdclk_state *cdclk_state = 3374 to_intel_cdclk_state(display->cdclk.obj.state); 3375 struct intel_crtc *crtc; 3376 3377 cdclk_state->active_pipes = 0; 3378 3379 for_each_intel_crtc(display->drm, crtc) { 3380 const struct intel_crtc_state *crtc_state = 3381 to_intel_crtc_state(crtc->base.state); 3382 enum pipe pipe = crtc->pipe; 3383 3384 if (crtc_state->hw.active) 3385 cdclk_state->active_pipes |= BIT(pipe); 3386 3387 cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state); 3388 cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level; 3389 } 3390 3391 cdclk_state->bw_min_cdclk = intel_bw_min_cdclk(display, bw_state); 3392 } 3393 3394 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc) 3395 { 3396 struct intel_display *display = to_intel_display(crtc); 3397 3398 intel_cdclk_update_hw_state(display); 3399 } 3400 3401 static int intel_compute_max_dotclk(struct intel_display *display) 3402 { 3403 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); 3404 int guardband = intel_cdclk_guardband(display); 3405 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3406 3407 return ppc * max_cdclk_freq * guardband / 100; 3408 } 3409 3410 /** 3411 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency 3412 * @display: display instance 3413 * 3414 * Determine the maximum CDCLK frequency the platform supports, and also 3415 * derive the maximum dot clock frequency the maximum CDCLK frequency 3416 * allows. 3417 */ 3418 void intel_update_max_cdclk(struct intel_display *display) 3419 { 3420 if (DISPLAY_VERx100(display) >= 3002) { 3421 display->cdclk.max_cdclk_freq = 480000; 3422 } else if (DISPLAY_VER(display) >= 30) { 3423 display->cdclk.max_cdclk_freq = 691200; 3424 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3425 if (display->cdclk.hw.ref == 24000) 3426 display->cdclk.max_cdclk_freq = 552000; 3427 else 3428 display->cdclk.max_cdclk_freq = 556800; 3429 } else if (DISPLAY_VER(display) >= 11) { 3430 if (display->cdclk.hw.ref == 24000) 3431 display->cdclk.max_cdclk_freq = 648000; 3432 else 3433 display->cdclk.max_cdclk_freq = 652800; 3434 } else if (display->platform.geminilake) { 3435 display->cdclk.max_cdclk_freq = 316800; 3436 } else if (display->platform.broxton) { 3437 display->cdclk.max_cdclk_freq = 624000; 3438 } else if (DISPLAY_VER(display) == 9) { 3439 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; 3440 int max_cdclk, vco; 3441 3442 vco = display->cdclk.skl_preferred_vco_freq; 3443 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); 3444 3445 /* 3446 * Use the lower (vco 8640) cdclk values as a 3447 * first guess. skl_calc_cdclk() will correct it 3448 * if the preferred vco is 8100 instead. 3449 */ 3450 if (limit == SKL_DFSM_CDCLK_LIMIT_675) 3451 max_cdclk = 617143; 3452 else if (limit == SKL_DFSM_CDCLK_LIMIT_540) 3453 max_cdclk = 540000; 3454 else if (limit == SKL_DFSM_CDCLK_LIMIT_450) 3455 max_cdclk = 432000; 3456 else 3457 max_cdclk = 308571; 3458 3459 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); 3460 } else if (display->platform.broadwell) { 3461 /* 3462 * FIXME with extra cooling we can allow 3463 * 540 MHz for ULX and 675 Mhz for ULT. 3464 * How can we know if extra cooling is 3465 * available? PCI ID, VTB, something else? 3466 */ 3467 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) 3468 display->cdclk.max_cdclk_freq = 450000; 3469 else if (display->platform.broadwell_ulx) 3470 display->cdclk.max_cdclk_freq = 450000; 3471 else if (display->platform.broadwell_ult) 3472 display->cdclk.max_cdclk_freq = 540000; 3473 else 3474 display->cdclk.max_cdclk_freq = 675000; 3475 } else if (display->platform.cherryview) { 3476 display->cdclk.max_cdclk_freq = 320000; 3477 } else if (display->platform.valleyview) { 3478 display->cdclk.max_cdclk_freq = 400000; 3479 } else { 3480 /* otherwise assume cdclk is fixed */ 3481 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; 3482 } 3483 3484 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); 3485 3486 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", 3487 display->cdclk.max_cdclk_freq); 3488 3489 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", 3490 display->cdclk.max_dotclk_freq); 3491 } 3492 3493 /** 3494 * intel_update_cdclk - Determine the current CDCLK frequency 3495 * @display: display instance 3496 * 3497 * Determine the current CDCLK frequency. 3498 */ 3499 void intel_update_cdclk(struct intel_display *display) 3500 { 3501 intel_cdclk_get_cdclk(display, &display->cdclk.hw); 3502 3503 /* 3504 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): 3505 * Programmng [sic] note: bit[9:2] should be programmed to the number 3506 * of cdclk that generates 4MHz reference clock freq which is used to 3507 * generate GMBus clock. This will vary with the cdclk freq. 3508 */ 3509 if (display->platform.valleyview || display->platform.cherryview) 3510 intel_de_write(display, GMBUSFREQ_VLV, 3511 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); 3512 } 3513 3514 static int dg1_rawclk(struct intel_display *display) 3515 { 3516 /* 3517 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us 3518 * "Program Numerator=2, Denominator=4, Divider=37 decimal." 3519 */ 3520 intel_de_write(display, PCH_RAWCLK_FREQ, 3521 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); 3522 3523 return 38400; 3524 } 3525 3526 static int cnp_rawclk(struct intel_display *display) 3527 { 3528 int divider, fraction; 3529 u32 rawclk; 3530 3531 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { 3532 /* 24 MHz */ 3533 divider = 24000; 3534 fraction = 0; 3535 } else { 3536 /* 19.2 MHz */ 3537 divider = 19000; 3538 fraction = 200; 3539 } 3540 3541 rawclk = CNP_RAWCLK_DIV(divider / 1000); 3542 if (fraction) { 3543 int numerator = 1; 3544 3545 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000, 3546 fraction) - 1); 3547 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 3548 rawclk |= ICP_RAWCLK_NUM(numerator); 3549 } 3550 3551 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); 3552 return divider + fraction; 3553 } 3554 3555 static int pch_rawclk(struct intel_display *display) 3556 { 3557 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; 3558 } 3559 3560 static int vlv_hrawclk(struct intel_display *display) 3561 { 3562 /* RAWCLK_FREQ_VLV register updated from power well code */ 3563 return vlv_get_cck_clock_hpll(display->drm, "hrawclk", 3564 CCK_DISPLAY_REF_CLOCK_CONTROL); 3565 } 3566 3567 static int i9xx_hrawclk(struct intel_display *display) 3568 { 3569 struct drm_i915_private *i915 = to_i915(display->drm); 3570 3571 /* hrawclock is 1/4 the FSB frequency */ 3572 return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); 3573 } 3574 3575 /** 3576 * intel_read_rawclk - Determine the current RAWCLK frequency 3577 * @display: display instance 3578 * 3579 * Determine the current RAWCLK frequency. RAWCLK is a fixed 3580 * frequency clock so this needs to done only once. 3581 */ 3582 u32 intel_read_rawclk(struct intel_display *display) 3583 { 3584 u32 freq; 3585 3586 if (INTEL_PCH_TYPE(display) >= PCH_MTL) 3587 /* 3588 * MTL always uses a 38.4 MHz rawclk. The bspec tells us 3589 * "RAWCLK_FREQ defaults to the values for 38.4 and does 3590 * not need to be programmed." 3591 */ 3592 freq = 38400; 3593 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 3594 freq = dg1_rawclk(display); 3595 else if (INTEL_PCH_TYPE(display) >= PCH_CNP) 3596 freq = cnp_rawclk(display); 3597 else if (HAS_PCH_SPLIT(display)) 3598 freq = pch_rawclk(display); 3599 else if (display->platform.valleyview || display->platform.cherryview) 3600 freq = vlv_hrawclk(display); 3601 else if (DISPLAY_VER(display) >= 3) 3602 freq = i9xx_hrawclk(display); 3603 else 3604 /* no rawclk on other platforms, or no need to know it */ 3605 return 0; 3606 3607 return freq; 3608 } 3609 3610 static int i915_cdclk_info_show(struct seq_file *m, void *unused) 3611 { 3612 struct intel_display *display = m->private; 3613 3614 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); 3615 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); 3616 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); 3617 3618 return 0; 3619 } 3620 3621 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); 3622 3623 void intel_cdclk_debugfs_register(struct intel_display *display) 3624 { 3625 struct drm_minor *minor = display->drm->primary; 3626 3627 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, 3628 display, &i915_cdclk_info_fops); 3629 } 3630 3631 static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = { 3632 .get_cdclk = bxt_get_cdclk, 3633 .set_cdclk = bxt_set_cdclk, 3634 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3635 .calc_voltage_level = xe3lpd_calc_voltage_level, 3636 }; 3637 3638 static const struct intel_cdclk_funcs rplu_cdclk_funcs = { 3639 .get_cdclk = bxt_get_cdclk, 3640 .set_cdclk = bxt_set_cdclk, 3641 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3642 .calc_voltage_level = rplu_calc_voltage_level, 3643 }; 3644 3645 static const struct intel_cdclk_funcs tgl_cdclk_funcs = { 3646 .get_cdclk = bxt_get_cdclk, 3647 .set_cdclk = bxt_set_cdclk, 3648 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3649 .calc_voltage_level = tgl_calc_voltage_level, 3650 }; 3651 3652 static const struct intel_cdclk_funcs ehl_cdclk_funcs = { 3653 .get_cdclk = bxt_get_cdclk, 3654 .set_cdclk = bxt_set_cdclk, 3655 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3656 .calc_voltage_level = ehl_calc_voltage_level, 3657 }; 3658 3659 static const struct intel_cdclk_funcs icl_cdclk_funcs = { 3660 .get_cdclk = bxt_get_cdclk, 3661 .set_cdclk = bxt_set_cdclk, 3662 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3663 .calc_voltage_level = icl_calc_voltage_level, 3664 }; 3665 3666 static const struct intel_cdclk_funcs bxt_cdclk_funcs = { 3667 .get_cdclk = bxt_get_cdclk, 3668 .set_cdclk = bxt_set_cdclk, 3669 .modeset_calc_cdclk = bxt_modeset_calc_cdclk, 3670 .calc_voltage_level = bxt_calc_voltage_level, 3671 }; 3672 3673 static const struct intel_cdclk_funcs skl_cdclk_funcs = { 3674 .get_cdclk = skl_get_cdclk, 3675 .set_cdclk = skl_set_cdclk, 3676 .modeset_calc_cdclk = skl_modeset_calc_cdclk, 3677 }; 3678 3679 static const struct intel_cdclk_funcs bdw_cdclk_funcs = { 3680 .get_cdclk = bdw_get_cdclk, 3681 .set_cdclk = bdw_set_cdclk, 3682 .modeset_calc_cdclk = bdw_modeset_calc_cdclk, 3683 }; 3684 3685 static const struct intel_cdclk_funcs chv_cdclk_funcs = { 3686 .get_cdclk = vlv_get_cdclk, 3687 .set_cdclk = chv_set_cdclk, 3688 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3689 }; 3690 3691 static const struct intel_cdclk_funcs vlv_cdclk_funcs = { 3692 .get_cdclk = vlv_get_cdclk, 3693 .set_cdclk = vlv_set_cdclk, 3694 .modeset_calc_cdclk = vlv_modeset_calc_cdclk, 3695 }; 3696 3697 static const struct intel_cdclk_funcs hsw_cdclk_funcs = { 3698 .get_cdclk = hsw_get_cdclk, 3699 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3700 }; 3701 3702 /* SNB, IVB, 965G, 945G */ 3703 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = { 3704 .get_cdclk = fixed_400mhz_get_cdclk, 3705 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3706 }; 3707 3708 static const struct intel_cdclk_funcs ilk_cdclk_funcs = { 3709 .get_cdclk = fixed_450mhz_get_cdclk, 3710 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3711 }; 3712 3713 static const struct intel_cdclk_funcs gm45_cdclk_funcs = { 3714 .get_cdclk = gm45_get_cdclk, 3715 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3716 }; 3717 3718 /* G45 uses G33 */ 3719 3720 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = { 3721 .get_cdclk = i965gm_get_cdclk, 3722 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3723 }; 3724 3725 /* i965G uses fixed 400 */ 3726 3727 static const struct intel_cdclk_funcs pnv_cdclk_funcs = { 3728 .get_cdclk = pnv_get_cdclk, 3729 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3730 }; 3731 3732 static const struct intel_cdclk_funcs g33_cdclk_funcs = { 3733 .get_cdclk = g33_get_cdclk, 3734 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3735 }; 3736 3737 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = { 3738 .get_cdclk = i945gm_get_cdclk, 3739 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3740 }; 3741 3742 /* i945G uses fixed 400 */ 3743 3744 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = { 3745 .get_cdclk = i915gm_get_cdclk, 3746 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3747 }; 3748 3749 static const struct intel_cdclk_funcs i915g_cdclk_funcs = { 3750 .get_cdclk = fixed_333mhz_get_cdclk, 3751 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3752 }; 3753 3754 static const struct intel_cdclk_funcs i865g_cdclk_funcs = { 3755 .get_cdclk = fixed_266mhz_get_cdclk, 3756 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3757 }; 3758 3759 static const struct intel_cdclk_funcs i85x_cdclk_funcs = { 3760 .get_cdclk = i85x_get_cdclk, 3761 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3762 }; 3763 3764 static const struct intel_cdclk_funcs i845g_cdclk_funcs = { 3765 .get_cdclk = fixed_200mhz_get_cdclk, 3766 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3767 }; 3768 3769 static const struct intel_cdclk_funcs i830_cdclk_funcs = { 3770 .get_cdclk = fixed_133mhz_get_cdclk, 3771 .modeset_calc_cdclk = fixed_modeset_calc_cdclk, 3772 }; 3773 3774 /** 3775 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks 3776 * @display: display instance 3777 */ 3778 void intel_init_cdclk_hooks(struct intel_display *display) 3779 { 3780 if (DISPLAY_VER(display) >= 30) { 3781 display->funcs.cdclk = &xe3lpd_cdclk_funcs; 3782 display->cdclk.table = xe3lpd_cdclk_table; 3783 } else if (DISPLAY_VER(display) >= 20) { 3784 display->funcs.cdclk = &rplu_cdclk_funcs; 3785 display->cdclk.table = xe2lpd_cdclk_table; 3786 } else if (DISPLAY_VERx100(display) >= 1401) { 3787 display->funcs.cdclk = &rplu_cdclk_funcs; 3788 display->cdclk.table = xe2hpd_cdclk_table; 3789 } else if (DISPLAY_VER(display) >= 14) { 3790 display->funcs.cdclk = &rplu_cdclk_funcs; 3791 display->cdclk.table = mtl_cdclk_table; 3792 } else if (display->platform.dg2) { 3793 display->funcs.cdclk = &tgl_cdclk_funcs; 3794 display->cdclk.table = dg2_cdclk_table; 3795 } else if (display->platform.alderlake_p) { 3796 /* Wa_22011320316:adl-p[a0] */ 3797 if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { 3798 display->cdclk.table = adlp_a_step_cdclk_table; 3799 display->funcs.cdclk = &tgl_cdclk_funcs; 3800 } else if (display->platform.alderlake_p_raptorlake_u) { 3801 display->cdclk.table = rplu_cdclk_table; 3802 display->funcs.cdclk = &rplu_cdclk_funcs; 3803 } else { 3804 display->cdclk.table = adlp_cdclk_table; 3805 display->funcs.cdclk = &tgl_cdclk_funcs; 3806 } 3807 } else if (display->platform.rocketlake) { 3808 display->funcs.cdclk = &tgl_cdclk_funcs; 3809 display->cdclk.table = rkl_cdclk_table; 3810 } else if (DISPLAY_VER(display) >= 12) { 3811 display->funcs.cdclk = &tgl_cdclk_funcs; 3812 display->cdclk.table = icl_cdclk_table; 3813 } else if (display->platform.jasperlake || display->platform.elkhartlake) { 3814 display->funcs.cdclk = &ehl_cdclk_funcs; 3815 display->cdclk.table = icl_cdclk_table; 3816 } else if (DISPLAY_VER(display) >= 11) { 3817 display->funcs.cdclk = &icl_cdclk_funcs; 3818 display->cdclk.table = icl_cdclk_table; 3819 } else if (display->platform.geminilake || display->platform.broxton) { 3820 display->funcs.cdclk = &bxt_cdclk_funcs; 3821 if (display->platform.geminilake) 3822 display->cdclk.table = glk_cdclk_table; 3823 else 3824 display->cdclk.table = bxt_cdclk_table; 3825 } else if (DISPLAY_VER(display) == 9) { 3826 display->funcs.cdclk = &skl_cdclk_funcs; 3827 } else if (display->platform.broadwell) { 3828 display->funcs.cdclk = &bdw_cdclk_funcs; 3829 } else if (display->platform.haswell) { 3830 display->funcs.cdclk = &hsw_cdclk_funcs; 3831 } else if (display->platform.cherryview) { 3832 display->funcs.cdclk = &chv_cdclk_funcs; 3833 } else if (display->platform.valleyview) { 3834 display->funcs.cdclk = &vlv_cdclk_funcs; 3835 } else if (display->platform.sandybridge || display->platform.ivybridge) { 3836 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3837 } else if (display->platform.ironlake) { 3838 display->funcs.cdclk = &ilk_cdclk_funcs; 3839 } else if (display->platform.gm45) { 3840 display->funcs.cdclk = &gm45_cdclk_funcs; 3841 } else if (display->platform.g45) { 3842 display->funcs.cdclk = &g33_cdclk_funcs; 3843 } else if (display->platform.i965gm) { 3844 display->funcs.cdclk = &i965gm_cdclk_funcs; 3845 } else if (display->platform.i965g) { 3846 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3847 } else if (display->platform.pineview) { 3848 display->funcs.cdclk = &pnv_cdclk_funcs; 3849 } else if (display->platform.g33) { 3850 display->funcs.cdclk = &g33_cdclk_funcs; 3851 } else if (display->platform.i945gm) { 3852 display->funcs.cdclk = &i945gm_cdclk_funcs; 3853 } else if (display->platform.i945g) { 3854 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; 3855 } else if (display->platform.i915gm) { 3856 display->funcs.cdclk = &i915gm_cdclk_funcs; 3857 } else if (display->platform.i915g) { 3858 display->funcs.cdclk = &i915g_cdclk_funcs; 3859 } else if (display->platform.i865g) { 3860 display->funcs.cdclk = &i865g_cdclk_funcs; 3861 } else if (display->platform.i85x) { 3862 display->funcs.cdclk = &i85x_cdclk_funcs; 3863 } else if (display->platform.i845g) { 3864 display->funcs.cdclk = &i845g_cdclk_funcs; 3865 } else if (display->platform.i830) { 3866 display->funcs.cdclk = &i830_cdclk_funcs; 3867 } 3868 3869 if (drm_WARN(display->drm, !display->funcs.cdclk, 3870 "Unknown platform. Assuming i830\n")) 3871 display->funcs.cdclk = &i830_cdclk_funcs; 3872 } 3873 3874 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state) 3875 { 3876 return cdclk_state->logical.cdclk; 3877 } 3878 3879 int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state) 3880 { 3881 return cdclk_state->actual.cdclk; 3882 } 3883 3884 int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state) 3885 { 3886 return cdclk_state->actual.voltage_level; 3887 } 3888 3889 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe) 3890 { 3891 return cdclk_state->min_cdclk[pipe]; 3892 } 3893 3894 int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state) 3895 { 3896 return cdclk_state->bw_min_cdclk; 3897 } 3898 3899 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state) 3900 { 3901 const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state; 3902 3903 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); 3904 old_cdclk_state = intel_atomic_get_old_cdclk_state(state); 3905 3906 if (new_cdclk_state && 3907 (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk || 3908 new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level)) 3909 return true; 3910 3911 return false; 3912 } 3913 3914 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk) 3915 { 3916 cdclk_state->force_min_cdclk = force_min_cdclk; 3917 } 3918 3919 void intel_cdclk_read_hw(struct intel_display *display) 3920 { 3921 struct intel_cdclk_state *cdclk_state; 3922 3923 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); 3924 3925 intel_update_cdclk(display); 3926 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); 3927 cdclk_state->actual = display->cdclk.hw; 3928 cdclk_state->logical = display->cdclk.hw; 3929 } 3930