1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2025 Intel Corporation 4 */ 5 6 #ifndef __INTEL_CASF_REGS_H__ 7 #define __INTEL_CASF_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 #define _SHARPNESS_CTL_A 0x682B0 12 #define _SHARPNESS_CTL_B 0x68AB0 13 #define SHARPNESS_CTL(pipe) _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B) 14 #define FILTER_EN REG_BIT(31) 15 #define FILTER_STRENGTH_MASK REG_GENMASK(15, 8) 16 #define FILTER_STRENGTH(x) REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x)) 17 #define FILTER_SIZE_MASK REG_GENMASK(1, 0) 18 #define SHARPNESS_FILTER_SIZE_3X3 REG_FIELD_PREP(FILTER_SIZE_MASK, 0) 19 #define SHARPNESS_FILTER_SIZE_5X5 REG_FIELD_PREP(FILTER_SIZE_MASK, 1) 20 #define SHARPNESS_FILTER_SIZE_7X7 REG_FIELD_PREP(FILTER_SIZE_MASK, 2) 21 22 #define _SHRPLUT_DATA_A 0x682B8 23 #define _SHRPLUT_DATA_B 0x68AB8 24 #define SHRPLUT_DATA(pipe) _MMIO_PIPE(pipe, _SHRPLUT_DATA_A, _SHRPLUT_DATA_B) 25 26 #define _SHRPLUT_INDEX_A 0x682B4 27 #define _SHRPLUT_INDEX_B 0x68AB4 28 #define SHRPLUT_INDEX(pipe) _MMIO_PIPE(pipe, _SHRPLUT_INDEX_A, _SHRPLUT_INDEX_B) 29 #define INDEX_AUTO_INCR REG_BIT(10) 30 #define INDEX_VALUE_MASK REG_GENMASK(4, 0) 31 #define INDEX_VALUE(x) REG_FIELD_PREP(INDEX_VALUE_MASK, (x)) 32 33 #endif /* __INTEL_CASF_REGS__ */ 34