174ad9ec9SNemesa Garg /* SPDX-License-Identifier: MIT */ 274ad9ec9SNemesa Garg /* 374ad9ec9SNemesa Garg * Copyright © 2025 Intel Corporation 474ad9ec9SNemesa Garg */ 574ad9ec9SNemesa Garg 674ad9ec9SNemesa Garg #ifndef __INTEL_CASF_REGS_H__ 774ad9ec9SNemesa Garg #define __INTEL_CASF_REGS_H__ 874ad9ec9SNemesa Garg 974ad9ec9SNemesa Garg #include "intel_display_reg_defs.h" 1074ad9ec9SNemesa Garg 1174ad9ec9SNemesa Garg #define _SHARPNESS_CTL_A 0x682B0 1274ad9ec9SNemesa Garg #define _SHARPNESS_CTL_B 0x68AB0 1374ad9ec9SNemesa Garg #define SHARPNESS_CTL(pipe) _MMIO_PIPE(pipe, _SHARPNESS_CTL_A, _SHARPNESS_CTL_B) 1474ad9ec9SNemesa Garg #define FILTER_EN REG_BIT(31) 1574ad9ec9SNemesa Garg #define FILTER_STRENGTH_MASK REG_GENMASK(15, 8) 1674ad9ec9SNemesa Garg #define FILTER_STRENGTH(x) REG_FIELD_PREP(FILTER_STRENGTH_MASK, (x)) 1774ad9ec9SNemesa Garg #define FILTER_SIZE_MASK REG_GENMASK(1, 0) 1874ad9ec9SNemesa Garg #define SHARPNESS_FILTER_SIZE_3X3 REG_FIELD_PREP(FILTER_SIZE_MASK, 0) 1974ad9ec9SNemesa Garg #define SHARPNESS_FILTER_SIZE_5X5 REG_FIELD_PREP(FILTER_SIZE_MASK, 1) 2074ad9ec9SNemesa Garg #define SHARPNESS_FILTER_SIZE_7X7 REG_FIELD_PREP(FILTER_SIZE_MASK, 2) 2174ad9ec9SNemesa Garg 22*515d1c89SNemesa Garg #define _SHRPLUT_DATA_A 0x682B8 23*515d1c89SNemesa Garg #define _SHRPLUT_DATA_B 0x68AB8 24*515d1c89SNemesa Garg #define SHRPLUT_DATA(pipe) _MMIO_PIPE(pipe, _SHRPLUT_DATA_A, _SHRPLUT_DATA_B) 25*515d1c89SNemesa Garg 26*515d1c89SNemesa Garg #define _SHRPLUT_INDEX_A 0x682B4 27*515d1c89SNemesa Garg #define _SHRPLUT_INDEX_B 0x68AB4 28*515d1c89SNemesa Garg #define SHRPLUT_INDEX(pipe) _MMIO_PIPE(pipe, _SHRPLUT_INDEX_A, _SHRPLUT_INDEX_B) 29*515d1c89SNemesa Garg #define INDEX_AUTO_INCR REG_BIT(10) 30*515d1c89SNemesa Garg #define INDEX_VALUE_MASK REG_GENMASK(4, 0) 31*515d1c89SNemesa Garg #define INDEX_VALUE(x) REG_FIELD_PREP(INDEX_VALUE_MASK, (x)) 32*515d1c89SNemesa Garg 3374ad9ec9SNemesa Garg #endif /* __INTEL_CASF_REGS__ */ 34