1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_BW_H__ 7 #define __INTEL_BW_H__ 8 9 #include <drm/drm_atomic.h> 10 11 #include "intel_display_limits.h" 12 #include "intel_display_power.h" 13 #include "intel_global_state.h" 14 15 struct intel_atomic_state; 16 struct intel_crtc; 17 struct intel_crtc_state; 18 struct intel_display; 19 20 struct intel_dbuf_bw { 21 unsigned int max_bw[I915_MAX_DBUF_SLICES]; 22 u8 active_planes[I915_MAX_DBUF_SLICES]; 23 }; 24 25 struct intel_bw_state { 26 struct intel_global_state base; 27 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES]; 28 29 /* 30 * Contains a bit mask, used to determine, whether correspondent 31 * pipe allows SAGV or not. 32 */ 33 u8 pipe_sagv_reject; 34 35 /* bitmask of active pipes */ 36 u8 active_pipes; 37 38 /* 39 * From MTL onwards, to lock a QGV point, punit expects the peak BW of 40 * the selected QGV point as the parameter in multiples of 100MB/s 41 */ 42 u16 qgv_point_peakbw; 43 44 /* 45 * Current QGV points mask, which restricts 46 * some particular SAGV states, not to confuse 47 * with pipe_sagv_mask. 48 */ 49 u16 qgv_points_mask; 50 51 unsigned int data_rate[I915_MAX_PIPES]; 52 u8 num_active_planes[I915_MAX_PIPES]; 53 }; 54 55 #define to_intel_bw_state(global_state) \ 56 container_of_const((global_state), struct intel_bw_state, base) 57 58 struct intel_bw_state * 59 intel_atomic_get_old_bw_state(struct intel_atomic_state *state); 60 61 struct intel_bw_state * 62 intel_atomic_get_new_bw_state(struct intel_atomic_state *state); 63 64 struct intel_bw_state * 65 intel_atomic_get_bw_state(struct intel_atomic_state *state); 66 67 void intel_bw_init_hw(struct intel_display *display); 68 int intel_bw_init(struct intel_display *display); 69 int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms); 70 int icl_pcode_restrict_qgv_points(struct intel_display *display, 71 u32 points_mask); 72 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, 73 bool *need_cdclk_calc); 74 int intel_bw_min_cdclk(struct intel_display *display, 75 const struct intel_bw_state *bw_state); 76 void intel_bw_update_hw_state(struct intel_display *display); 77 void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc); 78 79 #endif /* __INTEL_BW_H__ */ 80