1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/drm_eld.h> 29 #include <drm/drm_fixed.h> 30 #include <drm/drm_print.h> 31 #include <drm/intel/i915_component.h> 32 33 #include "intel_atomic.h" 34 #include "intel_audio.h" 35 #include "intel_audio_regs.h" 36 #include "intel_cdclk.h" 37 #include "intel_crtc.h" 38 #include "intel_de.h" 39 #include "intel_display_types.h" 40 #include "intel_lpe_audio.h" 41 42 /** 43 * DOC: High Definition Audio over HDMI and Display Port 44 * 45 * The graphics and audio drivers together support High Definition Audio over 46 * HDMI and Display Port. The audio programming sequences are divided into audio 47 * codec and controller enable and disable sequences. The graphics driver 48 * handles the audio codec sequences, while the audio driver handles the audio 49 * controller sequences. 50 * 51 * The disable sequences must be performed before disabling the transcoder or 52 * port. The enable sequences may only be performed after enabling the 53 * transcoder and port, and after completed link training. Therefore the audio 54 * enable/disable sequences are part of the modeset sequence. 55 * 56 * The codec and controller sequences could be done either parallel or serial, 57 * but generally the ELDV/PD change in the codec sequence indicates to the audio 58 * driver that the controller sequence should start. Indeed, most of the 59 * co-operation between the graphics and audio drivers is handled via audio 60 * related registers. (The notable exception is the power management, not 61 * covered here.) 62 * 63 * The struct &i915_audio_component is used to interact between the graphics 64 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 65 * defined in graphics driver and called in audio driver. The 66 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 67 */ 68 69 struct intel_audio_funcs { 70 void (*audio_codec_enable)(struct intel_encoder *encoder, 71 const struct intel_crtc_state *crtc_state, 72 const struct drm_connector_state *conn_state); 73 void (*audio_codec_disable)(struct intel_encoder *encoder, 74 const struct intel_crtc_state *old_crtc_state, 75 const struct drm_connector_state *old_conn_state); 76 void (*audio_codec_get_config)(struct intel_encoder *encoder, 77 struct intel_crtc_state *crtc_state); 78 }; 79 80 struct hdmi_aud_ncts { 81 int sample_rate; 82 int clock; 83 int n; 84 int cts; 85 }; 86 87 static const struct { 88 int clock; 89 u32 config; 90 } hdmi_audio_clock[] = { 91 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 92 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 93 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 94 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 95 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 96 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 97 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 98 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 99 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 100 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 101 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 102 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 103 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 104 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 105 }; 106 107 /* HDMI N/CTS table */ 108 #define TMDS_297M 297000 109 #define TMDS_296M 296703 110 #define TMDS_594M 594000 111 #define TMDS_593M 593407 112 113 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 114 { 32000, TMDS_296M, 5824, 421875 }, 115 { 32000, TMDS_297M, 3072, 222750 }, 116 { 32000, TMDS_593M, 5824, 843750 }, 117 { 32000, TMDS_594M, 3072, 445500 }, 118 { 44100, TMDS_296M, 4459, 234375 }, 119 { 44100, TMDS_297M, 4704, 247500 }, 120 { 44100, TMDS_593M, 8918, 937500 }, 121 { 44100, TMDS_594M, 9408, 990000 }, 122 { 88200, TMDS_296M, 8918, 234375 }, 123 { 88200, TMDS_297M, 9408, 247500 }, 124 { 88200, TMDS_593M, 17836, 937500 }, 125 { 88200, TMDS_594M, 18816, 990000 }, 126 { 176400, TMDS_296M, 17836, 234375 }, 127 { 176400, TMDS_297M, 18816, 247500 }, 128 { 176400, TMDS_593M, 35672, 937500 }, 129 { 176400, TMDS_594M, 37632, 990000 }, 130 { 48000, TMDS_296M, 5824, 281250 }, 131 { 48000, TMDS_297M, 5120, 247500 }, 132 { 48000, TMDS_593M, 5824, 562500 }, 133 { 48000, TMDS_594M, 6144, 594000 }, 134 { 96000, TMDS_296M, 11648, 281250 }, 135 { 96000, TMDS_297M, 10240, 247500 }, 136 { 96000, TMDS_593M, 11648, 562500 }, 137 { 96000, TMDS_594M, 12288, 594000 }, 138 { 192000, TMDS_296M, 23296, 281250 }, 139 { 192000, TMDS_297M, 20480, 247500 }, 140 { 192000, TMDS_593M, 23296, 562500 }, 141 { 192000, TMDS_594M, 24576, 594000 }, 142 }; 143 144 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 145 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 146 #define TMDS_371M 371250 147 #define TMDS_370M 370878 148 149 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 150 { 32000, TMDS_370M, 5824, 527344 }, 151 { 32000, TMDS_371M, 6144, 556875 }, 152 { 44100, TMDS_370M, 8918, 585938 }, 153 { 44100, TMDS_371M, 4704, 309375 }, 154 { 88200, TMDS_370M, 17836, 585938 }, 155 { 88200, TMDS_371M, 9408, 309375 }, 156 { 176400, TMDS_370M, 35672, 585938 }, 157 { 176400, TMDS_371M, 18816, 309375 }, 158 { 48000, TMDS_370M, 11648, 703125 }, 159 { 48000, TMDS_371M, 5120, 309375 }, 160 { 96000, TMDS_370M, 23296, 703125 }, 161 { 96000, TMDS_371M, 10240, 309375 }, 162 { 192000, TMDS_370M, 46592, 703125 }, 163 { 192000, TMDS_371M, 20480, 309375 }, 164 }; 165 166 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 167 #define TMDS_445_5M 445500 168 #define TMDS_445M 445054 169 170 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 171 { 32000, TMDS_445M, 5824, 632813 }, 172 { 32000, TMDS_445_5M, 4096, 445500 }, 173 { 44100, TMDS_445M, 8918, 703125 }, 174 { 44100, TMDS_445_5M, 4704, 371250 }, 175 { 88200, TMDS_445M, 17836, 703125 }, 176 { 88200, TMDS_445_5M, 9408, 371250 }, 177 { 176400, TMDS_445M, 35672, 703125 }, 178 { 176400, TMDS_445_5M, 18816, 371250 }, 179 { 48000, TMDS_445M, 5824, 421875 }, 180 { 48000, TMDS_445_5M, 5120, 371250 }, 181 { 96000, TMDS_445M, 11648, 421875 }, 182 { 96000, TMDS_445_5M, 10240, 371250 }, 183 { 192000, TMDS_445M, 23296, 421875 }, 184 { 192000, TMDS_445_5M, 20480, 371250 }, 185 }; 186 187 /* 188 * WA_14020863754: Implement Audio Workaround 189 * Corner case with Min Hblank Fix can cause audio hang 190 */ 191 static bool needs_wa_14020863754(struct intel_display *display) 192 { 193 return DISPLAY_VERx100(display) == 3000 || 194 DISPLAY_VERx100(display) == 2000 || 195 DISPLAY_VERx100(display) == 1401; 196 } 197 198 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 199 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 200 { 201 struct intel_display *display = to_intel_display(crtc_state); 202 const struct drm_display_mode *adjusted_mode = 203 &crtc_state->hw.adjusted_mode; 204 int i; 205 206 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 207 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 208 break; 209 } 210 211 if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500) 212 i = ARRAY_SIZE(hdmi_audio_clock); 213 214 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 215 drm_dbg_kms(display->drm, 216 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 217 adjusted_mode->crtc_clock); 218 i = 1; 219 } 220 221 drm_dbg_kms(display->drm, 222 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 223 hdmi_audio_clock[i].clock, 224 hdmi_audio_clock[i].config); 225 226 return hdmi_audio_clock[i].config; 227 } 228 229 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 230 int rate) 231 { 232 const struct hdmi_aud_ncts *hdmi_ncts_table; 233 int i, size; 234 235 if (crtc_state->pipe_bpp == 36) { 236 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 237 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 238 } else if (crtc_state->pipe_bpp == 30) { 239 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 240 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 241 } else { 242 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 243 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 244 } 245 246 for (i = 0; i < size; i++) { 247 if (rate == hdmi_ncts_table[i].sample_rate && 248 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 249 return hdmi_ncts_table[i].n; 250 } 251 } 252 return 0; 253 } 254 255 /* ELD buffer size in dwords */ 256 static int g4x_eld_buffer_size(struct intel_display *display) 257 { 258 u32 tmp; 259 260 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); 261 262 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); 263 } 264 265 static void g4x_audio_codec_get_config(struct intel_encoder *encoder, 266 struct intel_crtc_state *crtc_state) 267 { 268 struct intel_display *display = to_intel_display(encoder); 269 u32 *eld = (u32 *)crtc_state->eld; 270 int eld_buffer_size, len, i; 271 u32 tmp; 272 273 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); 274 if ((tmp & G4X_ELD_VALID) == 0) 275 return; 276 277 intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); 278 279 eld_buffer_size = g4x_eld_buffer_size(display); 280 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size); 281 282 for (i = 0; i < len; i++) 283 eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID); 284 } 285 286 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 287 const struct intel_crtc_state *old_crtc_state, 288 const struct drm_connector_state *old_conn_state) 289 { 290 struct intel_display *display = to_intel_display(encoder); 291 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 292 293 /* Invalidate ELD */ 294 intel_de_rmw(display, G4X_AUD_CNTL_ST, 295 G4X_ELD_VALID, 0); 296 297 intel_crtc_wait_for_next_vblank(crtc); 298 intel_crtc_wait_for_next_vblank(crtc); 299 } 300 301 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 302 const struct intel_crtc_state *crtc_state, 303 const struct drm_connector_state *conn_state) 304 { 305 struct intel_display *display = to_intel_display(encoder); 306 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 307 const u32 *eld = (const u32 *)crtc_state->eld; 308 int eld_buffer_size, len, i; 309 310 intel_crtc_wait_for_next_vblank(crtc); 311 312 intel_de_rmw(display, G4X_AUD_CNTL_ST, 313 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); 314 315 eld_buffer_size = g4x_eld_buffer_size(display); 316 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size); 317 318 for (i = 0; i < len; i++) 319 intel_de_write(display, G4X_HDMIW_HDMIEDID, eld[i]); 320 for (; i < eld_buffer_size; i++) 321 intel_de_write(display, G4X_HDMIW_HDMIEDID, 0); 322 323 drm_WARN_ON(display->drm, 324 (intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); 325 326 intel_de_rmw(display, G4X_AUD_CNTL_ST, 327 0, G4X_ELD_VALID); 328 } 329 330 static void 331 hsw_dp_audio_config_update(struct intel_encoder *encoder, 332 const struct intel_crtc_state *crtc_state) 333 { 334 struct intel_display *display = to_intel_display(encoder); 335 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 336 337 /* Enable time stamps. Let HW calculate Maud/Naud values */ 338 intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), 339 AUD_CONFIG_N_VALUE_INDEX | 340 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK | 341 AUD_CONFIG_UPPER_N_MASK | 342 AUD_CONFIG_LOWER_N_MASK | 343 AUD_CONFIG_N_PROG_ENABLE, 344 AUD_CONFIG_N_VALUE_INDEX); 345 346 } 347 348 static void 349 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 350 const struct intel_crtc_state *crtc_state) 351 { 352 struct intel_display *display = to_intel_display(encoder); 353 struct i915_audio_component *acomp = display->audio.component; 354 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 355 enum port port = encoder->port; 356 int n, rate; 357 u32 tmp; 358 359 rate = acomp ? acomp->aud_sample_rate[port] : 0; 360 361 tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder)); 362 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 363 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 364 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 365 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 366 367 n = audio_config_hdmi_get_n(crtc_state, rate); 368 if (n != 0) { 369 drm_dbg_kms(display->drm, "using N %d\n", n); 370 371 tmp &= ~AUD_CONFIG_N_MASK; 372 tmp |= AUD_CONFIG_N(n); 373 tmp |= AUD_CONFIG_N_PROG_ENABLE; 374 } else { 375 drm_dbg_kms(display->drm, "using automatic N\n"); 376 } 377 378 intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp); 379 380 /* 381 * Let's disable "Enable CTS or M Prog bit" 382 * and let HW calculate the value 383 */ 384 tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 385 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 386 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 387 intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 388 } 389 390 static void 391 hsw_audio_config_update(struct intel_encoder *encoder, 392 const struct intel_crtc_state *crtc_state) 393 { 394 if (intel_crtc_has_dp_encoder(crtc_state)) 395 hsw_dp_audio_config_update(encoder, crtc_state); 396 else 397 hsw_hdmi_audio_config_update(encoder, crtc_state); 398 } 399 400 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 401 const struct intel_crtc_state *old_crtc_state, 402 const struct drm_connector_state *old_conn_state) 403 { 404 struct intel_display *display = to_intel_display(encoder); 405 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 406 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 407 408 mutex_lock(&display->audio.mutex); 409 410 /* Disable timestamps */ 411 intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), 412 AUD_CONFIG_N_VALUE_INDEX | 413 AUD_CONFIG_UPPER_N_MASK | 414 AUD_CONFIG_LOWER_N_MASK, 415 AUD_CONFIG_N_PROG_ENABLE | 416 (intel_crtc_has_dp_encoder(old_crtc_state) ? 417 AUD_CONFIG_N_VALUE_INDEX : 0)); 418 419 /* Invalidate ELD */ 420 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 421 AUDIO_ELD_VALID(cpu_transcoder), 0); 422 423 intel_crtc_wait_for_next_vblank(crtc); 424 intel_crtc_wait_for_next_vblank(crtc); 425 426 /* Disable audio presence detect */ 427 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 428 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); 429 430 if (needs_wa_14020863754(display)) 431 intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); 432 433 mutex_unlock(&display->audio.mutex); 434 } 435 436 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 437 const struct intel_crtc_state *crtc_state) 438 { 439 struct intel_display *display = to_intel_display(encoder); 440 unsigned int link_clks_available, link_clks_required; 441 unsigned int tu_data, tu_line, link_clks_active; 442 unsigned int h_active, h_total, hblank_delta, pixel_clk; 443 unsigned int fec_coeff, cdclk, vdsc_bppx16; 444 unsigned int link_clk, lanes; 445 unsigned int hblank_rise; 446 447 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 448 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 449 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 450 vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16; 451 cdclk = display->cdclk.hw.cdclk; 452 /* fec= 0.972261, using rounding multiplier of 1000000 */ 453 fec_coeff = 972261; 454 link_clk = crtc_state->port_clock; 455 lanes = crtc_state->lane_count; 456 457 drm_dbg_kms(display->drm, 458 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n", 459 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); 460 461 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) 462 return 0; 463 464 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 465 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 466 467 if (link_clks_available > link_clks_required) 468 hblank_delta = 32; 469 else 470 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 471 mul_u32_u32(link_clk, cdclk)); 472 473 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), 474 mul_u32_u32(link_clk * lanes * 16, fec_coeff)); 475 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 476 mul_u32_u32(64 * pixel_clk, 1000000)); 477 link_clks_active = (tu_line - 1) * 64 + tu_data; 478 479 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 480 481 return h_active - hblank_rise + hblank_delta; 482 } 483 484 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 485 { 486 unsigned int h_active, h_total, pixel_clk; 487 unsigned int link_clk, lanes; 488 489 h_active = crtc_state->hw.adjusted_mode.hdisplay; 490 h_total = crtc_state->hw.adjusted_mode.htotal; 491 pixel_clk = crtc_state->hw.adjusted_mode.clock; 492 link_clk = crtc_state->port_clock; 493 lanes = crtc_state->lane_count; 494 495 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 496 (pixel_clk * (48 / lanes + 2)); 497 } 498 499 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 500 const struct intel_crtc_state *crtc_state) 501 { 502 struct intel_display *display = to_intel_display(encoder); 503 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 504 unsigned int hblank_early_prog, samples_room; 505 unsigned int val; 506 507 if (DISPLAY_VER(display) < 11) 508 return; 509 510 val = intel_de_read(display, AUD_CONFIG_BE); 511 512 if (DISPLAY_VER(display) == 11) 513 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder); 514 else if (DISPLAY_VER(display) >= 12) 515 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder); 516 517 if (crtc_state->dsc.compression_enable && 518 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 519 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 520 /* Get hblank early enable value required */ 521 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder); 522 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 523 if (hblank_early_prog < 32) 524 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32); 525 else if (hblank_early_prog < 64) 526 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64); 527 else if (hblank_early_prog < 96) 528 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96); 529 else 530 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128); 531 532 /* Get samples room value required */ 533 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder); 534 samples_room = calc_samples_room(crtc_state); 535 if (samples_room < 3) 536 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room); 537 else /* Program 0 i.e "All Samples available in buffer" */ 538 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0); 539 } 540 541 intel_de_write(display, AUD_CONFIG_BE, val); 542 } 543 544 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 545 const struct intel_crtc_state *crtc_state, 546 const struct drm_connector_state *conn_state) 547 { 548 struct intel_display *display = to_intel_display(encoder); 549 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 551 552 mutex_lock(&display->audio.mutex); 553 554 /* Enable Audio WA for 4k DSC usecases */ 555 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 556 enable_audio_dsc_wa(encoder, crtc_state); 557 558 if (needs_wa_14020863754(display)) 559 intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); 560 561 /* Enable audio presence detect */ 562 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 563 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); 564 565 intel_crtc_wait_for_next_vblank(crtc); 566 567 /* Invalidate ELD */ 568 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 569 AUDIO_ELD_VALID(cpu_transcoder), 0); 570 571 /* 572 * The audio component is used to convey the ELD 573 * instead using of the hardware ELD buffer. 574 */ 575 576 /* Enable timestamps */ 577 hsw_audio_config_update(encoder, crtc_state); 578 579 mutex_unlock(&display->audio.mutex); 580 } 581 582 struct ibx_audio_regs { 583 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 584 }; 585 586 static void ibx_audio_regs_init(struct intel_display *display, 587 enum pipe pipe, 588 struct ibx_audio_regs *regs) 589 { 590 if (display->platform.valleyview || display->platform.cherryview) { 591 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 592 regs->aud_config = VLV_AUD_CFG(pipe); 593 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 594 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 595 } else if (HAS_PCH_CPT(display)) { 596 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 597 regs->aud_config = CPT_AUD_CFG(pipe); 598 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 599 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 600 } else if (HAS_PCH_IBX(display)) { 601 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 602 regs->aud_config = IBX_AUD_CFG(pipe); 603 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 604 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 605 } 606 } 607 608 static void ibx_audio_codec_disable(struct intel_encoder *encoder, 609 const struct intel_crtc_state *old_crtc_state, 610 const struct drm_connector_state *old_conn_state) 611 { 612 struct intel_display *display = to_intel_display(encoder); 613 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 614 enum port port = encoder->port; 615 enum pipe pipe = crtc->pipe; 616 struct ibx_audio_regs regs; 617 618 if (drm_WARN_ON(display->drm, port == PORT_A)) 619 return; 620 621 ibx_audio_regs_init(display, pipe, ®s); 622 623 mutex_lock(&display->audio.mutex); 624 625 /* Disable timestamps */ 626 intel_de_rmw(display, regs.aud_config, 627 AUD_CONFIG_N_VALUE_INDEX | 628 AUD_CONFIG_UPPER_N_MASK | 629 AUD_CONFIG_LOWER_N_MASK, 630 AUD_CONFIG_N_PROG_ENABLE | 631 (intel_crtc_has_dp_encoder(old_crtc_state) ? 632 AUD_CONFIG_N_VALUE_INDEX : 0)); 633 634 /* Invalidate ELD */ 635 intel_de_rmw(display, regs.aud_cntrl_st2, 636 IBX_ELD_VALID(port), 0); 637 638 mutex_unlock(&display->audio.mutex); 639 640 intel_crtc_wait_for_next_vblank(crtc); 641 intel_crtc_wait_for_next_vblank(crtc); 642 } 643 644 static void ibx_audio_codec_enable(struct intel_encoder *encoder, 645 const struct intel_crtc_state *crtc_state, 646 const struct drm_connector_state *conn_state) 647 { 648 struct intel_display *display = to_intel_display(encoder); 649 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 650 enum port port = encoder->port; 651 enum pipe pipe = crtc->pipe; 652 struct ibx_audio_regs regs; 653 654 if (drm_WARN_ON(display->drm, port == PORT_A)) 655 return; 656 657 intel_crtc_wait_for_next_vblank(crtc); 658 659 ibx_audio_regs_init(display, pipe, ®s); 660 661 mutex_lock(&display->audio.mutex); 662 663 /* Invalidate ELD */ 664 intel_de_rmw(display, regs.aud_cntrl_st2, 665 IBX_ELD_VALID(port), 0); 666 667 /* 668 * The audio component is used to convey the ELD 669 * instead using of the hardware ELD buffer. 670 */ 671 672 /* Enable timestamps */ 673 intel_de_rmw(display, regs.aud_config, 674 AUD_CONFIG_N_VALUE_INDEX | 675 AUD_CONFIG_N_PROG_ENABLE | 676 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 677 (intel_crtc_has_dp_encoder(crtc_state) ? 678 AUD_CONFIG_N_VALUE_INDEX : 679 audio_config_hdmi_pixel_clock(crtc_state))); 680 681 mutex_unlock(&display->audio.mutex); 682 } 683 684 void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state) 685 { 686 struct intel_display *display = to_intel_display(crtc_state); 687 enum transcoder trans = crtc_state->cpu_transcoder; 688 689 if (HAS_DP20(display)) 690 intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 691 crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); 692 } 693 694 bool intel_audio_compute_config(struct intel_encoder *encoder, 695 struct intel_crtc_state *crtc_state, 696 struct drm_connector_state *conn_state) 697 { 698 struct intel_display *display = to_intel_display(encoder); 699 struct drm_connector *connector = conn_state->connector; 700 const struct drm_display_mode *adjusted_mode = 701 &crtc_state->hw.adjusted_mode; 702 703 mutex_lock(&connector->eld_mutex); 704 if (!connector->eld[0]) { 705 drm_dbg_kms(display->drm, 706 "Bogus ELD on [CONNECTOR:%d:%s]\n", 707 connector->base.id, connector->name); 708 mutex_unlock(&connector->eld_mutex); 709 return false; 710 } 711 712 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld)); 713 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); 714 715 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 716 mutex_unlock(&connector->eld_mutex); 717 718 return true; 719 } 720 721 /** 722 * intel_audio_codec_enable - Enable the audio codec for HD audio 723 * @encoder: encoder on which to enable audio 724 * @crtc_state: pointer to the current crtc state. 725 * @conn_state: pointer to the current connector state. 726 * 727 * The enable sequences may only be performed after enabling the transcoder and 728 * port, and after completed link training. 729 */ 730 void intel_audio_codec_enable(struct intel_encoder *encoder, 731 const struct intel_crtc_state *crtc_state, 732 const struct drm_connector_state *conn_state) 733 { 734 struct intel_display *display = to_intel_display(encoder); 735 struct i915_audio_component *acomp = display->audio.component; 736 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 737 struct intel_connector *connector = to_intel_connector(conn_state->connector); 738 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 739 struct intel_audio_state *audio_state; 740 enum port port = encoder->port; 741 742 if (!crtc_state->has_audio) 743 return; 744 745 drm_dbg_kms(display->drm, 746 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", 747 connector->base.base.id, connector->base.name, 748 encoder->base.base.id, encoder->base.name, 749 crtc->base.base.id, crtc->base.name, 750 drm_eld_size(crtc_state->eld)); 751 752 if (display->funcs.audio) 753 display->funcs.audio->audio_codec_enable(encoder, 754 crtc_state, 755 conn_state); 756 757 mutex_lock(&display->audio.mutex); 758 759 audio_state = &display->audio.state[cpu_transcoder]; 760 761 audio_state->encoder = encoder; 762 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld)); 763 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld)); 764 765 mutex_unlock(&display->audio.mutex); 766 767 if (acomp && acomp->base.audio_ops && 768 acomp->base.audio_ops->pin_eld_notify) { 769 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 770 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 771 cpu_transcoder = -1; 772 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 773 (int)port, (int)cpu_transcoder); 774 } 775 776 intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld, 777 crtc_state->port_clock, 778 intel_crtc_has_dp_encoder(crtc_state)); 779 } 780 781 /** 782 * intel_audio_codec_disable - Disable the audio codec for HD audio 783 * @encoder: encoder on which to disable audio 784 * @old_crtc_state: pointer to the old crtc state. 785 * @old_conn_state: pointer to the old connector state. 786 * 787 * The disable sequences must be performed before disabling the transcoder or 788 * port. 789 */ 790 void intel_audio_codec_disable(struct intel_encoder *encoder, 791 const struct intel_crtc_state *old_crtc_state, 792 const struct drm_connector_state *old_conn_state) 793 { 794 struct intel_display *display = to_intel_display(encoder); 795 struct i915_audio_component *acomp = display->audio.component; 796 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 797 struct intel_connector *connector = to_intel_connector(old_conn_state->connector); 798 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 799 struct intel_audio_state *audio_state; 800 enum port port = encoder->port; 801 802 if (!old_crtc_state->has_audio) 803 return; 804 805 drm_dbg_kms(display->drm, 806 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", 807 connector->base.base.id, connector->base.name, 808 encoder->base.base.id, encoder->base.name, 809 crtc->base.base.id, crtc->base.name); 810 811 if (display->funcs.audio) 812 display->funcs.audio->audio_codec_disable(encoder, 813 old_crtc_state, 814 old_conn_state); 815 816 mutex_lock(&display->audio.mutex); 817 818 audio_state = &display->audio.state[cpu_transcoder]; 819 820 audio_state->encoder = NULL; 821 memset(audio_state->eld, 0, sizeof(audio_state->eld)); 822 823 mutex_unlock(&display->audio.mutex); 824 825 if (acomp && acomp->base.audio_ops && 826 acomp->base.audio_ops->pin_eld_notify) { 827 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 828 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 829 cpu_transcoder = -1; 830 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 831 (int)port, (int)cpu_transcoder); 832 } 833 834 intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false); 835 } 836 837 static void intel_acomp_get_config(struct intel_encoder *encoder, 838 struct intel_crtc_state *crtc_state) 839 { 840 struct intel_display *display = to_intel_display(encoder); 841 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 842 struct intel_audio_state *audio_state; 843 844 mutex_lock(&display->audio.mutex); 845 846 audio_state = &display->audio.state[cpu_transcoder]; 847 848 if (audio_state->encoder) 849 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld)); 850 851 mutex_unlock(&display->audio.mutex); 852 } 853 854 void intel_audio_codec_get_config(struct intel_encoder *encoder, 855 struct intel_crtc_state *crtc_state) 856 { 857 struct intel_display *display = to_intel_display(encoder); 858 859 if (!crtc_state->has_audio) 860 return; 861 862 if (display->funcs.audio) 863 display->funcs.audio->audio_codec_get_config(encoder, crtc_state); 864 } 865 866 static const struct intel_audio_funcs g4x_audio_funcs = { 867 .audio_codec_enable = g4x_audio_codec_enable, 868 .audio_codec_disable = g4x_audio_codec_disable, 869 .audio_codec_get_config = g4x_audio_codec_get_config, 870 }; 871 872 static const struct intel_audio_funcs ibx_audio_funcs = { 873 .audio_codec_enable = ibx_audio_codec_enable, 874 .audio_codec_disable = ibx_audio_codec_disable, 875 .audio_codec_get_config = intel_acomp_get_config, 876 }; 877 878 static const struct intel_audio_funcs hsw_audio_funcs = { 879 .audio_codec_enable = hsw_audio_codec_enable, 880 .audio_codec_disable = hsw_audio_codec_disable, 881 .audio_codec_get_config = intel_acomp_get_config, 882 }; 883 884 /** 885 * intel_audio_hooks_init - Set up chip specific audio hooks 886 * @display: display device 887 */ 888 void intel_audio_hooks_init(struct intel_display *display) 889 { 890 if (display->platform.g4x) 891 display->funcs.audio = &g4x_audio_funcs; 892 else if (display->platform.valleyview || display->platform.cherryview || 893 HAS_PCH_CPT(display) || HAS_PCH_IBX(display)) 894 display->funcs.audio = &ibx_audio_funcs; 895 else if (display->platform.haswell || DISPLAY_VER(display) >= 8) 896 display->funcs.audio = &hsw_audio_funcs; 897 } 898 899 struct aud_ts_cdclk_m_n { 900 u8 m; 901 u16 n; 902 }; 903 904 void intel_audio_cdclk_change_pre(struct intel_display *display) 905 { 906 if (DISPLAY_VER(display) >= 13) 907 intel_de_rmw(display, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 908 } 909 910 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 911 { 912 aud_ts->m = 60; 913 aud_ts->n = cdclk * aud_ts->m / 24000; 914 } 915 916 void intel_audio_cdclk_change_post(struct intel_display *display) 917 { 918 struct aud_ts_cdclk_m_n aud_ts; 919 920 if (DISPLAY_VER(display) >= 13) { 921 get_aud_ts_cdclk_m_n(display->cdclk.hw.ref, 922 display->cdclk.hw.cdclk, &aud_ts); 923 924 intel_de_write(display, AUD_TS_CDCLK_N, aud_ts.n); 925 intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 926 drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n", 927 aud_ts.m, aud_ts.n); 928 } 929 } 930 931 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 932 struct intel_crtc *crtc, 933 bool enable) 934 { 935 struct intel_cdclk_state *cdclk_state; 936 int ret; 937 938 /* need to hold at least one crtc lock for the global state */ 939 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 940 if (ret) 941 return ret; 942 943 cdclk_state = intel_atomic_get_cdclk_state(state); 944 if (IS_ERR(cdclk_state)) 945 return PTR_ERR(cdclk_state); 946 947 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; 948 949 return drm_atomic_commit(&state->base); 950 } 951 952 static void glk_force_audio_cdclk(struct intel_display *display, 953 bool enable) 954 { 955 struct drm_modeset_acquire_ctx ctx; 956 struct drm_atomic_state *state; 957 struct intel_crtc *crtc; 958 int ret; 959 960 crtc = intel_first_crtc(display); 961 if (!crtc) 962 return; 963 964 drm_modeset_acquire_init(&ctx, 0); 965 state = drm_atomic_state_alloc(display->drm); 966 if (drm_WARN_ON(display->drm, !state)) 967 return; 968 969 state->acquire_ctx = &ctx; 970 to_intel_atomic_state(state)->internal = true; 971 972 retry: 973 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 974 enable); 975 if (ret == -EDEADLK) { 976 drm_atomic_state_clear(state); 977 drm_modeset_backoff(&ctx); 978 goto retry; 979 } 980 981 drm_WARN_ON(display->drm, ret); 982 983 drm_atomic_state_put(state); 984 985 drm_modeset_drop_locks(&ctx); 986 drm_modeset_acquire_fini(&ctx); 987 } 988 989 int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) 990 { 991 struct intel_display *display = to_intel_display(crtc_state); 992 int min_cdclk = 0; 993 994 if (!crtc_state->has_audio) 995 return 0; 996 997 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 998 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 999 * there may be audio corruption or screen corruption." This cdclk 1000 * restriction for GLK is 316.8 MHz. 1001 */ 1002 if (intel_crtc_has_dp_encoder(crtc_state) && 1003 crtc_state->port_clock >= 540000 && 1004 crtc_state->lane_count == 4) { 1005 if (DISPLAY_VER(display) == 10) { 1006 /* Display WA #1145: glk */ 1007 min_cdclk = max(min_cdclk, 316800); 1008 } else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) { 1009 /* Display WA #1144: skl,bxt */ 1010 min_cdclk = max(min_cdclk, 432000); 1011 } 1012 } 1013 1014 /* 1015 * According to BSpec, "The CD clock frequency must be at least twice 1016 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 1017 */ 1018 if (DISPLAY_VER(display) >= 9) 1019 min_cdclk = max(min_cdclk, 2 * 96000); 1020 1021 /* 1022 * "For DP audio configuration, cdclk frequency shall be set to 1023 * meet the following requirements: 1024 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 1025 * 270 | 320 or higher 1026 * 162 | 200 or higher" 1027 */ 1028 if ((display->platform.valleyview || display->platform.cherryview) && 1029 intel_crtc_has_dp_encoder(crtc_state)) 1030 min_cdclk = max(min_cdclk, crtc_state->port_clock); 1031 1032 return min_cdclk; 1033 } 1034 1035 static unsigned long intel_audio_component_get_power(struct device *kdev) 1036 { 1037 struct intel_display *display = to_intel_display(kdev); 1038 intel_wakeref_t wakeref; 1039 1040 /* Catch potential impedance mismatches before they occur! */ 1041 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 1042 1043 wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK); 1044 1045 if (display->audio.power_refcount++ == 0) { 1046 if (DISPLAY_VER(display) >= 9) { 1047 intel_de_write(display, AUD_FREQ_CNTRL, 1048 display->audio.freq_cntrl); 1049 drm_dbg_kms(display->drm, 1050 "restored AUD_FREQ_CNTRL to 0x%x\n", 1051 display->audio.freq_cntrl); 1052 } 1053 1054 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1055 if (display->platform.geminilake) 1056 glk_force_audio_cdclk(display, true); 1057 1058 if (DISPLAY_VER(display) >= 10) 1059 intel_de_rmw(display, AUD_PIN_BUF_CTL, 1060 0, AUD_PIN_BUF_ENABLE); 1061 } 1062 1063 return (unsigned long)wakeref; 1064 } 1065 1066 static void intel_audio_component_put_power(struct device *kdev, 1067 unsigned long cookie) 1068 { 1069 struct intel_display *display = to_intel_display(kdev); 1070 intel_wakeref_t wakeref = (intel_wakeref_t)cookie; 1071 1072 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1073 if (--display->audio.power_refcount == 0) 1074 if (display->platform.geminilake) 1075 glk_force_audio_cdclk(display, false); 1076 1077 intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref); 1078 } 1079 1080 static void intel_audio_component_codec_wake_override(struct device *kdev, 1081 bool enable) 1082 { 1083 struct intel_display *display = to_intel_display(kdev); 1084 unsigned long cookie; 1085 1086 if (DISPLAY_VER(display) < 9) 1087 return; 1088 1089 cookie = intel_audio_component_get_power(kdev); 1090 1091 /* 1092 * Enable/disable generating the codec wake signal, overriding the 1093 * internal logic to generate the codec wake to controller. 1094 */ 1095 intel_de_rmw(display, HSW_AUD_CHICKENBIT, 1096 SKL_AUD_CODEC_WAKE_SIGNAL, 0); 1097 usleep_range(1000, 1500); 1098 1099 if (enable) { 1100 intel_de_rmw(display, HSW_AUD_CHICKENBIT, 1101 0, SKL_AUD_CODEC_WAKE_SIGNAL); 1102 usleep_range(1000, 1500); 1103 } 1104 1105 intel_audio_component_put_power(kdev, cookie); 1106 } 1107 1108 /* Get CDCLK in kHz */ 1109 static int intel_audio_component_get_cdclk_freq(struct device *kdev) 1110 { 1111 struct intel_display *display = to_intel_display(kdev); 1112 1113 if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display))) 1114 return -ENODEV; 1115 1116 return display->cdclk.hw.cdclk; 1117 } 1118 1119 /* 1120 * get the intel audio state according to the parameter port and cpu_transcoder 1121 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder], 1122 * when port is matched 1123 * MST & (cpu_transcoder < 0): this is invalid 1124 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry) 1125 * will get the right intel_encoder with port matched 1126 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched 1127 */ 1128 static struct intel_audio_state *find_audio_state(struct intel_display *display, 1129 int port, int cpu_transcoder) 1130 { 1131 /* MST */ 1132 if (cpu_transcoder >= 0) { 1133 struct intel_audio_state *audio_state; 1134 struct intel_encoder *encoder; 1135 1136 if (drm_WARN_ON(display->drm, 1137 cpu_transcoder >= ARRAY_SIZE(display->audio.state))) 1138 return NULL; 1139 1140 audio_state = &display->audio.state[cpu_transcoder]; 1141 encoder = audio_state->encoder; 1142 1143 if (encoder && encoder->port == port && 1144 encoder->type == INTEL_OUTPUT_DP_MST) 1145 return audio_state; 1146 } 1147 1148 /* Non-MST */ 1149 if (cpu_transcoder > 0) 1150 return NULL; 1151 1152 for_each_cpu_transcoder(display, cpu_transcoder) { 1153 struct intel_audio_state *audio_state; 1154 struct intel_encoder *encoder; 1155 1156 audio_state = &display->audio.state[cpu_transcoder]; 1157 encoder = audio_state->encoder; 1158 1159 if (encoder && encoder->port == port && 1160 encoder->type != INTEL_OUTPUT_DP_MST) 1161 return audio_state; 1162 } 1163 1164 return NULL; 1165 } 1166 1167 static int intel_audio_component_sync_audio_rate(struct device *kdev, int port, 1168 int cpu_transcoder, int rate) 1169 { 1170 struct intel_display *display = to_intel_display(kdev); 1171 struct i915_audio_component *acomp = display->audio.component; 1172 const struct intel_audio_state *audio_state; 1173 struct intel_encoder *encoder; 1174 struct intel_crtc *crtc; 1175 unsigned long cookie; 1176 int err = 0; 1177 1178 if (!HAS_DDI(display)) 1179 return 0; 1180 1181 cookie = intel_audio_component_get_power(kdev); 1182 mutex_lock(&display->audio.mutex); 1183 1184 audio_state = find_audio_state(display, port, cpu_transcoder); 1185 if (!audio_state) { 1186 drm_dbg_kms(display->drm, "Not valid for port %c\n", 1187 port_name(port)); 1188 err = -ENODEV; 1189 goto unlock; 1190 } 1191 1192 encoder = audio_state->encoder; 1193 1194 /* FIXME stop using the legacy crtc pointer */ 1195 crtc = to_intel_crtc(encoder->base.crtc); 1196 1197 /* port must be valid now, otherwise the cpu_transcoder will be invalid */ 1198 acomp->aud_sample_rate[port] = rate; 1199 1200 /* FIXME get rid of the crtc->config stuff */ 1201 hsw_audio_config_update(encoder, crtc->config); 1202 1203 unlock: 1204 mutex_unlock(&display->audio.mutex); 1205 intel_audio_component_put_power(kdev, cookie); 1206 return err; 1207 } 1208 1209 static int intel_audio_component_get_eld(struct device *kdev, int port, 1210 int cpu_transcoder, bool *enabled, 1211 unsigned char *buf, int max_bytes) 1212 { 1213 struct intel_display *display = to_intel_display(kdev); 1214 const struct intel_audio_state *audio_state; 1215 int ret = 0; 1216 1217 mutex_lock(&display->audio.mutex); 1218 1219 audio_state = find_audio_state(display, port, cpu_transcoder); 1220 if (!audio_state) { 1221 drm_dbg_kms(display->drm, "Not valid for port %c\n", 1222 port_name(port)); 1223 mutex_unlock(&display->audio.mutex); 1224 return -EINVAL; 1225 } 1226 1227 *enabled = audio_state->encoder != NULL; 1228 if (*enabled) { 1229 const u8 *eld = audio_state->eld; 1230 1231 ret = drm_eld_size(eld); 1232 memcpy(buf, eld, min(max_bytes, ret)); 1233 } 1234 1235 mutex_unlock(&display->audio.mutex); 1236 return ret; 1237 } 1238 1239 static const struct drm_audio_component_ops intel_audio_component_ops = { 1240 .owner = THIS_MODULE, 1241 .get_power = intel_audio_component_get_power, 1242 .put_power = intel_audio_component_put_power, 1243 .codec_wake_override = intel_audio_component_codec_wake_override, 1244 .get_cdclk_freq = intel_audio_component_get_cdclk_freq, 1245 .sync_audio_rate = intel_audio_component_sync_audio_rate, 1246 .get_eld = intel_audio_component_get_eld, 1247 }; 1248 1249 static int intel_audio_component_bind(struct device *drv_kdev, 1250 struct device *hda_kdev, void *data) 1251 { 1252 struct intel_display *display = to_intel_display(drv_kdev); 1253 struct i915_audio_component *acomp = data; 1254 int i; 1255 1256 if (drm_WARN_ON(display->drm, acomp->base.ops || acomp->base.dev)) 1257 return -EEXIST; 1258 1259 if (drm_WARN_ON(display->drm, 1260 !device_link_add(hda_kdev, drv_kdev, 1261 DL_FLAG_STATELESS))) 1262 return -ENOMEM; 1263 1264 drm_modeset_lock_all(display->drm); 1265 acomp->base.ops = &intel_audio_component_ops; 1266 acomp->base.dev = drv_kdev; 1267 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1268 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1269 acomp->aud_sample_rate[i] = 0; 1270 display->audio.component = acomp; 1271 drm_modeset_unlock_all(display->drm); 1272 1273 return 0; 1274 } 1275 1276 static void intel_audio_component_unbind(struct device *drv_kdev, 1277 struct device *hda_kdev, void *data) 1278 { 1279 struct intel_display *display = to_intel_display(drv_kdev); 1280 struct i915_audio_component *acomp = data; 1281 1282 drm_modeset_lock_all(display->drm); 1283 acomp->base.ops = NULL; 1284 acomp->base.dev = NULL; 1285 display->audio.component = NULL; 1286 drm_modeset_unlock_all(display->drm); 1287 1288 device_link_remove(hda_kdev, drv_kdev); 1289 1290 if (display->audio.power_refcount) 1291 drm_err(display->drm, 1292 "audio power refcount %d after unbind\n", 1293 display->audio.power_refcount); 1294 } 1295 1296 static const struct component_ops intel_audio_component_bind_ops = { 1297 .bind = intel_audio_component_bind, 1298 .unbind = intel_audio_component_unbind, 1299 }; 1300 1301 #define AUD_FREQ_TMODE_SHIFT 14 1302 #define AUD_FREQ_4T 0 1303 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1304 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1305 #define AUD_FREQ_BCLK_96M BIT(4) 1306 1307 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1308 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1309 1310 /** 1311 * intel_audio_component_init - initialize and register the audio component 1312 * @display: display device 1313 * 1314 * This will register with the component framework a child component which 1315 * will bind dynamically to the snd_hda_intel driver's corresponding master 1316 * component when the latter is registered. During binding the child 1317 * initializes an instance of struct i915_audio_component which it receives 1318 * from the master. The master can then start to use the interface defined by 1319 * this struct. Each side can break the binding at any point by deregistering 1320 * its own component after which each side's component unbind callback is 1321 * called. 1322 * 1323 * We ignore any error during registration and continue with reduced 1324 * functionality (i.e. without HDMI audio). 1325 */ 1326 static void intel_audio_component_init(struct intel_display *display) 1327 { 1328 u32 aud_freq, aud_freq_init; 1329 1330 if (DISPLAY_VER(display) >= 9) { 1331 aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL); 1332 1333 if (DISPLAY_VER(display) >= 12) 1334 aud_freq = AUD_FREQ_GEN12; 1335 else 1336 aud_freq = aud_freq_init; 1337 1338 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1339 if ((display->platform.tigerlake || display->platform.rocketlake) && 1340 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1341 aud_freq = aud_freq_init; 1342 1343 drm_dbg_kms(display->drm, 1344 "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1345 aud_freq, aud_freq_init); 1346 1347 display->audio.freq_cntrl = aud_freq; 1348 } 1349 1350 /* init with current cdclk */ 1351 intel_audio_cdclk_change_post(display); 1352 } 1353 1354 static void intel_audio_component_register(struct intel_display *display) 1355 { 1356 int ret; 1357 1358 ret = component_add_typed(display->drm->dev, 1359 &intel_audio_component_bind_ops, 1360 I915_COMPONENT_AUDIO); 1361 if (ret < 0) { 1362 drm_err(display->drm, 1363 "failed to add audio component (%d)\n", ret); 1364 /* continue with reduced functionality */ 1365 return; 1366 } 1367 1368 display->audio.component_registered = true; 1369 } 1370 1371 /** 1372 * intel_audio_component_cleanup - deregister the audio component 1373 * @display: display device 1374 * 1375 * Deregisters the audio component, breaking any existing binding to the 1376 * corresponding snd_hda_intel driver's master component. 1377 */ 1378 static void intel_audio_component_cleanup(struct intel_display *display) 1379 { 1380 if (!display->audio.component_registered) 1381 return; 1382 1383 component_del(display->drm->dev, &intel_audio_component_bind_ops); 1384 display->audio.component_registered = false; 1385 } 1386 1387 /** 1388 * intel_audio_init() - Initialize the audio driver either using 1389 * component framework or using lpe audio bridge 1390 * @display: display device 1391 * 1392 */ 1393 void intel_audio_init(struct intel_display *display) 1394 { 1395 if (intel_lpe_audio_init(display) < 0) 1396 intel_audio_component_init(display); 1397 } 1398 1399 void intel_audio_register(struct intel_display *display) 1400 { 1401 if (!display->audio.lpe.platdev) 1402 intel_audio_component_register(display); 1403 } 1404 1405 /** 1406 * intel_audio_deinit() - deinitialize the audio driver 1407 * @display: display device 1408 */ 1409 void intel_audio_deinit(struct intel_display *display) 1410 { 1411 if (display->audio.lpe.platdev) 1412 intel_lpe_audio_teardown(display); 1413 else 1414 intel_audio_component_cleanup(display); 1415 } 1416