1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/drm_eld.h> 29 #include <drm/drm_fixed.h> 30 #include <drm/intel/i915_component.h> 31 32 #include "i915_drv.h" 33 #include "intel_atomic.h" 34 #include "intel_audio.h" 35 #include "intel_audio_regs.h" 36 #include "intel_cdclk.h" 37 #include "intel_crtc.h" 38 #include "intel_de.h" 39 #include "intel_display_types.h" 40 #include "intel_lpe_audio.h" 41 42 /** 43 * DOC: High Definition Audio over HDMI and Display Port 44 * 45 * The graphics and audio drivers together support High Definition Audio over 46 * HDMI and Display Port. The audio programming sequences are divided into audio 47 * codec and controller enable and disable sequences. The graphics driver 48 * handles the audio codec sequences, while the audio driver handles the audio 49 * controller sequences. 50 * 51 * The disable sequences must be performed before disabling the transcoder or 52 * port. The enable sequences may only be performed after enabling the 53 * transcoder and port, and after completed link training. Therefore the audio 54 * enable/disable sequences are part of the modeset sequence. 55 * 56 * The codec and controller sequences could be done either parallel or serial, 57 * but generally the ELDV/PD change in the codec sequence indicates to the audio 58 * driver that the controller sequence should start. Indeed, most of the 59 * co-operation between the graphics and audio drivers is handled via audio 60 * related registers. (The notable exception is the power management, not 61 * covered here.) 62 * 63 * The struct &i915_audio_component is used to interact between the graphics 64 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 65 * defined in graphics driver and called in audio driver. The 66 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 67 */ 68 69 struct intel_audio_funcs { 70 void (*audio_codec_enable)(struct intel_encoder *encoder, 71 const struct intel_crtc_state *crtc_state, 72 const struct drm_connector_state *conn_state); 73 void (*audio_codec_disable)(struct intel_encoder *encoder, 74 const struct intel_crtc_state *old_crtc_state, 75 const struct drm_connector_state *old_conn_state); 76 void (*audio_codec_get_config)(struct intel_encoder *encoder, 77 struct intel_crtc_state *crtc_state); 78 }; 79 80 struct hdmi_aud_ncts { 81 int sample_rate; 82 int clock; 83 int n; 84 int cts; 85 }; 86 87 static const struct { 88 int clock; 89 u32 config; 90 } hdmi_audio_clock[] = { 91 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 92 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 93 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 94 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 95 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 96 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 97 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 98 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 99 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 100 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 101 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 102 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 103 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 104 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 105 }; 106 107 /* HDMI N/CTS table */ 108 #define TMDS_297M 297000 109 #define TMDS_296M 296703 110 #define TMDS_594M 594000 111 #define TMDS_593M 593407 112 113 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 114 { 32000, TMDS_296M, 5824, 421875 }, 115 { 32000, TMDS_297M, 3072, 222750 }, 116 { 32000, TMDS_593M, 5824, 843750 }, 117 { 32000, TMDS_594M, 3072, 445500 }, 118 { 44100, TMDS_296M, 4459, 234375 }, 119 { 44100, TMDS_297M, 4704, 247500 }, 120 { 44100, TMDS_593M, 8918, 937500 }, 121 { 44100, TMDS_594M, 9408, 990000 }, 122 { 88200, TMDS_296M, 8918, 234375 }, 123 { 88200, TMDS_297M, 9408, 247500 }, 124 { 88200, TMDS_593M, 17836, 937500 }, 125 { 88200, TMDS_594M, 18816, 990000 }, 126 { 176400, TMDS_296M, 17836, 234375 }, 127 { 176400, TMDS_297M, 18816, 247500 }, 128 { 176400, TMDS_593M, 35672, 937500 }, 129 { 176400, TMDS_594M, 37632, 990000 }, 130 { 48000, TMDS_296M, 5824, 281250 }, 131 { 48000, TMDS_297M, 5120, 247500 }, 132 { 48000, TMDS_593M, 5824, 562500 }, 133 { 48000, TMDS_594M, 6144, 594000 }, 134 { 96000, TMDS_296M, 11648, 281250 }, 135 { 96000, TMDS_297M, 10240, 247500 }, 136 { 96000, TMDS_593M, 11648, 562500 }, 137 { 96000, TMDS_594M, 12288, 594000 }, 138 { 192000, TMDS_296M, 23296, 281250 }, 139 { 192000, TMDS_297M, 20480, 247500 }, 140 { 192000, TMDS_593M, 23296, 562500 }, 141 { 192000, TMDS_594M, 24576, 594000 }, 142 }; 143 144 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 145 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 146 #define TMDS_371M 371250 147 #define TMDS_370M 370878 148 149 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 150 { 32000, TMDS_370M, 5824, 527344 }, 151 { 32000, TMDS_371M, 6144, 556875 }, 152 { 44100, TMDS_370M, 8918, 585938 }, 153 { 44100, TMDS_371M, 4704, 309375 }, 154 { 88200, TMDS_370M, 17836, 585938 }, 155 { 88200, TMDS_371M, 9408, 309375 }, 156 { 176400, TMDS_370M, 35672, 585938 }, 157 { 176400, TMDS_371M, 18816, 309375 }, 158 { 48000, TMDS_370M, 11648, 703125 }, 159 { 48000, TMDS_371M, 5120, 309375 }, 160 { 96000, TMDS_370M, 23296, 703125 }, 161 { 96000, TMDS_371M, 10240, 309375 }, 162 { 192000, TMDS_370M, 46592, 703125 }, 163 { 192000, TMDS_371M, 20480, 309375 }, 164 }; 165 166 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 167 #define TMDS_445_5M 445500 168 #define TMDS_445M 445054 169 170 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 171 { 32000, TMDS_445M, 5824, 632813 }, 172 { 32000, TMDS_445_5M, 4096, 445500 }, 173 { 44100, TMDS_445M, 8918, 703125 }, 174 { 44100, TMDS_445_5M, 4704, 371250 }, 175 { 88200, TMDS_445M, 17836, 703125 }, 176 { 88200, TMDS_445_5M, 9408, 371250 }, 177 { 176400, TMDS_445M, 35672, 703125 }, 178 { 176400, TMDS_445_5M, 18816, 371250 }, 179 { 48000, TMDS_445M, 5824, 421875 }, 180 { 48000, TMDS_445_5M, 5120, 371250 }, 181 { 96000, TMDS_445M, 11648, 421875 }, 182 { 96000, TMDS_445_5M, 10240, 371250 }, 183 { 192000, TMDS_445M, 23296, 421875 }, 184 { 192000, TMDS_445_5M, 20480, 371250 }, 185 }; 186 187 /* 188 * WA_14020863754: Implement Audio Workaround 189 * Corner case with Min Hblank Fix can cause audio hang 190 */ 191 static bool needs_wa_14020863754(struct drm_i915_private *i915) 192 { 193 return (DISPLAY_VER(i915) == 20 || IS_BATTLEMAGE(i915)); 194 } 195 196 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 197 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 198 { 199 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 200 const struct drm_display_mode *adjusted_mode = 201 &crtc_state->hw.adjusted_mode; 202 int i; 203 204 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 205 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 206 break; 207 } 208 209 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500) 210 i = ARRAY_SIZE(hdmi_audio_clock); 211 212 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 213 drm_dbg_kms(&i915->drm, 214 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 215 adjusted_mode->crtc_clock); 216 i = 1; 217 } 218 219 drm_dbg_kms(&i915->drm, 220 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 221 hdmi_audio_clock[i].clock, 222 hdmi_audio_clock[i].config); 223 224 return hdmi_audio_clock[i].config; 225 } 226 227 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 228 int rate) 229 { 230 const struct hdmi_aud_ncts *hdmi_ncts_table; 231 int i, size; 232 233 if (crtc_state->pipe_bpp == 36) { 234 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 235 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 236 } else if (crtc_state->pipe_bpp == 30) { 237 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 238 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 239 } else { 240 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 241 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 242 } 243 244 for (i = 0; i < size; i++) { 245 if (rate == hdmi_ncts_table[i].sample_rate && 246 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 247 return hdmi_ncts_table[i].n; 248 } 249 } 250 return 0; 251 } 252 253 /* ELD buffer size in dwords */ 254 static int g4x_eld_buffer_size(struct drm_i915_private *i915) 255 { 256 u32 tmp; 257 258 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); 259 260 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); 261 } 262 263 static void g4x_audio_codec_get_config(struct intel_encoder *encoder, 264 struct intel_crtc_state *crtc_state) 265 { 266 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 267 u32 *eld = (u32 *)crtc_state->eld; 268 int eld_buffer_size, len, i; 269 u32 tmp; 270 271 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); 272 if ((tmp & G4X_ELD_VALID) == 0) 273 return; 274 275 intel_de_rmw(i915, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); 276 277 eld_buffer_size = g4x_eld_buffer_size(i915); 278 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size); 279 280 for (i = 0; i < len; i++) 281 eld[i] = intel_de_read(i915, G4X_HDMIW_HDMIEDID); 282 } 283 284 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 285 const struct intel_crtc_state *old_crtc_state, 286 const struct drm_connector_state *old_conn_state) 287 { 288 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 289 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 290 291 /* Invalidate ELD */ 292 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 293 G4X_ELD_VALID, 0); 294 295 intel_crtc_wait_for_next_vblank(crtc); 296 intel_crtc_wait_for_next_vblank(crtc); 297 } 298 299 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 300 const struct intel_crtc_state *crtc_state, 301 const struct drm_connector_state *conn_state) 302 { 303 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 305 const u32 *eld = (const u32 *)crtc_state->eld; 306 int eld_buffer_size, len, i; 307 308 intel_crtc_wait_for_next_vblank(crtc); 309 310 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 311 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); 312 313 eld_buffer_size = g4x_eld_buffer_size(i915); 314 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size); 315 316 for (i = 0; i < len; i++) 317 intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]); 318 for (; i < eld_buffer_size; i++) 319 intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0); 320 321 drm_WARN_ON(&i915->drm, 322 (intel_de_read(i915, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); 323 324 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 325 0, G4X_ELD_VALID); 326 } 327 328 static void 329 hsw_dp_audio_config_update(struct intel_encoder *encoder, 330 const struct intel_crtc_state *crtc_state) 331 { 332 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 333 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 334 335 /* Enable time stamps. Let HW calculate Maud/Naud values */ 336 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), 337 AUD_CONFIG_N_VALUE_INDEX | 338 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK | 339 AUD_CONFIG_UPPER_N_MASK | 340 AUD_CONFIG_LOWER_N_MASK | 341 AUD_CONFIG_N_PROG_ENABLE, 342 AUD_CONFIG_N_VALUE_INDEX); 343 344 } 345 346 static void 347 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 348 const struct intel_crtc_state *crtc_state) 349 { 350 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 351 struct i915_audio_component *acomp = i915->display.audio.component; 352 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 353 enum port port = encoder->port; 354 int n, rate; 355 u32 tmp; 356 357 rate = acomp ? acomp->aud_sample_rate[port] : 0; 358 359 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder)); 360 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 361 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 362 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 363 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 364 365 n = audio_config_hdmi_get_n(crtc_state, rate); 366 if (n != 0) { 367 drm_dbg_kms(&i915->drm, "using N %d\n", n); 368 369 tmp &= ~AUD_CONFIG_N_MASK; 370 tmp |= AUD_CONFIG_N(n); 371 tmp |= AUD_CONFIG_N_PROG_ENABLE; 372 } else { 373 drm_dbg_kms(&i915->drm, "using automatic N\n"); 374 } 375 376 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp); 377 378 /* 379 * Let's disable "Enable CTS or M Prog bit" 380 * and let HW calculate the value 381 */ 382 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 383 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 384 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 385 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 386 } 387 388 static void 389 hsw_audio_config_update(struct intel_encoder *encoder, 390 const struct intel_crtc_state *crtc_state) 391 { 392 if (intel_crtc_has_dp_encoder(crtc_state)) 393 hsw_dp_audio_config_update(encoder, crtc_state); 394 else 395 hsw_hdmi_audio_config_update(encoder, crtc_state); 396 } 397 398 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 399 const struct intel_crtc_state *old_crtc_state, 400 const struct drm_connector_state *old_conn_state) 401 { 402 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 403 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 404 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 405 406 mutex_lock(&i915->display.audio.mutex); 407 408 /* Disable timestamps */ 409 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), 410 AUD_CONFIG_N_VALUE_INDEX | 411 AUD_CONFIG_UPPER_N_MASK | 412 AUD_CONFIG_LOWER_N_MASK, 413 AUD_CONFIG_N_PROG_ENABLE | 414 (intel_crtc_has_dp_encoder(old_crtc_state) ? 415 AUD_CONFIG_N_VALUE_INDEX : 0)); 416 417 /* Invalidate ELD */ 418 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 419 AUDIO_ELD_VALID(cpu_transcoder), 0); 420 421 intel_crtc_wait_for_next_vblank(crtc); 422 intel_crtc_wait_for_next_vblank(crtc); 423 424 /* Disable audio presence detect */ 425 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 426 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); 427 428 if (needs_wa_14020863754(i915)) 429 intel_de_rmw(i915, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); 430 431 mutex_unlock(&i915->display.audio.mutex); 432 } 433 434 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 435 const struct intel_crtc_state *crtc_state) 436 { 437 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 438 unsigned int link_clks_available, link_clks_required; 439 unsigned int tu_data, tu_line, link_clks_active; 440 unsigned int h_active, h_total, hblank_delta, pixel_clk; 441 unsigned int fec_coeff, cdclk, vdsc_bppx16; 442 unsigned int link_clk, lanes; 443 unsigned int hblank_rise; 444 445 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 446 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 447 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 448 vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16; 449 cdclk = i915->display.cdclk.hw.cdclk; 450 /* fec= 0.972261, using rounding multiplier of 1000000 */ 451 fec_coeff = 972261; 452 link_clk = crtc_state->port_clock; 453 lanes = crtc_state->lane_count; 454 455 drm_dbg_kms(&i915->drm, 456 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n", 457 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); 458 459 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) 460 return 0; 461 462 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 463 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 464 465 if (link_clks_available > link_clks_required) 466 hblank_delta = 32; 467 else 468 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 469 mul_u32_u32(link_clk, cdclk)); 470 471 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), 472 mul_u32_u32(link_clk * lanes * 16, fec_coeff)); 473 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 474 mul_u32_u32(64 * pixel_clk, 1000000)); 475 link_clks_active = (tu_line - 1) * 64 + tu_data; 476 477 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 478 479 return h_active - hblank_rise + hblank_delta; 480 } 481 482 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 483 { 484 unsigned int h_active, h_total, pixel_clk; 485 unsigned int link_clk, lanes; 486 487 h_active = crtc_state->hw.adjusted_mode.hdisplay; 488 h_total = crtc_state->hw.adjusted_mode.htotal; 489 pixel_clk = crtc_state->hw.adjusted_mode.clock; 490 link_clk = crtc_state->port_clock; 491 lanes = crtc_state->lane_count; 492 493 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 494 (pixel_clk * (48 / lanes + 2)); 495 } 496 497 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 498 const struct intel_crtc_state *crtc_state) 499 { 500 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 501 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 502 unsigned int hblank_early_prog, samples_room; 503 unsigned int val; 504 505 if (DISPLAY_VER(i915) < 11) 506 return; 507 508 val = intel_de_read(i915, AUD_CONFIG_BE); 509 510 if (DISPLAY_VER(i915) == 11) 511 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder); 512 else if (DISPLAY_VER(i915) >= 12) 513 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder); 514 515 if (crtc_state->dsc.compression_enable && 516 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 517 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 518 /* Get hblank early enable value required */ 519 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder); 520 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 521 if (hblank_early_prog < 32) 522 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32); 523 else if (hblank_early_prog < 64) 524 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64); 525 else if (hblank_early_prog < 96) 526 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96); 527 else 528 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128); 529 530 /* Get samples room value required */ 531 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder); 532 samples_room = calc_samples_room(crtc_state); 533 if (samples_room < 3) 534 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room); 535 else /* Program 0 i.e "All Samples available in buffer" */ 536 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0); 537 } 538 539 intel_de_write(i915, AUD_CONFIG_BE, val); 540 } 541 542 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 543 const struct intel_crtc_state *crtc_state, 544 const struct drm_connector_state *conn_state) 545 { 546 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 547 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 548 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 549 550 mutex_lock(&i915->display.audio.mutex); 551 552 /* Enable Audio WA for 4k DSC usecases */ 553 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 554 enable_audio_dsc_wa(encoder, crtc_state); 555 556 if (needs_wa_14020863754(i915)) 557 intel_de_rmw(i915, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); 558 559 /* Enable audio presence detect */ 560 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 561 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); 562 563 intel_crtc_wait_for_next_vblank(crtc); 564 565 /* Invalidate ELD */ 566 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 567 AUDIO_ELD_VALID(cpu_transcoder), 0); 568 569 /* 570 * The audio componenent is used to convey the ELD 571 * instead using of the hardware ELD buffer. 572 */ 573 574 /* Enable timestamps */ 575 hsw_audio_config_update(encoder, crtc_state); 576 577 mutex_unlock(&i915->display.audio.mutex); 578 } 579 580 struct ibx_audio_regs { 581 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 582 }; 583 584 static void ibx_audio_regs_init(struct drm_i915_private *i915, 585 enum pipe pipe, 586 struct ibx_audio_regs *regs) 587 { 588 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 589 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 590 regs->aud_config = VLV_AUD_CFG(pipe); 591 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 592 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 593 } else if (HAS_PCH_CPT(i915)) { 594 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 595 regs->aud_config = CPT_AUD_CFG(pipe); 596 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 597 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 598 } else if (HAS_PCH_IBX(i915)) { 599 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 600 regs->aud_config = IBX_AUD_CFG(pipe); 601 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 602 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 603 } 604 } 605 606 static void ibx_audio_codec_disable(struct intel_encoder *encoder, 607 const struct intel_crtc_state *old_crtc_state, 608 const struct drm_connector_state *old_conn_state) 609 { 610 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 611 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 612 enum port port = encoder->port; 613 enum pipe pipe = crtc->pipe; 614 struct ibx_audio_regs regs; 615 616 if (drm_WARN_ON(&i915->drm, port == PORT_A)) 617 return; 618 619 ibx_audio_regs_init(i915, pipe, ®s); 620 621 mutex_lock(&i915->display.audio.mutex); 622 623 /* Disable timestamps */ 624 intel_de_rmw(i915, regs.aud_config, 625 AUD_CONFIG_N_VALUE_INDEX | 626 AUD_CONFIG_UPPER_N_MASK | 627 AUD_CONFIG_LOWER_N_MASK, 628 AUD_CONFIG_N_PROG_ENABLE | 629 (intel_crtc_has_dp_encoder(old_crtc_state) ? 630 AUD_CONFIG_N_VALUE_INDEX : 0)); 631 632 /* Invalidate ELD */ 633 intel_de_rmw(i915, regs.aud_cntrl_st2, 634 IBX_ELD_VALID(port), 0); 635 636 mutex_unlock(&i915->display.audio.mutex); 637 638 intel_crtc_wait_for_next_vblank(crtc); 639 intel_crtc_wait_for_next_vblank(crtc); 640 } 641 642 static void ibx_audio_codec_enable(struct intel_encoder *encoder, 643 const struct intel_crtc_state *crtc_state, 644 const struct drm_connector_state *conn_state) 645 { 646 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 648 enum port port = encoder->port; 649 enum pipe pipe = crtc->pipe; 650 struct ibx_audio_regs regs; 651 652 if (drm_WARN_ON(&i915->drm, port == PORT_A)) 653 return; 654 655 intel_crtc_wait_for_next_vblank(crtc); 656 657 ibx_audio_regs_init(i915, pipe, ®s); 658 659 mutex_lock(&i915->display.audio.mutex); 660 661 /* Invalidate ELD */ 662 intel_de_rmw(i915, regs.aud_cntrl_st2, 663 IBX_ELD_VALID(port), 0); 664 665 /* 666 * The audio componenent is used to convey the ELD 667 * instead using of the hardware ELD buffer. 668 */ 669 670 /* Enable timestamps */ 671 intel_de_rmw(i915, regs.aud_config, 672 AUD_CONFIG_N_VALUE_INDEX | 673 AUD_CONFIG_N_PROG_ENABLE | 674 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 675 (intel_crtc_has_dp_encoder(crtc_state) ? 676 AUD_CONFIG_N_VALUE_INDEX : 677 audio_config_hdmi_pixel_clock(crtc_state))); 678 679 mutex_unlock(&i915->display.audio.mutex); 680 } 681 682 void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state) 683 { 684 struct intel_display *display = to_intel_display(crtc_state); 685 enum transcoder trans = crtc_state->cpu_transcoder; 686 687 if (HAS_DP20(display)) 688 intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 689 crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); 690 } 691 692 bool intel_audio_compute_config(struct intel_encoder *encoder, 693 struct intel_crtc_state *crtc_state, 694 struct drm_connector_state *conn_state) 695 { 696 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 697 struct drm_connector *connector = conn_state->connector; 698 const struct drm_display_mode *adjusted_mode = 699 &crtc_state->hw.adjusted_mode; 700 701 mutex_lock(&connector->eld_mutex); 702 if (!connector->eld[0]) { 703 drm_dbg_kms(&i915->drm, 704 "Bogus ELD on [CONNECTOR:%d:%s]\n", 705 connector->base.id, connector->name); 706 mutex_unlock(&connector->eld_mutex); 707 return false; 708 } 709 710 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld)); 711 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); 712 713 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 714 mutex_unlock(&connector->eld_mutex); 715 716 return true; 717 } 718 719 /** 720 * intel_audio_codec_enable - Enable the audio codec for HD audio 721 * @encoder: encoder on which to enable audio 722 * @crtc_state: pointer to the current crtc state. 723 * @conn_state: pointer to the current connector state. 724 * 725 * The enable sequences may only be performed after enabling the transcoder and 726 * port, and after completed link training. 727 */ 728 void intel_audio_codec_enable(struct intel_encoder *encoder, 729 const struct intel_crtc_state *crtc_state, 730 const struct drm_connector_state *conn_state) 731 { 732 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 733 struct i915_audio_component *acomp = i915->display.audio.component; 734 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 735 struct intel_connector *connector = to_intel_connector(conn_state->connector); 736 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 737 struct intel_audio_state *audio_state; 738 enum port port = encoder->port; 739 740 if (!crtc_state->has_audio) 741 return; 742 743 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", 744 connector->base.base.id, connector->base.name, 745 encoder->base.base.id, encoder->base.name, 746 crtc->base.base.id, crtc->base.name, 747 drm_eld_size(crtc_state->eld)); 748 749 if (i915->display.funcs.audio) 750 i915->display.funcs.audio->audio_codec_enable(encoder, 751 crtc_state, 752 conn_state); 753 754 mutex_lock(&i915->display.audio.mutex); 755 756 audio_state = &i915->display.audio.state[cpu_transcoder]; 757 758 audio_state->encoder = encoder; 759 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld)); 760 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld)); 761 762 mutex_unlock(&i915->display.audio.mutex); 763 764 if (acomp && acomp->base.audio_ops && 765 acomp->base.audio_ops->pin_eld_notify) { 766 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 767 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 768 cpu_transcoder = -1; 769 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 770 (int)port, (int)cpu_transcoder); 771 } 772 773 intel_lpe_audio_notify(i915, cpu_transcoder, port, crtc_state->eld, 774 crtc_state->port_clock, 775 intel_crtc_has_dp_encoder(crtc_state)); 776 } 777 778 /** 779 * intel_audio_codec_disable - Disable the audio codec for HD audio 780 * @encoder: encoder on which to disable audio 781 * @old_crtc_state: pointer to the old crtc state. 782 * @old_conn_state: pointer to the old connector state. 783 * 784 * The disable sequences must be performed before disabling the transcoder or 785 * port. 786 */ 787 void intel_audio_codec_disable(struct intel_encoder *encoder, 788 const struct intel_crtc_state *old_crtc_state, 789 const struct drm_connector_state *old_conn_state) 790 { 791 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 792 struct i915_audio_component *acomp = i915->display.audio.component; 793 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 794 struct intel_connector *connector = to_intel_connector(old_conn_state->connector); 795 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 796 struct intel_audio_state *audio_state; 797 enum port port = encoder->port; 798 799 if (!old_crtc_state->has_audio) 800 return; 801 802 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", 803 connector->base.base.id, connector->base.name, 804 encoder->base.base.id, encoder->base.name, 805 crtc->base.base.id, crtc->base.name); 806 807 if (i915->display.funcs.audio) 808 i915->display.funcs.audio->audio_codec_disable(encoder, 809 old_crtc_state, 810 old_conn_state); 811 812 mutex_lock(&i915->display.audio.mutex); 813 814 audio_state = &i915->display.audio.state[cpu_transcoder]; 815 816 audio_state->encoder = NULL; 817 memset(audio_state->eld, 0, sizeof(audio_state->eld)); 818 819 mutex_unlock(&i915->display.audio.mutex); 820 821 if (acomp && acomp->base.audio_ops && 822 acomp->base.audio_ops->pin_eld_notify) { 823 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 824 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 825 cpu_transcoder = -1; 826 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 827 (int)port, (int)cpu_transcoder); 828 } 829 830 intel_lpe_audio_notify(i915, cpu_transcoder, port, NULL, 0, false); 831 } 832 833 static void intel_acomp_get_config(struct intel_encoder *encoder, 834 struct intel_crtc_state *crtc_state) 835 { 836 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 837 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 838 struct intel_audio_state *audio_state; 839 840 mutex_lock(&i915->display.audio.mutex); 841 842 audio_state = &i915->display.audio.state[cpu_transcoder]; 843 844 if (audio_state->encoder) 845 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld)); 846 847 mutex_unlock(&i915->display.audio.mutex); 848 } 849 850 void intel_audio_codec_get_config(struct intel_encoder *encoder, 851 struct intel_crtc_state *crtc_state) 852 { 853 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 854 855 if (!crtc_state->has_audio) 856 return; 857 858 if (i915->display.funcs.audio) 859 i915->display.funcs.audio->audio_codec_get_config(encoder, crtc_state); 860 } 861 862 static const struct intel_audio_funcs g4x_audio_funcs = { 863 .audio_codec_enable = g4x_audio_codec_enable, 864 .audio_codec_disable = g4x_audio_codec_disable, 865 .audio_codec_get_config = g4x_audio_codec_get_config, 866 }; 867 868 static const struct intel_audio_funcs ibx_audio_funcs = { 869 .audio_codec_enable = ibx_audio_codec_enable, 870 .audio_codec_disable = ibx_audio_codec_disable, 871 .audio_codec_get_config = intel_acomp_get_config, 872 }; 873 874 static const struct intel_audio_funcs hsw_audio_funcs = { 875 .audio_codec_enable = hsw_audio_codec_enable, 876 .audio_codec_disable = hsw_audio_codec_disable, 877 .audio_codec_get_config = intel_acomp_get_config, 878 }; 879 880 /** 881 * intel_audio_hooks_init - Set up chip specific audio hooks 882 * @i915: device private 883 */ 884 void intel_audio_hooks_init(struct drm_i915_private *i915) 885 { 886 if (IS_G4X(i915)) 887 i915->display.funcs.audio = &g4x_audio_funcs; 888 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915) || 889 HAS_PCH_CPT(i915) || HAS_PCH_IBX(i915)) 890 i915->display.funcs.audio = &ibx_audio_funcs; 891 else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8) 892 i915->display.funcs.audio = &hsw_audio_funcs; 893 } 894 895 struct aud_ts_cdclk_m_n { 896 u8 m; 897 u16 n; 898 }; 899 900 void intel_audio_cdclk_change_pre(struct drm_i915_private *i915) 901 { 902 if (DISPLAY_VER(i915) >= 13) 903 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 904 } 905 906 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 907 { 908 aud_ts->m = 60; 909 aud_ts->n = cdclk * aud_ts->m / 24000; 910 } 911 912 void intel_audio_cdclk_change_post(struct drm_i915_private *i915) 913 { 914 struct aud_ts_cdclk_m_n aud_ts; 915 916 if (DISPLAY_VER(i915) >= 13) { 917 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); 918 919 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n); 920 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 921 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n); 922 } 923 } 924 925 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 926 struct intel_crtc *crtc, 927 bool enable) 928 { 929 struct intel_cdclk_state *cdclk_state; 930 int ret; 931 932 /* need to hold at least one crtc lock for the global state */ 933 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 934 if (ret) 935 return ret; 936 937 cdclk_state = intel_atomic_get_cdclk_state(state); 938 if (IS_ERR(cdclk_state)) 939 return PTR_ERR(cdclk_state); 940 941 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; 942 943 return drm_atomic_commit(&state->base); 944 } 945 946 static void glk_force_audio_cdclk(struct drm_i915_private *i915, 947 bool enable) 948 { 949 struct drm_modeset_acquire_ctx ctx; 950 struct drm_atomic_state *state; 951 struct intel_crtc *crtc; 952 int ret; 953 954 crtc = intel_first_crtc(i915); 955 if (!crtc) 956 return; 957 958 drm_modeset_acquire_init(&ctx, 0); 959 state = drm_atomic_state_alloc(&i915->drm); 960 if (drm_WARN_ON(&i915->drm, !state)) 961 return; 962 963 state->acquire_ctx = &ctx; 964 to_intel_atomic_state(state)->internal = true; 965 966 retry: 967 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 968 enable); 969 if (ret == -EDEADLK) { 970 drm_atomic_state_clear(state); 971 drm_modeset_backoff(&ctx); 972 goto retry; 973 } 974 975 drm_WARN_ON(&i915->drm, ret); 976 977 drm_atomic_state_put(state); 978 979 drm_modeset_drop_locks(&ctx); 980 drm_modeset_acquire_fini(&ctx); 981 } 982 983 int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) 984 { 985 struct intel_display *display = to_intel_display(crtc_state); 986 struct drm_i915_private *dev_priv = to_i915(display->drm); 987 int min_cdclk = 0; 988 989 if (!crtc_state->has_audio) 990 return 0; 991 992 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 993 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 994 * there may be audio corruption or screen corruption." This cdclk 995 * restriction for GLK is 316.8 MHz. 996 */ 997 if (intel_crtc_has_dp_encoder(crtc_state) && 998 crtc_state->port_clock >= 540000 && 999 crtc_state->lane_count == 4) { 1000 if (DISPLAY_VER(display) == 10) { 1001 /* Display WA #1145: glk */ 1002 min_cdclk = max(min_cdclk, 316800); 1003 } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) { 1004 /* Display WA #1144: skl,bxt */ 1005 min_cdclk = max(min_cdclk, 432000); 1006 } 1007 } 1008 1009 /* 1010 * According to BSpec, "The CD clock frequency must be at least twice 1011 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 1012 */ 1013 if (DISPLAY_VER(display) >= 9) 1014 min_cdclk = max(min_cdclk, 2 * 96000); 1015 1016 /* 1017 * "For DP audio configuration, cdclk frequency shall be set to 1018 * meet the following requirements: 1019 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 1020 * 270 | 320 or higher 1021 * 162 | 200 or higher" 1022 */ 1023 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1024 intel_crtc_has_dp_encoder(crtc_state)) 1025 min_cdclk = max(min_cdclk, crtc_state->port_clock); 1026 1027 return min_cdclk; 1028 } 1029 1030 static unsigned long i915_audio_component_get_power(struct device *kdev) 1031 { 1032 struct intel_display *display = to_intel_display(kdev); 1033 struct drm_i915_private *i915 = to_i915(display->drm); 1034 intel_wakeref_t wakeref; 1035 1036 /* Catch potential impedance mismatches before they occur! */ 1037 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 1038 1039 wakeref = intel_display_power_get(i915, POWER_DOMAIN_AUDIO_PLAYBACK); 1040 1041 if (i915->display.audio.power_refcount++ == 0) { 1042 if (DISPLAY_VER(i915) >= 9) { 1043 intel_de_write(i915, AUD_FREQ_CNTRL, 1044 i915->display.audio.freq_cntrl); 1045 drm_dbg_kms(&i915->drm, 1046 "restored AUD_FREQ_CNTRL to 0x%x\n", 1047 i915->display.audio.freq_cntrl); 1048 } 1049 1050 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1051 if (IS_GEMINILAKE(i915)) 1052 glk_force_audio_cdclk(i915, true); 1053 1054 if (DISPLAY_VER(i915) >= 10) 1055 intel_de_rmw(i915, AUD_PIN_BUF_CTL, 1056 0, AUD_PIN_BUF_ENABLE); 1057 } 1058 1059 return (unsigned long)wakeref; 1060 } 1061 1062 static void i915_audio_component_put_power(struct device *kdev, 1063 unsigned long cookie) 1064 { 1065 struct intel_display *display = to_intel_display(kdev); 1066 struct drm_i915_private *i915 = to_i915(display->drm); 1067 intel_wakeref_t wakeref = (intel_wakeref_t)cookie; 1068 1069 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1070 if (--i915->display.audio.power_refcount == 0) 1071 if (IS_GEMINILAKE(i915)) 1072 glk_force_audio_cdclk(i915, false); 1073 1074 intel_display_power_put(i915, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref); 1075 } 1076 1077 static void i915_audio_component_codec_wake_override(struct device *kdev, 1078 bool enable) 1079 { 1080 struct intel_display *display = to_intel_display(kdev); 1081 struct drm_i915_private *i915 = to_i915(display->drm); 1082 unsigned long cookie; 1083 1084 if (DISPLAY_VER(i915) < 9) 1085 return; 1086 1087 cookie = i915_audio_component_get_power(kdev); 1088 1089 /* 1090 * Enable/disable generating the codec wake signal, overriding the 1091 * internal logic to generate the codec wake to controller. 1092 */ 1093 intel_de_rmw(i915, HSW_AUD_CHICKENBIT, 1094 SKL_AUD_CODEC_WAKE_SIGNAL, 0); 1095 usleep_range(1000, 1500); 1096 1097 if (enable) { 1098 intel_de_rmw(i915, HSW_AUD_CHICKENBIT, 1099 0, SKL_AUD_CODEC_WAKE_SIGNAL); 1100 usleep_range(1000, 1500); 1101 } 1102 1103 i915_audio_component_put_power(kdev, cookie); 1104 } 1105 1106 /* Get CDCLK in kHz */ 1107 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 1108 { 1109 struct intel_display *display = to_intel_display(kdev); 1110 struct drm_i915_private *i915 = to_i915(display->drm); 1111 1112 if (drm_WARN_ON_ONCE(&i915->drm, !HAS_DDI(i915))) 1113 return -ENODEV; 1114 1115 return i915->display.cdclk.hw.cdclk; 1116 } 1117 1118 /* 1119 * get the intel audio state according to the parameter port and cpu_transcoder 1120 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder], 1121 * when port is matched 1122 * MST & (cpu_transcoder < 0): this is invalid 1123 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry) 1124 * will get the right intel_encoder with port matched 1125 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched 1126 */ 1127 static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915, 1128 int port, int cpu_transcoder) 1129 { 1130 /* MST */ 1131 if (cpu_transcoder >= 0) { 1132 struct intel_audio_state *audio_state; 1133 struct intel_encoder *encoder; 1134 1135 if (drm_WARN_ON(&i915->drm, 1136 cpu_transcoder >= ARRAY_SIZE(i915->display.audio.state))) 1137 return NULL; 1138 1139 audio_state = &i915->display.audio.state[cpu_transcoder]; 1140 encoder = audio_state->encoder; 1141 1142 if (encoder && encoder->port == port && 1143 encoder->type == INTEL_OUTPUT_DP_MST) 1144 return audio_state; 1145 } 1146 1147 /* Non-MST */ 1148 if (cpu_transcoder > 0) 1149 return NULL; 1150 1151 for_each_cpu_transcoder(i915, cpu_transcoder) { 1152 struct intel_audio_state *audio_state; 1153 struct intel_encoder *encoder; 1154 1155 audio_state = &i915->display.audio.state[cpu_transcoder]; 1156 encoder = audio_state->encoder; 1157 1158 if (encoder && encoder->port == port && 1159 encoder->type != INTEL_OUTPUT_DP_MST) 1160 return audio_state; 1161 } 1162 1163 return NULL; 1164 } 1165 1166 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 1167 int cpu_transcoder, int rate) 1168 { 1169 struct intel_display *display = to_intel_display(kdev); 1170 struct drm_i915_private *i915 = to_i915(display->drm); 1171 struct i915_audio_component *acomp = i915->display.audio.component; 1172 const struct intel_audio_state *audio_state; 1173 struct intel_encoder *encoder; 1174 struct intel_crtc *crtc; 1175 unsigned long cookie; 1176 int err = 0; 1177 1178 if (!HAS_DDI(i915)) 1179 return 0; 1180 1181 cookie = i915_audio_component_get_power(kdev); 1182 mutex_lock(&i915->display.audio.mutex); 1183 1184 audio_state = find_audio_state(i915, port, cpu_transcoder); 1185 if (!audio_state) { 1186 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port)); 1187 err = -ENODEV; 1188 goto unlock; 1189 } 1190 1191 encoder = audio_state->encoder; 1192 1193 /* FIXME stop using the legacy crtc pointer */ 1194 crtc = to_intel_crtc(encoder->base.crtc); 1195 1196 /* port must be valid now, otherwise the cpu_transcoder will be invalid */ 1197 acomp->aud_sample_rate[port] = rate; 1198 1199 /* FIXME get rid of the crtc->config stuff */ 1200 hsw_audio_config_update(encoder, crtc->config); 1201 1202 unlock: 1203 mutex_unlock(&i915->display.audio.mutex); 1204 i915_audio_component_put_power(kdev, cookie); 1205 return err; 1206 } 1207 1208 static int i915_audio_component_get_eld(struct device *kdev, int port, 1209 int cpu_transcoder, bool *enabled, 1210 unsigned char *buf, int max_bytes) 1211 { 1212 struct intel_display *display = to_intel_display(kdev); 1213 struct drm_i915_private *i915 = to_i915(display->drm); 1214 const struct intel_audio_state *audio_state; 1215 int ret = 0; 1216 1217 mutex_lock(&i915->display.audio.mutex); 1218 1219 audio_state = find_audio_state(i915, port, cpu_transcoder); 1220 if (!audio_state) { 1221 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port)); 1222 mutex_unlock(&i915->display.audio.mutex); 1223 return -EINVAL; 1224 } 1225 1226 *enabled = audio_state->encoder != NULL; 1227 if (*enabled) { 1228 const u8 *eld = audio_state->eld; 1229 1230 ret = drm_eld_size(eld); 1231 memcpy(buf, eld, min(max_bytes, ret)); 1232 } 1233 1234 mutex_unlock(&i915->display.audio.mutex); 1235 return ret; 1236 } 1237 1238 static const struct drm_audio_component_ops i915_audio_component_ops = { 1239 .owner = THIS_MODULE, 1240 .get_power = i915_audio_component_get_power, 1241 .put_power = i915_audio_component_put_power, 1242 .codec_wake_override = i915_audio_component_codec_wake_override, 1243 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1244 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1245 .get_eld = i915_audio_component_get_eld, 1246 }; 1247 1248 static int i915_audio_component_bind(struct device *drv_kdev, 1249 struct device *hda_kdev, void *data) 1250 { 1251 struct intel_display *display = to_intel_display(drv_kdev); 1252 struct drm_i915_private *i915 = to_i915(display->drm); 1253 struct i915_audio_component *acomp = data; 1254 int i; 1255 1256 if (drm_WARN_ON(&i915->drm, acomp->base.ops || acomp->base.dev)) 1257 return -EEXIST; 1258 1259 if (drm_WARN_ON(&i915->drm, 1260 !device_link_add(hda_kdev, drv_kdev, 1261 DL_FLAG_STATELESS))) 1262 return -ENOMEM; 1263 1264 drm_modeset_lock_all(&i915->drm); 1265 acomp->base.ops = &i915_audio_component_ops; 1266 acomp->base.dev = drv_kdev; 1267 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1268 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1269 acomp->aud_sample_rate[i] = 0; 1270 i915->display.audio.component = acomp; 1271 drm_modeset_unlock_all(&i915->drm); 1272 1273 return 0; 1274 } 1275 1276 static void i915_audio_component_unbind(struct device *drv_kdev, 1277 struct device *hda_kdev, void *data) 1278 { 1279 struct intel_display *display = to_intel_display(drv_kdev); 1280 struct drm_i915_private *i915 = to_i915(display->drm); 1281 struct i915_audio_component *acomp = data; 1282 1283 drm_modeset_lock_all(&i915->drm); 1284 acomp->base.ops = NULL; 1285 acomp->base.dev = NULL; 1286 i915->display.audio.component = NULL; 1287 drm_modeset_unlock_all(&i915->drm); 1288 1289 device_link_remove(hda_kdev, drv_kdev); 1290 1291 if (i915->display.audio.power_refcount) 1292 drm_err(&i915->drm, "audio power refcount %d after unbind\n", 1293 i915->display.audio.power_refcount); 1294 } 1295 1296 static const struct component_ops i915_audio_component_bind_ops = { 1297 .bind = i915_audio_component_bind, 1298 .unbind = i915_audio_component_unbind, 1299 }; 1300 1301 #define AUD_FREQ_TMODE_SHIFT 14 1302 #define AUD_FREQ_4T 0 1303 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1304 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1305 #define AUD_FREQ_BCLK_96M BIT(4) 1306 1307 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1308 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1309 1310 /** 1311 * i915_audio_component_init - initialize and register the audio component 1312 * @i915: i915 device instance 1313 * 1314 * This will register with the component framework a child component which 1315 * will bind dynamically to the snd_hda_intel driver's corresponding master 1316 * component when the latter is registered. During binding the child 1317 * initializes an instance of struct i915_audio_component which it receives 1318 * from the master. The master can then start to use the interface defined by 1319 * this struct. Each side can break the binding at any point by deregistering 1320 * its own component after which each side's component unbind callback is 1321 * called. 1322 * 1323 * We ignore any error during registration and continue with reduced 1324 * functionality (i.e. without HDMI audio). 1325 */ 1326 static void i915_audio_component_init(struct drm_i915_private *i915) 1327 { 1328 u32 aud_freq, aud_freq_init; 1329 1330 if (DISPLAY_VER(i915) >= 9) { 1331 aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL); 1332 1333 if (DISPLAY_VER(i915) >= 12) 1334 aud_freq = AUD_FREQ_GEN12; 1335 else 1336 aud_freq = aud_freq_init; 1337 1338 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1339 if ((IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) && 1340 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1341 aud_freq = aud_freq_init; 1342 1343 drm_dbg_kms(&i915->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1344 aud_freq, aud_freq_init); 1345 1346 i915->display.audio.freq_cntrl = aud_freq; 1347 } 1348 1349 /* init with current cdclk */ 1350 intel_audio_cdclk_change_post(i915); 1351 } 1352 1353 static void i915_audio_component_register(struct drm_i915_private *i915) 1354 { 1355 int ret; 1356 1357 ret = component_add_typed(i915->drm.dev, 1358 &i915_audio_component_bind_ops, 1359 I915_COMPONENT_AUDIO); 1360 if (ret < 0) { 1361 drm_err(&i915->drm, 1362 "failed to add audio component (%d)\n", ret); 1363 /* continue with reduced functionality */ 1364 return; 1365 } 1366 1367 i915->display.audio.component_registered = true; 1368 } 1369 1370 /** 1371 * i915_audio_component_cleanup - deregister the audio component 1372 * @i915: i915 device instance 1373 * 1374 * Deregisters the audio component, breaking any existing binding to the 1375 * corresponding snd_hda_intel driver's master component. 1376 */ 1377 static void i915_audio_component_cleanup(struct drm_i915_private *i915) 1378 { 1379 if (!i915->display.audio.component_registered) 1380 return; 1381 1382 component_del(i915->drm.dev, &i915_audio_component_bind_ops); 1383 i915->display.audio.component_registered = false; 1384 } 1385 1386 /** 1387 * intel_audio_init() - Initialize the audio driver either using 1388 * component framework or using lpe audio bridge 1389 * @i915: the i915 drm device private data 1390 * 1391 */ 1392 void intel_audio_init(struct drm_i915_private *i915) 1393 { 1394 if (intel_lpe_audio_init(i915) < 0) 1395 i915_audio_component_init(i915); 1396 } 1397 1398 void intel_audio_register(struct drm_i915_private *i915) 1399 { 1400 if (!i915->display.audio.lpe.platdev) 1401 i915_audio_component_register(i915); 1402 } 1403 1404 /** 1405 * intel_audio_deinit() - deinitialize the audio driver 1406 * @i915: the i915 drm device private data 1407 * 1408 */ 1409 void intel_audio_deinit(struct drm_i915_private *i915) 1410 { 1411 if (i915->display.audio.lpe.platdev != NULL) 1412 intel_lpe_audio_teardown(i915); 1413 else 1414 i915_audio_component_cleanup(i915); 1415 } 1416