1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/drm_eld.h> 29 #include <drm/drm_fixed.h> 30 #include <drm/drm_print.h> 31 #include <drm/intel/i915_component.h> 32 33 #include "intel_atomic.h" 34 #include "intel_audio.h" 35 #include "intel_audio_regs.h" 36 #include "intel_cdclk.h" 37 #include "intel_crtc.h" 38 #include "intel_de.h" 39 #include "intel_display_types.h" 40 #include "intel_display_wa.h" 41 #include "intel_lpe_audio.h" 42 43 /** 44 * DOC: High Definition Audio over HDMI and Display Port 45 * 46 * The graphics and audio drivers together support High Definition Audio over 47 * HDMI and Display Port. The audio programming sequences are divided into audio 48 * codec and controller enable and disable sequences. The graphics driver 49 * handles the audio codec sequences, while the audio driver handles the audio 50 * controller sequences. 51 * 52 * The disable sequences must be performed before disabling the transcoder or 53 * port. The enable sequences may only be performed after enabling the 54 * transcoder and port, and after completed link training. Therefore the audio 55 * enable/disable sequences are part of the modeset sequence. 56 * 57 * The codec and controller sequences could be done either parallel or serial, 58 * but generally the ELDV/PD change in the codec sequence indicates to the audio 59 * driver that the controller sequence should start. Indeed, most of the 60 * co-operation between the graphics and audio drivers is handled via audio 61 * related registers. (The notable exception is the power management, not 62 * covered here.) 63 * 64 * The struct &i915_audio_component is used to interact between the graphics 65 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 66 * defined in graphics driver and called in audio driver. The 67 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 68 */ 69 70 struct intel_audio_funcs { 71 void (*audio_codec_enable)(struct intel_encoder *encoder, 72 const struct intel_crtc_state *crtc_state, 73 const struct drm_connector_state *conn_state); 74 void (*audio_codec_disable)(struct intel_encoder *encoder, 75 const struct intel_crtc_state *old_crtc_state, 76 const struct drm_connector_state *old_conn_state); 77 void (*audio_codec_get_config)(struct intel_encoder *encoder, 78 struct intel_crtc_state *crtc_state); 79 }; 80 81 struct hdmi_aud_ncts { 82 int sample_rate; 83 int clock; 84 int n; 85 int cts; 86 }; 87 88 static const struct { 89 int clock; 90 u32 config; 91 } hdmi_audio_clock[] = { 92 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 93 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 94 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 95 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 96 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 97 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 98 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 99 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 100 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 101 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 102 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 103 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 104 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 105 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 106 }; 107 108 /* HDMI N/CTS table */ 109 #define TMDS_297M 297000 110 #define TMDS_296M 296703 111 #define TMDS_594M 594000 112 #define TMDS_593M 593407 113 114 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 115 { 32000, TMDS_296M, 5824, 421875 }, 116 { 32000, TMDS_297M, 3072, 222750 }, 117 { 32000, TMDS_593M, 5824, 843750 }, 118 { 32000, TMDS_594M, 3072, 445500 }, 119 { 44100, TMDS_296M, 4459, 234375 }, 120 { 44100, TMDS_297M, 4704, 247500 }, 121 { 44100, TMDS_593M, 8918, 937500 }, 122 { 44100, TMDS_594M, 9408, 990000 }, 123 { 88200, TMDS_296M, 8918, 234375 }, 124 { 88200, TMDS_297M, 9408, 247500 }, 125 { 88200, TMDS_593M, 17836, 937500 }, 126 { 88200, TMDS_594M, 18816, 990000 }, 127 { 176400, TMDS_296M, 17836, 234375 }, 128 { 176400, TMDS_297M, 18816, 247500 }, 129 { 176400, TMDS_593M, 35672, 937500 }, 130 { 176400, TMDS_594M, 37632, 990000 }, 131 { 48000, TMDS_296M, 5824, 281250 }, 132 { 48000, TMDS_297M, 5120, 247500 }, 133 { 48000, TMDS_593M, 5824, 562500 }, 134 { 48000, TMDS_594M, 6144, 594000 }, 135 { 96000, TMDS_296M, 11648, 281250 }, 136 { 96000, TMDS_297M, 10240, 247500 }, 137 { 96000, TMDS_593M, 11648, 562500 }, 138 { 96000, TMDS_594M, 12288, 594000 }, 139 { 192000, TMDS_296M, 23296, 281250 }, 140 { 192000, TMDS_297M, 20480, 247500 }, 141 { 192000, TMDS_593M, 23296, 562500 }, 142 { 192000, TMDS_594M, 24576, 594000 }, 143 }; 144 145 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 146 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 147 #define TMDS_371M 371250 148 #define TMDS_370M 370878 149 150 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 151 { 32000, TMDS_370M, 5824, 527344 }, 152 { 32000, TMDS_371M, 6144, 556875 }, 153 { 44100, TMDS_370M, 8918, 585938 }, 154 { 44100, TMDS_371M, 4704, 309375 }, 155 { 88200, TMDS_370M, 17836, 585938 }, 156 { 88200, TMDS_371M, 9408, 309375 }, 157 { 176400, TMDS_370M, 35672, 585938 }, 158 { 176400, TMDS_371M, 18816, 309375 }, 159 { 48000, TMDS_370M, 11648, 703125 }, 160 { 48000, TMDS_371M, 5120, 309375 }, 161 { 96000, TMDS_370M, 23296, 703125 }, 162 { 96000, TMDS_371M, 10240, 309375 }, 163 { 192000, TMDS_370M, 46592, 703125 }, 164 { 192000, TMDS_371M, 20480, 309375 }, 165 }; 166 167 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 168 #define TMDS_445_5M 445500 169 #define TMDS_445M 445054 170 171 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 172 { 32000, TMDS_445M, 5824, 632813 }, 173 { 32000, TMDS_445_5M, 4096, 445500 }, 174 { 44100, TMDS_445M, 8918, 703125 }, 175 { 44100, TMDS_445_5M, 4704, 371250 }, 176 { 88200, TMDS_445M, 17836, 703125 }, 177 { 88200, TMDS_445_5M, 9408, 371250 }, 178 { 176400, TMDS_445M, 35672, 703125 }, 179 { 176400, TMDS_445_5M, 18816, 371250 }, 180 { 48000, TMDS_445M, 5824, 421875 }, 181 { 48000, TMDS_445_5M, 5120, 371250 }, 182 { 96000, TMDS_445M, 11648, 421875 }, 183 { 96000, TMDS_445_5M, 10240, 371250 }, 184 { 192000, TMDS_445M, 23296, 421875 }, 185 { 192000, TMDS_445_5M, 20480, 371250 }, 186 }; 187 188 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 189 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 190 { 191 struct intel_display *display = to_intel_display(crtc_state); 192 const struct drm_display_mode *adjusted_mode = 193 &crtc_state->hw.adjusted_mode; 194 int i; 195 196 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 197 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 198 break; 199 } 200 201 if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500) 202 i = ARRAY_SIZE(hdmi_audio_clock); 203 204 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 205 drm_dbg_kms(display->drm, 206 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 207 adjusted_mode->crtc_clock); 208 i = 1; 209 } 210 211 drm_dbg_kms(display->drm, 212 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 213 hdmi_audio_clock[i].clock, 214 hdmi_audio_clock[i].config); 215 216 return hdmi_audio_clock[i].config; 217 } 218 219 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 220 int rate) 221 { 222 const struct hdmi_aud_ncts *hdmi_ncts_table; 223 int i, size; 224 225 if (crtc_state->pipe_bpp == 36) { 226 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 227 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 228 } else if (crtc_state->pipe_bpp == 30) { 229 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 230 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 231 } else { 232 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 233 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 234 } 235 236 for (i = 0; i < size; i++) { 237 if (rate == hdmi_ncts_table[i].sample_rate && 238 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 239 return hdmi_ncts_table[i].n; 240 } 241 } 242 return 0; 243 } 244 245 /* ELD buffer size in dwords */ 246 static int g4x_eld_buffer_size(struct intel_display *display) 247 { 248 u32 tmp; 249 250 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); 251 252 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); 253 } 254 255 static void g4x_audio_codec_get_config(struct intel_encoder *encoder, 256 struct intel_crtc_state *crtc_state) 257 { 258 struct intel_display *display = to_intel_display(encoder); 259 u32 *eld = (u32 *)crtc_state->eld; 260 int eld_buffer_size, len, i; 261 u32 tmp; 262 263 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); 264 if ((tmp & G4X_ELD_VALID) == 0) 265 return; 266 267 intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); 268 269 eld_buffer_size = g4x_eld_buffer_size(display); 270 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size); 271 272 for (i = 0; i < len; i++) 273 eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID); 274 } 275 276 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 277 const struct intel_crtc_state *old_crtc_state, 278 const struct drm_connector_state *old_conn_state) 279 { 280 struct intel_display *display = to_intel_display(encoder); 281 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 282 283 /* Invalidate ELD */ 284 intel_de_rmw(display, G4X_AUD_CNTL_ST, 285 G4X_ELD_VALID, 0); 286 287 intel_crtc_wait_for_next_vblank(crtc); 288 intel_crtc_wait_for_next_vblank(crtc); 289 } 290 291 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 292 const struct intel_crtc_state *crtc_state, 293 const struct drm_connector_state *conn_state) 294 { 295 struct intel_display *display = to_intel_display(encoder); 296 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 297 const u32 *eld = (const u32 *)crtc_state->eld; 298 int eld_buffer_size, len, i; 299 300 intel_crtc_wait_for_next_vblank(crtc); 301 302 intel_de_rmw(display, G4X_AUD_CNTL_ST, 303 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); 304 305 eld_buffer_size = g4x_eld_buffer_size(display); 306 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size); 307 308 for (i = 0; i < len; i++) 309 intel_de_write(display, G4X_HDMIW_HDMIEDID, eld[i]); 310 for (; i < eld_buffer_size; i++) 311 intel_de_write(display, G4X_HDMIW_HDMIEDID, 0); 312 313 drm_WARN_ON(display->drm, 314 (intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); 315 316 intel_de_rmw(display, G4X_AUD_CNTL_ST, 317 0, G4X_ELD_VALID); 318 } 319 320 static void 321 hsw_dp_audio_config_update(struct intel_encoder *encoder, 322 const struct intel_crtc_state *crtc_state) 323 { 324 struct intel_display *display = to_intel_display(encoder); 325 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 326 327 /* Enable time stamps. Let HW calculate Maud/Naud values */ 328 intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), 329 AUD_CONFIG_N_VALUE_INDEX | 330 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK | 331 AUD_CONFIG_UPPER_N_MASK | 332 AUD_CONFIG_LOWER_N_MASK | 333 AUD_CONFIG_N_PROG_ENABLE, 334 AUD_CONFIG_N_VALUE_INDEX); 335 336 } 337 338 static void 339 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 340 const struct intel_crtc_state *crtc_state) 341 { 342 struct intel_display *display = to_intel_display(encoder); 343 struct i915_audio_component *acomp = display->audio.component; 344 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 345 enum port port = encoder->port; 346 int n, rate; 347 u32 tmp; 348 349 rate = acomp ? acomp->aud_sample_rate[port] : 0; 350 351 tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder)); 352 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 353 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 354 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 355 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 356 357 n = audio_config_hdmi_get_n(crtc_state, rate); 358 if (n != 0) { 359 drm_dbg_kms(display->drm, "using N %d\n", n); 360 361 tmp &= ~AUD_CONFIG_N_MASK; 362 tmp |= AUD_CONFIG_N(n); 363 tmp |= AUD_CONFIG_N_PROG_ENABLE; 364 } else { 365 drm_dbg_kms(display->drm, "using automatic N\n"); 366 } 367 368 intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp); 369 370 /* 371 * Let's disable "Enable CTS or M Prog bit" 372 * and let HW calculate the value 373 */ 374 tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 375 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 376 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 377 intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 378 } 379 380 static void 381 hsw_audio_config_update(struct intel_encoder *encoder, 382 const struct intel_crtc_state *crtc_state) 383 { 384 if (intel_crtc_has_dp_encoder(crtc_state)) 385 hsw_dp_audio_config_update(encoder, crtc_state); 386 else 387 hsw_hdmi_audio_config_update(encoder, crtc_state); 388 } 389 390 static void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state, 391 bool enable) 392 { 393 struct intel_display *display = to_intel_display(crtc_state); 394 enum transcoder trans = crtc_state->cpu_transcoder; 395 396 if (!HAS_DP20(display)) 397 return; 398 399 intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 400 enable && crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); 401 } 402 403 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 404 const struct intel_crtc_state *old_crtc_state, 405 const struct drm_connector_state *old_conn_state) 406 { 407 struct intel_display *display = to_intel_display(encoder); 408 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 409 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 410 411 mutex_lock(&display->audio.mutex); 412 413 /* Disable timestamps */ 414 intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), 415 AUD_CONFIG_N_VALUE_INDEX | 416 AUD_CONFIG_UPPER_N_MASK | 417 AUD_CONFIG_LOWER_N_MASK, 418 AUD_CONFIG_N_PROG_ENABLE | 419 (intel_crtc_has_dp_encoder(old_crtc_state) ? 420 AUD_CONFIG_N_VALUE_INDEX : 0)); 421 422 /* Invalidate ELD */ 423 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 424 AUDIO_ELD_VALID(cpu_transcoder), 0); 425 426 intel_crtc_wait_for_next_vblank(crtc); 427 intel_crtc_wait_for_next_vblank(crtc); 428 429 /* Disable audio presence detect */ 430 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 431 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); 432 433 /* 434 * WA_14020863754: Implement Audio Workaround 435 * Corner case with Min Hblank Fix can cause audio hang 436 */ 437 if (intel_display_wa(display, INTEL_DISPLAY_WA_14020863754)) 438 intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); 439 440 intel_audio_sdp_split_update(old_crtc_state, false); 441 442 mutex_unlock(&display->audio.mutex); 443 } 444 445 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 446 const struct intel_crtc_state *crtc_state) 447 { 448 struct intel_display *display = to_intel_display(encoder); 449 unsigned int link_clks_available, link_clks_required; 450 unsigned int tu_data, tu_line, link_clks_active; 451 unsigned int h_active, h_total, hblank_delta, pixel_clk; 452 unsigned int fec_coeff, cdclk, vdsc_bppx16; 453 unsigned int link_clk, lanes; 454 unsigned int hblank_rise; 455 456 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 457 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 458 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 459 vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16; 460 cdclk = display->cdclk.hw.cdclk; 461 /* fec= 0.972261, using rounding multiplier of 1000000 */ 462 fec_coeff = 972261; 463 link_clk = crtc_state->port_clock; 464 lanes = crtc_state->lane_count; 465 466 drm_dbg_kms(display->drm, 467 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n", 468 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); 469 470 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) 471 return 0; 472 473 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 474 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 475 476 if (link_clks_available > link_clks_required) 477 hblank_delta = 32; 478 else 479 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 480 mul_u32_u32(link_clk, cdclk)); 481 482 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), 483 mul_u32_u32(link_clk * lanes * 16, fec_coeff)); 484 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 485 mul_u32_u32(64 * pixel_clk, 1000000)); 486 link_clks_active = (tu_line - 1) * 64 + tu_data; 487 488 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 489 490 return h_active - hblank_rise + hblank_delta; 491 } 492 493 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 494 { 495 unsigned int h_active, h_total, pixel_clk; 496 unsigned int link_clk, lanes; 497 498 h_active = crtc_state->hw.adjusted_mode.hdisplay; 499 h_total = crtc_state->hw.adjusted_mode.htotal; 500 pixel_clk = crtc_state->hw.adjusted_mode.clock; 501 link_clk = crtc_state->port_clock; 502 lanes = crtc_state->lane_count; 503 504 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 505 (pixel_clk * (48 / lanes + 2)); 506 } 507 508 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 509 const struct intel_crtc_state *crtc_state) 510 { 511 struct intel_display *display = to_intel_display(encoder); 512 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 513 unsigned int hblank_early_prog, samples_room; 514 unsigned int val; 515 516 if (DISPLAY_VER(display) < 11) 517 return; 518 519 val = intel_de_read(display, AUD_CONFIG_BE); 520 521 if (DISPLAY_VER(display) == 11) 522 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder); 523 else if (DISPLAY_VER(display) >= 12) 524 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder); 525 526 if (crtc_state->dsc.compression_enable && 527 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 528 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 529 /* Get hblank early enable value required */ 530 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder); 531 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 532 if (hblank_early_prog < 32) 533 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32); 534 else if (hblank_early_prog < 64) 535 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64); 536 else if (hblank_early_prog < 96) 537 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96); 538 else 539 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128); 540 541 /* Get samples room value required */ 542 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder); 543 samples_room = calc_samples_room(crtc_state); 544 if (samples_room < 3) 545 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room); 546 else /* Program 0 i.e "All Samples available in buffer" */ 547 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0); 548 } 549 550 intel_de_write(display, AUD_CONFIG_BE, val); 551 } 552 553 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 554 const struct intel_crtc_state *crtc_state, 555 const struct drm_connector_state *conn_state) 556 { 557 struct intel_display *display = to_intel_display(encoder); 558 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 559 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 560 561 mutex_lock(&display->audio.mutex); 562 563 /* Enable Audio WA for 4k DSC usecases */ 564 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 565 enable_audio_dsc_wa(encoder, crtc_state); 566 567 intel_audio_sdp_split_update(crtc_state, true); 568 569 /* 570 * WA_14020863754: Implement Audio Workaround 571 * Corner case with Min Hblank Fix can cause audio hang 572 */ 573 if (intel_display_wa(display, INTEL_DISPLAY_WA_14020863754)) 574 intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); 575 576 /* Enable audio presence detect */ 577 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 578 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); 579 580 intel_crtc_wait_for_next_vblank(crtc); 581 582 /* Invalidate ELD */ 583 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 584 AUDIO_ELD_VALID(cpu_transcoder), 0); 585 586 /* 587 * The audio component is used to convey the ELD 588 * instead using of the hardware ELD buffer. 589 */ 590 591 /* Enable timestamps */ 592 hsw_audio_config_update(encoder, crtc_state); 593 594 mutex_unlock(&display->audio.mutex); 595 } 596 597 struct ibx_audio_regs { 598 intel_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 599 }; 600 601 static void ibx_audio_regs_init(struct intel_display *display, 602 enum pipe pipe, 603 struct ibx_audio_regs *regs) 604 { 605 if (display->platform.valleyview || display->platform.cherryview) { 606 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 607 regs->aud_config = VLV_AUD_CFG(pipe); 608 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 609 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 610 } else if (HAS_PCH_CPT(display)) { 611 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 612 regs->aud_config = CPT_AUD_CFG(pipe); 613 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 614 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 615 } else if (HAS_PCH_IBX(display)) { 616 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 617 regs->aud_config = IBX_AUD_CFG(pipe); 618 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 619 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 620 } 621 } 622 623 static void ibx_audio_codec_disable(struct intel_encoder *encoder, 624 const struct intel_crtc_state *old_crtc_state, 625 const struct drm_connector_state *old_conn_state) 626 { 627 struct intel_display *display = to_intel_display(encoder); 628 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 629 enum port port = encoder->port; 630 enum pipe pipe = crtc->pipe; 631 struct ibx_audio_regs regs; 632 633 if (drm_WARN_ON(display->drm, port == PORT_A)) 634 return; 635 636 ibx_audio_regs_init(display, pipe, ®s); 637 638 mutex_lock(&display->audio.mutex); 639 640 /* Disable timestamps */ 641 intel_de_rmw(display, regs.aud_config, 642 AUD_CONFIG_N_VALUE_INDEX | 643 AUD_CONFIG_UPPER_N_MASK | 644 AUD_CONFIG_LOWER_N_MASK, 645 AUD_CONFIG_N_PROG_ENABLE | 646 (intel_crtc_has_dp_encoder(old_crtc_state) ? 647 AUD_CONFIG_N_VALUE_INDEX : 0)); 648 649 /* Invalidate ELD */ 650 intel_de_rmw(display, regs.aud_cntrl_st2, 651 IBX_ELD_VALID(port), 0); 652 653 mutex_unlock(&display->audio.mutex); 654 655 intel_crtc_wait_for_next_vblank(crtc); 656 intel_crtc_wait_for_next_vblank(crtc); 657 } 658 659 static void ibx_audio_codec_enable(struct intel_encoder *encoder, 660 const struct intel_crtc_state *crtc_state, 661 const struct drm_connector_state *conn_state) 662 { 663 struct intel_display *display = to_intel_display(encoder); 664 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 665 enum port port = encoder->port; 666 enum pipe pipe = crtc->pipe; 667 struct ibx_audio_regs regs; 668 669 if (drm_WARN_ON(display->drm, port == PORT_A)) 670 return; 671 672 intel_crtc_wait_for_next_vblank(crtc); 673 674 ibx_audio_regs_init(display, pipe, ®s); 675 676 mutex_lock(&display->audio.mutex); 677 678 /* Invalidate ELD */ 679 intel_de_rmw(display, regs.aud_cntrl_st2, 680 IBX_ELD_VALID(port), 0); 681 682 /* 683 * The audio component is used to convey the ELD 684 * instead using of the hardware ELD buffer. 685 */ 686 687 /* Enable timestamps */ 688 intel_de_rmw(display, regs.aud_config, 689 AUD_CONFIG_N_VALUE_INDEX | 690 AUD_CONFIG_N_PROG_ENABLE | 691 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 692 (intel_crtc_has_dp_encoder(crtc_state) ? 693 AUD_CONFIG_N_VALUE_INDEX : 694 audio_config_hdmi_pixel_clock(crtc_state))); 695 696 mutex_unlock(&display->audio.mutex); 697 } 698 699 bool intel_audio_compute_config(struct intel_encoder *encoder, 700 struct intel_crtc_state *crtc_state, 701 struct drm_connector_state *conn_state) 702 { 703 struct intel_display *display = to_intel_display(encoder); 704 struct drm_connector *connector = conn_state->connector; 705 const struct drm_display_mode *adjusted_mode = 706 &crtc_state->hw.adjusted_mode; 707 708 mutex_lock(&connector->eld_mutex); 709 if (!connector->eld[0]) { 710 drm_dbg_kms(display->drm, 711 "Bogus ELD on [CONNECTOR:%d:%s]\n", 712 connector->base.id, connector->name); 713 mutex_unlock(&connector->eld_mutex); 714 return false; 715 } 716 717 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld)); 718 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); 719 720 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 721 mutex_unlock(&connector->eld_mutex); 722 723 return true; 724 } 725 726 /** 727 * intel_audio_codec_enable - Enable the audio codec for HD audio 728 * @encoder: encoder on which to enable audio 729 * @crtc_state: pointer to the current crtc state. 730 * @conn_state: pointer to the current connector state. 731 * 732 * The enable sequences may only be performed after enabling the transcoder and 733 * port, and after completed link training. 734 */ 735 void intel_audio_codec_enable(struct intel_encoder *encoder, 736 const struct intel_crtc_state *crtc_state, 737 const struct drm_connector_state *conn_state) 738 { 739 struct intel_display *display = to_intel_display(encoder); 740 struct i915_audio_component *acomp = display->audio.component; 741 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 742 struct intel_connector *connector = to_intel_connector(conn_state->connector); 743 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 744 struct intel_audio_state *audio_state; 745 enum port port = encoder->port; 746 747 if (!crtc_state->has_audio) 748 return; 749 750 drm_dbg_kms(display->drm, 751 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", 752 connector->base.base.id, connector->base.name, 753 encoder->base.base.id, encoder->base.name, 754 crtc->base.base.id, crtc->base.name, 755 drm_eld_size(crtc_state->eld)); 756 757 if (display->audio.funcs) 758 display->audio.funcs->audio_codec_enable(encoder, crtc_state, conn_state); 759 760 mutex_lock(&display->audio.mutex); 761 762 audio_state = &display->audio.state[cpu_transcoder]; 763 764 audio_state->encoder = encoder; 765 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld)); 766 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld)); 767 768 mutex_unlock(&display->audio.mutex); 769 770 if (acomp && acomp->base.audio_ops && 771 acomp->base.audio_ops->pin_eld_notify) { 772 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 773 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 774 cpu_transcoder = -1; 775 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 776 (int)port, (int)cpu_transcoder); 777 } 778 779 intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld, 780 crtc_state->port_clock, 781 intel_crtc_has_dp_encoder(crtc_state)); 782 } 783 784 /** 785 * intel_audio_codec_disable - Disable the audio codec for HD audio 786 * @encoder: encoder on which to disable audio 787 * @old_crtc_state: pointer to the old crtc state. 788 * @old_conn_state: pointer to the old connector state. 789 * 790 * The disable sequences must be performed before disabling the transcoder or 791 * port. 792 */ 793 void intel_audio_codec_disable(struct intel_encoder *encoder, 794 const struct intel_crtc_state *old_crtc_state, 795 const struct drm_connector_state *old_conn_state) 796 { 797 struct intel_display *display = to_intel_display(encoder); 798 struct i915_audio_component *acomp = display->audio.component; 799 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 800 struct intel_connector *connector = to_intel_connector(old_conn_state->connector); 801 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 802 struct intel_audio_state *audio_state; 803 enum port port = encoder->port; 804 805 if (!old_crtc_state->has_audio) 806 return; 807 808 drm_dbg_kms(display->drm, 809 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", 810 connector->base.base.id, connector->base.name, 811 encoder->base.base.id, encoder->base.name, 812 crtc->base.base.id, crtc->base.name); 813 814 if (display->audio.funcs) 815 display->audio.funcs->audio_codec_disable(encoder, old_crtc_state, old_conn_state); 816 817 mutex_lock(&display->audio.mutex); 818 819 audio_state = &display->audio.state[cpu_transcoder]; 820 821 audio_state->encoder = NULL; 822 memset(audio_state->eld, 0, sizeof(audio_state->eld)); 823 824 mutex_unlock(&display->audio.mutex); 825 826 if (acomp && acomp->base.audio_ops && 827 acomp->base.audio_ops->pin_eld_notify) { 828 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 829 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 830 cpu_transcoder = -1; 831 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 832 (int)port, (int)cpu_transcoder); 833 } 834 835 intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false); 836 } 837 838 static void intel_acomp_get_config(struct intel_encoder *encoder, 839 struct intel_crtc_state *crtc_state) 840 { 841 struct intel_display *display = to_intel_display(encoder); 842 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 843 struct intel_audio_state *audio_state; 844 845 mutex_lock(&display->audio.mutex); 846 847 audio_state = &display->audio.state[cpu_transcoder]; 848 849 if (audio_state->encoder) 850 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld)); 851 852 mutex_unlock(&display->audio.mutex); 853 } 854 855 void intel_audio_codec_get_config(struct intel_encoder *encoder, 856 struct intel_crtc_state *crtc_state) 857 { 858 struct intel_display *display = to_intel_display(encoder); 859 860 if (!crtc_state->has_audio) 861 return; 862 863 if (display->audio.funcs) 864 display->audio.funcs->audio_codec_get_config(encoder, crtc_state); 865 } 866 867 static const struct intel_audio_funcs g4x_audio_funcs = { 868 .audio_codec_enable = g4x_audio_codec_enable, 869 .audio_codec_disable = g4x_audio_codec_disable, 870 .audio_codec_get_config = g4x_audio_codec_get_config, 871 }; 872 873 static const struct intel_audio_funcs ibx_audio_funcs = { 874 .audio_codec_enable = ibx_audio_codec_enable, 875 .audio_codec_disable = ibx_audio_codec_disable, 876 .audio_codec_get_config = intel_acomp_get_config, 877 }; 878 879 static const struct intel_audio_funcs hsw_audio_funcs = { 880 .audio_codec_enable = hsw_audio_codec_enable, 881 .audio_codec_disable = hsw_audio_codec_disable, 882 .audio_codec_get_config = intel_acomp_get_config, 883 }; 884 885 /** 886 * intel_audio_hooks_init - Set up chip specific audio hooks 887 * @display: display device 888 */ 889 void intel_audio_hooks_init(struct intel_display *display) 890 { 891 if (display->platform.g4x) 892 display->audio.funcs = &g4x_audio_funcs; 893 else if (display->platform.valleyview || display->platform.cherryview || 894 HAS_PCH_CPT(display) || HAS_PCH_IBX(display)) 895 display->audio.funcs = &ibx_audio_funcs; 896 else if (display->platform.haswell || DISPLAY_VER(display) >= 8) 897 display->audio.funcs = &hsw_audio_funcs; 898 } 899 900 struct aud_ts_cdclk_m_n { 901 u8 m; 902 u16 n; 903 }; 904 905 void intel_audio_cdclk_change_pre(struct intel_display *display) 906 { 907 if (DISPLAY_VER(display) >= 13) 908 intel_de_rmw(display, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 909 } 910 911 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 912 { 913 aud_ts->m = 60; 914 aud_ts->n = cdclk * aud_ts->m / 24000; 915 } 916 917 void intel_audio_cdclk_change_post(struct intel_display *display) 918 { 919 struct aud_ts_cdclk_m_n aud_ts; 920 921 if (DISPLAY_VER(display) >= 13) { 922 get_aud_ts_cdclk_m_n(display->cdclk.hw.ref, 923 display->cdclk.hw.cdclk, &aud_ts); 924 925 intel_de_write(display, AUD_TS_CDCLK_N, aud_ts.n); 926 intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 927 drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n", 928 aud_ts.m, aud_ts.n); 929 } 930 } 931 932 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 933 struct intel_crtc *crtc, 934 bool enable) 935 { 936 struct intel_cdclk_state *cdclk_state; 937 int ret; 938 939 /* need to hold at least one crtc lock for the global state */ 940 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 941 if (ret) 942 return ret; 943 944 cdclk_state = intel_atomic_get_cdclk_state(state); 945 if (IS_ERR(cdclk_state)) 946 return PTR_ERR(cdclk_state); 947 948 intel_cdclk_force_min_cdclk(cdclk_state, enable ? 2 * 96000 : 0); 949 950 return drm_atomic_commit(&state->base); 951 } 952 953 static void glk_force_audio_cdclk(struct intel_display *display, 954 bool enable) 955 { 956 struct drm_modeset_acquire_ctx ctx; 957 struct drm_atomic_commit *state; 958 struct intel_crtc *crtc; 959 int ret; 960 961 crtc = intel_first_crtc(display); 962 if (!crtc) 963 return; 964 965 drm_modeset_acquire_init(&ctx, 0); 966 state = drm_atomic_commit_alloc(display->drm); 967 if (drm_WARN_ON(display->drm, !state)) 968 return; 969 970 state->acquire_ctx = &ctx; 971 to_intel_atomic_state(state)->internal = true; 972 973 retry: 974 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 975 enable); 976 if (ret == -EDEADLK) { 977 drm_atomic_commit_clear(state); 978 drm_modeset_backoff(&ctx); 979 goto retry; 980 } 981 982 drm_WARN_ON(display->drm, ret); 983 984 drm_atomic_commit_put(state); 985 986 drm_modeset_drop_locks(&ctx); 987 drm_modeset_acquire_fini(&ctx); 988 } 989 990 int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) 991 { 992 struct intel_display *display = to_intel_display(crtc_state); 993 int min_cdclk = 0; 994 995 if (!crtc_state->has_audio) 996 return 0; 997 998 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 999 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 1000 * there may be audio corruption or screen corruption." This cdclk 1001 * restriction for GLK is 316.8 MHz. 1002 */ 1003 if (intel_crtc_has_dp_encoder(crtc_state) && 1004 crtc_state->port_clock >= 540000 && 1005 crtc_state->lane_count == 4) { 1006 if (DISPLAY_VER(display) == 10) { 1007 /* Display WA #1145: glk */ 1008 min_cdclk = max(min_cdclk, 316800); 1009 } else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) { 1010 /* Display WA #1144: skl,bxt */ 1011 min_cdclk = max(min_cdclk, 432000); 1012 } 1013 } 1014 1015 /* 1016 * According to BSpec, "The CD clock frequency must be at least twice 1017 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 1018 */ 1019 if (DISPLAY_VER(display) >= 9) 1020 min_cdclk = max(min_cdclk, 2 * 96000); 1021 1022 /* 1023 * "For DP audio configuration, cdclk frequency shall be set to 1024 * meet the following requirements: 1025 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 1026 * 270 | 320 or higher 1027 * 162 | 200 or higher" 1028 */ 1029 if ((display->platform.valleyview || display->platform.cherryview) && 1030 intel_crtc_has_dp_encoder(crtc_state)) 1031 min_cdclk = max(min_cdclk, crtc_state->port_clock); 1032 1033 return min_cdclk; 1034 } 1035 1036 static unsigned long intel_audio_component_get_power(struct device *kdev) 1037 { 1038 struct intel_display *display = to_intel_display(kdev); 1039 struct ref_tracker *wakeref; 1040 1041 /* Catch potential impedance mismatches before they occur! */ 1042 BUILD_BUG_ON(sizeof(wakeref) > sizeof(unsigned long)); 1043 1044 wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK); 1045 1046 if (display->audio.power_refcount++ == 0) { 1047 if (DISPLAY_VER(display) >= 9) { 1048 intel_de_write(display, AUD_FREQ_CNTRL, 1049 display->audio.freq_cntrl); 1050 drm_dbg_kms(display->drm, 1051 "restored AUD_FREQ_CNTRL to 0x%x\n", 1052 display->audio.freq_cntrl); 1053 } 1054 1055 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1056 if (display->platform.geminilake) 1057 glk_force_audio_cdclk(display, true); 1058 1059 if (DISPLAY_VER(display) >= 10) 1060 intel_de_rmw(display, AUD_PIN_BUF_CTL, 1061 0, AUD_PIN_BUF_ENABLE); 1062 } 1063 1064 return (unsigned long)wakeref; 1065 } 1066 1067 static void intel_audio_component_put_power(struct device *kdev, 1068 unsigned long cookie) 1069 { 1070 struct intel_display *display = to_intel_display(kdev); 1071 struct ref_tracker *wakeref = (struct ref_tracker *)cookie; 1072 1073 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1074 if (--display->audio.power_refcount == 0) 1075 if (display->platform.geminilake) 1076 glk_force_audio_cdclk(display, false); 1077 1078 intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref); 1079 } 1080 1081 static void intel_audio_component_codec_wake_override(struct device *kdev, 1082 bool enable) 1083 { 1084 struct intel_display *display = to_intel_display(kdev); 1085 unsigned long cookie; 1086 1087 if (DISPLAY_VER(display) < 9) 1088 return; 1089 1090 cookie = intel_audio_component_get_power(kdev); 1091 1092 /* 1093 * Enable/disable generating the codec wake signal, overriding the 1094 * internal logic to generate the codec wake to controller. 1095 */ 1096 intel_de_rmw(display, HSW_AUD_CHICKENBIT, 1097 SKL_AUD_CODEC_WAKE_SIGNAL, 0); 1098 usleep_range(1000, 1500); 1099 1100 if (enable) { 1101 intel_de_rmw(display, HSW_AUD_CHICKENBIT, 1102 0, SKL_AUD_CODEC_WAKE_SIGNAL); 1103 usleep_range(1000, 1500); 1104 } 1105 1106 intel_audio_component_put_power(kdev, cookie); 1107 } 1108 1109 /* Get CDCLK in kHz */ 1110 static int intel_audio_component_get_cdclk_freq(struct device *kdev) 1111 { 1112 struct intel_display *display = to_intel_display(kdev); 1113 1114 if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display))) 1115 return -ENODEV; 1116 1117 return display->cdclk.hw.cdclk; 1118 } 1119 1120 /* 1121 * get the intel audio state according to the parameter port and cpu_transcoder 1122 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder], 1123 * when port is matched 1124 * MST & (cpu_transcoder < 0): this is invalid 1125 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry) 1126 * will get the right intel_encoder with port matched 1127 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched 1128 */ 1129 static struct intel_audio_state *find_audio_state(struct intel_display *display, 1130 int port, int cpu_transcoder) 1131 { 1132 /* MST */ 1133 if (cpu_transcoder >= 0) { 1134 struct intel_audio_state *audio_state; 1135 struct intel_encoder *encoder; 1136 1137 if (drm_WARN_ON(display->drm, 1138 cpu_transcoder >= ARRAY_SIZE(display->audio.state))) 1139 return NULL; 1140 1141 audio_state = &display->audio.state[cpu_transcoder]; 1142 encoder = audio_state->encoder; 1143 1144 if (encoder && encoder->port == port && 1145 encoder->type == INTEL_OUTPUT_DP_MST) 1146 return audio_state; 1147 } 1148 1149 /* Non-MST */ 1150 if (cpu_transcoder > 0) 1151 return NULL; 1152 1153 for_each_cpu_transcoder(display, cpu_transcoder) { 1154 struct intel_audio_state *audio_state; 1155 struct intel_encoder *encoder; 1156 1157 audio_state = &display->audio.state[cpu_transcoder]; 1158 encoder = audio_state->encoder; 1159 1160 if (encoder && encoder->port == port && 1161 encoder->type != INTEL_OUTPUT_DP_MST) 1162 return audio_state; 1163 } 1164 1165 return NULL; 1166 } 1167 1168 static int intel_audio_component_sync_audio_rate(struct device *kdev, int port, 1169 int cpu_transcoder, int rate) 1170 { 1171 struct intel_display *display = to_intel_display(kdev); 1172 struct i915_audio_component *acomp = display->audio.component; 1173 const struct intel_audio_state *audio_state; 1174 struct intel_encoder *encoder; 1175 struct intel_crtc *crtc; 1176 unsigned long cookie; 1177 int err = 0; 1178 1179 if (!HAS_DDI(display)) 1180 return 0; 1181 1182 cookie = intel_audio_component_get_power(kdev); 1183 mutex_lock(&display->audio.mutex); 1184 1185 audio_state = find_audio_state(display, port, cpu_transcoder); 1186 if (!audio_state) { 1187 drm_dbg_kms(display->drm, "Not valid for port %c\n", 1188 port_name(port)); 1189 err = -ENODEV; 1190 goto unlock; 1191 } 1192 1193 encoder = audio_state->encoder; 1194 1195 /* FIXME stop using the legacy crtc pointer */ 1196 crtc = to_intel_crtc(encoder->base.crtc); 1197 1198 /* port must be valid now, otherwise the cpu_transcoder will be invalid */ 1199 acomp->aud_sample_rate[port] = rate; 1200 1201 /* FIXME get rid of the crtc->config stuff */ 1202 hsw_audio_config_update(encoder, crtc->config); 1203 1204 unlock: 1205 mutex_unlock(&display->audio.mutex); 1206 intel_audio_component_put_power(kdev, cookie); 1207 return err; 1208 } 1209 1210 static int intel_audio_component_get_eld(struct device *kdev, int port, 1211 int cpu_transcoder, bool *enabled, 1212 unsigned char *buf, int max_bytes) 1213 { 1214 struct intel_display *display = to_intel_display(kdev); 1215 const struct intel_audio_state *audio_state; 1216 int ret = 0; 1217 1218 mutex_lock(&display->audio.mutex); 1219 1220 audio_state = find_audio_state(display, port, cpu_transcoder); 1221 if (!audio_state) { 1222 drm_dbg_kms(display->drm, "Not valid for port %c\n", 1223 port_name(port)); 1224 mutex_unlock(&display->audio.mutex); 1225 return -EINVAL; 1226 } 1227 1228 *enabled = audio_state->encoder != NULL; 1229 if (*enabled) { 1230 const u8 *eld = audio_state->eld; 1231 1232 ret = drm_eld_size(eld); 1233 memcpy(buf, eld, min(max_bytes, ret)); 1234 } 1235 1236 mutex_unlock(&display->audio.mutex); 1237 return ret; 1238 } 1239 1240 static const struct drm_audio_component_ops intel_audio_component_ops = { 1241 .owner = THIS_MODULE, 1242 .get_power = intel_audio_component_get_power, 1243 .put_power = intel_audio_component_put_power, 1244 .codec_wake_override = intel_audio_component_codec_wake_override, 1245 .get_cdclk_freq = intel_audio_component_get_cdclk_freq, 1246 .sync_audio_rate = intel_audio_component_sync_audio_rate, 1247 .get_eld = intel_audio_component_get_eld, 1248 }; 1249 1250 static int intel_audio_component_bind(struct device *drv_kdev, 1251 struct device *hda_kdev, void *data) 1252 { 1253 struct intel_display *display = to_intel_display(drv_kdev); 1254 struct i915_audio_component *acomp = data; 1255 int i; 1256 1257 if (drm_WARN_ON(display->drm, acomp->base.ops || acomp->base.dev)) 1258 return -EEXIST; 1259 1260 if (drm_WARN_ON(display->drm, 1261 !device_link_add(hda_kdev, drv_kdev, 1262 DL_FLAG_STATELESS))) 1263 return -ENOMEM; 1264 1265 drm_modeset_lock_all(display->drm); 1266 acomp->base.ops = &intel_audio_component_ops; 1267 acomp->base.dev = drv_kdev; 1268 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1269 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1270 acomp->aud_sample_rate[i] = 0; 1271 display->audio.component = acomp; 1272 drm_modeset_unlock_all(display->drm); 1273 1274 return 0; 1275 } 1276 1277 static void intel_audio_component_unbind(struct device *drv_kdev, 1278 struct device *hda_kdev, void *data) 1279 { 1280 struct intel_display *display = to_intel_display(drv_kdev); 1281 struct i915_audio_component *acomp = data; 1282 1283 drm_modeset_lock_all(display->drm); 1284 acomp->base.ops = NULL; 1285 acomp->base.dev = NULL; 1286 display->audio.component = NULL; 1287 drm_modeset_unlock_all(display->drm); 1288 1289 device_link_remove(hda_kdev, drv_kdev); 1290 1291 if (display->audio.power_refcount) 1292 drm_err(display->drm, 1293 "audio power refcount %d after unbind\n", 1294 display->audio.power_refcount); 1295 } 1296 1297 static const struct component_ops intel_audio_component_bind_ops = { 1298 .bind = intel_audio_component_bind, 1299 .unbind = intel_audio_component_unbind, 1300 }; 1301 1302 #define AUD_FREQ_TMODE_SHIFT 14 1303 #define AUD_FREQ_4T 0 1304 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1305 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1306 #define AUD_FREQ_BCLK_96M BIT(4) 1307 1308 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1309 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1310 1311 /** 1312 * intel_audio_component_init - initialize and register the audio component 1313 * @display: display device 1314 * 1315 * This will register with the component framework a child component which 1316 * will bind dynamically to the snd_hda_intel driver's corresponding master 1317 * component when the latter is registered. During binding the child 1318 * initializes an instance of struct i915_audio_component which it receives 1319 * from the master. The master can then start to use the interface defined by 1320 * this struct. Each side can break the binding at any point by deregistering 1321 * its own component after which each side's component unbind callback is 1322 * called. 1323 * 1324 * We ignore any error during registration and continue with reduced 1325 * functionality (i.e. without HDMI audio). 1326 */ 1327 static void intel_audio_component_init(struct intel_display *display) 1328 { 1329 u32 aud_freq, aud_freq_init; 1330 1331 if (DISPLAY_VER(display) >= 9) { 1332 aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL); 1333 1334 if (DISPLAY_VER(display) >= 12) 1335 aud_freq = AUD_FREQ_GEN12; 1336 else 1337 aud_freq = aud_freq_init; 1338 1339 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1340 if ((display->platform.tigerlake || display->platform.rocketlake) && 1341 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1342 aud_freq = aud_freq_init; 1343 1344 drm_dbg_kms(display->drm, 1345 "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1346 aud_freq, aud_freq_init); 1347 1348 display->audio.freq_cntrl = aud_freq; 1349 } 1350 1351 /* init with current cdclk */ 1352 intel_audio_cdclk_change_post(display); 1353 } 1354 1355 static void intel_audio_component_register(struct intel_display *display) 1356 { 1357 int ret; 1358 1359 ret = component_add_typed(display->drm->dev, 1360 &intel_audio_component_bind_ops, 1361 I915_COMPONENT_AUDIO); 1362 if (ret < 0) { 1363 drm_err(display->drm, 1364 "failed to add audio component (%d)\n", ret); 1365 /* continue with reduced functionality */ 1366 return; 1367 } 1368 1369 display->audio.component_registered = true; 1370 } 1371 1372 /** 1373 * intel_audio_component_cleanup - deregister the audio component 1374 * @display: display device 1375 * 1376 * Deregisters the audio component, breaking any existing binding to the 1377 * corresponding snd_hda_intel driver's master component. 1378 */ 1379 static void intel_audio_component_cleanup(struct intel_display *display) 1380 { 1381 if (!display->audio.component_registered) 1382 return; 1383 1384 component_del(display->drm->dev, &intel_audio_component_bind_ops); 1385 display->audio.component_registered = false; 1386 } 1387 1388 /** 1389 * intel_audio_init() - Initialize the audio driver either using 1390 * component framework or using lpe audio bridge 1391 * @display: display device 1392 * 1393 */ 1394 void intel_audio_init(struct intel_display *display) 1395 { 1396 if (intel_lpe_audio_init(display) < 0) 1397 intel_audio_component_init(display); 1398 } 1399 1400 void intel_audio_register(struct intel_display *display) 1401 { 1402 if (!display->audio.lpe.platdev) 1403 intel_audio_component_register(display); 1404 } 1405 1406 /** 1407 * intel_audio_deinit() - deinitialize the audio driver 1408 * @display: display device 1409 */ 1410 void intel_audio_deinit(struct intel_display *display) 1411 { 1412 if (display->audio.lpe.platdev) 1413 intel_lpe_audio_teardown(display); 1414 else 1415 intel_audio_component_cleanup(display); 1416 } 1417