1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/drm_eld.h> 29 #include <drm/i915_component.h> 30 31 #include "i915_drv.h" 32 #include "intel_atomic.h" 33 #include "intel_audio.h" 34 #include "intel_audio_regs.h" 35 #include "intel_cdclk.h" 36 #include "intel_crtc.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_lpe_audio.h" 40 41 /** 42 * DOC: High Definition Audio over HDMI and Display Port 43 * 44 * The graphics and audio drivers together support High Definition Audio over 45 * HDMI and Display Port. The audio programming sequences are divided into audio 46 * codec and controller enable and disable sequences. The graphics driver 47 * handles the audio codec sequences, while the audio driver handles the audio 48 * controller sequences. 49 * 50 * The disable sequences must be performed before disabling the transcoder or 51 * port. The enable sequences may only be performed after enabling the 52 * transcoder and port, and after completed link training. Therefore the audio 53 * enable/disable sequences are part of the modeset sequence. 54 * 55 * The codec and controller sequences could be done either parallel or serial, 56 * but generally the ELDV/PD change in the codec sequence indicates to the audio 57 * driver that the controller sequence should start. Indeed, most of the 58 * co-operation between the graphics and audio drivers is handled via audio 59 * related registers. (The notable exception is the power management, not 60 * covered here.) 61 * 62 * The struct &i915_audio_component is used to interact between the graphics 63 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 64 * defined in graphics driver and called in audio driver. The 65 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 66 */ 67 68 struct intel_audio_funcs { 69 void (*audio_codec_enable)(struct intel_encoder *encoder, 70 const struct intel_crtc_state *crtc_state, 71 const struct drm_connector_state *conn_state); 72 void (*audio_codec_disable)(struct intel_encoder *encoder, 73 const struct intel_crtc_state *old_crtc_state, 74 const struct drm_connector_state *old_conn_state); 75 void (*audio_codec_get_config)(struct intel_encoder *encoder, 76 struct intel_crtc_state *crtc_state); 77 }; 78 79 /* DP N/M table */ 80 #define LC_810M 810000 81 #define LC_540M 540000 82 #define LC_270M 270000 83 #define LC_162M 162000 84 85 struct dp_aud_n_m { 86 int sample_rate; 87 int clock; 88 u16 m; 89 u16 n; 90 }; 91 92 struct hdmi_aud_ncts { 93 int sample_rate; 94 int clock; 95 int n; 96 int cts; 97 }; 98 99 /* Values according to DP 1.4 Table 2-104 */ 100 static const struct dp_aud_n_m dp_aud_n_m[] = { 101 { 32000, LC_162M, 1024, 10125 }, 102 { 44100, LC_162M, 784, 5625 }, 103 { 48000, LC_162M, 512, 3375 }, 104 { 64000, LC_162M, 2048, 10125 }, 105 { 88200, LC_162M, 1568, 5625 }, 106 { 96000, LC_162M, 1024, 3375 }, 107 { 128000, LC_162M, 4096, 10125 }, 108 { 176400, LC_162M, 3136, 5625 }, 109 { 192000, LC_162M, 2048, 3375 }, 110 { 32000, LC_270M, 1024, 16875 }, 111 { 44100, LC_270M, 784, 9375 }, 112 { 48000, LC_270M, 512, 5625 }, 113 { 64000, LC_270M, 2048, 16875 }, 114 { 88200, LC_270M, 1568, 9375 }, 115 { 96000, LC_270M, 1024, 5625 }, 116 { 128000, LC_270M, 4096, 16875 }, 117 { 176400, LC_270M, 3136, 9375 }, 118 { 192000, LC_270M, 2048, 5625 }, 119 { 32000, LC_540M, 1024, 33750 }, 120 { 44100, LC_540M, 784, 18750 }, 121 { 48000, LC_540M, 512, 11250 }, 122 { 64000, LC_540M, 2048, 33750 }, 123 { 88200, LC_540M, 1568, 18750 }, 124 { 96000, LC_540M, 1024, 11250 }, 125 { 128000, LC_540M, 4096, 33750 }, 126 { 176400, LC_540M, 3136, 18750 }, 127 { 192000, LC_540M, 2048, 11250 }, 128 { 32000, LC_810M, 1024, 50625 }, 129 { 44100, LC_810M, 784, 28125 }, 130 { 48000, LC_810M, 512, 16875 }, 131 { 64000, LC_810M, 2048, 50625 }, 132 { 88200, LC_810M, 1568, 28125 }, 133 { 96000, LC_810M, 1024, 16875 }, 134 { 128000, LC_810M, 4096, 50625 }, 135 { 176400, LC_810M, 3136, 28125 }, 136 { 192000, LC_810M, 2048, 16875 }, 137 }; 138 139 static const struct dp_aud_n_m * 140 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) 141 { 142 int i; 143 144 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { 145 if (rate == dp_aud_n_m[i].sample_rate && 146 crtc_state->port_clock == dp_aud_n_m[i].clock) 147 return &dp_aud_n_m[i]; 148 } 149 150 return NULL; 151 } 152 153 static const struct { 154 int clock; 155 u32 config; 156 } hdmi_audio_clock[] = { 157 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 158 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 159 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 160 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 161 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 162 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 163 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 164 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 165 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 166 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 167 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 168 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 169 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 170 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 171 }; 172 173 /* HDMI N/CTS table */ 174 #define TMDS_297M 297000 175 #define TMDS_296M 296703 176 #define TMDS_594M 594000 177 #define TMDS_593M 593407 178 179 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 180 { 32000, TMDS_296M, 5824, 421875 }, 181 { 32000, TMDS_297M, 3072, 222750 }, 182 { 32000, TMDS_593M, 5824, 843750 }, 183 { 32000, TMDS_594M, 3072, 445500 }, 184 { 44100, TMDS_296M, 4459, 234375 }, 185 { 44100, TMDS_297M, 4704, 247500 }, 186 { 44100, TMDS_593M, 8918, 937500 }, 187 { 44100, TMDS_594M, 9408, 990000 }, 188 { 88200, TMDS_296M, 8918, 234375 }, 189 { 88200, TMDS_297M, 9408, 247500 }, 190 { 88200, TMDS_593M, 17836, 937500 }, 191 { 88200, TMDS_594M, 18816, 990000 }, 192 { 176400, TMDS_296M, 17836, 234375 }, 193 { 176400, TMDS_297M, 18816, 247500 }, 194 { 176400, TMDS_593M, 35672, 937500 }, 195 { 176400, TMDS_594M, 37632, 990000 }, 196 { 48000, TMDS_296M, 5824, 281250 }, 197 { 48000, TMDS_297M, 5120, 247500 }, 198 { 48000, TMDS_593M, 5824, 562500 }, 199 { 48000, TMDS_594M, 6144, 594000 }, 200 { 96000, TMDS_296M, 11648, 281250 }, 201 { 96000, TMDS_297M, 10240, 247500 }, 202 { 96000, TMDS_593M, 11648, 562500 }, 203 { 96000, TMDS_594M, 12288, 594000 }, 204 { 192000, TMDS_296M, 23296, 281250 }, 205 { 192000, TMDS_297M, 20480, 247500 }, 206 { 192000, TMDS_593M, 23296, 562500 }, 207 { 192000, TMDS_594M, 24576, 594000 }, 208 }; 209 210 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 211 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 212 #define TMDS_371M 371250 213 #define TMDS_370M 370878 214 215 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 216 { 32000, TMDS_370M, 5824, 527344 }, 217 { 32000, TMDS_371M, 6144, 556875 }, 218 { 44100, TMDS_370M, 8918, 585938 }, 219 { 44100, TMDS_371M, 4704, 309375 }, 220 { 88200, TMDS_370M, 17836, 585938 }, 221 { 88200, TMDS_371M, 9408, 309375 }, 222 { 176400, TMDS_370M, 35672, 585938 }, 223 { 176400, TMDS_371M, 18816, 309375 }, 224 { 48000, TMDS_370M, 11648, 703125 }, 225 { 48000, TMDS_371M, 5120, 309375 }, 226 { 96000, TMDS_370M, 23296, 703125 }, 227 { 96000, TMDS_371M, 10240, 309375 }, 228 { 192000, TMDS_370M, 46592, 703125 }, 229 { 192000, TMDS_371M, 20480, 309375 }, 230 }; 231 232 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 233 #define TMDS_445_5M 445500 234 #define TMDS_445M 445054 235 236 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 237 { 32000, TMDS_445M, 5824, 632813 }, 238 { 32000, TMDS_445_5M, 4096, 445500 }, 239 { 44100, TMDS_445M, 8918, 703125 }, 240 { 44100, TMDS_445_5M, 4704, 371250 }, 241 { 88200, TMDS_445M, 17836, 703125 }, 242 { 88200, TMDS_445_5M, 9408, 371250 }, 243 { 176400, TMDS_445M, 35672, 703125 }, 244 { 176400, TMDS_445_5M, 18816, 371250 }, 245 { 48000, TMDS_445M, 5824, 421875 }, 246 { 48000, TMDS_445_5M, 5120, 371250 }, 247 { 96000, TMDS_445M, 11648, 421875 }, 248 { 96000, TMDS_445_5M, 10240, 371250 }, 249 { 192000, TMDS_445M, 23296, 421875 }, 250 { 192000, TMDS_445_5M, 20480, 371250 }, 251 }; 252 253 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 254 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 255 { 256 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 257 const struct drm_display_mode *adjusted_mode = 258 &crtc_state->hw.adjusted_mode; 259 int i; 260 261 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 262 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 263 break; 264 } 265 266 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500) 267 i = ARRAY_SIZE(hdmi_audio_clock); 268 269 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 270 drm_dbg_kms(&i915->drm, 271 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 272 adjusted_mode->crtc_clock); 273 i = 1; 274 } 275 276 drm_dbg_kms(&i915->drm, 277 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 278 hdmi_audio_clock[i].clock, 279 hdmi_audio_clock[i].config); 280 281 return hdmi_audio_clock[i].config; 282 } 283 284 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 285 int rate) 286 { 287 const struct hdmi_aud_ncts *hdmi_ncts_table; 288 int i, size; 289 290 if (crtc_state->pipe_bpp == 36) { 291 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 292 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 293 } else if (crtc_state->pipe_bpp == 30) { 294 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 295 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 296 } else { 297 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 298 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 299 } 300 301 for (i = 0; i < size; i++) { 302 if (rate == hdmi_ncts_table[i].sample_rate && 303 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 304 return hdmi_ncts_table[i].n; 305 } 306 } 307 return 0; 308 } 309 310 /* ELD buffer size in dwords */ 311 static int g4x_eld_buffer_size(struct drm_i915_private *i915) 312 { 313 u32 tmp; 314 315 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); 316 317 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); 318 } 319 320 static void g4x_audio_codec_get_config(struct intel_encoder *encoder, 321 struct intel_crtc_state *crtc_state) 322 { 323 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 324 u32 *eld = (u32 *)crtc_state->eld; 325 int eld_buffer_size, len, i; 326 u32 tmp; 327 328 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); 329 if ((tmp & G4X_ELD_VALID) == 0) 330 return; 331 332 intel_de_rmw(i915, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); 333 334 eld_buffer_size = g4x_eld_buffer_size(i915); 335 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size); 336 337 for (i = 0; i < len; i++) 338 eld[i] = intel_de_read(i915, G4X_HDMIW_HDMIEDID); 339 } 340 341 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 342 const struct intel_crtc_state *old_crtc_state, 343 const struct drm_connector_state *old_conn_state) 344 { 345 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 346 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 347 348 /* Invalidate ELD */ 349 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 350 G4X_ELD_VALID, 0); 351 352 intel_crtc_wait_for_next_vblank(crtc); 353 intel_crtc_wait_for_next_vblank(crtc); 354 } 355 356 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 357 const struct intel_crtc_state *crtc_state, 358 const struct drm_connector_state *conn_state) 359 { 360 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 361 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 362 const u32 *eld = (const u32 *)crtc_state->eld; 363 int eld_buffer_size, len, i; 364 365 intel_crtc_wait_for_next_vblank(crtc); 366 367 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 368 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); 369 370 eld_buffer_size = g4x_eld_buffer_size(i915); 371 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size); 372 373 for (i = 0; i < len; i++) 374 intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]); 375 for (; i < eld_buffer_size; i++) 376 intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0); 377 378 drm_WARN_ON(&i915->drm, 379 (intel_de_read(i915, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); 380 381 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 382 0, G4X_ELD_VALID); 383 } 384 385 static void 386 hsw_dp_audio_config_update(struct intel_encoder *encoder, 387 const struct intel_crtc_state *crtc_state) 388 { 389 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 390 struct i915_audio_component *acomp = i915->display.audio.component; 391 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 392 enum port port = encoder->port; 393 const struct dp_aud_n_m *nm; 394 int rate; 395 u32 tmp; 396 397 rate = acomp ? acomp->aud_sample_rate[port] : 0; 398 nm = audio_config_dp_get_n_m(crtc_state, rate); 399 if (nm) 400 drm_dbg_kms(&i915->drm, "using Maud %u, Naud %u\n", nm->m, 401 nm->n); 402 else 403 drm_dbg_kms(&i915->drm, "using automatic Maud, Naud\n"); 404 405 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder)); 406 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 407 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 408 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 409 tmp |= AUD_CONFIG_N_VALUE_INDEX; 410 411 if (nm) { 412 tmp &= ~AUD_CONFIG_N_MASK; 413 tmp |= AUD_CONFIG_N(nm->n); 414 tmp |= AUD_CONFIG_N_PROG_ENABLE; 415 } 416 417 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp); 418 419 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 420 tmp &= ~AUD_CONFIG_M_MASK; 421 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 422 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 423 424 if (nm) { 425 tmp |= nm->m; 426 tmp |= AUD_M_CTS_M_VALUE_INDEX; 427 tmp |= AUD_M_CTS_M_PROG_ENABLE; 428 } 429 430 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 431 } 432 433 static void 434 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 435 const struct intel_crtc_state *crtc_state) 436 { 437 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 438 struct i915_audio_component *acomp = i915->display.audio.component; 439 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 440 enum port port = encoder->port; 441 int n, rate; 442 u32 tmp; 443 444 rate = acomp ? acomp->aud_sample_rate[port] : 0; 445 446 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder)); 447 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 448 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 449 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 450 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 451 452 n = audio_config_hdmi_get_n(crtc_state, rate); 453 if (n != 0) { 454 drm_dbg_kms(&i915->drm, "using N %d\n", n); 455 456 tmp &= ~AUD_CONFIG_N_MASK; 457 tmp |= AUD_CONFIG_N(n); 458 tmp |= AUD_CONFIG_N_PROG_ENABLE; 459 } else { 460 drm_dbg_kms(&i915->drm, "using automatic N\n"); 461 } 462 463 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp); 464 465 /* 466 * Let's disable "Enable CTS or M Prog bit" 467 * and let HW calculate the value 468 */ 469 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 470 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 471 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 472 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 473 } 474 475 static void 476 hsw_audio_config_update(struct intel_encoder *encoder, 477 const struct intel_crtc_state *crtc_state) 478 { 479 if (intel_crtc_has_dp_encoder(crtc_state)) 480 hsw_dp_audio_config_update(encoder, crtc_state); 481 else 482 hsw_hdmi_audio_config_update(encoder, crtc_state); 483 } 484 485 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 486 const struct intel_crtc_state *old_crtc_state, 487 const struct drm_connector_state *old_conn_state) 488 { 489 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 490 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 491 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 492 493 mutex_lock(&i915->display.audio.mutex); 494 495 /* Disable timestamps */ 496 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), 497 AUD_CONFIG_N_VALUE_INDEX | 498 AUD_CONFIG_UPPER_N_MASK | 499 AUD_CONFIG_LOWER_N_MASK, 500 AUD_CONFIG_N_PROG_ENABLE | 501 (intel_crtc_has_dp_encoder(old_crtc_state) ? 502 AUD_CONFIG_N_VALUE_INDEX : 0)); 503 504 /* Invalidate ELD */ 505 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 506 AUDIO_ELD_VALID(cpu_transcoder), 0); 507 508 intel_crtc_wait_for_next_vblank(crtc); 509 intel_crtc_wait_for_next_vblank(crtc); 510 511 /* Disable audio presence detect */ 512 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 513 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); 514 515 mutex_unlock(&i915->display.audio.mutex); 516 } 517 518 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 519 const struct intel_crtc_state *crtc_state) 520 { 521 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 522 unsigned int link_clks_available, link_clks_required; 523 unsigned int tu_data, tu_line, link_clks_active; 524 unsigned int h_active, h_total, hblank_delta, pixel_clk; 525 unsigned int fec_coeff, cdclk, vdsc_bppx16; 526 unsigned int link_clk, lanes; 527 unsigned int hblank_rise; 528 529 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 530 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 531 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 532 vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16; 533 cdclk = i915->display.cdclk.hw.cdclk; 534 /* fec= 0.972261, using rounding multiplier of 1000000 */ 535 fec_coeff = 972261; 536 link_clk = crtc_state->port_clock; 537 lanes = crtc_state->lane_count; 538 539 drm_dbg_kms(&i915->drm, 540 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " BPP_X16_FMT " cdclk = %u\n", 541 h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16), cdclk); 542 543 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) 544 return 0; 545 546 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 547 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 548 549 if (link_clks_available > link_clks_required) 550 hblank_delta = 32; 551 else 552 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 553 mul_u32_u32(link_clk, cdclk)); 554 555 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), 556 mul_u32_u32(link_clk * lanes * 16, fec_coeff)); 557 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 558 mul_u32_u32(64 * pixel_clk, 1000000)); 559 link_clks_active = (tu_line - 1) * 64 + tu_data; 560 561 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 562 563 return h_active - hblank_rise + hblank_delta; 564 } 565 566 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 567 { 568 unsigned int h_active, h_total, pixel_clk; 569 unsigned int link_clk, lanes; 570 571 h_active = crtc_state->hw.adjusted_mode.hdisplay; 572 h_total = crtc_state->hw.adjusted_mode.htotal; 573 pixel_clk = crtc_state->hw.adjusted_mode.clock; 574 link_clk = crtc_state->port_clock; 575 lanes = crtc_state->lane_count; 576 577 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 578 (pixel_clk * (48 / lanes + 2)); 579 } 580 581 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 582 const struct intel_crtc_state *crtc_state) 583 { 584 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 585 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 586 unsigned int hblank_early_prog, samples_room; 587 unsigned int val; 588 589 if (DISPLAY_VER(i915) < 11) 590 return; 591 592 val = intel_de_read(i915, AUD_CONFIG_BE); 593 594 if (DISPLAY_VER(i915) == 11) 595 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder); 596 else if (DISPLAY_VER(i915) >= 12) 597 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder); 598 599 if (crtc_state->dsc.compression_enable && 600 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 601 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 602 /* Get hblank early enable value required */ 603 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder); 604 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 605 if (hblank_early_prog < 32) 606 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32); 607 else if (hblank_early_prog < 64) 608 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64); 609 else if (hblank_early_prog < 96) 610 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96); 611 else 612 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128); 613 614 /* Get samples room value required */ 615 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder); 616 samples_room = calc_samples_room(crtc_state); 617 if (samples_room < 3) 618 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room); 619 else /* Program 0 i.e "All Samples available in buffer" */ 620 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0); 621 } 622 623 intel_de_write(i915, AUD_CONFIG_BE, val); 624 } 625 626 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 627 const struct intel_crtc_state *crtc_state, 628 const struct drm_connector_state *conn_state) 629 { 630 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 631 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 632 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 633 634 mutex_lock(&i915->display.audio.mutex); 635 636 /* Enable Audio WA for 4k DSC usecases */ 637 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 638 enable_audio_dsc_wa(encoder, crtc_state); 639 640 /* Enable audio presence detect */ 641 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 642 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); 643 644 intel_crtc_wait_for_next_vblank(crtc); 645 646 /* Invalidate ELD */ 647 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 648 AUDIO_ELD_VALID(cpu_transcoder), 0); 649 650 /* 651 * The audio componenent is used to convey the ELD 652 * instead using of the hardware ELD buffer. 653 */ 654 655 /* Enable timestamps */ 656 hsw_audio_config_update(encoder, crtc_state); 657 658 mutex_unlock(&i915->display.audio.mutex); 659 } 660 661 struct ibx_audio_regs { 662 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 663 }; 664 665 static void ibx_audio_regs_init(struct drm_i915_private *i915, 666 enum pipe pipe, 667 struct ibx_audio_regs *regs) 668 { 669 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 670 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 671 regs->aud_config = VLV_AUD_CFG(pipe); 672 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 673 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 674 } else if (HAS_PCH_CPT(i915)) { 675 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 676 regs->aud_config = CPT_AUD_CFG(pipe); 677 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 678 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 679 } else if (HAS_PCH_IBX(i915)) { 680 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 681 regs->aud_config = IBX_AUD_CFG(pipe); 682 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 683 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 684 } 685 } 686 687 static void ibx_audio_codec_disable(struct intel_encoder *encoder, 688 const struct intel_crtc_state *old_crtc_state, 689 const struct drm_connector_state *old_conn_state) 690 { 691 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 692 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 693 enum port port = encoder->port; 694 enum pipe pipe = crtc->pipe; 695 struct ibx_audio_regs regs; 696 697 if (drm_WARN_ON(&i915->drm, port == PORT_A)) 698 return; 699 700 ibx_audio_regs_init(i915, pipe, ®s); 701 702 mutex_lock(&i915->display.audio.mutex); 703 704 /* Disable timestamps */ 705 intel_de_rmw(i915, regs.aud_config, 706 AUD_CONFIG_N_VALUE_INDEX | 707 AUD_CONFIG_UPPER_N_MASK | 708 AUD_CONFIG_LOWER_N_MASK, 709 AUD_CONFIG_N_PROG_ENABLE | 710 (intel_crtc_has_dp_encoder(old_crtc_state) ? 711 AUD_CONFIG_N_VALUE_INDEX : 0)); 712 713 /* Invalidate ELD */ 714 intel_de_rmw(i915, regs.aud_cntrl_st2, 715 IBX_ELD_VALID(port), 0); 716 717 mutex_unlock(&i915->display.audio.mutex); 718 719 intel_crtc_wait_for_next_vblank(crtc); 720 intel_crtc_wait_for_next_vblank(crtc); 721 } 722 723 static void ibx_audio_codec_enable(struct intel_encoder *encoder, 724 const struct intel_crtc_state *crtc_state, 725 const struct drm_connector_state *conn_state) 726 { 727 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 728 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 729 enum port port = encoder->port; 730 enum pipe pipe = crtc->pipe; 731 struct ibx_audio_regs regs; 732 733 if (drm_WARN_ON(&i915->drm, port == PORT_A)) 734 return; 735 736 intel_crtc_wait_for_next_vblank(crtc); 737 738 ibx_audio_regs_init(i915, pipe, ®s); 739 740 mutex_lock(&i915->display.audio.mutex); 741 742 /* Invalidate ELD */ 743 intel_de_rmw(i915, regs.aud_cntrl_st2, 744 IBX_ELD_VALID(port), 0); 745 746 /* 747 * The audio componenent is used to convey the ELD 748 * instead using of the hardware ELD buffer. 749 */ 750 751 /* Enable timestamps */ 752 intel_de_rmw(i915, regs.aud_config, 753 AUD_CONFIG_N_VALUE_INDEX | 754 AUD_CONFIG_N_PROG_ENABLE | 755 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 756 (intel_crtc_has_dp_encoder(crtc_state) ? 757 AUD_CONFIG_N_VALUE_INDEX : 758 audio_config_hdmi_pixel_clock(crtc_state))); 759 760 mutex_unlock(&i915->display.audio.mutex); 761 } 762 763 void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state) 764 { 765 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 766 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 767 enum transcoder trans = crtc_state->cpu_transcoder; 768 769 if (HAS_DP20(i915)) 770 intel_de_rmw(i915, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 771 crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); 772 } 773 774 bool intel_audio_compute_config(struct intel_encoder *encoder, 775 struct intel_crtc_state *crtc_state, 776 struct drm_connector_state *conn_state) 777 { 778 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 779 struct drm_connector *connector = conn_state->connector; 780 const struct drm_display_mode *adjusted_mode = 781 &crtc_state->hw.adjusted_mode; 782 783 if (!connector->eld[0]) { 784 drm_dbg_kms(&i915->drm, 785 "Bogus ELD on [CONNECTOR:%d:%s]\n", 786 connector->base.id, connector->name); 787 return false; 788 } 789 790 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld)); 791 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); 792 793 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 794 795 return true; 796 } 797 798 /** 799 * intel_audio_codec_enable - Enable the audio codec for HD audio 800 * @encoder: encoder on which to enable audio 801 * @crtc_state: pointer to the current crtc state. 802 * @conn_state: pointer to the current connector state. 803 * 804 * The enable sequences may only be performed after enabling the transcoder and 805 * port, and after completed link training. 806 */ 807 void intel_audio_codec_enable(struct intel_encoder *encoder, 808 const struct intel_crtc_state *crtc_state, 809 const struct drm_connector_state *conn_state) 810 { 811 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 812 struct i915_audio_component *acomp = i915->display.audio.component; 813 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 814 struct intel_connector *connector = to_intel_connector(conn_state->connector); 815 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 816 struct intel_audio_state *audio_state; 817 enum port port = encoder->port; 818 819 if (!crtc_state->has_audio) 820 return; 821 822 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", 823 connector->base.base.id, connector->base.name, 824 encoder->base.base.id, encoder->base.name, 825 crtc->base.base.id, crtc->base.name, 826 drm_eld_size(crtc_state->eld)); 827 828 if (i915->display.funcs.audio) 829 i915->display.funcs.audio->audio_codec_enable(encoder, 830 crtc_state, 831 conn_state); 832 833 mutex_lock(&i915->display.audio.mutex); 834 835 audio_state = &i915->display.audio.state[cpu_transcoder]; 836 837 audio_state->encoder = encoder; 838 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld)); 839 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld)); 840 841 mutex_unlock(&i915->display.audio.mutex); 842 843 if (acomp && acomp->base.audio_ops && 844 acomp->base.audio_ops->pin_eld_notify) { 845 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 846 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 847 cpu_transcoder = -1; 848 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 849 (int)port, (int)cpu_transcoder); 850 } 851 852 intel_lpe_audio_notify(i915, cpu_transcoder, port, crtc_state->eld, 853 crtc_state->port_clock, 854 intel_crtc_has_dp_encoder(crtc_state)); 855 } 856 857 /** 858 * intel_audio_codec_disable - Disable the audio codec for HD audio 859 * @encoder: encoder on which to disable audio 860 * @old_crtc_state: pointer to the old crtc state. 861 * @old_conn_state: pointer to the old connector state. 862 * 863 * The disable sequences must be performed before disabling the transcoder or 864 * port. 865 */ 866 void intel_audio_codec_disable(struct intel_encoder *encoder, 867 const struct intel_crtc_state *old_crtc_state, 868 const struct drm_connector_state *old_conn_state) 869 { 870 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 871 struct i915_audio_component *acomp = i915->display.audio.component; 872 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 873 struct intel_connector *connector = to_intel_connector(old_conn_state->connector); 874 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 875 struct intel_audio_state *audio_state; 876 enum port port = encoder->port; 877 878 if (!old_crtc_state->has_audio) 879 return; 880 881 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", 882 connector->base.base.id, connector->base.name, 883 encoder->base.base.id, encoder->base.name, 884 crtc->base.base.id, crtc->base.name); 885 886 if (i915->display.funcs.audio) 887 i915->display.funcs.audio->audio_codec_disable(encoder, 888 old_crtc_state, 889 old_conn_state); 890 891 mutex_lock(&i915->display.audio.mutex); 892 893 audio_state = &i915->display.audio.state[cpu_transcoder]; 894 895 audio_state->encoder = NULL; 896 memset(audio_state->eld, 0, sizeof(audio_state->eld)); 897 898 mutex_unlock(&i915->display.audio.mutex); 899 900 if (acomp && acomp->base.audio_ops && 901 acomp->base.audio_ops->pin_eld_notify) { 902 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 903 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 904 cpu_transcoder = -1; 905 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 906 (int)port, (int)cpu_transcoder); 907 } 908 909 intel_lpe_audio_notify(i915, cpu_transcoder, port, NULL, 0, false); 910 } 911 912 static void intel_acomp_get_config(struct intel_encoder *encoder, 913 struct intel_crtc_state *crtc_state) 914 { 915 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 916 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 917 struct intel_audio_state *audio_state; 918 919 mutex_lock(&i915->display.audio.mutex); 920 921 audio_state = &i915->display.audio.state[cpu_transcoder]; 922 923 if (audio_state->encoder) 924 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld)); 925 926 mutex_unlock(&i915->display.audio.mutex); 927 } 928 929 void intel_audio_codec_get_config(struct intel_encoder *encoder, 930 struct intel_crtc_state *crtc_state) 931 { 932 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 933 934 if (!crtc_state->has_audio) 935 return; 936 937 if (i915->display.funcs.audio) 938 i915->display.funcs.audio->audio_codec_get_config(encoder, crtc_state); 939 } 940 941 static const struct intel_audio_funcs g4x_audio_funcs = { 942 .audio_codec_enable = g4x_audio_codec_enable, 943 .audio_codec_disable = g4x_audio_codec_disable, 944 .audio_codec_get_config = g4x_audio_codec_get_config, 945 }; 946 947 static const struct intel_audio_funcs ibx_audio_funcs = { 948 .audio_codec_enable = ibx_audio_codec_enable, 949 .audio_codec_disable = ibx_audio_codec_disable, 950 .audio_codec_get_config = intel_acomp_get_config, 951 }; 952 953 static const struct intel_audio_funcs hsw_audio_funcs = { 954 .audio_codec_enable = hsw_audio_codec_enable, 955 .audio_codec_disable = hsw_audio_codec_disable, 956 .audio_codec_get_config = intel_acomp_get_config, 957 }; 958 959 /** 960 * intel_audio_hooks_init - Set up chip specific audio hooks 961 * @i915: device private 962 */ 963 void intel_audio_hooks_init(struct drm_i915_private *i915) 964 { 965 if (IS_G4X(i915)) 966 i915->display.funcs.audio = &g4x_audio_funcs; 967 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915) || 968 HAS_PCH_CPT(i915) || HAS_PCH_IBX(i915)) 969 i915->display.funcs.audio = &ibx_audio_funcs; 970 else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8) 971 i915->display.funcs.audio = &hsw_audio_funcs; 972 } 973 974 struct aud_ts_cdclk_m_n { 975 u8 m; 976 u16 n; 977 }; 978 979 void intel_audio_cdclk_change_pre(struct drm_i915_private *i915) 980 { 981 if (DISPLAY_VER(i915) >= 13) 982 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 983 } 984 985 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 986 { 987 aud_ts->m = 60; 988 aud_ts->n = cdclk * aud_ts->m / 24000; 989 } 990 991 void intel_audio_cdclk_change_post(struct drm_i915_private *i915) 992 { 993 struct aud_ts_cdclk_m_n aud_ts; 994 995 if (DISPLAY_VER(i915) >= 13) { 996 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); 997 998 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n); 999 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 1000 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n); 1001 } 1002 } 1003 1004 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 1005 struct intel_crtc *crtc, 1006 bool enable) 1007 { 1008 struct intel_cdclk_state *cdclk_state; 1009 int ret; 1010 1011 /* need to hold at least one crtc lock for the global state */ 1012 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 1013 if (ret) 1014 return ret; 1015 1016 cdclk_state = intel_atomic_get_cdclk_state(state); 1017 if (IS_ERR(cdclk_state)) 1018 return PTR_ERR(cdclk_state); 1019 1020 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; 1021 1022 return drm_atomic_commit(&state->base); 1023 } 1024 1025 static void glk_force_audio_cdclk(struct drm_i915_private *i915, 1026 bool enable) 1027 { 1028 struct drm_modeset_acquire_ctx ctx; 1029 struct drm_atomic_state *state; 1030 struct intel_crtc *crtc; 1031 int ret; 1032 1033 crtc = intel_first_crtc(i915); 1034 if (!crtc) 1035 return; 1036 1037 drm_modeset_acquire_init(&ctx, 0); 1038 state = drm_atomic_state_alloc(&i915->drm); 1039 if (drm_WARN_ON(&i915->drm, !state)) 1040 return; 1041 1042 state->acquire_ctx = &ctx; 1043 to_intel_atomic_state(state)->internal = true; 1044 1045 retry: 1046 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 1047 enable); 1048 if (ret == -EDEADLK) { 1049 drm_atomic_state_clear(state); 1050 drm_modeset_backoff(&ctx); 1051 goto retry; 1052 } 1053 1054 drm_WARN_ON(&i915->drm, ret); 1055 1056 drm_atomic_state_put(state); 1057 1058 drm_modeset_drop_locks(&ctx); 1059 drm_modeset_acquire_fini(&ctx); 1060 } 1061 1062 static unsigned long i915_audio_component_get_power(struct device *kdev) 1063 { 1064 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1065 intel_wakeref_t ret; 1066 1067 /* Catch potential impedance mismatches before they occur! */ 1068 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 1069 1070 ret = intel_display_power_get(i915, POWER_DOMAIN_AUDIO_PLAYBACK); 1071 1072 if (i915->display.audio.power_refcount++ == 0) { 1073 if (DISPLAY_VER(i915) >= 9) { 1074 intel_de_write(i915, AUD_FREQ_CNTRL, 1075 i915->display.audio.freq_cntrl); 1076 drm_dbg_kms(&i915->drm, 1077 "restored AUD_FREQ_CNTRL to 0x%x\n", 1078 i915->display.audio.freq_cntrl); 1079 } 1080 1081 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1082 if (IS_GEMINILAKE(i915)) 1083 glk_force_audio_cdclk(i915, true); 1084 1085 if (DISPLAY_VER(i915) >= 10) 1086 intel_de_rmw(i915, AUD_PIN_BUF_CTL, 1087 0, AUD_PIN_BUF_ENABLE); 1088 } 1089 1090 return ret; 1091 } 1092 1093 static void i915_audio_component_put_power(struct device *kdev, 1094 unsigned long cookie) 1095 { 1096 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1097 1098 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1099 if (--i915->display.audio.power_refcount == 0) 1100 if (IS_GEMINILAKE(i915)) 1101 glk_force_audio_cdclk(i915, false); 1102 1103 intel_display_power_put(i915, POWER_DOMAIN_AUDIO_PLAYBACK, cookie); 1104 } 1105 1106 static void i915_audio_component_codec_wake_override(struct device *kdev, 1107 bool enable) 1108 { 1109 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1110 unsigned long cookie; 1111 1112 if (DISPLAY_VER(i915) < 9) 1113 return; 1114 1115 cookie = i915_audio_component_get_power(kdev); 1116 1117 /* 1118 * Enable/disable generating the codec wake signal, overriding the 1119 * internal logic to generate the codec wake to controller. 1120 */ 1121 intel_de_rmw(i915, HSW_AUD_CHICKENBIT, 1122 SKL_AUD_CODEC_WAKE_SIGNAL, 0); 1123 usleep_range(1000, 1500); 1124 1125 if (enable) { 1126 intel_de_rmw(i915, HSW_AUD_CHICKENBIT, 1127 0, SKL_AUD_CODEC_WAKE_SIGNAL); 1128 usleep_range(1000, 1500); 1129 } 1130 1131 i915_audio_component_put_power(kdev, cookie); 1132 } 1133 1134 /* Get CDCLK in kHz */ 1135 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 1136 { 1137 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1138 1139 if (drm_WARN_ON_ONCE(&i915->drm, !HAS_DDI(i915))) 1140 return -ENODEV; 1141 1142 return i915->display.cdclk.hw.cdclk; 1143 } 1144 1145 /* 1146 * get the intel audio state according to the parameter port and cpu_transcoder 1147 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder], 1148 * when port is matched 1149 * MST & (cpu_transcoder < 0): this is invalid 1150 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry) 1151 * will get the right intel_encoder with port matched 1152 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched 1153 */ 1154 static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915, 1155 int port, int cpu_transcoder) 1156 { 1157 /* MST */ 1158 if (cpu_transcoder >= 0) { 1159 struct intel_audio_state *audio_state; 1160 struct intel_encoder *encoder; 1161 1162 if (drm_WARN_ON(&i915->drm, 1163 cpu_transcoder >= ARRAY_SIZE(i915->display.audio.state))) 1164 return NULL; 1165 1166 audio_state = &i915->display.audio.state[cpu_transcoder]; 1167 encoder = audio_state->encoder; 1168 1169 if (encoder && encoder->port == port && 1170 encoder->type == INTEL_OUTPUT_DP_MST) 1171 return audio_state; 1172 } 1173 1174 /* Non-MST */ 1175 if (cpu_transcoder > 0) 1176 return NULL; 1177 1178 for_each_cpu_transcoder(i915, cpu_transcoder) { 1179 struct intel_audio_state *audio_state; 1180 struct intel_encoder *encoder; 1181 1182 audio_state = &i915->display.audio.state[cpu_transcoder]; 1183 encoder = audio_state->encoder; 1184 1185 if (encoder && encoder->port == port && 1186 encoder->type != INTEL_OUTPUT_DP_MST) 1187 return audio_state; 1188 } 1189 1190 return NULL; 1191 } 1192 1193 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 1194 int cpu_transcoder, int rate) 1195 { 1196 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1197 struct i915_audio_component *acomp = i915->display.audio.component; 1198 const struct intel_audio_state *audio_state; 1199 struct intel_encoder *encoder; 1200 struct intel_crtc *crtc; 1201 unsigned long cookie; 1202 int err = 0; 1203 1204 if (!HAS_DDI(i915)) 1205 return 0; 1206 1207 cookie = i915_audio_component_get_power(kdev); 1208 mutex_lock(&i915->display.audio.mutex); 1209 1210 audio_state = find_audio_state(i915, port, cpu_transcoder); 1211 if (!audio_state) { 1212 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port)); 1213 err = -ENODEV; 1214 goto unlock; 1215 } 1216 1217 encoder = audio_state->encoder; 1218 1219 /* FIXME stop using the legacy crtc pointer */ 1220 crtc = to_intel_crtc(encoder->base.crtc); 1221 1222 /* port must be valid now, otherwise the cpu_transcoder will be invalid */ 1223 acomp->aud_sample_rate[port] = rate; 1224 1225 /* FIXME get rid of the crtc->config stuff */ 1226 hsw_audio_config_update(encoder, crtc->config); 1227 1228 unlock: 1229 mutex_unlock(&i915->display.audio.mutex); 1230 i915_audio_component_put_power(kdev, cookie); 1231 return err; 1232 } 1233 1234 static int i915_audio_component_get_eld(struct device *kdev, int port, 1235 int cpu_transcoder, bool *enabled, 1236 unsigned char *buf, int max_bytes) 1237 { 1238 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1239 const struct intel_audio_state *audio_state; 1240 int ret = 0; 1241 1242 mutex_lock(&i915->display.audio.mutex); 1243 1244 audio_state = find_audio_state(i915, port, cpu_transcoder); 1245 if (!audio_state) { 1246 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port)); 1247 mutex_unlock(&i915->display.audio.mutex); 1248 return -EINVAL; 1249 } 1250 1251 *enabled = audio_state->encoder != NULL; 1252 if (*enabled) { 1253 const u8 *eld = audio_state->eld; 1254 1255 ret = drm_eld_size(eld); 1256 memcpy(buf, eld, min(max_bytes, ret)); 1257 } 1258 1259 mutex_unlock(&i915->display.audio.mutex); 1260 return ret; 1261 } 1262 1263 static const struct drm_audio_component_ops i915_audio_component_ops = { 1264 .owner = THIS_MODULE, 1265 .get_power = i915_audio_component_get_power, 1266 .put_power = i915_audio_component_put_power, 1267 .codec_wake_override = i915_audio_component_codec_wake_override, 1268 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1269 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1270 .get_eld = i915_audio_component_get_eld, 1271 }; 1272 1273 static int i915_audio_component_bind(struct device *i915_kdev, 1274 struct device *hda_kdev, void *data) 1275 { 1276 struct i915_audio_component *acomp = data; 1277 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 1278 int i; 1279 1280 if (drm_WARN_ON(&i915->drm, acomp->base.ops || acomp->base.dev)) 1281 return -EEXIST; 1282 1283 if (drm_WARN_ON(&i915->drm, 1284 !device_link_add(hda_kdev, i915_kdev, 1285 DL_FLAG_STATELESS))) 1286 return -ENOMEM; 1287 1288 drm_modeset_lock_all(&i915->drm); 1289 acomp->base.ops = &i915_audio_component_ops; 1290 acomp->base.dev = i915_kdev; 1291 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1292 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1293 acomp->aud_sample_rate[i] = 0; 1294 i915->display.audio.component = acomp; 1295 drm_modeset_unlock_all(&i915->drm); 1296 1297 return 0; 1298 } 1299 1300 static void i915_audio_component_unbind(struct device *i915_kdev, 1301 struct device *hda_kdev, void *data) 1302 { 1303 struct i915_audio_component *acomp = data; 1304 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 1305 1306 drm_modeset_lock_all(&i915->drm); 1307 acomp->base.ops = NULL; 1308 acomp->base.dev = NULL; 1309 i915->display.audio.component = NULL; 1310 drm_modeset_unlock_all(&i915->drm); 1311 1312 device_link_remove(hda_kdev, i915_kdev); 1313 1314 if (i915->display.audio.power_refcount) 1315 drm_err(&i915->drm, "audio power refcount %d after unbind\n", 1316 i915->display.audio.power_refcount); 1317 } 1318 1319 static const struct component_ops i915_audio_component_bind_ops = { 1320 .bind = i915_audio_component_bind, 1321 .unbind = i915_audio_component_unbind, 1322 }; 1323 1324 #define AUD_FREQ_TMODE_SHIFT 14 1325 #define AUD_FREQ_4T 0 1326 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1327 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1328 #define AUD_FREQ_BCLK_96M BIT(4) 1329 1330 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1331 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1332 1333 /** 1334 * i915_audio_component_init - initialize and register the audio component 1335 * @i915: i915 device instance 1336 * 1337 * This will register with the component framework a child component which 1338 * will bind dynamically to the snd_hda_intel driver's corresponding master 1339 * component when the latter is registered. During binding the child 1340 * initializes an instance of struct i915_audio_component which it receives 1341 * from the master. The master can then start to use the interface defined by 1342 * this struct. Each side can break the binding at any point by deregistering 1343 * its own component after which each side's component unbind callback is 1344 * called. 1345 * 1346 * We ignore any error during registration and continue with reduced 1347 * functionality (i.e. without HDMI audio). 1348 */ 1349 static void i915_audio_component_init(struct drm_i915_private *i915) 1350 { 1351 u32 aud_freq, aud_freq_init; 1352 int ret; 1353 1354 ret = component_add_typed(i915->drm.dev, 1355 &i915_audio_component_bind_ops, 1356 I915_COMPONENT_AUDIO); 1357 if (ret < 0) { 1358 drm_err(&i915->drm, 1359 "failed to add audio component (%d)\n", ret); 1360 /* continue with reduced functionality */ 1361 return; 1362 } 1363 1364 if (DISPLAY_VER(i915) >= 9) { 1365 aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL); 1366 1367 if (DISPLAY_VER(i915) >= 12) 1368 aud_freq = AUD_FREQ_GEN12; 1369 else 1370 aud_freq = aud_freq_init; 1371 1372 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1373 if ((IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) && 1374 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1375 aud_freq = aud_freq_init; 1376 1377 drm_dbg_kms(&i915->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1378 aud_freq, aud_freq_init); 1379 1380 i915->display.audio.freq_cntrl = aud_freq; 1381 } 1382 1383 /* init with current cdclk */ 1384 intel_audio_cdclk_change_post(i915); 1385 1386 i915->display.audio.component_registered = true; 1387 } 1388 1389 /** 1390 * i915_audio_component_cleanup - deregister the audio component 1391 * @i915: i915 device instance 1392 * 1393 * Deregisters the audio component, breaking any existing binding to the 1394 * corresponding snd_hda_intel driver's master component. 1395 */ 1396 static void i915_audio_component_cleanup(struct drm_i915_private *i915) 1397 { 1398 if (!i915->display.audio.component_registered) 1399 return; 1400 1401 component_del(i915->drm.dev, &i915_audio_component_bind_ops); 1402 i915->display.audio.component_registered = false; 1403 } 1404 1405 /** 1406 * intel_audio_init() - Initialize the audio driver either using 1407 * component framework or using lpe audio bridge 1408 * @i915: the i915 drm device private data 1409 * 1410 */ 1411 void intel_audio_init(struct drm_i915_private *i915) 1412 { 1413 if (intel_lpe_audio_init(i915) < 0) 1414 i915_audio_component_init(i915); 1415 } 1416 1417 /** 1418 * intel_audio_deinit() - deinitialize the audio driver 1419 * @i915: the i915 drm device private data 1420 * 1421 */ 1422 void intel_audio_deinit(struct drm_i915_private *i915) 1423 { 1424 if (i915->display.audio.lpe.platdev != NULL) 1425 intel_lpe_audio_teardown(i915); 1426 else 1427 i915_audio_component_cleanup(i915); 1428 } 1429