1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/drm_eld.h> 29 #include <drm/intel/i915_component.h> 30 31 #include "i915_drv.h" 32 #include "intel_atomic.h" 33 #include "intel_audio.h" 34 #include "intel_audio_regs.h" 35 #include "intel_cdclk.h" 36 #include "intel_crtc.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_lpe_audio.h" 40 41 /** 42 * DOC: High Definition Audio over HDMI and Display Port 43 * 44 * The graphics and audio drivers together support High Definition Audio over 45 * HDMI and Display Port. The audio programming sequences are divided into audio 46 * codec and controller enable and disable sequences. The graphics driver 47 * handles the audio codec sequences, while the audio driver handles the audio 48 * controller sequences. 49 * 50 * The disable sequences must be performed before disabling the transcoder or 51 * port. The enable sequences may only be performed after enabling the 52 * transcoder and port, and after completed link training. Therefore the audio 53 * enable/disable sequences are part of the modeset sequence. 54 * 55 * The codec and controller sequences could be done either parallel or serial, 56 * but generally the ELDV/PD change in the codec sequence indicates to the audio 57 * driver that the controller sequence should start. Indeed, most of the 58 * co-operation between the graphics and audio drivers is handled via audio 59 * related registers. (The notable exception is the power management, not 60 * covered here.) 61 * 62 * The struct &i915_audio_component is used to interact between the graphics 63 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 64 * defined in graphics driver and called in audio driver. The 65 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 66 */ 67 68 struct intel_audio_funcs { 69 void (*audio_codec_enable)(struct intel_encoder *encoder, 70 const struct intel_crtc_state *crtc_state, 71 const struct drm_connector_state *conn_state); 72 void (*audio_codec_disable)(struct intel_encoder *encoder, 73 const struct intel_crtc_state *old_crtc_state, 74 const struct drm_connector_state *old_conn_state); 75 void (*audio_codec_get_config)(struct intel_encoder *encoder, 76 struct intel_crtc_state *crtc_state); 77 }; 78 79 struct hdmi_aud_ncts { 80 int sample_rate; 81 int clock; 82 int n; 83 int cts; 84 }; 85 86 static const struct { 87 int clock; 88 u32 config; 89 } hdmi_audio_clock[] = { 90 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 91 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 92 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 93 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 94 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 95 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 96 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 97 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 98 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 99 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 100 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 101 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 102 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 103 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 104 }; 105 106 /* HDMI N/CTS table */ 107 #define TMDS_297M 297000 108 #define TMDS_296M 296703 109 #define TMDS_594M 594000 110 #define TMDS_593M 593407 111 112 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 113 { 32000, TMDS_296M, 5824, 421875 }, 114 { 32000, TMDS_297M, 3072, 222750 }, 115 { 32000, TMDS_593M, 5824, 843750 }, 116 { 32000, TMDS_594M, 3072, 445500 }, 117 { 44100, TMDS_296M, 4459, 234375 }, 118 { 44100, TMDS_297M, 4704, 247500 }, 119 { 44100, TMDS_593M, 8918, 937500 }, 120 { 44100, TMDS_594M, 9408, 990000 }, 121 { 88200, TMDS_296M, 8918, 234375 }, 122 { 88200, TMDS_297M, 9408, 247500 }, 123 { 88200, TMDS_593M, 17836, 937500 }, 124 { 88200, TMDS_594M, 18816, 990000 }, 125 { 176400, TMDS_296M, 17836, 234375 }, 126 { 176400, TMDS_297M, 18816, 247500 }, 127 { 176400, TMDS_593M, 35672, 937500 }, 128 { 176400, TMDS_594M, 37632, 990000 }, 129 { 48000, TMDS_296M, 5824, 281250 }, 130 { 48000, TMDS_297M, 5120, 247500 }, 131 { 48000, TMDS_593M, 5824, 562500 }, 132 { 48000, TMDS_594M, 6144, 594000 }, 133 { 96000, TMDS_296M, 11648, 281250 }, 134 { 96000, TMDS_297M, 10240, 247500 }, 135 { 96000, TMDS_593M, 11648, 562500 }, 136 { 96000, TMDS_594M, 12288, 594000 }, 137 { 192000, TMDS_296M, 23296, 281250 }, 138 { 192000, TMDS_297M, 20480, 247500 }, 139 { 192000, TMDS_593M, 23296, 562500 }, 140 { 192000, TMDS_594M, 24576, 594000 }, 141 }; 142 143 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 144 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 145 #define TMDS_371M 371250 146 #define TMDS_370M 370878 147 148 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 149 { 32000, TMDS_370M, 5824, 527344 }, 150 { 32000, TMDS_371M, 6144, 556875 }, 151 { 44100, TMDS_370M, 8918, 585938 }, 152 { 44100, TMDS_371M, 4704, 309375 }, 153 { 88200, TMDS_370M, 17836, 585938 }, 154 { 88200, TMDS_371M, 9408, 309375 }, 155 { 176400, TMDS_370M, 35672, 585938 }, 156 { 176400, TMDS_371M, 18816, 309375 }, 157 { 48000, TMDS_370M, 11648, 703125 }, 158 { 48000, TMDS_371M, 5120, 309375 }, 159 { 96000, TMDS_370M, 23296, 703125 }, 160 { 96000, TMDS_371M, 10240, 309375 }, 161 { 192000, TMDS_370M, 46592, 703125 }, 162 { 192000, TMDS_371M, 20480, 309375 }, 163 }; 164 165 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 166 #define TMDS_445_5M 445500 167 #define TMDS_445M 445054 168 169 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 170 { 32000, TMDS_445M, 5824, 632813 }, 171 { 32000, TMDS_445_5M, 4096, 445500 }, 172 { 44100, TMDS_445M, 8918, 703125 }, 173 { 44100, TMDS_445_5M, 4704, 371250 }, 174 { 88200, TMDS_445M, 17836, 703125 }, 175 { 88200, TMDS_445_5M, 9408, 371250 }, 176 { 176400, TMDS_445M, 35672, 703125 }, 177 { 176400, TMDS_445_5M, 18816, 371250 }, 178 { 48000, TMDS_445M, 5824, 421875 }, 179 { 48000, TMDS_445_5M, 5120, 371250 }, 180 { 96000, TMDS_445M, 11648, 421875 }, 181 { 96000, TMDS_445_5M, 10240, 371250 }, 182 { 192000, TMDS_445M, 23296, 421875 }, 183 { 192000, TMDS_445_5M, 20480, 371250 }, 184 }; 185 186 /* 187 * WA_14020863754: Implement Audio Workaround 188 * Corner case with Min Hblank Fix can cause audio hang 189 */ 190 static bool needs_wa_14020863754(struct drm_i915_private *i915) 191 { 192 return (DISPLAY_VER(i915) == 20 || IS_BATTLEMAGE(i915)); 193 } 194 195 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 196 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 197 { 198 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 199 const struct drm_display_mode *adjusted_mode = 200 &crtc_state->hw.adjusted_mode; 201 int i; 202 203 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 204 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 205 break; 206 } 207 208 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500) 209 i = ARRAY_SIZE(hdmi_audio_clock); 210 211 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 212 drm_dbg_kms(&i915->drm, 213 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 214 adjusted_mode->crtc_clock); 215 i = 1; 216 } 217 218 drm_dbg_kms(&i915->drm, 219 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 220 hdmi_audio_clock[i].clock, 221 hdmi_audio_clock[i].config); 222 223 return hdmi_audio_clock[i].config; 224 } 225 226 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 227 int rate) 228 { 229 const struct hdmi_aud_ncts *hdmi_ncts_table; 230 int i, size; 231 232 if (crtc_state->pipe_bpp == 36) { 233 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 234 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 235 } else if (crtc_state->pipe_bpp == 30) { 236 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 237 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 238 } else { 239 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 240 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 241 } 242 243 for (i = 0; i < size; i++) { 244 if (rate == hdmi_ncts_table[i].sample_rate && 245 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 246 return hdmi_ncts_table[i].n; 247 } 248 } 249 return 0; 250 } 251 252 /* ELD buffer size in dwords */ 253 static int g4x_eld_buffer_size(struct drm_i915_private *i915) 254 { 255 u32 tmp; 256 257 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); 258 259 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); 260 } 261 262 static void g4x_audio_codec_get_config(struct intel_encoder *encoder, 263 struct intel_crtc_state *crtc_state) 264 { 265 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 266 u32 *eld = (u32 *)crtc_state->eld; 267 int eld_buffer_size, len, i; 268 u32 tmp; 269 270 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); 271 if ((tmp & G4X_ELD_VALID) == 0) 272 return; 273 274 intel_de_rmw(i915, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); 275 276 eld_buffer_size = g4x_eld_buffer_size(i915); 277 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size); 278 279 for (i = 0; i < len; i++) 280 eld[i] = intel_de_read(i915, G4X_HDMIW_HDMIEDID); 281 } 282 283 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 284 const struct intel_crtc_state *old_crtc_state, 285 const struct drm_connector_state *old_conn_state) 286 { 287 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 288 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 289 290 /* Invalidate ELD */ 291 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 292 G4X_ELD_VALID, 0); 293 294 intel_crtc_wait_for_next_vblank(crtc); 295 intel_crtc_wait_for_next_vblank(crtc); 296 } 297 298 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 299 const struct intel_crtc_state *crtc_state, 300 const struct drm_connector_state *conn_state) 301 { 302 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 303 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 304 const u32 *eld = (const u32 *)crtc_state->eld; 305 int eld_buffer_size, len, i; 306 307 intel_crtc_wait_for_next_vblank(crtc); 308 309 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 310 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); 311 312 eld_buffer_size = g4x_eld_buffer_size(i915); 313 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size); 314 315 for (i = 0; i < len; i++) 316 intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]); 317 for (; i < eld_buffer_size; i++) 318 intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0); 319 320 drm_WARN_ON(&i915->drm, 321 (intel_de_read(i915, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); 322 323 intel_de_rmw(i915, G4X_AUD_CNTL_ST, 324 0, G4X_ELD_VALID); 325 } 326 327 static void 328 hsw_dp_audio_config_update(struct intel_encoder *encoder, 329 const struct intel_crtc_state *crtc_state) 330 { 331 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 332 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 333 334 /* Enable time stamps. Let HW calculate Maud/Naud values */ 335 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), 336 AUD_CONFIG_N_VALUE_INDEX | 337 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK | 338 AUD_CONFIG_UPPER_N_MASK | 339 AUD_CONFIG_LOWER_N_MASK | 340 AUD_CONFIG_N_PROG_ENABLE, 341 AUD_CONFIG_N_VALUE_INDEX); 342 343 } 344 345 static void 346 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 347 const struct intel_crtc_state *crtc_state) 348 { 349 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 350 struct i915_audio_component *acomp = i915->display.audio.component; 351 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 352 enum port port = encoder->port; 353 int n, rate; 354 u32 tmp; 355 356 rate = acomp ? acomp->aud_sample_rate[port] : 0; 357 358 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder)); 359 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 360 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 361 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 362 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 363 364 n = audio_config_hdmi_get_n(crtc_state, rate); 365 if (n != 0) { 366 drm_dbg_kms(&i915->drm, "using N %d\n", n); 367 368 tmp &= ~AUD_CONFIG_N_MASK; 369 tmp |= AUD_CONFIG_N(n); 370 tmp |= AUD_CONFIG_N_PROG_ENABLE; 371 } else { 372 drm_dbg_kms(&i915->drm, "using automatic N\n"); 373 } 374 375 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp); 376 377 /* 378 * Let's disable "Enable CTS or M Prog bit" 379 * and let HW calculate the value 380 */ 381 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 382 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 383 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 384 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 385 } 386 387 static void 388 hsw_audio_config_update(struct intel_encoder *encoder, 389 const struct intel_crtc_state *crtc_state) 390 { 391 if (intel_crtc_has_dp_encoder(crtc_state)) 392 hsw_dp_audio_config_update(encoder, crtc_state); 393 else 394 hsw_hdmi_audio_config_update(encoder, crtc_state); 395 } 396 397 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 398 const struct intel_crtc_state *old_crtc_state, 399 const struct drm_connector_state *old_conn_state) 400 { 401 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 402 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 403 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 404 405 mutex_lock(&i915->display.audio.mutex); 406 407 /* Disable timestamps */ 408 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), 409 AUD_CONFIG_N_VALUE_INDEX | 410 AUD_CONFIG_UPPER_N_MASK | 411 AUD_CONFIG_LOWER_N_MASK, 412 AUD_CONFIG_N_PROG_ENABLE | 413 (intel_crtc_has_dp_encoder(old_crtc_state) ? 414 AUD_CONFIG_N_VALUE_INDEX : 0)); 415 416 /* Invalidate ELD */ 417 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 418 AUDIO_ELD_VALID(cpu_transcoder), 0); 419 420 intel_crtc_wait_for_next_vblank(crtc); 421 intel_crtc_wait_for_next_vblank(crtc); 422 423 /* Disable audio presence detect */ 424 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 425 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); 426 427 if (needs_wa_14020863754(i915)) 428 intel_de_rmw(i915, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); 429 430 mutex_unlock(&i915->display.audio.mutex); 431 } 432 433 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 434 const struct intel_crtc_state *crtc_state) 435 { 436 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 437 unsigned int link_clks_available, link_clks_required; 438 unsigned int tu_data, tu_line, link_clks_active; 439 unsigned int h_active, h_total, hblank_delta, pixel_clk; 440 unsigned int fec_coeff, cdclk, vdsc_bppx16; 441 unsigned int link_clk, lanes; 442 unsigned int hblank_rise; 443 444 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 445 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 446 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 447 vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16; 448 cdclk = i915->display.cdclk.hw.cdclk; 449 /* fec= 0.972261, using rounding multiplier of 1000000 */ 450 fec_coeff = 972261; 451 link_clk = crtc_state->port_clock; 452 lanes = crtc_state->lane_count; 453 454 drm_dbg_kms(&i915->drm, 455 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " BPP_X16_FMT " cdclk = %u\n", 456 h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16), cdclk); 457 458 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) 459 return 0; 460 461 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 462 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 463 464 if (link_clks_available > link_clks_required) 465 hblank_delta = 32; 466 else 467 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 468 mul_u32_u32(link_clk, cdclk)); 469 470 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), 471 mul_u32_u32(link_clk * lanes * 16, fec_coeff)); 472 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 473 mul_u32_u32(64 * pixel_clk, 1000000)); 474 link_clks_active = (tu_line - 1) * 64 + tu_data; 475 476 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 477 478 return h_active - hblank_rise + hblank_delta; 479 } 480 481 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 482 { 483 unsigned int h_active, h_total, pixel_clk; 484 unsigned int link_clk, lanes; 485 486 h_active = crtc_state->hw.adjusted_mode.hdisplay; 487 h_total = crtc_state->hw.adjusted_mode.htotal; 488 pixel_clk = crtc_state->hw.adjusted_mode.clock; 489 link_clk = crtc_state->port_clock; 490 lanes = crtc_state->lane_count; 491 492 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 493 (pixel_clk * (48 / lanes + 2)); 494 } 495 496 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 497 const struct intel_crtc_state *crtc_state) 498 { 499 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 500 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 501 unsigned int hblank_early_prog, samples_room; 502 unsigned int val; 503 504 if (DISPLAY_VER(i915) < 11) 505 return; 506 507 val = intel_de_read(i915, AUD_CONFIG_BE); 508 509 if (DISPLAY_VER(i915) == 11) 510 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder); 511 else if (DISPLAY_VER(i915) >= 12) 512 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder); 513 514 if (crtc_state->dsc.compression_enable && 515 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 516 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 517 /* Get hblank early enable value required */ 518 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder); 519 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 520 if (hblank_early_prog < 32) 521 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32); 522 else if (hblank_early_prog < 64) 523 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64); 524 else if (hblank_early_prog < 96) 525 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96); 526 else 527 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128); 528 529 /* Get samples room value required */ 530 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder); 531 samples_room = calc_samples_room(crtc_state); 532 if (samples_room < 3) 533 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room); 534 else /* Program 0 i.e "All Samples available in buffer" */ 535 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0); 536 } 537 538 intel_de_write(i915, AUD_CONFIG_BE, val); 539 } 540 541 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 542 const struct intel_crtc_state *crtc_state, 543 const struct drm_connector_state *conn_state) 544 { 545 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 546 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 547 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 548 549 mutex_lock(&i915->display.audio.mutex); 550 551 /* Enable Audio WA for 4k DSC usecases */ 552 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 553 enable_audio_dsc_wa(encoder, crtc_state); 554 555 if (needs_wa_14020863754(i915)) 556 intel_de_rmw(i915, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); 557 558 /* Enable audio presence detect */ 559 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 560 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); 561 562 intel_crtc_wait_for_next_vblank(crtc); 563 564 /* Invalidate ELD */ 565 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 566 AUDIO_ELD_VALID(cpu_transcoder), 0); 567 568 /* 569 * The audio componenent is used to convey the ELD 570 * instead using of the hardware ELD buffer. 571 */ 572 573 /* Enable timestamps */ 574 hsw_audio_config_update(encoder, crtc_state); 575 576 mutex_unlock(&i915->display.audio.mutex); 577 } 578 579 struct ibx_audio_regs { 580 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 581 }; 582 583 static void ibx_audio_regs_init(struct drm_i915_private *i915, 584 enum pipe pipe, 585 struct ibx_audio_regs *regs) 586 { 587 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 588 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 589 regs->aud_config = VLV_AUD_CFG(pipe); 590 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 591 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 592 } else if (HAS_PCH_CPT(i915)) { 593 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 594 regs->aud_config = CPT_AUD_CFG(pipe); 595 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 596 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 597 } else if (HAS_PCH_IBX(i915)) { 598 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 599 regs->aud_config = IBX_AUD_CFG(pipe); 600 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 601 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 602 } 603 } 604 605 static void ibx_audio_codec_disable(struct intel_encoder *encoder, 606 const struct intel_crtc_state *old_crtc_state, 607 const struct drm_connector_state *old_conn_state) 608 { 609 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 610 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 611 enum port port = encoder->port; 612 enum pipe pipe = crtc->pipe; 613 struct ibx_audio_regs regs; 614 615 if (drm_WARN_ON(&i915->drm, port == PORT_A)) 616 return; 617 618 ibx_audio_regs_init(i915, pipe, ®s); 619 620 mutex_lock(&i915->display.audio.mutex); 621 622 /* Disable timestamps */ 623 intel_de_rmw(i915, regs.aud_config, 624 AUD_CONFIG_N_VALUE_INDEX | 625 AUD_CONFIG_UPPER_N_MASK | 626 AUD_CONFIG_LOWER_N_MASK, 627 AUD_CONFIG_N_PROG_ENABLE | 628 (intel_crtc_has_dp_encoder(old_crtc_state) ? 629 AUD_CONFIG_N_VALUE_INDEX : 0)); 630 631 /* Invalidate ELD */ 632 intel_de_rmw(i915, regs.aud_cntrl_st2, 633 IBX_ELD_VALID(port), 0); 634 635 mutex_unlock(&i915->display.audio.mutex); 636 637 intel_crtc_wait_for_next_vblank(crtc); 638 intel_crtc_wait_for_next_vblank(crtc); 639 } 640 641 static void ibx_audio_codec_enable(struct intel_encoder *encoder, 642 const struct intel_crtc_state *crtc_state, 643 const struct drm_connector_state *conn_state) 644 { 645 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 646 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 647 enum port port = encoder->port; 648 enum pipe pipe = crtc->pipe; 649 struct ibx_audio_regs regs; 650 651 if (drm_WARN_ON(&i915->drm, port == PORT_A)) 652 return; 653 654 intel_crtc_wait_for_next_vblank(crtc); 655 656 ibx_audio_regs_init(i915, pipe, ®s); 657 658 mutex_lock(&i915->display.audio.mutex); 659 660 /* Invalidate ELD */ 661 intel_de_rmw(i915, regs.aud_cntrl_st2, 662 IBX_ELD_VALID(port), 0); 663 664 /* 665 * The audio componenent is used to convey the ELD 666 * instead using of the hardware ELD buffer. 667 */ 668 669 /* Enable timestamps */ 670 intel_de_rmw(i915, regs.aud_config, 671 AUD_CONFIG_N_VALUE_INDEX | 672 AUD_CONFIG_N_PROG_ENABLE | 673 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 674 (intel_crtc_has_dp_encoder(crtc_state) ? 675 AUD_CONFIG_N_VALUE_INDEX : 676 audio_config_hdmi_pixel_clock(crtc_state))); 677 678 mutex_unlock(&i915->display.audio.mutex); 679 } 680 681 void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state) 682 { 683 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 684 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 685 enum transcoder trans = crtc_state->cpu_transcoder; 686 687 if (HAS_DP20(i915)) 688 intel_de_rmw(i915, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 689 crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); 690 } 691 692 bool intel_audio_compute_config(struct intel_encoder *encoder, 693 struct intel_crtc_state *crtc_state, 694 struct drm_connector_state *conn_state) 695 { 696 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 697 struct drm_connector *connector = conn_state->connector; 698 const struct drm_display_mode *adjusted_mode = 699 &crtc_state->hw.adjusted_mode; 700 701 if (!connector->eld[0]) { 702 drm_dbg_kms(&i915->drm, 703 "Bogus ELD on [CONNECTOR:%d:%s]\n", 704 connector->base.id, connector->name); 705 return false; 706 } 707 708 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld)); 709 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); 710 711 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 712 713 return true; 714 } 715 716 /** 717 * intel_audio_codec_enable - Enable the audio codec for HD audio 718 * @encoder: encoder on which to enable audio 719 * @crtc_state: pointer to the current crtc state. 720 * @conn_state: pointer to the current connector state. 721 * 722 * The enable sequences may only be performed after enabling the transcoder and 723 * port, and after completed link training. 724 */ 725 void intel_audio_codec_enable(struct intel_encoder *encoder, 726 const struct intel_crtc_state *crtc_state, 727 const struct drm_connector_state *conn_state) 728 { 729 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 730 struct i915_audio_component *acomp = i915->display.audio.component; 731 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 732 struct intel_connector *connector = to_intel_connector(conn_state->connector); 733 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 734 struct intel_audio_state *audio_state; 735 enum port port = encoder->port; 736 737 if (!crtc_state->has_audio) 738 return; 739 740 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", 741 connector->base.base.id, connector->base.name, 742 encoder->base.base.id, encoder->base.name, 743 crtc->base.base.id, crtc->base.name, 744 drm_eld_size(crtc_state->eld)); 745 746 if (i915->display.funcs.audio) 747 i915->display.funcs.audio->audio_codec_enable(encoder, 748 crtc_state, 749 conn_state); 750 751 mutex_lock(&i915->display.audio.mutex); 752 753 audio_state = &i915->display.audio.state[cpu_transcoder]; 754 755 audio_state->encoder = encoder; 756 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld)); 757 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld)); 758 759 mutex_unlock(&i915->display.audio.mutex); 760 761 if (acomp && acomp->base.audio_ops && 762 acomp->base.audio_ops->pin_eld_notify) { 763 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 764 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 765 cpu_transcoder = -1; 766 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 767 (int)port, (int)cpu_transcoder); 768 } 769 770 intel_lpe_audio_notify(i915, cpu_transcoder, port, crtc_state->eld, 771 crtc_state->port_clock, 772 intel_crtc_has_dp_encoder(crtc_state)); 773 } 774 775 /** 776 * intel_audio_codec_disable - Disable the audio codec for HD audio 777 * @encoder: encoder on which to disable audio 778 * @old_crtc_state: pointer to the old crtc state. 779 * @old_conn_state: pointer to the old connector state. 780 * 781 * The disable sequences must be performed before disabling the transcoder or 782 * port. 783 */ 784 void intel_audio_codec_disable(struct intel_encoder *encoder, 785 const struct intel_crtc_state *old_crtc_state, 786 const struct drm_connector_state *old_conn_state) 787 { 788 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 789 struct i915_audio_component *acomp = i915->display.audio.component; 790 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 791 struct intel_connector *connector = to_intel_connector(old_conn_state->connector); 792 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 793 struct intel_audio_state *audio_state; 794 enum port port = encoder->port; 795 796 if (!old_crtc_state->has_audio) 797 return; 798 799 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", 800 connector->base.base.id, connector->base.name, 801 encoder->base.base.id, encoder->base.name, 802 crtc->base.base.id, crtc->base.name); 803 804 if (i915->display.funcs.audio) 805 i915->display.funcs.audio->audio_codec_disable(encoder, 806 old_crtc_state, 807 old_conn_state); 808 809 mutex_lock(&i915->display.audio.mutex); 810 811 audio_state = &i915->display.audio.state[cpu_transcoder]; 812 813 audio_state->encoder = NULL; 814 memset(audio_state->eld, 0, sizeof(audio_state->eld)); 815 816 mutex_unlock(&i915->display.audio.mutex); 817 818 if (acomp && acomp->base.audio_ops && 819 acomp->base.audio_ops->pin_eld_notify) { 820 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 821 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 822 cpu_transcoder = -1; 823 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 824 (int)port, (int)cpu_transcoder); 825 } 826 827 intel_lpe_audio_notify(i915, cpu_transcoder, port, NULL, 0, false); 828 } 829 830 static void intel_acomp_get_config(struct intel_encoder *encoder, 831 struct intel_crtc_state *crtc_state) 832 { 833 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 834 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 835 struct intel_audio_state *audio_state; 836 837 mutex_lock(&i915->display.audio.mutex); 838 839 audio_state = &i915->display.audio.state[cpu_transcoder]; 840 841 if (audio_state->encoder) 842 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld)); 843 844 mutex_unlock(&i915->display.audio.mutex); 845 } 846 847 void intel_audio_codec_get_config(struct intel_encoder *encoder, 848 struct intel_crtc_state *crtc_state) 849 { 850 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 851 852 if (!crtc_state->has_audio) 853 return; 854 855 if (i915->display.funcs.audio) 856 i915->display.funcs.audio->audio_codec_get_config(encoder, crtc_state); 857 } 858 859 static const struct intel_audio_funcs g4x_audio_funcs = { 860 .audio_codec_enable = g4x_audio_codec_enable, 861 .audio_codec_disable = g4x_audio_codec_disable, 862 .audio_codec_get_config = g4x_audio_codec_get_config, 863 }; 864 865 static const struct intel_audio_funcs ibx_audio_funcs = { 866 .audio_codec_enable = ibx_audio_codec_enable, 867 .audio_codec_disable = ibx_audio_codec_disable, 868 .audio_codec_get_config = intel_acomp_get_config, 869 }; 870 871 static const struct intel_audio_funcs hsw_audio_funcs = { 872 .audio_codec_enable = hsw_audio_codec_enable, 873 .audio_codec_disable = hsw_audio_codec_disable, 874 .audio_codec_get_config = intel_acomp_get_config, 875 }; 876 877 /** 878 * intel_audio_hooks_init - Set up chip specific audio hooks 879 * @i915: device private 880 */ 881 void intel_audio_hooks_init(struct drm_i915_private *i915) 882 { 883 if (IS_G4X(i915)) 884 i915->display.funcs.audio = &g4x_audio_funcs; 885 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915) || 886 HAS_PCH_CPT(i915) || HAS_PCH_IBX(i915)) 887 i915->display.funcs.audio = &ibx_audio_funcs; 888 else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8) 889 i915->display.funcs.audio = &hsw_audio_funcs; 890 } 891 892 struct aud_ts_cdclk_m_n { 893 u8 m; 894 u16 n; 895 }; 896 897 void intel_audio_cdclk_change_pre(struct drm_i915_private *i915) 898 { 899 if (DISPLAY_VER(i915) >= 13) 900 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 901 } 902 903 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 904 { 905 aud_ts->m = 60; 906 aud_ts->n = cdclk * aud_ts->m / 24000; 907 } 908 909 void intel_audio_cdclk_change_post(struct drm_i915_private *i915) 910 { 911 struct aud_ts_cdclk_m_n aud_ts; 912 913 if (DISPLAY_VER(i915) >= 13) { 914 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); 915 916 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n); 917 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 918 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n); 919 } 920 } 921 922 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 923 struct intel_crtc *crtc, 924 bool enable) 925 { 926 struct intel_cdclk_state *cdclk_state; 927 int ret; 928 929 /* need to hold at least one crtc lock for the global state */ 930 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 931 if (ret) 932 return ret; 933 934 cdclk_state = intel_atomic_get_cdclk_state(state); 935 if (IS_ERR(cdclk_state)) 936 return PTR_ERR(cdclk_state); 937 938 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; 939 940 return drm_atomic_commit(&state->base); 941 } 942 943 static void glk_force_audio_cdclk(struct drm_i915_private *i915, 944 bool enable) 945 { 946 struct drm_modeset_acquire_ctx ctx; 947 struct drm_atomic_state *state; 948 struct intel_crtc *crtc; 949 int ret; 950 951 crtc = intel_first_crtc(i915); 952 if (!crtc) 953 return; 954 955 drm_modeset_acquire_init(&ctx, 0); 956 state = drm_atomic_state_alloc(&i915->drm); 957 if (drm_WARN_ON(&i915->drm, !state)) 958 return; 959 960 state->acquire_ctx = &ctx; 961 to_intel_atomic_state(state)->internal = true; 962 963 retry: 964 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 965 enable); 966 if (ret == -EDEADLK) { 967 drm_atomic_state_clear(state); 968 drm_modeset_backoff(&ctx); 969 goto retry; 970 } 971 972 drm_WARN_ON(&i915->drm, ret); 973 974 drm_atomic_state_put(state); 975 976 drm_modeset_drop_locks(&ctx); 977 drm_modeset_acquire_fini(&ctx); 978 } 979 980 static unsigned long i915_audio_component_get_power(struct device *kdev) 981 { 982 struct drm_i915_private *i915 = kdev_to_i915(kdev); 983 intel_wakeref_t ret; 984 985 /* Catch potential impedance mismatches before they occur! */ 986 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 987 988 ret = intel_display_power_get(i915, POWER_DOMAIN_AUDIO_PLAYBACK); 989 990 if (i915->display.audio.power_refcount++ == 0) { 991 if (DISPLAY_VER(i915) >= 9) { 992 intel_de_write(i915, AUD_FREQ_CNTRL, 993 i915->display.audio.freq_cntrl); 994 drm_dbg_kms(&i915->drm, 995 "restored AUD_FREQ_CNTRL to 0x%x\n", 996 i915->display.audio.freq_cntrl); 997 } 998 999 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1000 if (IS_GEMINILAKE(i915)) 1001 glk_force_audio_cdclk(i915, true); 1002 1003 if (DISPLAY_VER(i915) >= 10) 1004 intel_de_rmw(i915, AUD_PIN_BUF_CTL, 1005 0, AUD_PIN_BUF_ENABLE); 1006 } 1007 1008 return ret; 1009 } 1010 1011 static void i915_audio_component_put_power(struct device *kdev, 1012 unsigned long cookie) 1013 { 1014 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1015 1016 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1017 if (--i915->display.audio.power_refcount == 0) 1018 if (IS_GEMINILAKE(i915)) 1019 glk_force_audio_cdclk(i915, false); 1020 1021 intel_display_power_put(i915, POWER_DOMAIN_AUDIO_PLAYBACK, cookie); 1022 } 1023 1024 static void i915_audio_component_codec_wake_override(struct device *kdev, 1025 bool enable) 1026 { 1027 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1028 unsigned long cookie; 1029 1030 if (DISPLAY_VER(i915) < 9) 1031 return; 1032 1033 cookie = i915_audio_component_get_power(kdev); 1034 1035 /* 1036 * Enable/disable generating the codec wake signal, overriding the 1037 * internal logic to generate the codec wake to controller. 1038 */ 1039 intel_de_rmw(i915, HSW_AUD_CHICKENBIT, 1040 SKL_AUD_CODEC_WAKE_SIGNAL, 0); 1041 usleep_range(1000, 1500); 1042 1043 if (enable) { 1044 intel_de_rmw(i915, HSW_AUD_CHICKENBIT, 1045 0, SKL_AUD_CODEC_WAKE_SIGNAL); 1046 usleep_range(1000, 1500); 1047 } 1048 1049 i915_audio_component_put_power(kdev, cookie); 1050 } 1051 1052 /* Get CDCLK in kHz */ 1053 static int i915_audio_component_get_cdclk_freq(struct device *kdev) 1054 { 1055 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1056 1057 if (drm_WARN_ON_ONCE(&i915->drm, !HAS_DDI(i915))) 1058 return -ENODEV; 1059 1060 return i915->display.cdclk.hw.cdclk; 1061 } 1062 1063 /* 1064 * get the intel audio state according to the parameter port and cpu_transcoder 1065 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder], 1066 * when port is matched 1067 * MST & (cpu_transcoder < 0): this is invalid 1068 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry) 1069 * will get the right intel_encoder with port matched 1070 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched 1071 */ 1072 static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915, 1073 int port, int cpu_transcoder) 1074 { 1075 /* MST */ 1076 if (cpu_transcoder >= 0) { 1077 struct intel_audio_state *audio_state; 1078 struct intel_encoder *encoder; 1079 1080 if (drm_WARN_ON(&i915->drm, 1081 cpu_transcoder >= ARRAY_SIZE(i915->display.audio.state))) 1082 return NULL; 1083 1084 audio_state = &i915->display.audio.state[cpu_transcoder]; 1085 encoder = audio_state->encoder; 1086 1087 if (encoder && encoder->port == port && 1088 encoder->type == INTEL_OUTPUT_DP_MST) 1089 return audio_state; 1090 } 1091 1092 /* Non-MST */ 1093 if (cpu_transcoder > 0) 1094 return NULL; 1095 1096 for_each_cpu_transcoder(i915, cpu_transcoder) { 1097 struct intel_audio_state *audio_state; 1098 struct intel_encoder *encoder; 1099 1100 audio_state = &i915->display.audio.state[cpu_transcoder]; 1101 encoder = audio_state->encoder; 1102 1103 if (encoder && encoder->port == port && 1104 encoder->type != INTEL_OUTPUT_DP_MST) 1105 return audio_state; 1106 } 1107 1108 return NULL; 1109 } 1110 1111 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, 1112 int cpu_transcoder, int rate) 1113 { 1114 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1115 struct i915_audio_component *acomp = i915->display.audio.component; 1116 const struct intel_audio_state *audio_state; 1117 struct intel_encoder *encoder; 1118 struct intel_crtc *crtc; 1119 unsigned long cookie; 1120 int err = 0; 1121 1122 if (!HAS_DDI(i915)) 1123 return 0; 1124 1125 cookie = i915_audio_component_get_power(kdev); 1126 mutex_lock(&i915->display.audio.mutex); 1127 1128 audio_state = find_audio_state(i915, port, cpu_transcoder); 1129 if (!audio_state) { 1130 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port)); 1131 err = -ENODEV; 1132 goto unlock; 1133 } 1134 1135 encoder = audio_state->encoder; 1136 1137 /* FIXME stop using the legacy crtc pointer */ 1138 crtc = to_intel_crtc(encoder->base.crtc); 1139 1140 /* port must be valid now, otherwise the cpu_transcoder will be invalid */ 1141 acomp->aud_sample_rate[port] = rate; 1142 1143 /* FIXME get rid of the crtc->config stuff */ 1144 hsw_audio_config_update(encoder, crtc->config); 1145 1146 unlock: 1147 mutex_unlock(&i915->display.audio.mutex); 1148 i915_audio_component_put_power(kdev, cookie); 1149 return err; 1150 } 1151 1152 static int i915_audio_component_get_eld(struct device *kdev, int port, 1153 int cpu_transcoder, bool *enabled, 1154 unsigned char *buf, int max_bytes) 1155 { 1156 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1157 const struct intel_audio_state *audio_state; 1158 int ret = 0; 1159 1160 mutex_lock(&i915->display.audio.mutex); 1161 1162 audio_state = find_audio_state(i915, port, cpu_transcoder); 1163 if (!audio_state) { 1164 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port)); 1165 mutex_unlock(&i915->display.audio.mutex); 1166 return -EINVAL; 1167 } 1168 1169 *enabled = audio_state->encoder != NULL; 1170 if (*enabled) { 1171 const u8 *eld = audio_state->eld; 1172 1173 ret = drm_eld_size(eld); 1174 memcpy(buf, eld, min(max_bytes, ret)); 1175 } 1176 1177 mutex_unlock(&i915->display.audio.mutex); 1178 return ret; 1179 } 1180 1181 static const struct drm_audio_component_ops i915_audio_component_ops = { 1182 .owner = THIS_MODULE, 1183 .get_power = i915_audio_component_get_power, 1184 .put_power = i915_audio_component_put_power, 1185 .codec_wake_override = i915_audio_component_codec_wake_override, 1186 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 1187 .sync_audio_rate = i915_audio_component_sync_audio_rate, 1188 .get_eld = i915_audio_component_get_eld, 1189 }; 1190 1191 static int i915_audio_component_bind(struct device *i915_kdev, 1192 struct device *hda_kdev, void *data) 1193 { 1194 struct i915_audio_component *acomp = data; 1195 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 1196 int i; 1197 1198 if (drm_WARN_ON(&i915->drm, acomp->base.ops || acomp->base.dev)) 1199 return -EEXIST; 1200 1201 if (drm_WARN_ON(&i915->drm, 1202 !device_link_add(hda_kdev, i915_kdev, 1203 DL_FLAG_STATELESS))) 1204 return -ENOMEM; 1205 1206 drm_modeset_lock_all(&i915->drm); 1207 acomp->base.ops = &i915_audio_component_ops; 1208 acomp->base.dev = i915_kdev; 1209 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1210 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1211 acomp->aud_sample_rate[i] = 0; 1212 i915->display.audio.component = acomp; 1213 drm_modeset_unlock_all(&i915->drm); 1214 1215 return 0; 1216 } 1217 1218 static void i915_audio_component_unbind(struct device *i915_kdev, 1219 struct device *hda_kdev, void *data) 1220 { 1221 struct i915_audio_component *acomp = data; 1222 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); 1223 1224 drm_modeset_lock_all(&i915->drm); 1225 acomp->base.ops = NULL; 1226 acomp->base.dev = NULL; 1227 i915->display.audio.component = NULL; 1228 drm_modeset_unlock_all(&i915->drm); 1229 1230 device_link_remove(hda_kdev, i915_kdev); 1231 1232 if (i915->display.audio.power_refcount) 1233 drm_err(&i915->drm, "audio power refcount %d after unbind\n", 1234 i915->display.audio.power_refcount); 1235 } 1236 1237 static const struct component_ops i915_audio_component_bind_ops = { 1238 .bind = i915_audio_component_bind, 1239 .unbind = i915_audio_component_unbind, 1240 }; 1241 1242 #define AUD_FREQ_TMODE_SHIFT 14 1243 #define AUD_FREQ_4T 0 1244 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1245 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1246 #define AUD_FREQ_BCLK_96M BIT(4) 1247 1248 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1249 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1250 1251 /** 1252 * i915_audio_component_init - initialize and register the audio component 1253 * @i915: i915 device instance 1254 * 1255 * This will register with the component framework a child component which 1256 * will bind dynamically to the snd_hda_intel driver's corresponding master 1257 * component when the latter is registered. During binding the child 1258 * initializes an instance of struct i915_audio_component which it receives 1259 * from the master. The master can then start to use the interface defined by 1260 * this struct. Each side can break the binding at any point by deregistering 1261 * its own component after which each side's component unbind callback is 1262 * called. 1263 * 1264 * We ignore any error during registration and continue with reduced 1265 * functionality (i.e. without HDMI audio). 1266 */ 1267 static void i915_audio_component_init(struct drm_i915_private *i915) 1268 { 1269 u32 aud_freq, aud_freq_init; 1270 1271 if (DISPLAY_VER(i915) >= 9) { 1272 aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL); 1273 1274 if (DISPLAY_VER(i915) >= 12) 1275 aud_freq = AUD_FREQ_GEN12; 1276 else 1277 aud_freq = aud_freq_init; 1278 1279 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1280 if ((IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) && 1281 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1282 aud_freq = aud_freq_init; 1283 1284 drm_dbg_kms(&i915->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1285 aud_freq, aud_freq_init); 1286 1287 i915->display.audio.freq_cntrl = aud_freq; 1288 } 1289 1290 /* init with current cdclk */ 1291 intel_audio_cdclk_change_post(i915); 1292 } 1293 1294 static void i915_audio_component_register(struct drm_i915_private *i915) 1295 { 1296 int ret; 1297 1298 ret = component_add_typed(i915->drm.dev, 1299 &i915_audio_component_bind_ops, 1300 I915_COMPONENT_AUDIO); 1301 if (ret < 0) { 1302 drm_err(&i915->drm, 1303 "failed to add audio component (%d)\n", ret); 1304 /* continue with reduced functionality */ 1305 return; 1306 } 1307 1308 i915->display.audio.component_registered = true; 1309 } 1310 1311 /** 1312 * i915_audio_component_cleanup - deregister the audio component 1313 * @i915: i915 device instance 1314 * 1315 * Deregisters the audio component, breaking any existing binding to the 1316 * corresponding snd_hda_intel driver's master component. 1317 */ 1318 static void i915_audio_component_cleanup(struct drm_i915_private *i915) 1319 { 1320 if (!i915->display.audio.component_registered) 1321 return; 1322 1323 component_del(i915->drm.dev, &i915_audio_component_bind_ops); 1324 i915->display.audio.component_registered = false; 1325 } 1326 1327 /** 1328 * intel_audio_init() - Initialize the audio driver either using 1329 * component framework or using lpe audio bridge 1330 * @i915: the i915 drm device private data 1331 * 1332 */ 1333 void intel_audio_init(struct drm_i915_private *i915) 1334 { 1335 if (intel_lpe_audio_init(i915) < 0) 1336 i915_audio_component_init(i915); 1337 } 1338 1339 void intel_audio_register(struct drm_i915_private *i915) 1340 { 1341 if (!i915->display.audio.lpe.platdev) 1342 i915_audio_component_register(i915); 1343 } 1344 1345 /** 1346 * intel_audio_deinit() - deinitialize the audio driver 1347 * @i915: the i915 drm device private data 1348 * 1349 */ 1350 void intel_audio_deinit(struct drm_i915_private *i915) 1351 { 1352 if (i915->display.audio.lpe.platdev != NULL) 1353 intel_lpe_audio_teardown(i915); 1354 else 1355 i915_audio_component_cleanup(i915); 1356 } 1357