1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/drm_eld.h> 29 #include <drm/drm_fixed.h> 30 #include <drm/drm_print.h> 31 #include <drm/intel/i915_component.h> 32 33 #include "intel_atomic.h" 34 #include "intel_audio.h" 35 #include "intel_audio_regs.h" 36 #include "intel_cdclk.h" 37 #include "intel_crtc.h" 38 #include "intel_de.h" 39 #include "intel_display_types.h" 40 #include "intel_display_wa.h" 41 #include "intel_lpe_audio.h" 42 43 /** 44 * DOC: High Definition Audio over HDMI and Display Port 45 * 46 * The graphics and audio drivers together support High Definition Audio over 47 * HDMI and Display Port. The audio programming sequences are divided into audio 48 * codec and controller enable and disable sequences. The graphics driver 49 * handles the audio codec sequences, while the audio driver handles the audio 50 * controller sequences. 51 * 52 * The disable sequences must be performed before disabling the transcoder or 53 * port. The enable sequences may only be performed after enabling the 54 * transcoder and port, and after completed link training. Therefore the audio 55 * enable/disable sequences are part of the modeset sequence. 56 * 57 * The codec and controller sequences could be done either parallel or serial, 58 * but generally the ELDV/PD change in the codec sequence indicates to the audio 59 * driver that the controller sequence should start. Indeed, most of the 60 * co-operation between the graphics and audio drivers is handled via audio 61 * related registers. (The notable exception is the power management, not 62 * covered here.) 63 * 64 * The struct &i915_audio_component is used to interact between the graphics 65 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 66 * defined in graphics driver and called in audio driver. The 67 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 68 */ 69 70 struct intel_audio_funcs { 71 void (*audio_codec_enable)(struct intel_encoder *encoder, 72 const struct intel_crtc_state *crtc_state, 73 const struct drm_connector_state *conn_state); 74 void (*audio_codec_disable)(struct intel_encoder *encoder, 75 const struct intel_crtc_state *old_crtc_state, 76 const struct drm_connector_state *old_conn_state); 77 void (*audio_codec_get_config)(struct intel_encoder *encoder, 78 struct intel_crtc_state *crtc_state); 79 }; 80 81 struct hdmi_aud_ncts { 82 int sample_rate; 83 int clock; 84 int n; 85 int cts; 86 }; 87 88 static const struct { 89 int clock; 90 u32 config; 91 } hdmi_audio_clock[] = { 92 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 93 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 94 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 95 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 96 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 97 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 98 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 99 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 100 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 101 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 102 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 103 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 104 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 105 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 106 }; 107 108 /* HDMI N/CTS table */ 109 #define TMDS_297M 297000 110 #define TMDS_296M 296703 111 #define TMDS_594M 594000 112 #define TMDS_593M 593407 113 114 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 115 { 32000, TMDS_296M, 5824, 421875 }, 116 { 32000, TMDS_297M, 3072, 222750 }, 117 { 32000, TMDS_593M, 5824, 843750 }, 118 { 32000, TMDS_594M, 3072, 445500 }, 119 { 44100, TMDS_296M, 4459, 234375 }, 120 { 44100, TMDS_297M, 4704, 247500 }, 121 { 44100, TMDS_593M, 8918, 937500 }, 122 { 44100, TMDS_594M, 9408, 990000 }, 123 { 88200, TMDS_296M, 8918, 234375 }, 124 { 88200, TMDS_297M, 9408, 247500 }, 125 { 88200, TMDS_593M, 17836, 937500 }, 126 { 88200, TMDS_594M, 18816, 990000 }, 127 { 176400, TMDS_296M, 17836, 234375 }, 128 { 176400, TMDS_297M, 18816, 247500 }, 129 { 176400, TMDS_593M, 35672, 937500 }, 130 { 176400, TMDS_594M, 37632, 990000 }, 131 { 48000, TMDS_296M, 5824, 281250 }, 132 { 48000, TMDS_297M, 5120, 247500 }, 133 { 48000, TMDS_593M, 5824, 562500 }, 134 { 48000, TMDS_594M, 6144, 594000 }, 135 { 96000, TMDS_296M, 11648, 281250 }, 136 { 96000, TMDS_297M, 10240, 247500 }, 137 { 96000, TMDS_593M, 11648, 562500 }, 138 { 96000, TMDS_594M, 12288, 594000 }, 139 { 192000, TMDS_296M, 23296, 281250 }, 140 { 192000, TMDS_297M, 20480, 247500 }, 141 { 192000, TMDS_593M, 23296, 562500 }, 142 { 192000, TMDS_594M, 24576, 594000 }, 143 }; 144 145 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 146 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 147 #define TMDS_371M 371250 148 #define TMDS_370M 370878 149 150 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 151 { 32000, TMDS_370M, 5824, 527344 }, 152 { 32000, TMDS_371M, 6144, 556875 }, 153 { 44100, TMDS_370M, 8918, 585938 }, 154 { 44100, TMDS_371M, 4704, 309375 }, 155 { 88200, TMDS_370M, 17836, 585938 }, 156 { 88200, TMDS_371M, 9408, 309375 }, 157 { 176400, TMDS_370M, 35672, 585938 }, 158 { 176400, TMDS_371M, 18816, 309375 }, 159 { 48000, TMDS_370M, 11648, 703125 }, 160 { 48000, TMDS_371M, 5120, 309375 }, 161 { 96000, TMDS_370M, 23296, 703125 }, 162 { 96000, TMDS_371M, 10240, 309375 }, 163 { 192000, TMDS_370M, 46592, 703125 }, 164 { 192000, TMDS_371M, 20480, 309375 }, 165 }; 166 167 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 168 #define TMDS_445_5M 445500 169 #define TMDS_445M 445054 170 171 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 172 { 32000, TMDS_445M, 5824, 632813 }, 173 { 32000, TMDS_445_5M, 4096, 445500 }, 174 { 44100, TMDS_445M, 8918, 703125 }, 175 { 44100, TMDS_445_5M, 4704, 371250 }, 176 { 88200, TMDS_445M, 17836, 703125 }, 177 { 88200, TMDS_445_5M, 9408, 371250 }, 178 { 176400, TMDS_445M, 35672, 703125 }, 179 { 176400, TMDS_445_5M, 18816, 371250 }, 180 { 48000, TMDS_445M, 5824, 421875 }, 181 { 48000, TMDS_445_5M, 5120, 371250 }, 182 { 96000, TMDS_445M, 11648, 421875 }, 183 { 96000, TMDS_445_5M, 10240, 371250 }, 184 { 192000, TMDS_445M, 23296, 421875 }, 185 { 192000, TMDS_445_5M, 20480, 371250 }, 186 }; 187 188 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 189 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 190 { 191 struct intel_display *display = to_intel_display(crtc_state); 192 const struct drm_display_mode *adjusted_mode = 193 &crtc_state->hw.adjusted_mode; 194 int i; 195 196 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 197 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 198 break; 199 } 200 201 if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500) 202 i = ARRAY_SIZE(hdmi_audio_clock); 203 204 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 205 drm_dbg_kms(display->drm, 206 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 207 adjusted_mode->crtc_clock); 208 i = 1; 209 } 210 211 drm_dbg_kms(display->drm, 212 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 213 hdmi_audio_clock[i].clock, 214 hdmi_audio_clock[i].config); 215 216 return hdmi_audio_clock[i].config; 217 } 218 219 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 220 int rate) 221 { 222 const struct hdmi_aud_ncts *hdmi_ncts_table; 223 int i, size; 224 225 if (crtc_state->pipe_bpp == 36) { 226 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 227 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 228 } else if (crtc_state->pipe_bpp == 30) { 229 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 230 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 231 } else { 232 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 233 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 234 } 235 236 for (i = 0; i < size; i++) { 237 if (rate == hdmi_ncts_table[i].sample_rate && 238 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 239 return hdmi_ncts_table[i].n; 240 } 241 } 242 return 0; 243 } 244 245 /* ELD buffer size in dwords */ 246 static int g4x_eld_buffer_size(struct intel_display *display) 247 { 248 u32 tmp; 249 250 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); 251 252 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); 253 } 254 255 static void g4x_audio_codec_get_config(struct intel_encoder *encoder, 256 struct intel_crtc_state *crtc_state) 257 { 258 struct intel_display *display = to_intel_display(encoder); 259 u32 *eld = (u32 *)crtc_state->eld; 260 int eld_buffer_size, len, i; 261 u32 tmp; 262 263 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); 264 if ((tmp & G4X_ELD_VALID) == 0) 265 return; 266 267 intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); 268 269 eld_buffer_size = g4x_eld_buffer_size(display); 270 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size); 271 272 for (i = 0; i < len; i++) 273 eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID); 274 } 275 276 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 277 const struct intel_crtc_state *old_crtc_state, 278 const struct drm_connector_state *old_conn_state) 279 { 280 struct intel_display *display = to_intel_display(encoder); 281 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 282 283 /* Invalidate ELD */ 284 intel_de_rmw(display, G4X_AUD_CNTL_ST, 285 G4X_ELD_VALID, 0); 286 287 intel_crtc_wait_for_next_vblank(crtc); 288 intel_crtc_wait_for_next_vblank(crtc); 289 } 290 291 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 292 const struct intel_crtc_state *crtc_state, 293 const struct drm_connector_state *conn_state) 294 { 295 struct intel_display *display = to_intel_display(encoder); 296 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 297 const u32 *eld = (const u32 *)crtc_state->eld; 298 int eld_buffer_size, len, i; 299 300 intel_crtc_wait_for_next_vblank(crtc); 301 302 intel_de_rmw(display, G4X_AUD_CNTL_ST, 303 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); 304 305 eld_buffer_size = g4x_eld_buffer_size(display); 306 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size); 307 308 for (i = 0; i < len; i++) 309 intel_de_write(display, G4X_HDMIW_HDMIEDID, eld[i]); 310 for (; i < eld_buffer_size; i++) 311 intel_de_write(display, G4X_HDMIW_HDMIEDID, 0); 312 313 drm_WARN_ON(display->drm, 314 (intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); 315 316 intel_de_rmw(display, G4X_AUD_CNTL_ST, 317 0, G4X_ELD_VALID); 318 } 319 320 static void 321 hsw_dp_audio_config_update(struct intel_encoder *encoder, 322 const struct intel_crtc_state *crtc_state) 323 { 324 struct intel_display *display = to_intel_display(encoder); 325 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 326 327 /* Enable time stamps. Let HW calculate Maud/Naud values */ 328 intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), 329 AUD_CONFIG_N_VALUE_INDEX | 330 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK | 331 AUD_CONFIG_UPPER_N_MASK | 332 AUD_CONFIG_LOWER_N_MASK | 333 AUD_CONFIG_N_PROG_ENABLE, 334 AUD_CONFIG_N_VALUE_INDEX); 335 336 } 337 338 static void 339 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 340 const struct intel_crtc_state *crtc_state) 341 { 342 struct intel_display *display = to_intel_display(encoder); 343 struct i915_audio_component *acomp = display->audio.component; 344 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 345 enum port port = encoder->port; 346 int n, rate; 347 u32 tmp; 348 349 rate = acomp ? acomp->aud_sample_rate[port] : 0; 350 351 tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder)); 352 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 353 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 354 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 355 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 356 357 n = audio_config_hdmi_get_n(crtc_state, rate); 358 if (n != 0) { 359 drm_dbg_kms(display->drm, "using N %d\n", n); 360 361 tmp &= ~AUD_CONFIG_N_MASK; 362 tmp |= AUD_CONFIG_N(n); 363 tmp |= AUD_CONFIG_N_PROG_ENABLE; 364 } else { 365 drm_dbg_kms(display->drm, "using automatic N\n"); 366 } 367 368 intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp); 369 370 /* 371 * Let's disable "Enable CTS or M Prog bit" 372 * and let HW calculate the value 373 */ 374 tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 375 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 376 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 377 intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 378 } 379 380 static void 381 hsw_audio_config_update(struct intel_encoder *encoder, 382 const struct intel_crtc_state *crtc_state) 383 { 384 if (intel_crtc_has_dp_encoder(crtc_state)) 385 hsw_dp_audio_config_update(encoder, crtc_state); 386 else 387 hsw_hdmi_audio_config_update(encoder, crtc_state); 388 } 389 390 static void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state, 391 bool enable) 392 { 393 struct intel_display *display = to_intel_display(crtc_state); 394 enum transcoder trans = crtc_state->cpu_transcoder; 395 396 if (!HAS_DP20(display)) 397 return; 398 399 intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 400 enable && crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); 401 } 402 403 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 404 const struct intel_crtc_state *old_crtc_state, 405 const struct drm_connector_state *old_conn_state) 406 { 407 struct intel_display *display = to_intel_display(encoder); 408 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 409 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 410 411 mutex_lock(&display->audio.mutex); 412 413 /* Disable timestamps */ 414 intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), 415 AUD_CONFIG_N_VALUE_INDEX | 416 AUD_CONFIG_UPPER_N_MASK | 417 AUD_CONFIG_LOWER_N_MASK, 418 AUD_CONFIG_N_PROG_ENABLE | 419 (intel_crtc_has_dp_encoder(old_crtc_state) ? 420 AUD_CONFIG_N_VALUE_INDEX : 0)); 421 422 /* Invalidate ELD */ 423 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 424 AUDIO_ELD_VALID(cpu_transcoder), 0); 425 426 intel_crtc_wait_for_next_vblank(crtc); 427 intel_crtc_wait_for_next_vblank(crtc); 428 429 /* Disable audio presence detect */ 430 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 431 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); 432 433 /* 434 * WA_14020863754: Implement Audio Workaround 435 * Corner case with Min Hblank Fix can cause audio hang 436 */ 437 if (intel_display_wa(display, INTEL_DISPLAY_WA_14020863754)) 438 intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); 439 440 intel_audio_sdp_split_update(old_crtc_state, false); 441 442 mutex_unlock(&display->audio.mutex); 443 } 444 445 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 446 const struct intel_crtc_state *crtc_state) 447 { 448 struct intel_display *display = to_intel_display(encoder); 449 unsigned int link_clks_available, link_clks_required; 450 unsigned int tu_data, tu_line, link_clks_active; 451 unsigned int h_active, h_total, hblank_delta, pixel_clk; 452 unsigned int fec_coeff, cdclk, vdsc_bppx16; 453 unsigned int link_clk, lanes; 454 unsigned int hblank_rise; 455 456 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 457 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 458 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 459 vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16; 460 cdclk = display->cdclk.hw.cdclk; 461 /* fec= 0.972261, using rounding multiplier of 1000000 */ 462 fec_coeff = 972261; 463 link_clk = crtc_state->port_clock; 464 lanes = crtc_state->lane_count; 465 466 drm_dbg_kms(display->drm, 467 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n", 468 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); 469 470 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) 471 return 0; 472 473 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 474 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 475 476 if (link_clks_available > link_clks_required) 477 hblank_delta = 32; 478 else 479 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 480 mul_u32_u32(link_clk, cdclk)); 481 482 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), 483 mul_u32_u32(link_clk * lanes * 16, fec_coeff)); 484 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 485 mul_u32_u32(64 * pixel_clk, 1000000)); 486 link_clks_active = (tu_line - 1) * 64 + tu_data; 487 488 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 489 490 return h_active - hblank_rise + hblank_delta; 491 } 492 493 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 494 { 495 unsigned int h_active, h_total, pixel_clk; 496 unsigned int link_clk, lanes; 497 498 h_active = crtc_state->hw.adjusted_mode.hdisplay; 499 h_total = crtc_state->hw.adjusted_mode.htotal; 500 pixel_clk = crtc_state->hw.adjusted_mode.clock; 501 link_clk = crtc_state->port_clock; 502 lanes = crtc_state->lane_count; 503 504 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 505 (pixel_clk * (48 / lanes + 2)); 506 } 507 508 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 509 const struct intel_crtc_state *crtc_state) 510 { 511 struct intel_display *display = to_intel_display(encoder); 512 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 513 unsigned int hblank_early_prog, samples_room; 514 unsigned int val; 515 516 if (DISPLAY_VER(display) < 11) 517 return; 518 519 val = intel_de_read(display, AUD_CONFIG_BE); 520 521 if (DISPLAY_VER(display) == 11) 522 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder); 523 else if (DISPLAY_VER(display) >= 12) 524 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder); 525 526 if (crtc_state->dsc.compression_enable && 527 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 528 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 529 /* Get hblank early enable value required */ 530 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder); 531 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 532 if (hblank_early_prog < 32) 533 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32); 534 else if (hblank_early_prog < 64) 535 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64); 536 else if (hblank_early_prog < 96) 537 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96); 538 else 539 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128); 540 541 /* Get samples room value required */ 542 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder); 543 samples_room = calc_samples_room(crtc_state); 544 if (samples_room < 3) 545 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room); 546 else /* Program 0 i.e "All Samples available in buffer" */ 547 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0); 548 } 549 550 intel_de_write(display, AUD_CONFIG_BE, val); 551 } 552 553 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 554 const struct intel_crtc_state *crtc_state, 555 const struct drm_connector_state *conn_state) 556 { 557 struct intel_display *display = to_intel_display(encoder); 558 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 559 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 560 561 mutex_lock(&display->audio.mutex); 562 563 /* Enable Audio WA for 4k DSC usecases */ 564 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 565 enable_audio_dsc_wa(encoder, crtc_state); 566 567 intel_audio_sdp_split_update(crtc_state, true); 568 569 /* 570 * WA_14020863754: Implement Audio Workaround 571 * Corner case with Min Hblank Fix can cause audio hang 572 */ 573 if (intel_display_wa(display, INTEL_DISPLAY_WA_14020863754)) 574 intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); 575 576 /* Enable audio presence detect */ 577 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 578 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); 579 580 intel_crtc_wait_for_next_vblank(crtc); 581 582 /* Invalidate ELD */ 583 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 584 AUDIO_ELD_VALID(cpu_transcoder), 0); 585 586 /* 587 * The audio component is used to convey the ELD 588 * instead using of the hardware ELD buffer. 589 */ 590 591 /* Enable timestamps */ 592 hsw_audio_config_update(encoder, crtc_state); 593 594 mutex_unlock(&display->audio.mutex); 595 } 596 597 struct ibx_audio_regs { 598 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 599 }; 600 601 static void ibx_audio_regs_init(struct intel_display *display, 602 enum pipe pipe, 603 struct ibx_audio_regs *regs) 604 { 605 if (display->platform.valleyview || display->platform.cherryview) { 606 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 607 regs->aud_config = VLV_AUD_CFG(pipe); 608 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 609 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 610 } else if (HAS_PCH_CPT(display)) { 611 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 612 regs->aud_config = CPT_AUD_CFG(pipe); 613 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 614 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 615 } else if (HAS_PCH_IBX(display)) { 616 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 617 regs->aud_config = IBX_AUD_CFG(pipe); 618 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 619 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 620 } 621 } 622 623 static void ibx_audio_codec_disable(struct intel_encoder *encoder, 624 const struct intel_crtc_state *old_crtc_state, 625 const struct drm_connector_state *old_conn_state) 626 { 627 struct intel_display *display = to_intel_display(encoder); 628 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 629 enum port port = encoder->port; 630 enum pipe pipe = crtc->pipe; 631 struct ibx_audio_regs regs; 632 633 if (drm_WARN_ON(display->drm, port == PORT_A)) 634 return; 635 636 ibx_audio_regs_init(display, pipe, ®s); 637 638 mutex_lock(&display->audio.mutex); 639 640 /* Disable timestamps */ 641 intel_de_rmw(display, regs.aud_config, 642 AUD_CONFIG_N_VALUE_INDEX | 643 AUD_CONFIG_UPPER_N_MASK | 644 AUD_CONFIG_LOWER_N_MASK, 645 AUD_CONFIG_N_PROG_ENABLE | 646 (intel_crtc_has_dp_encoder(old_crtc_state) ? 647 AUD_CONFIG_N_VALUE_INDEX : 0)); 648 649 /* Invalidate ELD */ 650 intel_de_rmw(display, regs.aud_cntrl_st2, 651 IBX_ELD_VALID(port), 0); 652 653 mutex_unlock(&display->audio.mutex); 654 655 intel_crtc_wait_for_next_vblank(crtc); 656 intel_crtc_wait_for_next_vblank(crtc); 657 } 658 659 static void ibx_audio_codec_enable(struct intel_encoder *encoder, 660 const struct intel_crtc_state *crtc_state, 661 const struct drm_connector_state *conn_state) 662 { 663 struct intel_display *display = to_intel_display(encoder); 664 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 665 enum port port = encoder->port; 666 enum pipe pipe = crtc->pipe; 667 struct ibx_audio_regs regs; 668 669 if (drm_WARN_ON(display->drm, port == PORT_A)) 670 return; 671 672 intel_crtc_wait_for_next_vblank(crtc); 673 674 ibx_audio_regs_init(display, pipe, ®s); 675 676 mutex_lock(&display->audio.mutex); 677 678 /* Invalidate ELD */ 679 intel_de_rmw(display, regs.aud_cntrl_st2, 680 IBX_ELD_VALID(port), 0); 681 682 /* 683 * The audio component is used to convey the ELD 684 * instead using of the hardware ELD buffer. 685 */ 686 687 /* Enable timestamps */ 688 intel_de_rmw(display, regs.aud_config, 689 AUD_CONFIG_N_VALUE_INDEX | 690 AUD_CONFIG_N_PROG_ENABLE | 691 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 692 (intel_crtc_has_dp_encoder(crtc_state) ? 693 AUD_CONFIG_N_VALUE_INDEX : 694 audio_config_hdmi_pixel_clock(crtc_state))); 695 696 mutex_unlock(&display->audio.mutex); 697 } 698 699 bool intel_audio_compute_config(struct intel_encoder *encoder, 700 struct intel_crtc_state *crtc_state, 701 struct drm_connector_state *conn_state) 702 { 703 struct intel_display *display = to_intel_display(encoder); 704 struct drm_connector *connector = conn_state->connector; 705 const struct drm_display_mode *adjusted_mode = 706 &crtc_state->hw.adjusted_mode; 707 708 mutex_lock(&connector->eld_mutex); 709 if (!connector->eld[0]) { 710 drm_dbg_kms(display->drm, 711 "Bogus ELD on [CONNECTOR:%d:%s]\n", 712 connector->base.id, connector->name); 713 mutex_unlock(&connector->eld_mutex); 714 return false; 715 } 716 717 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld)); 718 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); 719 720 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 721 mutex_unlock(&connector->eld_mutex); 722 723 return true; 724 } 725 726 /** 727 * intel_audio_codec_enable - Enable the audio codec for HD audio 728 * @encoder: encoder on which to enable audio 729 * @crtc_state: pointer to the current crtc state. 730 * @conn_state: pointer to the current connector state. 731 * 732 * The enable sequences may only be performed after enabling the transcoder and 733 * port, and after completed link training. 734 */ 735 void intel_audio_codec_enable(struct intel_encoder *encoder, 736 const struct intel_crtc_state *crtc_state, 737 const struct drm_connector_state *conn_state) 738 { 739 struct intel_display *display = to_intel_display(encoder); 740 struct i915_audio_component *acomp = display->audio.component; 741 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 742 struct intel_connector *connector = to_intel_connector(conn_state->connector); 743 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 744 struct intel_audio_state *audio_state; 745 enum port port = encoder->port; 746 747 if (!crtc_state->has_audio) 748 return; 749 750 drm_dbg_kms(display->drm, 751 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", 752 connector->base.base.id, connector->base.name, 753 encoder->base.base.id, encoder->base.name, 754 crtc->base.base.id, crtc->base.name, 755 drm_eld_size(crtc_state->eld)); 756 757 if (display->funcs.audio) 758 display->funcs.audio->audio_codec_enable(encoder, 759 crtc_state, 760 conn_state); 761 762 mutex_lock(&display->audio.mutex); 763 764 audio_state = &display->audio.state[cpu_transcoder]; 765 766 audio_state->encoder = encoder; 767 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld)); 768 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld)); 769 770 mutex_unlock(&display->audio.mutex); 771 772 if (acomp && acomp->base.audio_ops && 773 acomp->base.audio_ops->pin_eld_notify) { 774 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 775 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) 776 cpu_transcoder = -1; 777 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 778 (int)port, (int)cpu_transcoder); 779 } 780 781 intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld, 782 crtc_state->port_clock, 783 intel_crtc_has_dp_encoder(crtc_state)); 784 } 785 786 /** 787 * intel_audio_codec_disable - Disable the audio codec for HD audio 788 * @encoder: encoder on which to disable audio 789 * @old_crtc_state: pointer to the old crtc state. 790 * @old_conn_state: pointer to the old connector state. 791 * 792 * The disable sequences must be performed before disabling the transcoder or 793 * port. 794 */ 795 void intel_audio_codec_disable(struct intel_encoder *encoder, 796 const struct intel_crtc_state *old_crtc_state, 797 const struct drm_connector_state *old_conn_state) 798 { 799 struct intel_display *display = to_intel_display(encoder); 800 struct i915_audio_component *acomp = display->audio.component; 801 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 802 struct intel_connector *connector = to_intel_connector(old_conn_state->connector); 803 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 804 struct intel_audio_state *audio_state; 805 enum port port = encoder->port; 806 807 if (!old_crtc_state->has_audio) 808 return; 809 810 drm_dbg_kms(display->drm, 811 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", 812 connector->base.base.id, connector->base.name, 813 encoder->base.base.id, encoder->base.name, 814 crtc->base.base.id, crtc->base.name); 815 816 if (display->funcs.audio) 817 display->funcs.audio->audio_codec_disable(encoder, 818 old_crtc_state, 819 old_conn_state); 820 821 mutex_lock(&display->audio.mutex); 822 823 audio_state = &display->audio.state[cpu_transcoder]; 824 825 audio_state->encoder = NULL; 826 memset(audio_state->eld, 0, sizeof(audio_state->eld)); 827 828 mutex_unlock(&display->audio.mutex); 829 830 if (acomp && acomp->base.audio_ops && 831 acomp->base.audio_ops->pin_eld_notify) { 832 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */ 833 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) 834 cpu_transcoder = -1; 835 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 836 (int)port, (int)cpu_transcoder); 837 } 838 839 intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false); 840 } 841 842 static void intel_acomp_get_config(struct intel_encoder *encoder, 843 struct intel_crtc_state *crtc_state) 844 { 845 struct intel_display *display = to_intel_display(encoder); 846 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 847 struct intel_audio_state *audio_state; 848 849 mutex_lock(&display->audio.mutex); 850 851 audio_state = &display->audio.state[cpu_transcoder]; 852 853 if (audio_state->encoder) 854 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld)); 855 856 mutex_unlock(&display->audio.mutex); 857 } 858 859 void intel_audio_codec_get_config(struct intel_encoder *encoder, 860 struct intel_crtc_state *crtc_state) 861 { 862 struct intel_display *display = to_intel_display(encoder); 863 864 if (!crtc_state->has_audio) 865 return; 866 867 if (display->funcs.audio) 868 display->funcs.audio->audio_codec_get_config(encoder, crtc_state); 869 } 870 871 static const struct intel_audio_funcs g4x_audio_funcs = { 872 .audio_codec_enable = g4x_audio_codec_enable, 873 .audio_codec_disable = g4x_audio_codec_disable, 874 .audio_codec_get_config = g4x_audio_codec_get_config, 875 }; 876 877 static const struct intel_audio_funcs ibx_audio_funcs = { 878 .audio_codec_enable = ibx_audio_codec_enable, 879 .audio_codec_disable = ibx_audio_codec_disable, 880 .audio_codec_get_config = intel_acomp_get_config, 881 }; 882 883 static const struct intel_audio_funcs hsw_audio_funcs = { 884 .audio_codec_enable = hsw_audio_codec_enable, 885 .audio_codec_disable = hsw_audio_codec_disable, 886 .audio_codec_get_config = intel_acomp_get_config, 887 }; 888 889 /** 890 * intel_audio_hooks_init - Set up chip specific audio hooks 891 * @display: display device 892 */ 893 void intel_audio_hooks_init(struct intel_display *display) 894 { 895 if (display->platform.g4x) 896 display->funcs.audio = &g4x_audio_funcs; 897 else if (display->platform.valleyview || display->platform.cherryview || 898 HAS_PCH_CPT(display) || HAS_PCH_IBX(display)) 899 display->funcs.audio = &ibx_audio_funcs; 900 else if (display->platform.haswell || DISPLAY_VER(display) >= 8) 901 display->funcs.audio = &hsw_audio_funcs; 902 } 903 904 struct aud_ts_cdclk_m_n { 905 u8 m; 906 u16 n; 907 }; 908 909 void intel_audio_cdclk_change_pre(struct intel_display *display) 910 { 911 if (DISPLAY_VER(display) >= 13) 912 intel_de_rmw(display, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 913 } 914 915 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 916 { 917 aud_ts->m = 60; 918 aud_ts->n = cdclk * aud_ts->m / 24000; 919 } 920 921 void intel_audio_cdclk_change_post(struct intel_display *display) 922 { 923 struct aud_ts_cdclk_m_n aud_ts; 924 925 if (DISPLAY_VER(display) >= 13) { 926 get_aud_ts_cdclk_m_n(display->cdclk.hw.ref, 927 display->cdclk.hw.cdclk, &aud_ts); 928 929 intel_de_write(display, AUD_TS_CDCLK_N, aud_ts.n); 930 intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 931 drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n", 932 aud_ts.m, aud_ts.n); 933 } 934 } 935 936 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 937 struct intel_crtc *crtc, 938 bool enable) 939 { 940 struct intel_cdclk_state *cdclk_state; 941 int ret; 942 943 /* need to hold at least one crtc lock for the global state */ 944 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 945 if (ret) 946 return ret; 947 948 cdclk_state = intel_atomic_get_cdclk_state(state); 949 if (IS_ERR(cdclk_state)) 950 return PTR_ERR(cdclk_state); 951 952 intel_cdclk_force_min_cdclk(cdclk_state, enable ? 2 * 96000 : 0); 953 954 return drm_atomic_commit(&state->base); 955 } 956 957 static void glk_force_audio_cdclk(struct intel_display *display, 958 bool enable) 959 { 960 struct drm_modeset_acquire_ctx ctx; 961 struct drm_atomic_state *state; 962 struct intel_crtc *crtc; 963 int ret; 964 965 crtc = intel_first_crtc(display); 966 if (!crtc) 967 return; 968 969 drm_modeset_acquire_init(&ctx, 0); 970 state = drm_atomic_state_alloc(display->drm); 971 if (drm_WARN_ON(display->drm, !state)) 972 return; 973 974 state->acquire_ctx = &ctx; 975 to_intel_atomic_state(state)->internal = true; 976 977 retry: 978 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 979 enable); 980 if (ret == -EDEADLK) { 981 drm_atomic_state_clear(state); 982 drm_modeset_backoff(&ctx); 983 goto retry; 984 } 985 986 drm_WARN_ON(display->drm, ret); 987 988 drm_atomic_state_put(state); 989 990 drm_modeset_drop_locks(&ctx); 991 drm_modeset_acquire_fini(&ctx); 992 } 993 994 int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) 995 { 996 struct intel_display *display = to_intel_display(crtc_state); 997 int min_cdclk = 0; 998 999 if (!crtc_state->has_audio) 1000 return 0; 1001 1002 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 1003 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 1004 * there may be audio corruption or screen corruption." This cdclk 1005 * restriction for GLK is 316.8 MHz. 1006 */ 1007 if (intel_crtc_has_dp_encoder(crtc_state) && 1008 crtc_state->port_clock >= 540000 && 1009 crtc_state->lane_count == 4) { 1010 if (DISPLAY_VER(display) == 10) { 1011 /* Display WA #1145: glk */ 1012 min_cdclk = max(min_cdclk, 316800); 1013 } else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) { 1014 /* Display WA #1144: skl,bxt */ 1015 min_cdclk = max(min_cdclk, 432000); 1016 } 1017 } 1018 1019 /* 1020 * According to BSpec, "The CD clock frequency must be at least twice 1021 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 1022 */ 1023 if (DISPLAY_VER(display) >= 9) 1024 min_cdclk = max(min_cdclk, 2 * 96000); 1025 1026 /* 1027 * "For DP audio configuration, cdclk frequency shall be set to 1028 * meet the following requirements: 1029 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 1030 * 270 | 320 or higher 1031 * 162 | 200 or higher" 1032 */ 1033 if ((display->platform.valleyview || display->platform.cherryview) && 1034 intel_crtc_has_dp_encoder(crtc_state)) 1035 min_cdclk = max(min_cdclk, crtc_state->port_clock); 1036 1037 return min_cdclk; 1038 } 1039 1040 static unsigned long intel_audio_component_get_power(struct device *kdev) 1041 { 1042 struct intel_display *display = to_intel_display(kdev); 1043 struct ref_tracker *wakeref; 1044 1045 /* Catch potential impedance mismatches before they occur! */ 1046 BUILD_BUG_ON(sizeof(wakeref) > sizeof(unsigned long)); 1047 1048 wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK); 1049 1050 if (display->audio.power_refcount++ == 0) { 1051 if (DISPLAY_VER(display) >= 9) { 1052 intel_de_write(display, AUD_FREQ_CNTRL, 1053 display->audio.freq_cntrl); 1054 drm_dbg_kms(display->drm, 1055 "restored AUD_FREQ_CNTRL to 0x%x\n", 1056 display->audio.freq_cntrl); 1057 } 1058 1059 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1060 if (display->platform.geminilake) 1061 glk_force_audio_cdclk(display, true); 1062 1063 if (DISPLAY_VER(display) >= 10) 1064 intel_de_rmw(display, AUD_PIN_BUF_CTL, 1065 0, AUD_PIN_BUF_ENABLE); 1066 } 1067 1068 return (unsigned long)wakeref; 1069 } 1070 1071 static void intel_audio_component_put_power(struct device *kdev, 1072 unsigned long cookie) 1073 { 1074 struct intel_display *display = to_intel_display(kdev); 1075 struct ref_tracker *wakeref = (struct ref_tracker *)cookie; 1076 1077 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1078 if (--display->audio.power_refcount == 0) 1079 if (display->platform.geminilake) 1080 glk_force_audio_cdclk(display, false); 1081 1082 intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref); 1083 } 1084 1085 static void intel_audio_component_codec_wake_override(struct device *kdev, 1086 bool enable) 1087 { 1088 struct intel_display *display = to_intel_display(kdev); 1089 unsigned long cookie; 1090 1091 if (DISPLAY_VER(display) < 9) 1092 return; 1093 1094 cookie = intel_audio_component_get_power(kdev); 1095 1096 /* 1097 * Enable/disable generating the codec wake signal, overriding the 1098 * internal logic to generate the codec wake to controller. 1099 */ 1100 intel_de_rmw(display, HSW_AUD_CHICKENBIT, 1101 SKL_AUD_CODEC_WAKE_SIGNAL, 0); 1102 usleep_range(1000, 1500); 1103 1104 if (enable) { 1105 intel_de_rmw(display, HSW_AUD_CHICKENBIT, 1106 0, SKL_AUD_CODEC_WAKE_SIGNAL); 1107 usleep_range(1000, 1500); 1108 } 1109 1110 intel_audio_component_put_power(kdev, cookie); 1111 } 1112 1113 /* Get CDCLK in kHz */ 1114 static int intel_audio_component_get_cdclk_freq(struct device *kdev) 1115 { 1116 struct intel_display *display = to_intel_display(kdev); 1117 1118 if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display))) 1119 return -ENODEV; 1120 1121 return display->cdclk.hw.cdclk; 1122 } 1123 1124 /* 1125 * get the intel audio state according to the parameter port and cpu_transcoder 1126 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder], 1127 * when port is matched 1128 * MST & (cpu_transcoder < 0): this is invalid 1129 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry) 1130 * will get the right intel_encoder with port matched 1131 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched 1132 */ 1133 static struct intel_audio_state *find_audio_state(struct intel_display *display, 1134 int port, int cpu_transcoder) 1135 { 1136 /* MST */ 1137 if (cpu_transcoder >= 0) { 1138 struct intel_audio_state *audio_state; 1139 struct intel_encoder *encoder; 1140 1141 if (drm_WARN_ON(display->drm, 1142 cpu_transcoder >= ARRAY_SIZE(display->audio.state))) 1143 return NULL; 1144 1145 audio_state = &display->audio.state[cpu_transcoder]; 1146 encoder = audio_state->encoder; 1147 1148 if (encoder && encoder->port == port && 1149 encoder->type == INTEL_OUTPUT_DP_MST) 1150 return audio_state; 1151 } 1152 1153 /* Non-MST */ 1154 if (cpu_transcoder > 0) 1155 return NULL; 1156 1157 for_each_cpu_transcoder(display, cpu_transcoder) { 1158 struct intel_audio_state *audio_state; 1159 struct intel_encoder *encoder; 1160 1161 audio_state = &display->audio.state[cpu_transcoder]; 1162 encoder = audio_state->encoder; 1163 1164 if (encoder && encoder->port == port && 1165 encoder->type != INTEL_OUTPUT_DP_MST) 1166 return audio_state; 1167 } 1168 1169 return NULL; 1170 } 1171 1172 static int intel_audio_component_sync_audio_rate(struct device *kdev, int port, 1173 int cpu_transcoder, int rate) 1174 { 1175 struct intel_display *display = to_intel_display(kdev); 1176 struct i915_audio_component *acomp = display->audio.component; 1177 const struct intel_audio_state *audio_state; 1178 struct intel_encoder *encoder; 1179 struct intel_crtc *crtc; 1180 unsigned long cookie; 1181 int err = 0; 1182 1183 if (!HAS_DDI(display)) 1184 return 0; 1185 1186 cookie = intel_audio_component_get_power(kdev); 1187 mutex_lock(&display->audio.mutex); 1188 1189 audio_state = find_audio_state(display, port, cpu_transcoder); 1190 if (!audio_state) { 1191 drm_dbg_kms(display->drm, "Not valid for port %c\n", 1192 port_name(port)); 1193 err = -ENODEV; 1194 goto unlock; 1195 } 1196 1197 encoder = audio_state->encoder; 1198 1199 /* FIXME stop using the legacy crtc pointer */ 1200 crtc = to_intel_crtc(encoder->base.crtc); 1201 1202 /* port must be valid now, otherwise the cpu_transcoder will be invalid */ 1203 acomp->aud_sample_rate[port] = rate; 1204 1205 /* FIXME get rid of the crtc->config stuff */ 1206 hsw_audio_config_update(encoder, crtc->config); 1207 1208 unlock: 1209 mutex_unlock(&display->audio.mutex); 1210 intel_audio_component_put_power(kdev, cookie); 1211 return err; 1212 } 1213 1214 static int intel_audio_component_get_eld(struct device *kdev, int port, 1215 int cpu_transcoder, bool *enabled, 1216 unsigned char *buf, int max_bytes) 1217 { 1218 struct intel_display *display = to_intel_display(kdev); 1219 const struct intel_audio_state *audio_state; 1220 int ret = 0; 1221 1222 mutex_lock(&display->audio.mutex); 1223 1224 audio_state = find_audio_state(display, port, cpu_transcoder); 1225 if (!audio_state) { 1226 drm_dbg_kms(display->drm, "Not valid for port %c\n", 1227 port_name(port)); 1228 mutex_unlock(&display->audio.mutex); 1229 return -EINVAL; 1230 } 1231 1232 *enabled = audio_state->encoder != NULL; 1233 if (*enabled) { 1234 const u8 *eld = audio_state->eld; 1235 1236 ret = drm_eld_size(eld); 1237 memcpy(buf, eld, min(max_bytes, ret)); 1238 } 1239 1240 mutex_unlock(&display->audio.mutex); 1241 return ret; 1242 } 1243 1244 static const struct drm_audio_component_ops intel_audio_component_ops = { 1245 .owner = THIS_MODULE, 1246 .get_power = intel_audio_component_get_power, 1247 .put_power = intel_audio_component_put_power, 1248 .codec_wake_override = intel_audio_component_codec_wake_override, 1249 .get_cdclk_freq = intel_audio_component_get_cdclk_freq, 1250 .sync_audio_rate = intel_audio_component_sync_audio_rate, 1251 .get_eld = intel_audio_component_get_eld, 1252 }; 1253 1254 static int intel_audio_component_bind(struct device *drv_kdev, 1255 struct device *hda_kdev, void *data) 1256 { 1257 struct intel_display *display = to_intel_display(drv_kdev); 1258 struct i915_audio_component *acomp = data; 1259 int i; 1260 1261 if (drm_WARN_ON(display->drm, acomp->base.ops || acomp->base.dev)) 1262 return -EEXIST; 1263 1264 if (drm_WARN_ON(display->drm, 1265 !device_link_add(hda_kdev, drv_kdev, 1266 DL_FLAG_STATELESS))) 1267 return -ENOMEM; 1268 1269 drm_modeset_lock_all(display->drm); 1270 acomp->base.ops = &intel_audio_component_ops; 1271 acomp->base.dev = drv_kdev; 1272 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1273 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1274 acomp->aud_sample_rate[i] = 0; 1275 display->audio.component = acomp; 1276 drm_modeset_unlock_all(display->drm); 1277 1278 return 0; 1279 } 1280 1281 static void intel_audio_component_unbind(struct device *drv_kdev, 1282 struct device *hda_kdev, void *data) 1283 { 1284 struct intel_display *display = to_intel_display(drv_kdev); 1285 struct i915_audio_component *acomp = data; 1286 1287 drm_modeset_lock_all(display->drm); 1288 acomp->base.ops = NULL; 1289 acomp->base.dev = NULL; 1290 display->audio.component = NULL; 1291 drm_modeset_unlock_all(display->drm); 1292 1293 device_link_remove(hda_kdev, drv_kdev); 1294 1295 if (display->audio.power_refcount) 1296 drm_err(display->drm, 1297 "audio power refcount %d after unbind\n", 1298 display->audio.power_refcount); 1299 } 1300 1301 static const struct component_ops intel_audio_component_bind_ops = { 1302 .bind = intel_audio_component_bind, 1303 .unbind = intel_audio_component_unbind, 1304 }; 1305 1306 #define AUD_FREQ_TMODE_SHIFT 14 1307 #define AUD_FREQ_4T 0 1308 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1309 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1310 #define AUD_FREQ_BCLK_96M BIT(4) 1311 1312 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1313 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1314 1315 /** 1316 * intel_audio_component_init - initialize and register the audio component 1317 * @display: display device 1318 * 1319 * This will register with the component framework a child component which 1320 * will bind dynamically to the snd_hda_intel driver's corresponding master 1321 * component when the latter is registered. During binding the child 1322 * initializes an instance of struct i915_audio_component which it receives 1323 * from the master. The master can then start to use the interface defined by 1324 * this struct. Each side can break the binding at any point by deregistering 1325 * its own component after which each side's component unbind callback is 1326 * called. 1327 * 1328 * We ignore any error during registration and continue with reduced 1329 * functionality (i.e. without HDMI audio). 1330 */ 1331 static void intel_audio_component_init(struct intel_display *display) 1332 { 1333 u32 aud_freq, aud_freq_init; 1334 1335 if (DISPLAY_VER(display) >= 9) { 1336 aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL); 1337 1338 if (DISPLAY_VER(display) >= 12) 1339 aud_freq = AUD_FREQ_GEN12; 1340 else 1341 aud_freq = aud_freq_init; 1342 1343 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1344 if ((display->platform.tigerlake || display->platform.rocketlake) && 1345 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1346 aud_freq = aud_freq_init; 1347 1348 drm_dbg_kms(display->drm, 1349 "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1350 aud_freq, aud_freq_init); 1351 1352 display->audio.freq_cntrl = aud_freq; 1353 } 1354 1355 /* init with current cdclk */ 1356 intel_audio_cdclk_change_post(display); 1357 } 1358 1359 static void intel_audio_component_register(struct intel_display *display) 1360 { 1361 int ret; 1362 1363 ret = component_add_typed(display->drm->dev, 1364 &intel_audio_component_bind_ops, 1365 I915_COMPONENT_AUDIO); 1366 if (ret < 0) { 1367 drm_err(display->drm, 1368 "failed to add audio component (%d)\n", ret); 1369 /* continue with reduced functionality */ 1370 return; 1371 } 1372 1373 display->audio.component_registered = true; 1374 } 1375 1376 /** 1377 * intel_audio_component_cleanup - deregister the audio component 1378 * @display: display device 1379 * 1380 * Deregisters the audio component, breaking any existing binding to the 1381 * corresponding snd_hda_intel driver's master component. 1382 */ 1383 static void intel_audio_component_cleanup(struct intel_display *display) 1384 { 1385 if (!display->audio.component_registered) 1386 return; 1387 1388 component_del(display->drm->dev, &intel_audio_component_bind_ops); 1389 display->audio.component_registered = false; 1390 } 1391 1392 /** 1393 * intel_audio_init() - Initialize the audio driver either using 1394 * component framework or using lpe audio bridge 1395 * @display: display device 1396 * 1397 */ 1398 void intel_audio_init(struct intel_display *display) 1399 { 1400 if (intel_lpe_audio_init(display) < 0) 1401 intel_audio_component_init(display); 1402 } 1403 1404 void intel_audio_register(struct intel_display *display) 1405 { 1406 if (!display->audio.lpe.platdev) 1407 intel_audio_component_register(display); 1408 } 1409 1410 /** 1411 * intel_audio_deinit() - deinitialize the audio driver 1412 * @display: display device 1413 */ 1414 void intel_audio_deinit(struct intel_display *display) 1415 { 1416 if (display->audio.lpe.platdev) 1417 intel_lpe_audio_teardown(display); 1418 else 1419 intel_audio_component_cleanup(display); 1420 } 1421