1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/component.h> 25 #include <linux/kernel.h> 26 27 #include <drm/drm_edid.h> 28 #include <drm/drm_eld.h> 29 #include <drm/drm_fixed.h> 30 #include <drm/drm_print.h> 31 #include <drm/intel/i915_component.h> 32 33 #include "intel_atomic.h" 34 #include "intel_audio.h" 35 #include "intel_audio_regs.h" 36 #include "intel_cdclk.h" 37 #include "intel_crtc.h" 38 #include "intel_de.h" 39 #include "intel_display_types.h" 40 #include "intel_display_wa.h" 41 #include "intel_dp.h" 42 #include "intel_lpe_audio.h" 43 44 /** 45 * DOC: High Definition Audio over HDMI and Display Port 46 * 47 * The graphics and audio drivers together support High Definition Audio over 48 * HDMI and Display Port. The audio programming sequences are divided into audio 49 * codec and controller enable and disable sequences. The graphics driver 50 * handles the audio codec sequences, while the audio driver handles the audio 51 * controller sequences. 52 * 53 * The disable sequences must be performed before disabling the transcoder or 54 * port. The enable sequences may only be performed after enabling the 55 * transcoder and port, and after completed link training. Therefore the audio 56 * enable/disable sequences are part of the modeset sequence. 57 * 58 * The codec and controller sequences could be done either parallel or serial, 59 * but generally the ELDV/PD change in the codec sequence indicates to the audio 60 * driver that the controller sequence should start. Indeed, most of the 61 * co-operation between the graphics and audio drivers is handled via audio 62 * related registers. (The notable exception is the power management, not 63 * covered here.) 64 * 65 * The struct &i915_audio_component is used to interact between the graphics 66 * and audio drivers. The struct &i915_audio_component_ops @ops in it is 67 * defined in graphics driver and called in audio driver. The 68 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver. 69 */ 70 71 struct intel_audio_funcs { 72 void (*audio_codec_enable)(struct intel_encoder *encoder, 73 const struct intel_crtc_state *crtc_state, 74 const struct drm_connector_state *conn_state); 75 void (*audio_codec_disable)(struct intel_encoder *encoder, 76 const struct intel_crtc_state *old_crtc_state, 77 const struct drm_connector_state *old_conn_state); 78 void (*audio_codec_get_config)(struct intel_encoder *encoder, 79 struct intel_crtc_state *crtc_state); 80 }; 81 82 struct hdmi_aud_ncts { 83 int sample_rate; 84 int clock; 85 int n; 86 int cts; 87 }; 88 89 static const struct { 90 int clock; 91 u32 config; 92 } hdmi_audio_clock[] = { 93 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 94 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 95 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 96 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 97 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 98 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 99 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 100 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 101 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 102 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 103 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, 104 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, 105 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, 106 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, 107 }; 108 109 /* HDMI N/CTS table */ 110 #define TMDS_297M 297000 111 #define TMDS_296M 296703 112 #define TMDS_594M 594000 113 #define TMDS_593M 593407 114 115 static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = { 116 { 32000, TMDS_296M, 5824, 421875 }, 117 { 32000, TMDS_297M, 3072, 222750 }, 118 { 32000, TMDS_593M, 5824, 843750 }, 119 { 32000, TMDS_594M, 3072, 445500 }, 120 { 44100, TMDS_296M, 4459, 234375 }, 121 { 44100, TMDS_297M, 4704, 247500 }, 122 { 44100, TMDS_593M, 8918, 937500 }, 123 { 44100, TMDS_594M, 9408, 990000 }, 124 { 88200, TMDS_296M, 8918, 234375 }, 125 { 88200, TMDS_297M, 9408, 247500 }, 126 { 88200, TMDS_593M, 17836, 937500 }, 127 { 88200, TMDS_594M, 18816, 990000 }, 128 { 176400, TMDS_296M, 17836, 234375 }, 129 { 176400, TMDS_297M, 18816, 247500 }, 130 { 176400, TMDS_593M, 35672, 937500 }, 131 { 176400, TMDS_594M, 37632, 990000 }, 132 { 48000, TMDS_296M, 5824, 281250 }, 133 { 48000, TMDS_297M, 5120, 247500 }, 134 { 48000, TMDS_593M, 5824, 562500 }, 135 { 48000, TMDS_594M, 6144, 594000 }, 136 { 96000, TMDS_296M, 11648, 281250 }, 137 { 96000, TMDS_297M, 10240, 247500 }, 138 { 96000, TMDS_593M, 11648, 562500 }, 139 { 96000, TMDS_594M, 12288, 594000 }, 140 { 192000, TMDS_296M, 23296, 281250 }, 141 { 192000, TMDS_297M, 20480, 247500 }, 142 { 192000, TMDS_593M, 23296, 562500 }, 143 { 192000, TMDS_594M, 24576, 594000 }, 144 }; 145 146 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/ 147 /* HDMI N/CTS table for 10 bit deep color(30 bpp)*/ 148 #define TMDS_371M 371250 149 #define TMDS_370M 370878 150 151 static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = { 152 { 32000, TMDS_370M, 5824, 527344 }, 153 { 32000, TMDS_371M, 6144, 556875 }, 154 { 44100, TMDS_370M, 8918, 585938 }, 155 { 44100, TMDS_371M, 4704, 309375 }, 156 { 88200, TMDS_370M, 17836, 585938 }, 157 { 88200, TMDS_371M, 9408, 309375 }, 158 { 176400, TMDS_370M, 35672, 585938 }, 159 { 176400, TMDS_371M, 18816, 309375 }, 160 { 48000, TMDS_370M, 11648, 703125 }, 161 { 48000, TMDS_371M, 5120, 309375 }, 162 { 96000, TMDS_370M, 23296, 703125 }, 163 { 96000, TMDS_371M, 10240, 309375 }, 164 { 192000, TMDS_370M, 46592, 703125 }, 165 { 192000, TMDS_371M, 20480, 309375 }, 166 }; 167 168 /* HDMI N/CTS table for 12 bit deep color(36 bpp)*/ 169 #define TMDS_445_5M 445500 170 #define TMDS_445M 445054 171 172 static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 173 { 32000, TMDS_445M, 5824, 632813 }, 174 { 32000, TMDS_445_5M, 4096, 445500 }, 175 { 44100, TMDS_445M, 8918, 703125 }, 176 { 44100, TMDS_445_5M, 4704, 371250 }, 177 { 88200, TMDS_445M, 17836, 703125 }, 178 { 88200, TMDS_445_5M, 9408, 371250 }, 179 { 176400, TMDS_445M, 35672, 703125 }, 180 { 176400, TMDS_445_5M, 18816, 371250 }, 181 { 48000, TMDS_445M, 5824, 421875 }, 182 { 48000, TMDS_445_5M, 5120, 371250 }, 183 { 96000, TMDS_445M, 11648, 421875 }, 184 { 96000, TMDS_445_5M, 10240, 371250 }, 185 { 192000, TMDS_445M, 23296, 421875 }, 186 { 192000, TMDS_445_5M, 20480, 371250 }, 187 }; 188 189 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 190 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) 191 { 192 struct intel_display *display = to_intel_display(crtc_state); 193 const struct drm_display_mode *adjusted_mode = 194 &crtc_state->hw.adjusted_mode; 195 int i; 196 197 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 198 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 199 break; 200 } 201 202 if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500) 203 i = ARRAY_SIZE(hdmi_audio_clock); 204 205 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 206 drm_dbg_kms(display->drm, 207 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 208 adjusted_mode->crtc_clock); 209 i = 1; 210 } 211 212 drm_dbg_kms(display->drm, 213 "Configuring HDMI audio for pixel clock %d (0x%08x)\n", 214 hdmi_audio_clock[i].clock, 215 hdmi_audio_clock[i].config); 216 217 return hdmi_audio_clock[i].config; 218 } 219 220 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, 221 int rate) 222 { 223 const struct hdmi_aud_ncts *hdmi_ncts_table; 224 int i, size; 225 226 if (crtc_state->pipe_bpp == 36) { 227 hdmi_ncts_table = hdmi_aud_ncts_36bpp; 228 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp); 229 } else if (crtc_state->pipe_bpp == 30) { 230 hdmi_ncts_table = hdmi_aud_ncts_30bpp; 231 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp); 232 } else { 233 hdmi_ncts_table = hdmi_aud_ncts_24bpp; 234 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp); 235 } 236 237 for (i = 0; i < size; i++) { 238 if (rate == hdmi_ncts_table[i].sample_rate && 239 crtc_state->port_clock == hdmi_ncts_table[i].clock) { 240 return hdmi_ncts_table[i].n; 241 } 242 } 243 return 0; 244 } 245 246 /* ELD buffer size in dwords */ 247 static int g4x_eld_buffer_size(struct intel_display *display) 248 { 249 u32 tmp; 250 251 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); 252 253 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); 254 } 255 256 static void g4x_audio_codec_get_config(struct intel_encoder *encoder, 257 struct intel_crtc_state *crtc_state) 258 { 259 struct intel_display *display = to_intel_display(encoder); 260 u32 *eld = (u32 *)crtc_state->eld; 261 int eld_buffer_size, len, i; 262 u32 tmp; 263 264 tmp = intel_de_read(display, G4X_AUD_CNTL_ST); 265 if ((tmp & G4X_ELD_VALID) == 0) 266 return; 267 268 intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); 269 270 eld_buffer_size = g4x_eld_buffer_size(display); 271 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size); 272 273 for (i = 0; i < len; i++) 274 eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID); 275 } 276 277 static void g4x_audio_codec_disable(struct intel_encoder *encoder, 278 const struct intel_crtc_state *old_crtc_state, 279 const struct drm_connector_state *old_conn_state) 280 { 281 struct intel_display *display = to_intel_display(encoder); 282 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 283 284 /* Invalidate ELD */ 285 intel_de_rmw(display, G4X_AUD_CNTL_ST, 286 G4X_ELD_VALID, 0); 287 288 intel_crtc_wait_for_next_vblank(crtc); 289 intel_crtc_wait_for_next_vblank(crtc); 290 } 291 292 static void g4x_audio_codec_enable(struct intel_encoder *encoder, 293 const struct intel_crtc_state *crtc_state, 294 const struct drm_connector_state *conn_state) 295 { 296 struct intel_display *display = to_intel_display(encoder); 297 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 298 const u32 *eld = (const u32 *)crtc_state->eld; 299 int eld_buffer_size, len, i; 300 301 intel_crtc_wait_for_next_vblank(crtc); 302 303 intel_de_rmw(display, G4X_AUD_CNTL_ST, 304 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); 305 306 eld_buffer_size = g4x_eld_buffer_size(display); 307 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size); 308 309 for (i = 0; i < len; i++) 310 intel_de_write(display, G4X_HDMIW_HDMIEDID, eld[i]); 311 for (; i < eld_buffer_size; i++) 312 intel_de_write(display, G4X_HDMIW_HDMIEDID, 0); 313 314 drm_WARN_ON(display->drm, 315 (intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); 316 317 intel_de_rmw(display, G4X_AUD_CNTL_ST, 318 0, G4X_ELD_VALID); 319 } 320 321 static void 322 hsw_dp_audio_config_update(struct intel_encoder *encoder, 323 const struct intel_crtc_state *crtc_state) 324 { 325 struct intel_display *display = to_intel_display(encoder); 326 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 327 328 /* Enable time stamps. Let HW calculate Maud/Naud values */ 329 intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), 330 AUD_CONFIG_N_VALUE_INDEX | 331 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK | 332 AUD_CONFIG_UPPER_N_MASK | 333 AUD_CONFIG_LOWER_N_MASK | 334 AUD_CONFIG_N_PROG_ENABLE, 335 AUD_CONFIG_N_VALUE_INDEX); 336 337 } 338 339 static void 340 hsw_hdmi_audio_config_update(struct intel_encoder *encoder, 341 const struct intel_crtc_state *crtc_state) 342 { 343 struct intel_display *display = to_intel_display(encoder); 344 struct i915_audio_component *acomp = display->audio.component; 345 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 346 enum port port = encoder->port; 347 int n, rate; 348 u32 tmp; 349 350 rate = acomp ? acomp->aud_sample_rate[port] : 0; 351 352 tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder)); 353 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 354 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 355 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 356 tmp |= audio_config_hdmi_pixel_clock(crtc_state); 357 358 n = audio_config_hdmi_get_n(crtc_state, rate); 359 if (n != 0) { 360 drm_dbg_kms(display->drm, "using N %d\n", n); 361 362 tmp &= ~AUD_CONFIG_N_MASK; 363 tmp |= AUD_CONFIG_N(n); 364 tmp |= AUD_CONFIG_N_PROG_ENABLE; 365 } else { 366 drm_dbg_kms(display->drm, "using automatic N\n"); 367 } 368 369 intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp); 370 371 /* 372 * Let's disable "Enable CTS or M Prog bit" 373 * and let HW calculate the value 374 */ 375 tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); 376 tmp &= ~AUD_M_CTS_M_PROG_ENABLE; 377 tmp &= ~AUD_M_CTS_M_VALUE_INDEX; 378 intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); 379 } 380 381 static void 382 hsw_audio_config_update(struct intel_encoder *encoder, 383 const struct intel_crtc_state *crtc_state) 384 { 385 if (intel_crtc_has_dp_encoder(crtc_state)) 386 hsw_dp_audio_config_update(encoder, crtc_state); 387 else 388 hsw_hdmi_audio_config_update(encoder, crtc_state); 389 } 390 391 static void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state, 392 bool enable) 393 { 394 struct intel_display *display = to_intel_display(crtc_state); 395 enum transcoder trans = crtc_state->cpu_transcoder; 396 397 if (!HAS_DP20(display)) 398 return; 399 400 intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 401 enable && crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); 402 } 403 404 static void hsw_audio_codec_disable(struct intel_encoder *encoder, 405 const struct intel_crtc_state *old_crtc_state, 406 const struct drm_connector_state *old_conn_state) 407 { 408 struct intel_display *display = to_intel_display(encoder); 409 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 410 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 411 412 mutex_lock(&display->audio.mutex); 413 414 /* Disable timestamps */ 415 intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), 416 AUD_CONFIG_N_VALUE_INDEX | 417 AUD_CONFIG_UPPER_N_MASK | 418 AUD_CONFIG_LOWER_N_MASK, 419 AUD_CONFIG_N_PROG_ENABLE | 420 (intel_crtc_has_dp_encoder(old_crtc_state) ? 421 AUD_CONFIG_N_VALUE_INDEX : 0)); 422 423 /* Invalidate ELD */ 424 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 425 AUDIO_ELD_VALID(cpu_transcoder), 0); 426 427 intel_crtc_wait_for_next_vblank(crtc); 428 intel_crtc_wait_for_next_vblank(crtc); 429 430 /* Disable audio presence detect */ 431 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 432 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); 433 434 /* 435 * WA_14020863754: Implement Audio Workaround 436 * Corner case with Min Hblank Fix can cause audio hang 437 */ 438 if (intel_display_wa(display, INTEL_DISPLAY_WA_14020863754)) 439 intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); 440 441 intel_audio_sdp_split_update(old_crtc_state, false); 442 443 mutex_unlock(&display->audio.mutex); 444 } 445 446 static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, 447 const struct intel_crtc_state *crtc_state) 448 { 449 struct intel_display *display = to_intel_display(encoder); 450 unsigned int link_clks_available, link_clks_required; 451 unsigned int tu_data, tu_line, link_clks_active; 452 unsigned int h_active, h_total, hblank_delta, pixel_clk; 453 unsigned int fec_coeff, cdclk, vdsc_bppx16; 454 unsigned int link_clk, lanes; 455 unsigned int hblank_rise; 456 457 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay; 458 h_total = crtc_state->hw.adjusted_mode.crtc_htotal; 459 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; 460 vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16; 461 cdclk = display->cdclk.hw.cdclk; 462 /* fec= 0.972261, using rounding multiplier of 1000000 */ 463 fec_coeff = 972261; 464 link_clk = crtc_state->port_clock; 465 lanes = crtc_state->lane_count; 466 467 drm_dbg_kms(display->drm, 468 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n", 469 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); 470 471 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk)) 472 return 0; 473 474 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; 475 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2); 476 477 if (link_clks_available > link_clks_required) 478 hblank_delta = 32; 479 else 480 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk), 481 mul_u32_u32(link_clk, cdclk)); 482 483 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000), 484 mul_u32_u32(link_clk * lanes * 16, fec_coeff)); 485 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff), 486 mul_u32_u32(64 * pixel_clk, 1000000)); 487 link_clks_active = (tu_line - 1) * 64 + tu_data; 488 489 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk; 490 491 return h_active - hblank_rise + hblank_delta; 492 } 493 494 static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) 495 { 496 unsigned int h_active, h_total, pixel_clk; 497 unsigned int link_clk, lanes; 498 499 h_active = crtc_state->hw.adjusted_mode.hdisplay; 500 h_total = crtc_state->hw.adjusted_mode.htotal; 501 pixel_clk = crtc_state->hw.adjusted_mode.clock; 502 link_clk = crtc_state->port_clock; 503 lanes = crtc_state->lane_count; 504 505 return ((h_total - h_active) * link_clk - 12 * pixel_clk) / 506 (pixel_clk * (48 / lanes + 2)); 507 } 508 509 static void enable_audio_dsc_wa(struct intel_encoder *encoder, 510 const struct intel_crtc_state *crtc_state) 511 { 512 struct intel_display *display = to_intel_display(encoder); 513 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 514 unsigned int hblank_early_prog, samples_room; 515 unsigned int val; 516 517 if (DISPLAY_VER(display) < 11) 518 return; 519 520 val = intel_de_read(display, AUD_CONFIG_BE); 521 522 if (DISPLAY_VER(display) == 11) 523 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder); 524 else if (DISPLAY_VER(display) >= 12) 525 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder); 526 527 if (crtc_state->dsc.compression_enable && 528 crtc_state->hw.adjusted_mode.hdisplay >= 3840 && 529 crtc_state->hw.adjusted_mode.vdisplay >= 2160) { 530 /* Get hblank early enable value required */ 531 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder); 532 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state); 533 if (hblank_early_prog < 32) 534 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32); 535 else if (hblank_early_prog < 64) 536 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64); 537 else if (hblank_early_prog < 96) 538 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96); 539 else 540 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128); 541 542 /* Get samples room value required */ 543 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder); 544 samples_room = calc_samples_room(crtc_state); 545 if (samples_room < 3) 546 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room); 547 else /* Program 0 i.e "All Samples available in buffer" */ 548 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0); 549 } 550 551 intel_de_write(display, AUD_CONFIG_BE, val); 552 } 553 554 static void hsw_audio_codec_enable(struct intel_encoder *encoder, 555 const struct intel_crtc_state *crtc_state, 556 const struct drm_connector_state *conn_state) 557 { 558 struct intel_display *display = to_intel_display(encoder); 559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 560 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 561 562 mutex_lock(&display->audio.mutex); 563 564 /* Enable Audio WA for 4k DSC usecases */ 565 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) 566 enable_audio_dsc_wa(encoder, crtc_state); 567 568 intel_audio_sdp_split_update(crtc_state, true); 569 570 /* 571 * WA_14020863754: Implement Audio Workaround 572 * Corner case with Min Hblank Fix can cause audio hang 573 */ 574 if (intel_display_wa(display, INTEL_DISPLAY_WA_14020863754)) 575 intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); 576 577 /* Enable audio presence detect */ 578 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 579 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); 580 581 intel_crtc_wait_for_next_vblank(crtc); 582 583 /* Invalidate ELD */ 584 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 585 AUDIO_ELD_VALID(cpu_transcoder), 0); 586 587 /* 588 * The audio component is used to convey the ELD 589 * instead using of the hardware ELD buffer. 590 */ 591 592 /* Enable timestamps */ 593 hsw_audio_config_update(encoder, crtc_state); 594 595 mutex_unlock(&display->audio.mutex); 596 } 597 598 struct ibx_audio_regs { 599 intel_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 600 }; 601 602 static void ibx_audio_regs_init(struct intel_display *display, 603 enum pipe pipe, 604 struct ibx_audio_regs *regs) 605 { 606 if (display->platform.valleyview || display->platform.cherryview) { 607 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 608 regs->aud_config = VLV_AUD_CFG(pipe); 609 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 610 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 611 } else if (HAS_PCH_CPT(display)) { 612 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 613 regs->aud_config = CPT_AUD_CFG(pipe); 614 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 615 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 616 } else if (HAS_PCH_IBX(display)) { 617 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 618 regs->aud_config = IBX_AUD_CFG(pipe); 619 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 620 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 621 } 622 } 623 624 static void ibx_audio_codec_disable(struct intel_encoder *encoder, 625 const struct intel_crtc_state *old_crtc_state, 626 const struct drm_connector_state *old_conn_state) 627 { 628 struct intel_display *display = to_intel_display(encoder); 629 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 630 enum port port = encoder->port; 631 enum pipe pipe = crtc->pipe; 632 struct ibx_audio_regs regs; 633 634 if (drm_WARN_ON(display->drm, port == PORT_A)) 635 return; 636 637 ibx_audio_regs_init(display, pipe, ®s); 638 639 mutex_lock(&display->audio.mutex); 640 641 /* Disable timestamps */ 642 intel_de_rmw(display, regs.aud_config, 643 AUD_CONFIG_N_VALUE_INDEX | 644 AUD_CONFIG_UPPER_N_MASK | 645 AUD_CONFIG_LOWER_N_MASK, 646 AUD_CONFIG_N_PROG_ENABLE | 647 (intel_crtc_has_dp_encoder(old_crtc_state) ? 648 AUD_CONFIG_N_VALUE_INDEX : 0)); 649 650 /* Invalidate ELD */ 651 intel_de_rmw(display, regs.aud_cntrl_st2, 652 IBX_ELD_VALID(port), 0); 653 654 mutex_unlock(&display->audio.mutex); 655 656 intel_crtc_wait_for_next_vblank(crtc); 657 intel_crtc_wait_for_next_vblank(crtc); 658 } 659 660 static void ibx_audio_codec_enable(struct intel_encoder *encoder, 661 const struct intel_crtc_state *crtc_state, 662 const struct drm_connector_state *conn_state) 663 { 664 struct intel_display *display = to_intel_display(encoder); 665 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 666 enum port port = encoder->port; 667 enum pipe pipe = crtc->pipe; 668 struct ibx_audio_regs regs; 669 670 if (drm_WARN_ON(display->drm, port == PORT_A)) 671 return; 672 673 intel_crtc_wait_for_next_vblank(crtc); 674 675 ibx_audio_regs_init(display, pipe, ®s); 676 677 mutex_lock(&display->audio.mutex); 678 679 /* Invalidate ELD */ 680 intel_de_rmw(display, regs.aud_cntrl_st2, 681 IBX_ELD_VALID(port), 0); 682 683 /* 684 * The audio component is used to convey the ELD 685 * instead using of the hardware ELD buffer. 686 */ 687 688 /* Enable timestamps */ 689 intel_de_rmw(display, regs.aud_config, 690 AUD_CONFIG_N_VALUE_INDEX | 691 AUD_CONFIG_N_PROG_ENABLE | 692 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 693 (intel_crtc_has_dp_encoder(crtc_state) ? 694 AUD_CONFIG_N_VALUE_INDEX : 695 audio_config_hdmi_pixel_clock(crtc_state))); 696 697 mutex_unlock(&display->audio.mutex); 698 } 699 700 static 701 bool intel_audio_needs_cpu_transcoder_id(const struct intel_crtc_state *crtc_state) 702 { 703 return intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || 704 intel_dp_is_uhbr(crtc_state); 705 } 706 707 bool intel_audio_compute_config(struct intel_encoder *encoder, 708 struct intel_crtc_state *crtc_state, 709 struct drm_connector_state *conn_state) 710 { 711 struct intel_display *display = to_intel_display(encoder); 712 struct drm_connector *connector = conn_state->connector; 713 const struct drm_display_mode *adjusted_mode = 714 &crtc_state->hw.adjusted_mode; 715 716 mutex_lock(&connector->eld_mutex); 717 if (!connector->eld[0]) { 718 drm_dbg_kms(display->drm, 719 "Bogus ELD on [CONNECTOR:%d:%s]\n", 720 connector->base.id, connector->name); 721 mutex_unlock(&connector->eld_mutex); 722 return false; 723 } 724 725 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld)); 726 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld)); 727 728 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 729 mutex_unlock(&connector->eld_mutex); 730 731 return true; 732 } 733 734 /** 735 * intel_audio_codec_enable - Enable the audio codec for HD audio 736 * @encoder: encoder on which to enable audio 737 * @crtc_state: pointer to the current crtc state. 738 * @conn_state: pointer to the current connector state. 739 * 740 * The enable sequences may only be performed after enabling the transcoder and 741 * port, and after completed link training. 742 */ 743 void intel_audio_codec_enable(struct intel_encoder *encoder, 744 const struct intel_crtc_state *crtc_state, 745 const struct drm_connector_state *conn_state) 746 { 747 struct intel_display *display = to_intel_display(encoder); 748 struct i915_audio_component *acomp = display->audio.component; 749 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 750 struct intel_connector *connector = to_intel_connector(conn_state->connector); 751 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 752 struct intel_audio_state *audio_state; 753 enum port port = encoder->port; 754 755 if (!crtc_state->has_audio) 756 return; 757 758 drm_dbg_kms(display->drm, 759 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", 760 connector->base.base.id, connector->base.name, 761 encoder->base.base.id, encoder->base.name, 762 crtc->base.base.id, crtc->base.name, 763 drm_eld_size(crtc_state->eld)); 764 765 if (display->audio.funcs) 766 display->audio.funcs->audio_codec_enable(encoder, crtc_state, conn_state); 767 768 mutex_lock(&display->audio.mutex); 769 770 audio_state = &display->audio.state[cpu_transcoder]; 771 772 audio_state->encoder = encoder; 773 audio_state->needs_cpu_transcoder_id = 774 intel_audio_needs_cpu_transcoder_id(crtc_state); 775 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld)); 776 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld)); 777 778 mutex_unlock(&display->audio.mutex); 779 780 if (acomp && acomp->base.audio_ops && 781 acomp->base.audio_ops->pin_eld_notify) { 782 /* 783 * Audio drivers expect cpu_transcoder = -1 to indicate 784 * Non-MST/HBR cases. MST and UHBR SST are addressed by 785 * a real cpu_transcoder. 786 */ 787 if (!intel_audio_needs_cpu_transcoder_id(crtc_state)) 788 cpu_transcoder = -1; 789 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 790 (int)port, (int)cpu_transcoder); 791 } 792 793 intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld, 794 crtc_state->port_clock, 795 intel_crtc_has_dp_encoder(crtc_state)); 796 } 797 798 /** 799 * intel_audio_codec_disable - Disable the audio codec for HD audio 800 * @encoder: encoder on which to disable audio 801 * @old_crtc_state: pointer to the old crtc state. 802 * @old_conn_state: pointer to the old connector state. 803 * 804 * The disable sequences must be performed before disabling the transcoder or 805 * port. 806 */ 807 void intel_audio_codec_disable(struct intel_encoder *encoder, 808 const struct intel_crtc_state *old_crtc_state, 809 const struct drm_connector_state *old_conn_state) 810 { 811 struct intel_display *display = to_intel_display(encoder); 812 struct i915_audio_component *acomp = display->audio.component; 813 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 814 struct intel_connector *connector = to_intel_connector(old_conn_state->connector); 815 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 816 struct intel_audio_state *audio_state; 817 enum port port = encoder->port; 818 819 if (!old_crtc_state->has_audio) 820 return; 821 822 drm_dbg_kms(display->drm, 823 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", 824 connector->base.base.id, connector->base.name, 825 encoder->base.base.id, encoder->base.name, 826 crtc->base.base.id, crtc->base.name); 827 828 if (display->audio.funcs) 829 display->audio.funcs->audio_codec_disable(encoder, old_crtc_state, old_conn_state); 830 831 mutex_lock(&display->audio.mutex); 832 833 audio_state = &display->audio.state[cpu_transcoder]; 834 835 audio_state->encoder = NULL; 836 audio_state->needs_cpu_transcoder_id = false; 837 memset(audio_state->eld, 0, sizeof(audio_state->eld)); 838 839 mutex_unlock(&display->audio.mutex); 840 841 if (acomp && acomp->base.audio_ops && 842 acomp->base.audio_ops->pin_eld_notify) { 843 /* 844 * Audio drivers expect cpu_transcoder = -1 to indicate 845 * Non-MST/HBR cases. MST and UHBR SST are addressed by 846 * a real cpu_transcoder. 847 */ 848 if (!intel_audio_needs_cpu_transcoder_id(old_crtc_state)) 849 cpu_transcoder = -1; 850 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr, 851 (int)port, (int)cpu_transcoder); 852 } 853 854 intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false); 855 } 856 857 static void intel_acomp_get_config(struct intel_encoder *encoder, 858 struct intel_crtc_state *crtc_state) 859 { 860 struct intel_display *display = to_intel_display(encoder); 861 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 862 struct intel_audio_state *audio_state; 863 864 mutex_lock(&display->audio.mutex); 865 866 audio_state = &display->audio.state[cpu_transcoder]; 867 868 if (audio_state->encoder) 869 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld)); 870 871 mutex_unlock(&display->audio.mutex); 872 } 873 874 void intel_audio_codec_get_config(struct intel_encoder *encoder, 875 struct intel_crtc_state *crtc_state) 876 { 877 struct intel_display *display = to_intel_display(encoder); 878 879 if (!crtc_state->has_audio) 880 return; 881 882 if (display->audio.funcs) 883 display->audio.funcs->audio_codec_get_config(encoder, crtc_state); 884 } 885 886 static const struct intel_audio_funcs g4x_audio_funcs = { 887 .audio_codec_enable = g4x_audio_codec_enable, 888 .audio_codec_disable = g4x_audio_codec_disable, 889 .audio_codec_get_config = g4x_audio_codec_get_config, 890 }; 891 892 static const struct intel_audio_funcs ibx_audio_funcs = { 893 .audio_codec_enable = ibx_audio_codec_enable, 894 .audio_codec_disable = ibx_audio_codec_disable, 895 .audio_codec_get_config = intel_acomp_get_config, 896 }; 897 898 static const struct intel_audio_funcs hsw_audio_funcs = { 899 .audio_codec_enable = hsw_audio_codec_enable, 900 .audio_codec_disable = hsw_audio_codec_disable, 901 .audio_codec_get_config = intel_acomp_get_config, 902 }; 903 904 /** 905 * intel_audio_hooks_init - Set up chip specific audio hooks 906 * @display: display device 907 */ 908 void intel_audio_hooks_init(struct intel_display *display) 909 { 910 if (display->platform.g4x) 911 display->audio.funcs = &g4x_audio_funcs; 912 else if (display->platform.valleyview || display->platform.cherryview || 913 HAS_PCH_CPT(display) || HAS_PCH_IBX(display)) 914 display->audio.funcs = &ibx_audio_funcs; 915 else if (display->platform.haswell || DISPLAY_VER(display) >= 8) 916 display->audio.funcs = &hsw_audio_funcs; 917 } 918 919 struct aud_ts_cdclk_m_n { 920 u8 m; 921 u16 n; 922 }; 923 924 void intel_audio_cdclk_change_pre(struct intel_display *display) 925 { 926 if (DISPLAY_VER(display) >= 13) 927 intel_de_rmw(display, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); 928 } 929 930 static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) 931 { 932 aud_ts->m = 60; 933 aud_ts->n = cdclk * aud_ts->m / 24000; 934 } 935 936 void intel_audio_cdclk_change_post(struct intel_display *display) 937 { 938 struct aud_ts_cdclk_m_n aud_ts; 939 940 if (DISPLAY_VER(display) >= 13) { 941 get_aud_ts_cdclk_m_n(display->cdclk.hw.ref, 942 display->cdclk.hw.cdclk, &aud_ts); 943 944 intel_de_write(display, AUD_TS_CDCLK_N, aud_ts.n); 945 intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); 946 drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n", 947 aud_ts.m, aud_ts.n); 948 } 949 } 950 951 static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, 952 struct intel_crtc *crtc, 953 bool enable) 954 { 955 struct intel_cdclk_state *cdclk_state; 956 int ret; 957 958 /* need to hold at least one crtc lock for the global state */ 959 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); 960 if (ret) 961 return ret; 962 963 cdclk_state = intel_atomic_get_cdclk_state(state); 964 if (IS_ERR(cdclk_state)) 965 return PTR_ERR(cdclk_state); 966 967 intel_cdclk_force_min_cdclk(cdclk_state, enable ? 2 * 96000 : 0); 968 969 return drm_atomic_commit(&state->base); 970 } 971 972 static void glk_force_audio_cdclk(struct intel_display *display, 973 bool enable) 974 { 975 struct drm_modeset_acquire_ctx ctx; 976 struct drm_atomic_commit *state; 977 struct intel_crtc *crtc; 978 int ret; 979 980 crtc = intel_first_crtc(display); 981 if (!crtc) 982 return; 983 984 drm_modeset_acquire_init(&ctx, 0); 985 state = drm_atomic_commit_alloc(display->drm); 986 if (drm_WARN_ON(display->drm, !state)) 987 return; 988 989 state->acquire_ctx = &ctx; 990 to_intel_atomic_state(state)->internal = true; 991 992 retry: 993 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, 994 enable); 995 if (ret == -EDEADLK) { 996 drm_atomic_commit_clear(state); 997 drm_modeset_backoff(&ctx); 998 goto retry; 999 } 1000 1001 drm_WARN_ON(display->drm, ret); 1002 1003 drm_atomic_commit_put(state); 1004 1005 drm_modeset_drop_locks(&ctx); 1006 drm_modeset_acquire_fini(&ctx); 1007 } 1008 1009 int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) 1010 { 1011 struct intel_display *display = to_intel_display(crtc_state); 1012 int min_cdclk = 0; 1013 1014 if (!crtc_state->has_audio) 1015 return 0; 1016 1017 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 1018 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 1019 * there may be audio corruption or screen corruption." This cdclk 1020 * restriction for GLK is 316.8 MHz. 1021 */ 1022 if (intel_crtc_has_dp_encoder(crtc_state) && 1023 crtc_state->port_clock >= 540000 && 1024 crtc_state->lane_count == 4) { 1025 if (DISPLAY_VER(display) == 10) { 1026 /* Display WA #1145: glk */ 1027 min_cdclk = max(min_cdclk, 316800); 1028 } else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) { 1029 /* Display WA #1144: skl,bxt */ 1030 min_cdclk = max(min_cdclk, 432000); 1031 } 1032 } 1033 1034 /* 1035 * According to BSpec, "The CD clock frequency must be at least twice 1036 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 1037 */ 1038 if (DISPLAY_VER(display) >= 9) 1039 min_cdclk = max(min_cdclk, 2 * 96000); 1040 1041 /* 1042 * "For DP audio configuration, cdclk frequency shall be set to 1043 * meet the following requirements: 1044 * DP Link Frequency(MHz) | Cdclk frequency(MHz) 1045 * 270 | 320 or higher 1046 * 162 | 200 or higher" 1047 */ 1048 if ((display->platform.valleyview || display->platform.cherryview) && 1049 intel_crtc_has_dp_encoder(crtc_state)) 1050 min_cdclk = max(min_cdclk, crtc_state->port_clock); 1051 1052 return min_cdclk; 1053 } 1054 1055 static unsigned long intel_audio_component_get_power(struct device *kdev) 1056 { 1057 struct intel_display *display = to_intel_display(kdev); 1058 struct ref_tracker *wakeref; 1059 1060 /* Catch potential impedance mismatches before they occur! */ 1061 BUILD_BUG_ON(sizeof(wakeref) > sizeof(unsigned long)); 1062 1063 wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK); 1064 1065 if (display->audio.power_refcount++ == 0) { 1066 if (DISPLAY_VER(display) >= 9) { 1067 intel_de_write(display, AUD_FREQ_CNTRL, 1068 display->audio.freq_cntrl); 1069 drm_dbg_kms(display->drm, 1070 "restored AUD_FREQ_CNTRL to 0x%x\n", 1071 display->audio.freq_cntrl); 1072 } 1073 1074 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 1075 if (display->platform.geminilake) 1076 glk_force_audio_cdclk(display, true); 1077 1078 if (DISPLAY_VER(display) >= 10) 1079 intel_de_rmw(display, AUD_PIN_BUF_CTL, 1080 0, AUD_PIN_BUF_ENABLE); 1081 } 1082 1083 return (unsigned long)wakeref; 1084 } 1085 1086 static void intel_audio_component_put_power(struct device *kdev, 1087 unsigned long cookie) 1088 { 1089 struct intel_display *display = to_intel_display(kdev); 1090 struct ref_tracker *wakeref = (struct ref_tracker *)cookie; 1091 1092 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1093 if (--display->audio.power_refcount == 0) 1094 if (display->platform.geminilake) 1095 glk_force_audio_cdclk(display, false); 1096 1097 intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref); 1098 } 1099 1100 static void intel_audio_component_codec_wake_override(struct device *kdev, 1101 bool enable) 1102 { 1103 struct intel_display *display = to_intel_display(kdev); 1104 unsigned long cookie; 1105 1106 if (DISPLAY_VER(display) < 9) 1107 return; 1108 1109 cookie = intel_audio_component_get_power(kdev); 1110 1111 /* 1112 * Enable/disable generating the codec wake signal, overriding the 1113 * internal logic to generate the codec wake to controller. 1114 */ 1115 intel_de_rmw(display, HSW_AUD_CHICKENBIT, 1116 SKL_AUD_CODEC_WAKE_SIGNAL, 0); 1117 usleep_range(1000, 1500); 1118 1119 if (enable) { 1120 intel_de_rmw(display, HSW_AUD_CHICKENBIT, 1121 0, SKL_AUD_CODEC_WAKE_SIGNAL); 1122 usleep_range(1000, 1500); 1123 } 1124 1125 intel_audio_component_put_power(kdev, cookie); 1126 } 1127 1128 /* Get CDCLK in kHz */ 1129 static int intel_audio_component_get_cdclk_freq(struct device *kdev) 1130 { 1131 struct intel_display *display = to_intel_display(kdev); 1132 1133 if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display))) 1134 return -ENODEV; 1135 1136 return display->cdclk.hw.cdclk; 1137 } 1138 1139 /* 1140 * Get the intel audio state for a given (port, cpu_transcoder). 1141 * 1142 * Streams are addressed either by a real cpu_transcoder (DP MST and UHBR SST, 1143 * i.e. entries whose stored needs_cpu_transcoder_id is true) or by port alone 1144 * (legacy SST). Both the signalling side (pin_eld_notify()) and the lookup 1145 * side use the same predicate, so the two are symmetric. 1146 * 1147 * cpu_transcoder >= 0 & needs_cpu_transcoder_id: return audio.state[cpu_transcoder] 1148 * when the port matches. 1149 * cpu_transcoder < 0 & !needs_cpu_transcoder_id: return the first port-matching 1150 * entry. 1151 * cpu_transcoder = 0 & !needs_cpu_transcoder_id: falls to the port-only 1152 * loop so the first device entry of a legacy SST port is still found. 1153 */ 1154 static struct intel_audio_state *find_audio_state(struct intel_display *display, 1155 int port, int cpu_transcoder) 1156 { 1157 /* MST, or UHBR SST. */ 1158 if (cpu_transcoder >= 0) { 1159 struct intel_audio_state *audio_state; 1160 struct intel_encoder *encoder; 1161 1162 if (drm_WARN_ON(display->drm, 1163 cpu_transcoder >= ARRAY_SIZE(display->audio.state))) 1164 return NULL; 1165 1166 audio_state = &display->audio.state[cpu_transcoder]; 1167 encoder = audio_state->encoder; 1168 1169 if (encoder && encoder->port == port && 1170 audio_state->needs_cpu_transcoder_id) 1171 return audio_state; 1172 } 1173 1174 /* Legacy SST. */ 1175 if (cpu_transcoder > 0) 1176 return NULL; 1177 1178 for_each_cpu_transcoder(display, cpu_transcoder) { 1179 struct intel_audio_state *audio_state; 1180 struct intel_encoder *encoder; 1181 1182 audio_state = &display->audio.state[cpu_transcoder]; 1183 encoder = audio_state->encoder; 1184 1185 if (encoder && encoder->port == port && 1186 !audio_state->needs_cpu_transcoder_id) 1187 return audio_state; 1188 } 1189 1190 return NULL; 1191 } 1192 1193 static int intel_audio_component_sync_audio_rate(struct device *kdev, int port, 1194 int cpu_transcoder, int rate) 1195 { 1196 struct intel_display *display = to_intel_display(kdev); 1197 struct i915_audio_component *acomp = display->audio.component; 1198 const struct intel_audio_state *audio_state; 1199 struct intel_encoder *encoder; 1200 struct intel_crtc *crtc; 1201 unsigned long cookie; 1202 int err = 0; 1203 1204 if (!HAS_DDI(display)) 1205 return 0; 1206 1207 cookie = intel_audio_component_get_power(kdev); 1208 mutex_lock(&display->audio.mutex); 1209 1210 audio_state = find_audio_state(display, port, cpu_transcoder); 1211 if (!audio_state) { 1212 drm_dbg_kms(display->drm, "Not valid for port %c\n", 1213 port_name(port)); 1214 err = -ENODEV; 1215 goto unlock; 1216 } 1217 1218 encoder = audio_state->encoder; 1219 1220 /* FIXME stop using the legacy crtc pointer */ 1221 crtc = to_intel_crtc(encoder->base.crtc); 1222 1223 /* port must be valid now, otherwise the cpu_transcoder will be invalid */ 1224 acomp->aud_sample_rate[port] = rate; 1225 1226 /* FIXME get rid of the crtc->config stuff */ 1227 hsw_audio_config_update(encoder, crtc->config); 1228 1229 unlock: 1230 mutex_unlock(&display->audio.mutex); 1231 intel_audio_component_put_power(kdev, cookie); 1232 return err; 1233 } 1234 1235 static int intel_audio_component_get_eld(struct device *kdev, int port, 1236 int cpu_transcoder, bool *enabled, 1237 unsigned char *buf, int max_bytes) 1238 { 1239 struct intel_display *display = to_intel_display(kdev); 1240 const struct intel_audio_state *audio_state; 1241 int ret = 0; 1242 1243 mutex_lock(&display->audio.mutex); 1244 1245 audio_state = find_audio_state(display, port, cpu_transcoder); 1246 if (!audio_state) { 1247 drm_dbg_kms(display->drm, "Not valid for port %c\n", 1248 port_name(port)); 1249 mutex_unlock(&display->audio.mutex); 1250 return -EINVAL; 1251 } 1252 1253 *enabled = audio_state->encoder != NULL; 1254 if (*enabled) { 1255 const u8 *eld = audio_state->eld; 1256 1257 ret = drm_eld_size(eld); 1258 memcpy(buf, eld, min(max_bytes, ret)); 1259 } 1260 1261 mutex_unlock(&display->audio.mutex); 1262 return ret; 1263 } 1264 1265 static const struct drm_audio_component_ops intel_audio_component_ops = { 1266 .owner = THIS_MODULE, 1267 .get_power = intel_audio_component_get_power, 1268 .put_power = intel_audio_component_put_power, 1269 .codec_wake_override = intel_audio_component_codec_wake_override, 1270 .get_cdclk_freq = intel_audio_component_get_cdclk_freq, 1271 .sync_audio_rate = intel_audio_component_sync_audio_rate, 1272 .get_eld = intel_audio_component_get_eld, 1273 }; 1274 1275 static int intel_audio_component_bind(struct device *drv_kdev, 1276 struct device *hda_kdev, void *data) 1277 { 1278 struct intel_display *display = to_intel_display(drv_kdev); 1279 struct i915_audio_component *acomp = data; 1280 int i; 1281 1282 if (drm_WARN_ON(display->drm, acomp->base.ops || acomp->base.dev)) 1283 return -EEXIST; 1284 1285 if (drm_WARN_ON(display->drm, 1286 !device_link_add(hda_kdev, drv_kdev, 1287 DL_FLAG_STATELESS))) 1288 return -ENOMEM; 1289 1290 drm_modeset_lock_all(display->drm); 1291 acomp->base.ops = &intel_audio_component_ops; 1292 acomp->base.dev = drv_kdev; 1293 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 1294 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 1295 acomp->aud_sample_rate[i] = 0; 1296 display->audio.component = acomp; 1297 drm_modeset_unlock_all(display->drm); 1298 1299 return 0; 1300 } 1301 1302 static void intel_audio_component_unbind(struct device *drv_kdev, 1303 struct device *hda_kdev, void *data) 1304 { 1305 struct intel_display *display = to_intel_display(drv_kdev); 1306 struct i915_audio_component *acomp = data; 1307 1308 drm_modeset_lock_all(display->drm); 1309 acomp->base.ops = NULL; 1310 acomp->base.dev = NULL; 1311 display->audio.component = NULL; 1312 drm_modeset_unlock_all(display->drm); 1313 1314 device_link_remove(hda_kdev, drv_kdev); 1315 1316 if (display->audio.power_refcount) 1317 drm_err(display->drm, 1318 "audio power refcount %d after unbind\n", 1319 display->audio.power_refcount); 1320 } 1321 1322 static const struct component_ops intel_audio_component_bind_ops = { 1323 .bind = intel_audio_component_bind, 1324 .unbind = intel_audio_component_unbind, 1325 }; 1326 1327 #define AUD_FREQ_TMODE_SHIFT 14 1328 #define AUD_FREQ_4T 0 1329 #define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT) 1330 #define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11) 1331 #define AUD_FREQ_BCLK_96M BIT(4) 1332 1333 #define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M) 1334 #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) 1335 1336 /** 1337 * intel_audio_component_init - initialize and register the audio component 1338 * @display: display device 1339 * 1340 * This will register with the component framework a child component which 1341 * will bind dynamically to the snd_hda_intel driver's corresponding master 1342 * component when the latter is registered. During binding the child 1343 * initializes an instance of struct i915_audio_component which it receives 1344 * from the master. The master can then start to use the interface defined by 1345 * this struct. Each side can break the binding at any point by deregistering 1346 * its own component after which each side's component unbind callback is 1347 * called. 1348 * 1349 * We ignore any error during registration and continue with reduced 1350 * functionality (i.e. without HDMI audio). 1351 */ 1352 static void intel_audio_component_init(struct intel_display *display) 1353 { 1354 u32 aud_freq, aud_freq_init; 1355 1356 if (DISPLAY_VER(display) >= 9) { 1357 aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL); 1358 1359 if (DISPLAY_VER(display) >= 12) 1360 aud_freq = AUD_FREQ_GEN12; 1361 else 1362 aud_freq = aud_freq_init; 1363 1364 /* use BIOS provided value for TGL and RKL unless it is a known bad value */ 1365 if ((display->platform.tigerlake || display->platform.rocketlake) && 1366 aud_freq_init != AUD_FREQ_TGL_BROKEN) 1367 aud_freq = aud_freq_init; 1368 1369 drm_dbg_kms(display->drm, 1370 "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", 1371 aud_freq, aud_freq_init); 1372 1373 display->audio.freq_cntrl = aud_freq; 1374 } 1375 1376 /* init with current cdclk */ 1377 intel_audio_cdclk_change_post(display); 1378 } 1379 1380 static void intel_audio_component_register(struct intel_display *display) 1381 { 1382 int ret; 1383 1384 ret = component_add_typed(display->drm->dev, 1385 &intel_audio_component_bind_ops, 1386 I915_COMPONENT_AUDIO); 1387 if (ret < 0) { 1388 drm_err(display->drm, 1389 "failed to add audio component (%d)\n", ret); 1390 /* continue with reduced functionality */ 1391 return; 1392 } 1393 1394 display->audio.component_registered = true; 1395 } 1396 1397 /** 1398 * intel_audio_component_cleanup - deregister the audio component 1399 * @display: display device 1400 * 1401 * Deregisters the audio component, breaking any existing binding to the 1402 * corresponding snd_hda_intel driver's master component. 1403 */ 1404 static void intel_audio_component_cleanup(struct intel_display *display) 1405 { 1406 if (!display->audio.component_registered) 1407 return; 1408 1409 component_del(display->drm->dev, &intel_audio_component_bind_ops); 1410 display->audio.component_registered = false; 1411 } 1412 1413 /** 1414 * intel_audio_init() - Initialize the audio driver either using 1415 * component framework or using lpe audio bridge 1416 * @display: display device 1417 * 1418 */ 1419 void intel_audio_init(struct intel_display *display) 1420 { 1421 if (intel_lpe_audio_init(display) < 0) 1422 intel_audio_component_init(display); 1423 } 1424 1425 void intel_audio_register(struct intel_display *display) 1426 { 1427 if (!display->audio.lpe.platdev) 1428 intel_audio_component_register(display); 1429 } 1430 1431 /** 1432 * intel_audio_deinit() - deinitialize the audio driver 1433 * @display: display device 1434 */ 1435 void intel_audio_deinit(struct intel_display *display) 1436 { 1437 if (display->audio.lpe.platdev) 1438 intel_lpe_audio_teardown(display); 1439 else 1440 intel_audio_component_cleanup(display); 1441 } 1442