xref: /linux/drivers/gpu/drm/i915/display/intel_atomic.c (revision 34f7c6e7d4396090692a09789db231e12cb4762b)
1 /*
2  * Copyright © 2015 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 /**
25  * DOC: atomic modeset support
26  *
27  * The functions here implement the state management and hardware programming
28  * dispatch required by the atomic modeset infrastructure.
29  * See intel_atomic_plane.c for the plane-specific atomic functionality.
30  */
31 
32 #include <drm/drm_atomic.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_plane_helper.h>
36 
37 #include "i915_drv.h"
38 #include "i915_reg.h"
39 #include "intel_atomic.h"
40 #include "intel_cdclk.h"
41 #include "intel_display_types.h"
42 #include "intel_global_state.h"
43 #include "intel_hdcp.h"
44 #include "intel_psr.h"
45 #include "skl_universal_plane.h"
46 
47 /**
48  * intel_digital_connector_atomic_get_property - hook for connector->atomic_get_property.
49  * @connector: Connector to get the property for.
50  * @state: Connector state to retrieve the property from.
51  * @property: Property to retrieve.
52  * @val: Return value for the property.
53  *
54  * Returns the atomic property value for a digital connector.
55  */
56 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
57 						const struct drm_connector_state *state,
58 						struct drm_property *property,
59 						u64 *val)
60 {
61 	struct drm_device *dev = connector->dev;
62 	struct drm_i915_private *dev_priv = to_i915(dev);
63 	struct intel_digital_connector_state *intel_conn_state =
64 		to_intel_digital_connector_state(state);
65 
66 	if (property == dev_priv->force_audio_property)
67 		*val = intel_conn_state->force_audio;
68 	else if (property == dev_priv->broadcast_rgb_property)
69 		*val = intel_conn_state->broadcast_rgb;
70 	else {
71 		drm_dbg_atomic(&dev_priv->drm,
72 			       "Unknown property [PROP:%d:%s]\n",
73 			       property->base.id, property->name);
74 		return -EINVAL;
75 	}
76 
77 	return 0;
78 }
79 
80 /**
81  * intel_digital_connector_atomic_set_property - hook for connector->atomic_set_property.
82  * @connector: Connector to set the property for.
83  * @state: Connector state to set the property on.
84  * @property: Property to set.
85  * @val: New value for the property.
86  *
87  * Sets the atomic property value for a digital connector.
88  */
89 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
90 						struct drm_connector_state *state,
91 						struct drm_property *property,
92 						u64 val)
93 {
94 	struct drm_device *dev = connector->dev;
95 	struct drm_i915_private *dev_priv = to_i915(dev);
96 	struct intel_digital_connector_state *intel_conn_state =
97 		to_intel_digital_connector_state(state);
98 
99 	if (property == dev_priv->force_audio_property) {
100 		intel_conn_state->force_audio = val;
101 		return 0;
102 	}
103 
104 	if (property == dev_priv->broadcast_rgb_property) {
105 		intel_conn_state->broadcast_rgb = val;
106 		return 0;
107 	}
108 
109 	drm_dbg_atomic(&dev_priv->drm, "Unknown property [PROP:%d:%s]\n",
110 		       property->base.id, property->name);
111 	return -EINVAL;
112 }
113 
114 int intel_digital_connector_atomic_check(struct drm_connector *conn,
115 					 struct drm_atomic_state *state)
116 {
117 	struct drm_connector_state *new_state =
118 		drm_atomic_get_new_connector_state(state, conn);
119 	struct intel_digital_connector_state *new_conn_state =
120 		to_intel_digital_connector_state(new_state);
121 	struct drm_connector_state *old_state =
122 		drm_atomic_get_old_connector_state(state, conn);
123 	struct intel_digital_connector_state *old_conn_state =
124 		to_intel_digital_connector_state(old_state);
125 	struct drm_crtc_state *crtc_state;
126 
127 	intel_hdcp_atomic_check(conn, old_state, new_state);
128 
129 	if (!new_state->crtc)
130 		return 0;
131 
132 	crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
133 
134 	/*
135 	 * These properties are handled by fastset, and might not end
136 	 * up in a modeset.
137 	 */
138 	if (new_conn_state->force_audio != old_conn_state->force_audio ||
139 	    new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
140 	    new_conn_state->base.colorspace != old_conn_state->base.colorspace ||
141 	    new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||
142 	    new_conn_state->base.content_type != old_conn_state->base.content_type ||
143 	    new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode ||
144 	    new_conn_state->base.privacy_screen_sw_state != old_conn_state->base.privacy_screen_sw_state ||
145 	    !drm_connector_atomic_hdr_metadata_equal(old_state, new_state))
146 		crtc_state->mode_changed = true;
147 
148 	return 0;
149 }
150 
151 /**
152  * intel_digital_connector_duplicate_state - duplicate connector state
153  * @connector: digital connector
154  *
155  * Allocates and returns a copy of the connector state (both common and
156  * digital connector specific) for the specified connector.
157  *
158  * Returns: The newly allocated connector state, or NULL on failure.
159  */
160 struct drm_connector_state *
161 intel_digital_connector_duplicate_state(struct drm_connector *connector)
162 {
163 	struct intel_digital_connector_state *state;
164 
165 	state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
166 	if (!state)
167 		return NULL;
168 
169 	__drm_atomic_helper_connector_duplicate_state(connector, &state->base);
170 	return &state->base;
171 }
172 
173 /**
174  * intel_connector_needs_modeset - check if connector needs a modeset
175  * @state: the atomic state corresponding to this modeset
176  * @connector: the connector
177  */
178 bool
179 intel_connector_needs_modeset(struct intel_atomic_state *state,
180 			      struct drm_connector *connector)
181 {
182 	const struct drm_connector_state *old_conn_state, *new_conn_state;
183 
184 	old_conn_state = drm_atomic_get_old_connector_state(&state->base, connector);
185 	new_conn_state = drm_atomic_get_new_connector_state(&state->base, connector);
186 
187 	return old_conn_state->crtc != new_conn_state->crtc ||
188 	       (new_conn_state->crtc &&
189 		drm_atomic_crtc_needs_modeset(drm_atomic_get_new_crtc_state(&state->base,
190 									    new_conn_state->crtc)));
191 }
192 
193 /**
194  * intel_any_crtc_needs_modeset - check if any CRTC needs a modeset
195  * @state: the atomic state corresponding to this modeset
196  *
197  * Returns true if any CRTC in @state needs a modeset.
198  */
199 bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state)
200 {
201 	struct intel_crtc *crtc;
202 	struct intel_crtc_state *crtc_state;
203 	int i;
204 
205 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
206 		if (intel_crtc_needs_modeset(crtc_state))
207 			return true;
208 	}
209 
210 	return false;
211 }
212 
213 struct intel_digital_connector_state *
214 intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
215 					 struct intel_connector *connector)
216 {
217 	struct drm_connector_state *conn_state;
218 
219 	conn_state = drm_atomic_get_connector_state(&state->base,
220 						    &connector->base);
221 	if (IS_ERR(conn_state))
222 		return ERR_CAST(conn_state);
223 
224 	return to_intel_digital_connector_state(conn_state);
225 }
226 
227 /**
228  * intel_crtc_duplicate_state - duplicate crtc state
229  * @crtc: drm crtc
230  *
231  * Allocates and returns a copy of the crtc state (both common and
232  * Intel-specific) for the specified crtc.
233  *
234  * Returns: The newly allocated crtc state, or NULL on failure.
235  */
236 struct drm_crtc_state *
237 intel_crtc_duplicate_state(struct drm_crtc *crtc)
238 {
239 	const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
240 	struct intel_crtc_state *crtc_state;
241 
242 	crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
243 	if (!crtc_state)
244 		return NULL;
245 
246 	__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
247 
248 	/* copy color blobs */
249 	if (crtc_state->hw.degamma_lut)
250 		drm_property_blob_get(crtc_state->hw.degamma_lut);
251 	if (crtc_state->hw.ctm)
252 		drm_property_blob_get(crtc_state->hw.ctm);
253 	if (crtc_state->hw.gamma_lut)
254 		drm_property_blob_get(crtc_state->hw.gamma_lut);
255 
256 	crtc_state->update_pipe = false;
257 	crtc_state->disable_lp_wm = false;
258 	crtc_state->disable_cxsr = false;
259 	crtc_state->update_wm_pre = false;
260 	crtc_state->update_wm_post = false;
261 	crtc_state->fifo_changed = false;
262 	crtc_state->preload_luts = false;
263 	crtc_state->inherited = false;
264 	crtc_state->wm.need_postvbl_update = false;
265 	crtc_state->do_async_flip = false;
266 	crtc_state->fb_bits = 0;
267 	crtc_state->update_planes = 0;
268 	crtc_state->dsb = NULL;
269 
270 	return &crtc_state->uapi;
271 }
272 
273 static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
274 {
275 	drm_property_blob_put(crtc_state->hw.degamma_lut);
276 	drm_property_blob_put(crtc_state->hw.gamma_lut);
277 	drm_property_blob_put(crtc_state->hw.ctm);
278 }
279 
280 void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
281 {
282 	intel_crtc_put_color_blobs(crtc_state);
283 }
284 
285 /**
286  * intel_crtc_destroy_state - destroy crtc state
287  * @crtc: drm crtc
288  * @state: the state to destroy
289  *
290  * Destroys the crtc state (both common and Intel-specific) for the
291  * specified crtc.
292  */
293 void
294 intel_crtc_destroy_state(struct drm_crtc *crtc,
295 			 struct drm_crtc_state *state)
296 {
297 	struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
298 
299 	drm_WARN_ON(crtc->dev, crtc_state->dsb);
300 
301 	__drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
302 	intel_crtc_free_hw_state(crtc_state);
303 	kfree(crtc_state);
304 }
305 
306 static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
307 				      int num_scalers_need, struct intel_crtc *intel_crtc,
308 				      const char *name, int idx,
309 				      struct intel_plane_state *plane_state,
310 				      int *scaler_id)
311 {
312 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
313 	int j;
314 	u32 mode;
315 
316 	if (*scaler_id < 0) {
317 		/* find a free scaler */
318 		for (j = 0; j < intel_crtc->num_scalers; j++) {
319 			if (scaler_state->scalers[j].in_use)
320 				continue;
321 
322 			*scaler_id = j;
323 			scaler_state->scalers[*scaler_id].in_use = 1;
324 			break;
325 		}
326 	}
327 
328 	if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
329 		     "Cannot find scaler for %s:%d\n", name, idx))
330 		return;
331 
332 	/* set scaler mode */
333 	if (plane_state && plane_state->hw.fb &&
334 	    plane_state->hw.fb->format->is_yuv &&
335 	    plane_state->hw.fb->format->num_planes > 1) {
336 		struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
337 		if (DISPLAY_VER(dev_priv) == 9) {
338 			mode = SKL_PS_SCALER_MODE_NV12;
339 		} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
340 			/*
341 			 * On gen11+'s HDR planes we only use the scaler for
342 			 * scaling. They have a dedicated chroma upsampler, so
343 			 * we don't need the scaler to upsample the UV plane.
344 			 */
345 			mode = PS_SCALER_MODE_NORMAL;
346 		} else {
347 			struct intel_plane *linked =
348 				plane_state->planar_linked_plane;
349 
350 			mode = PS_SCALER_MODE_PLANAR;
351 
352 			if (linked)
353 				mode |= PS_PLANE_Y_SEL(linked->id);
354 		}
355 	} else if (DISPLAY_VER(dev_priv) >= 10) {
356 		mode = PS_SCALER_MODE_NORMAL;
357 	} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
358 		/*
359 		 * when only 1 scaler is in use on a pipe with 2 scalers
360 		 * scaler 0 operates in high quality (HQ) mode.
361 		 * In this case use scaler 0 to take advantage of HQ mode
362 		 */
363 		scaler_state->scalers[*scaler_id].in_use = 0;
364 		*scaler_id = 0;
365 		scaler_state->scalers[0].in_use = 1;
366 		mode = SKL_PS_SCALER_MODE_HQ;
367 	} else {
368 		mode = SKL_PS_SCALER_MODE_DYN;
369 	}
370 
371 	drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
372 		    intel_crtc->pipe, *scaler_id, name, idx);
373 	scaler_state->scalers[*scaler_id].mode = mode;
374 }
375 
376 /**
377  * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
378  * @dev_priv: i915 device
379  * @intel_crtc: intel crtc
380  * @crtc_state: incoming crtc_state to validate and setup scalers
381  *
382  * This function sets up scalers based on staged scaling requests for
383  * a @crtc and its planes. It is called from crtc level check path. If request
384  * is a supportable request, it attaches scalers to requested planes and crtc.
385  *
386  * This function takes into account the current scaler(s) in use by any planes
387  * not being part of this atomic state
388  *
389  *  Returns:
390  *         0 - scalers were setup succesfully
391  *         error code - otherwise
392  */
393 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
394 			       struct intel_crtc *intel_crtc,
395 			       struct intel_crtc_state *crtc_state)
396 {
397 	struct drm_plane *plane = NULL;
398 	struct intel_plane *intel_plane;
399 	struct intel_plane_state *plane_state = NULL;
400 	struct intel_crtc_scaler_state *scaler_state =
401 		&crtc_state->scaler_state;
402 	struct drm_atomic_state *drm_state = crtc_state->uapi.state;
403 	struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
404 	int num_scalers_need;
405 	int i;
406 
407 	num_scalers_need = hweight32(scaler_state->scaler_users);
408 
409 	/*
410 	 * High level flow:
411 	 * - staged scaler requests are already in scaler_state->scaler_users
412 	 * - check whether staged scaling requests can be supported
413 	 * - add planes using scalers that aren't in current transaction
414 	 * - assign scalers to requested users
415 	 * - as part of plane commit, scalers will be committed
416 	 *   (i.e., either attached or detached) to respective planes in hw
417 	 * - as part of crtc_commit, scaler will be either attached or detached
418 	 *   to crtc in hw
419 	 */
420 
421 	/* fail if required scalers > available scalers */
422 	if (num_scalers_need > intel_crtc->num_scalers){
423 		drm_dbg_kms(&dev_priv->drm,
424 			    "Too many scaling requests %d > %d\n",
425 			    num_scalers_need, intel_crtc->num_scalers);
426 		return -EINVAL;
427 	}
428 
429 	/* walkthrough scaler_users bits and start assigning scalers */
430 	for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
431 		int *scaler_id;
432 		const char *name;
433 		int idx;
434 
435 		/* skip if scaler not required */
436 		if (!(scaler_state->scaler_users & (1 << i)))
437 			continue;
438 
439 		if (i == SKL_CRTC_INDEX) {
440 			name = "CRTC";
441 			idx = intel_crtc->base.base.id;
442 
443 			/* panel fitter case: assign as a crtc scaler */
444 			scaler_id = &scaler_state->scaler_id;
445 		} else {
446 			name = "PLANE";
447 
448 			/* plane scaler case: assign as a plane scaler */
449 			/* find the plane that set the bit as scaler_user */
450 			plane = drm_state->planes[i].ptr;
451 
452 			/*
453 			 * to enable/disable hq mode, add planes that are using scaler
454 			 * into this transaction
455 			 */
456 			if (!plane) {
457 				struct drm_plane_state *state;
458 
459 				/*
460 				 * GLK+ scalers don't have a HQ mode so it
461 				 * isn't necessary to change between HQ and dyn mode
462 				 * on those platforms.
463 				 */
464 				if (DISPLAY_VER(dev_priv) >= 10)
465 					continue;
466 
467 				plane = drm_plane_from_index(&dev_priv->drm, i);
468 				state = drm_atomic_get_plane_state(drm_state, plane);
469 				if (IS_ERR(state)) {
470 					drm_dbg_kms(&dev_priv->drm,
471 						    "Failed to add [PLANE:%d] to drm_state\n",
472 						    plane->base.id);
473 					return PTR_ERR(state);
474 				}
475 			}
476 
477 			intel_plane = to_intel_plane(plane);
478 			idx = plane->base.id;
479 
480 			/* plane on different crtc cannot be a scaler user of this crtc */
481 			if (drm_WARN_ON(&dev_priv->drm,
482 					intel_plane->pipe != intel_crtc->pipe))
483 				continue;
484 
485 			plane_state = intel_atomic_get_new_plane_state(intel_state,
486 								       intel_plane);
487 			scaler_id = &plane_state->scaler_id;
488 		}
489 
490 		intel_atomic_setup_scaler(scaler_state, num_scalers_need,
491 					  intel_crtc, name, idx,
492 					  plane_state, scaler_id);
493 	}
494 
495 	return 0;
496 }
497 
498 struct drm_atomic_state *
499 intel_atomic_state_alloc(struct drm_device *dev)
500 {
501 	struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
502 
503 	if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
504 		kfree(state);
505 		return NULL;
506 	}
507 
508 	return &state->base;
509 }
510 
511 void intel_atomic_state_free(struct drm_atomic_state *_state)
512 {
513 	struct intel_atomic_state *state = to_intel_atomic_state(_state);
514 
515 	drm_atomic_state_default_release(&state->base);
516 	kfree(state->global_objs);
517 
518 	i915_sw_fence_fini(&state->commit_ready);
519 
520 	kfree(state);
521 }
522 
523 void intel_atomic_state_clear(struct drm_atomic_state *s)
524 {
525 	struct intel_atomic_state *state = to_intel_atomic_state(s);
526 
527 	drm_atomic_state_default_clear(&state->base);
528 	intel_atomic_clear_global_state(state);
529 
530 	state->dpll_set = state->modeset = false;
531 }
532 
533 struct intel_crtc_state *
534 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
535 			    struct intel_crtc *crtc)
536 {
537 	struct drm_crtc_state *crtc_state;
538 	crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
539 	if (IS_ERR(crtc_state))
540 		return ERR_CAST(crtc_state);
541 
542 	return to_intel_crtc_state(crtc_state);
543 }
544