1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2024, Intel Corporation. 4 */ 5 6 #include <linux/debugfs.h> 7 8 #include <drm/drm_print.h> 9 10 #include "intel_alpm.h" 11 #include "intel_crtc.h" 12 #include "intel_de.h" 13 #include "intel_display_types.h" 14 #include "intel_dp.h" 15 #include "intel_dp_aux.h" 16 #include "intel_psr.h" 17 #include "intel_psr_regs.h" 18 19 #define SILENCE_PERIOD_MIN_TIME 80 20 #define SILENCE_PERIOD_MAX_TIME 180 21 #define SILENCE_PERIOD_TIME (SILENCE_PERIOD_MIN_TIME + \ 22 (SILENCE_PERIOD_MAX_TIME - \ 23 SILENCE_PERIOD_MIN_TIME) / 2) 24 25 #define LFPS_CYCLE_COUNT 10 26 27 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp) 28 { 29 return intel_dp->alpm_dpcd & DP_ALPM_CAP; 30 } 31 32 bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp) 33 { 34 return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP; 35 } 36 37 bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp, 38 const struct intel_crtc_state *crtc_state) 39 { 40 return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) || 41 (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp)); 42 } 43 44 void intel_alpm_init(struct intel_dp *intel_dp) 45 { 46 u8 dpcd; 47 48 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0) 49 return; 50 51 intel_dp->alpm_dpcd = dpcd; 52 mutex_init(&intel_dp->alpm.lock); 53 } 54 55 static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state) 56 { 57 return SILENCE_PERIOD_TIME * intel_dp_link_symbol_clock(crtc_state->port_clock) / 58 1000 / 1000; 59 } 60 61 static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state, 62 int *min, int *max) 63 { 64 if (crtc_state->port_clock < 540000) { 65 *min = 65 * LFPS_CYCLE_COUNT; 66 *max = 75 * LFPS_CYCLE_COUNT; 67 } else { 68 *min = 140; 69 *max = 800; 70 } 71 } 72 73 static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state) 74 { 75 int tlfps_cycle_min, tlfps_cycle_max; 76 77 get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min, 78 &tlfps_cycle_max); 79 80 return tlfps_cycle_min + (tlfps_cycle_max - tlfps_cycle_min) / 2; 81 } 82 83 static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state) 84 { 85 return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 / 86 1000 / (2 * LFPS_CYCLE_COUNT); 87 } 88 89 /* 90 * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+ 91 * tSilence, Max+ tPHY Establishment + tCDS) / tline) 92 * For the "PHY P2 to P0" latency see the PHY Power Control page 93 * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965 94 * : 12 us 95 * The tLFPS_Period, Max term is 800ns 96 * The tSilence, Max term is 180ns 97 * The tPHY Establishment (a.k.a. t1) term is 50us 98 * The tCDS term is 1 or 2 times t2 99 * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK 100 * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1) 101 * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and 102 * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start 103 * within the CDS period complete within the CDS period regardless of 104 * entry into the period 105 * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) ) 106 * TPS4 Length = 252 Symbols 107 */ 108 static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state) 109 { 110 int tphy2_p2_to_p0 = 12 * 1000; 111 int t1 = 50 * 1000; 112 int tps4 = 252; 113 /* port_clock is link rate in 10kbit/s units */ 114 int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock; 115 int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1; 116 int t2 = num_ml_phy_lock * tml_phy_lock; 117 int tcds = 1 * t2; 118 119 return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) + 120 SILENCE_PERIOD_TIME + t1 + tcds, 1000); 121 } 122 123 static int 124 _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, 125 struct intel_crtc_state *crtc_state) 126 { 127 struct intel_display *display = to_intel_display(intel_dp); 128 int aux_less_wake_time, aux_less_wake_lines, silence_period, 129 lfps_half_cycle; 130 131 aux_less_wake_time = 132 _lnl_compute_aux_less_wake_time(crtc_state); 133 aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 134 aux_less_wake_time); 135 silence_period = get_silence_period_symbols(crtc_state); 136 137 lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state); 138 139 if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK || 140 silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK || 141 lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK) 142 return false; 143 144 if (display->params.psr_safest_params) 145 aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK; 146 147 crtc_state->alpm_state.aux_less_wake_lines = aux_less_wake_lines; 148 crtc_state->alpm_state.silence_period_sym_clocks = silence_period; 149 crtc_state->alpm_state.lfps_half_cycle_num_of_syms = lfps_half_cycle; 150 151 return true; 152 } 153 154 static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, 155 struct intel_crtc_state *crtc_state) 156 { 157 struct intel_display *display = to_intel_display(intel_dp); 158 int check_entry_lines; 159 160 if (DISPLAY_VER(display) < 20) 161 return true; 162 163 /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */ 164 check_entry_lines = 2 + 165 intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5); 166 167 if (check_entry_lines > 15) 168 return false; 169 170 if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state)) 171 return false; 172 173 if (display->params.psr_safest_params) 174 check_entry_lines = 15; 175 176 crtc_state->alpm_state.check_entry_lines = check_entry_lines; 177 178 return true; 179 } 180 181 /* 182 * IO wake time for DISPLAY_VER < 12 is not directly mentioned in Bspec. There 183 * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are 184 * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us. 185 */ 186 static int skl_io_buffer_wake_time(void) 187 { 188 return 18; 189 } 190 191 static int tgl_io_buffer_wake_time(void) 192 { 193 return 10; 194 } 195 196 static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state) 197 { 198 struct intel_display *display = to_intel_display(crtc_state); 199 200 if (DISPLAY_VER(display) >= 12) 201 return tgl_io_buffer_wake_time(); 202 else 203 return skl_io_buffer_wake_time(); 204 } 205 206 bool intel_alpm_compute_params(struct intel_dp *intel_dp, 207 struct intel_crtc_state *crtc_state) 208 { 209 struct intel_display *display = to_intel_display(intel_dp); 210 int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time; 211 int tfw_exit_latency = 20; /* eDP spec */ 212 int phy_wake = 4; /* eDP spec */ 213 int preamble = 8; /* eDP spec */ 214 int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble; 215 u8 max_wake_lines; 216 217 io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) + 218 preamble + phy_wake + tfw_exit_latency; 219 fast_wake_time = precharge + preamble + phy_wake + 220 tfw_exit_latency; 221 222 if (DISPLAY_VER(display) >= 20) 223 max_wake_lines = 68; 224 else if (DISPLAY_VER(display) >= 12) 225 max_wake_lines = 12; 226 else 227 max_wake_lines = 8; 228 229 io_wake_lines = intel_usecs_to_scanlines( 230 &crtc_state->hw.adjusted_mode, io_wake_time); 231 fast_wake_lines = intel_usecs_to_scanlines( 232 &crtc_state->hw.adjusted_mode, fast_wake_time); 233 234 if (io_wake_lines > max_wake_lines || 235 fast_wake_lines > max_wake_lines) 236 return false; 237 238 if (!_lnl_compute_alpm_params(intel_dp, crtc_state)) 239 return false; 240 241 if (display->params.psr_safest_params) 242 io_wake_lines = fast_wake_lines = max_wake_lines; 243 244 /* According to Bspec lower limit should be set as 7 lines. */ 245 crtc_state->alpm_state.io_wake_lines = max(io_wake_lines, 7); 246 crtc_state->alpm_state.fast_wake_lines = max(fast_wake_lines, 7); 247 248 return true; 249 } 250 251 void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, 252 struct intel_crtc_state *crtc_state, 253 struct drm_connector_state *conn_state) 254 { 255 struct intel_display *display = to_intel_display(intel_dp); 256 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 257 int waketime_in_lines, first_sdp_position; 258 int context_latency, guardband; 259 260 if (intel_dp->alpm.lobf_disable_debug) { 261 drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n"); 262 return; 263 } 264 265 if (intel_dp->alpm.sink_alpm_error) 266 return; 267 268 if (!intel_dp_is_edp(intel_dp)) 269 return; 270 271 if (DISPLAY_VER(display) < 20) 272 return; 273 274 if (!intel_dp->as_sdp_supported) 275 return; 276 277 if (crtc_state->has_psr) 278 return; 279 280 if (crtc_state->vrr.vmin != crtc_state->vrr.vmax || 281 crtc_state->vrr.vmin != crtc_state->vrr.flipline) 282 return; 283 284 if (!(intel_alpm_aux_wake_supported(intel_dp) || 285 intel_alpm_aux_less_wake_supported(intel_dp))) 286 return; 287 288 if (!intel_alpm_compute_params(intel_dp, crtc_state)) 289 return; 290 291 context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; 292 guardband = adjusted_mode->crtc_vtotal - 293 adjusted_mode->crtc_vdisplay - context_latency; 294 first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start; 295 if (intel_alpm_aux_less_wake_supported(intel_dp)) 296 waketime_in_lines = crtc_state->alpm_state.io_wake_lines; 297 else 298 waketime_in_lines = crtc_state->alpm_state.aux_less_wake_lines; 299 300 crtc_state->has_lobf = (context_latency + guardband) > 301 (first_sdp_position + waketime_in_lines); 302 } 303 304 static void lnl_alpm_configure(struct intel_dp *intel_dp, 305 const struct intel_crtc_state *crtc_state) 306 { 307 struct intel_display *display = to_intel_display(intel_dp); 308 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 309 u32 alpm_ctl; 310 311 if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) && 312 !crtc_state->has_lobf)) 313 return; 314 315 mutex_lock(&intel_dp->alpm.lock); 316 /* 317 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to 318 * check panel support at this point. 319 */ 320 if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) { 321 alpm_ctl = ALPM_CTL_ALPM_ENABLE | 322 ALPM_CTL_ALPM_AUX_LESS_ENABLE | 323 ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS | 324 ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines); 325 326 if (intel_dp->as_sdp_supported) { 327 u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1; 328 329 if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 330 DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP) 331 pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU; 332 if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 333 DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR)) 334 pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE; 335 336 intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder), 337 pr_alpm_ctl); 338 } 339 340 } else { 341 alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE | 342 ALPM_CTL_EXTENDED_FAST_WAKE_TIME(crtc_state->alpm_state.fast_wake_lines); 343 } 344 345 if (crtc_state->has_lobf) { 346 alpm_ctl |= ALPM_CTL_LOBF_ENABLE; 347 drm_dbg_kms(display->drm, "Link off between frames (LOBF) enabled\n"); 348 } 349 350 alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state->alpm_state.check_entry_lines); 351 352 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl); 353 mutex_unlock(&intel_dp->alpm.lock); 354 } 355 356 void intel_alpm_configure(struct intel_dp *intel_dp, 357 const struct intel_crtc_state *crtc_state) 358 { 359 lnl_alpm_configure(intel_dp, crtc_state); 360 intel_dp->alpm.transcoder = crtc_state->cpu_transcoder; 361 } 362 363 void intel_alpm_port_configure(struct intel_dp *intel_dp, 364 const struct intel_crtc_state *crtc_state) 365 { 366 struct intel_display *display = to_intel_display(intel_dp); 367 enum port port = dp_to_dig_port(intel_dp)->base.port; 368 u32 alpm_ctl_val = 0, lfps_ctl_val = 0; 369 370 if (DISPLAY_VER(display) < 20) 371 return; 372 373 if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) { 374 alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | 375 PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | 376 PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | 377 PORT_ALPM_CTL_SILENCE_PERIOD( 378 crtc_state->alpm_state.silence_period_sym_clocks); 379 lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) | 380 PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( 381 crtc_state->alpm_state.lfps_half_cycle_num_of_syms) | 382 PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( 383 crtc_state->alpm_state.lfps_half_cycle_num_of_syms) | 384 PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION( 385 crtc_state->alpm_state.lfps_half_cycle_num_of_syms); 386 } 387 388 intel_de_write(display, PORT_ALPM_CTL(port), alpm_ctl_val); 389 390 intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val); 391 } 392 393 void intel_alpm_pre_plane_update(struct intel_atomic_state *state, 394 struct intel_crtc *crtc) 395 { 396 struct intel_display *display = to_intel_display(state); 397 const struct intel_crtc_state *crtc_state = 398 intel_atomic_get_new_crtc_state(state, crtc); 399 const struct intel_crtc_state *old_crtc_state = 400 intel_atomic_get_old_crtc_state(state, crtc); 401 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 402 struct intel_encoder *encoder; 403 404 if (DISPLAY_VER(display) < 20) 405 return; 406 407 if (crtc_state->has_lobf || crtc_state->has_lobf == old_crtc_state->has_lobf) 408 return; 409 410 for_each_intel_encoder_mask(display->drm, encoder, 411 crtc_state->uapi.encoder_mask) { 412 struct intel_dp *intel_dp; 413 414 if (!intel_encoder_is_dp(encoder)) 415 continue; 416 417 intel_dp = enc_to_intel_dp(encoder); 418 419 if (!intel_dp_is_edp(intel_dp)) 420 continue; 421 422 if (old_crtc_state->has_lobf) { 423 mutex_lock(&intel_dp->alpm.lock); 424 intel_de_write(display, ALPM_CTL(display, cpu_transcoder), 0); 425 drm_dbg_kms(display->drm, "Link off between frames (LOBF) disabled\n"); 426 mutex_unlock(&intel_dp->alpm.lock); 427 } 428 } 429 } 430 431 void intel_alpm_enable_sink(struct intel_dp *intel_dp, 432 const struct intel_crtc_state *crtc_state) 433 { 434 u8 val; 435 436 if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf) 437 return; 438 439 val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE; 440 441 if (crtc_state->has_panel_replay || (crtc_state->has_lobf && 442 intel_alpm_aux_less_wake_supported(intel_dp))) 443 val |= DP_ALPM_MODE_AUX_LESS; 444 445 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); 446 } 447 448 void intel_alpm_post_plane_update(struct intel_atomic_state *state, 449 struct intel_crtc *crtc) 450 { 451 struct intel_display *display = to_intel_display(state); 452 const struct intel_crtc_state *crtc_state = 453 intel_atomic_get_new_crtc_state(state, crtc); 454 const struct intel_crtc_state *old_crtc_state = 455 intel_atomic_get_old_crtc_state(state, crtc); 456 struct intel_encoder *encoder; 457 458 if (crtc_state->has_psr || !crtc_state->has_lobf || 459 crtc_state->has_lobf == old_crtc_state->has_lobf) 460 return; 461 462 for_each_intel_encoder_mask(display->drm, encoder, 463 crtc_state->uapi.encoder_mask) { 464 struct intel_dp *intel_dp; 465 466 if (!intel_encoder_is_dp(encoder)) 467 continue; 468 469 intel_dp = enc_to_intel_dp(encoder); 470 471 if (intel_dp_is_edp(intel_dp)) { 472 intel_alpm_enable_sink(intel_dp, crtc_state); 473 intel_alpm_configure(intel_dp, crtc_state); 474 } 475 } 476 } 477 478 static int i915_edp_lobf_info_show(struct seq_file *m, void *data) 479 { 480 struct intel_connector *connector = m->private; 481 struct intel_display *display = to_intel_display(connector); 482 struct drm_crtc *crtc; 483 struct intel_crtc_state *crtc_state; 484 enum transcoder cpu_transcoder; 485 u32 alpm_ctl; 486 int ret; 487 488 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 489 if (ret) 490 return ret; 491 492 crtc = connector->base.state->crtc; 493 if (connector->base.status != connector_status_connected || !crtc) { 494 ret = -ENODEV; 495 goto out; 496 } 497 498 crtc_state = to_intel_crtc_state(crtc->state); 499 cpu_transcoder = crtc_state->cpu_transcoder; 500 alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder)); 501 seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE)); 502 seq_printf(m, "Aux-wake alpm status: %s\n", 503 str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE))); 504 seq_printf(m, "Aux-less alpm status: %s\n", 505 str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)); 506 out: 507 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 508 509 return ret; 510 } 511 512 DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info); 513 514 static int 515 i915_edp_lobf_debug_get(void *data, u64 *val) 516 { 517 struct intel_connector *connector = data; 518 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 519 520 *val = intel_dp->alpm.lobf_disable_debug; 521 522 return 0; 523 } 524 525 static int 526 i915_edp_lobf_debug_set(void *data, u64 val) 527 { 528 struct intel_connector *connector = data; 529 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 530 531 intel_dp->alpm.lobf_disable_debug = val; 532 533 return 0; 534 } 535 536 DEFINE_SIMPLE_ATTRIBUTE(i915_edp_lobf_debug_fops, 537 i915_edp_lobf_debug_get, i915_edp_lobf_debug_set, 538 "%llu\n"); 539 540 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector) 541 { 542 struct intel_display *display = to_intel_display(connector); 543 struct dentry *root = connector->base.debugfs_entry; 544 545 if (DISPLAY_VER(display) < 20 || 546 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 547 return; 548 549 debugfs_create_file("i915_edp_lobf_debug", 0644, root, 550 connector, &i915_edp_lobf_debug_fops); 551 552 debugfs_create_file("i915_edp_lobf_info", 0444, root, 553 connector, &i915_edp_lobf_info_fops); 554 } 555 556 void intel_alpm_disable(struct intel_dp *intel_dp) 557 { 558 struct intel_display *display = to_intel_display(intel_dp); 559 enum transcoder cpu_transcoder = intel_dp->alpm.transcoder; 560 561 if (DISPLAY_VER(display) < 20 || !intel_dp->alpm_dpcd) 562 return; 563 564 mutex_lock(&intel_dp->alpm.lock); 565 566 intel_de_rmw(display, ALPM_CTL(display, cpu_transcoder), 567 ALPM_CTL_ALPM_ENABLE | ALPM_CTL_LOBF_ENABLE | 568 ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); 569 570 intel_de_rmw(display, 571 PORT_ALPM_CTL(cpu_transcoder), 572 PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); 573 574 drm_dbg_kms(display->drm, "Disabling ALPM\n"); 575 mutex_unlock(&intel_dp->alpm.lock); 576 } 577 578 bool intel_alpm_get_error(struct intel_dp *intel_dp) 579 { 580 struct intel_display *display = to_intel_display(intel_dp); 581 struct drm_dp_aux *aux = &intel_dp->aux; 582 u8 val; 583 int r; 584 585 r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); 586 if (r != 1) { 587 drm_err(display->drm, "Error reading ALPM status\n"); 588 return true; 589 } 590 591 if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { 592 drm_dbg_kms(display->drm, "ALPM lock timeout error\n"); 593 594 /* Clearing error */ 595 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); 596 return true; 597 } 598 599 return false; 600 } 601