1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2024, Intel Corporation. 4 */ 5 6 #include "intel_alpm.h" 7 #include "intel_crtc.h" 8 #include "intel_de.h" 9 #include "intel_display_types.h" 10 #include "intel_dp.h" 11 #include "intel_dp_aux.h" 12 #include "intel_psr_regs.h" 13 14 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp) 15 { 16 return intel_dp->alpm_dpcd & DP_ALPM_CAP; 17 } 18 19 bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp) 20 { 21 return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP; 22 } 23 24 void intel_alpm_init_dpcd(struct intel_dp *intel_dp) 25 { 26 u8 dpcd; 27 28 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0) 29 return; 30 31 intel_dp->alpm_dpcd = dpcd; 32 } 33 34 /* 35 * See Bspec: 71632 for the table 36 * 37 * Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2) 38 * 39 * Half cycle duration: 40 * 41 * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns 42 * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) ) 43 * 44 * Link rates 5.4 - 8.1 45 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10 46 * LFPS Period chosen is the mid-point of the min:max values from the table 47 * FLOOR( LFPS Period in Symbol clocks / 48 * (2 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ]) ) 49 */ 50 static bool _lnl_get_silence_period_and_lfps_half_cycle(int link_rate, 51 int *silence_period, 52 int *lfps_half_cycle) 53 { 54 switch (link_rate) { 55 case 162000: 56 *silence_period = 20; 57 *lfps_half_cycle = 5; 58 break; 59 case 216000: 60 *silence_period = 27; 61 *lfps_half_cycle = 7; 62 break; 63 case 243000: 64 *silence_period = 31; 65 *lfps_half_cycle = 8; 66 break; 67 case 270000: 68 *silence_period = 34; 69 *lfps_half_cycle = 9; 70 break; 71 case 324000: 72 *silence_period = 41; 73 *lfps_half_cycle = 11; 74 break; 75 case 432000: 76 *silence_period = 56; 77 *lfps_half_cycle = 15; 78 break; 79 case 540000: 80 *silence_period = 69; 81 *lfps_half_cycle = 12; 82 break; 83 case 648000: 84 *silence_period = 84; 85 *lfps_half_cycle = 15; 86 break; 87 case 675000: 88 *silence_period = 87; 89 *lfps_half_cycle = 15; 90 break; 91 case 810000: 92 *silence_period = 104; 93 *lfps_half_cycle = 19; 94 break; 95 default: 96 *silence_period = *lfps_half_cycle = -1; 97 return false; 98 } 99 return true; 100 } 101 102 /* 103 * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+ 104 * tSilence, Max+ tPHY Establishment + tCDS) / tline) 105 * For the "PHY P2 to P0" latency see the PHY Power Control page 106 * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965 107 * : 12 us 108 * The tLFPS_Period, Max term is 800ns 109 * The tSilence, Max term is 180ns 110 * The tPHY Establishment (a.k.a. t1) term is 50us 111 * The tCDS term is 1 or 2 times t2 112 * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK 113 * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1) 114 * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and 115 * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start 116 * within the CDS period complete within the CDS period regardless of 117 * entry into the period 118 * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) ) 119 * TPS4 Length = 252 Symbols 120 */ 121 static int _lnl_compute_aux_less_wake_time(int port_clock) 122 { 123 int tphy2_p2_to_p0 = 12 * 1000; 124 int tlfps_period_max = 800; 125 int tsilence_max = 180; 126 int t1 = 50 * 1000; 127 int tps4 = 252; 128 /* port_clock is link rate in 10kbit/s units */ 129 int tml_phy_lock = 1000 * 1000 * tps4 / port_clock; 130 int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1; 131 int t2 = num_ml_phy_lock * tml_phy_lock; 132 int tcds = 1 * t2; 133 134 return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max + tsilence_max + 135 t1 + tcds, 1000); 136 } 137 138 static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, 139 struct intel_crtc_state *crtc_state) 140 { 141 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 142 int aux_less_wake_time, aux_less_wake_lines, silence_period, 143 lfps_half_cycle; 144 145 aux_less_wake_time = 146 _lnl_compute_aux_less_wake_time(crtc_state->port_clock); 147 aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 148 aux_less_wake_time); 149 150 if (!_lnl_get_silence_period_and_lfps_half_cycle(crtc_state->port_clock, 151 &silence_period, 152 &lfps_half_cycle)) 153 return false; 154 155 if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK || 156 silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK || 157 lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK) 158 return false; 159 160 if (i915->display.params.psr_safest_params) 161 aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK; 162 163 intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines; 164 intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period; 165 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle; 166 167 return true; 168 } 169 170 static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, 171 struct intel_crtc_state *crtc_state) 172 { 173 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 174 int check_entry_lines; 175 176 if (DISPLAY_VER(i915) < 20) 177 return true; 178 179 /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */ 180 check_entry_lines = 2 + 181 intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5); 182 183 if (check_entry_lines > 15) 184 return false; 185 186 if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state)) 187 return false; 188 189 if (i915->display.params.psr_safest_params) 190 check_entry_lines = 15; 191 192 intel_dp->alpm_parameters.check_entry_lines = check_entry_lines; 193 194 return true; 195 } 196 197 /* 198 * IO wake time for DISPLAY_VER < 12 is not directly mentioned in Bspec. There 199 * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are 200 * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us. 201 */ 202 static int skl_io_buffer_wake_time(void) 203 { 204 return 18; 205 } 206 207 static int tgl_io_buffer_wake_time(void) 208 { 209 return 10; 210 } 211 212 static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state) 213 { 214 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 215 216 if (DISPLAY_VER(i915) >= 12) 217 return tgl_io_buffer_wake_time(); 218 else 219 return skl_io_buffer_wake_time(); 220 } 221 222 bool intel_alpm_compute_params(struct intel_dp *intel_dp, 223 struct intel_crtc_state *crtc_state) 224 { 225 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 226 int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time; 227 int tfw_exit_latency = 20; /* eDP spec */ 228 int phy_wake = 4; /* eDP spec */ 229 int preamble = 8; /* eDP spec */ 230 int precharge = intel_dp_aux_fw_sync_len() - preamble; 231 u8 max_wake_lines; 232 233 io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) + 234 preamble + phy_wake + tfw_exit_latency; 235 fast_wake_time = precharge + preamble + phy_wake + 236 tfw_exit_latency; 237 238 if (DISPLAY_VER(i915) >= 20) 239 max_wake_lines = 68; 240 else if (DISPLAY_VER(i915) >= 12) 241 max_wake_lines = 12; 242 else 243 max_wake_lines = 8; 244 245 io_wake_lines = intel_usecs_to_scanlines( 246 &crtc_state->hw.adjusted_mode, io_wake_time); 247 fast_wake_lines = intel_usecs_to_scanlines( 248 &crtc_state->hw.adjusted_mode, fast_wake_time); 249 250 if (io_wake_lines > max_wake_lines || 251 fast_wake_lines > max_wake_lines) 252 return false; 253 254 if (!_lnl_compute_alpm_params(intel_dp, crtc_state)) 255 return false; 256 257 if (i915->display.params.psr_safest_params) 258 io_wake_lines = fast_wake_lines = max_wake_lines; 259 260 /* According to Bspec lower limit should be set as 7 lines. */ 261 intel_dp->alpm_parameters.io_wake_lines = max(io_wake_lines, 7); 262 intel_dp->alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7); 263 264 return true; 265 } 266 267 void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, 268 struct intel_crtc_state *crtc_state, 269 struct drm_connector_state *conn_state) 270 { 271 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 272 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 273 int waketime_in_lines, first_sdp_position; 274 int context_latency, guardband; 275 276 if (!intel_dp_is_edp(intel_dp)) 277 return; 278 279 if (DISPLAY_VER(i915) < 20) 280 return; 281 282 if (!intel_dp_as_sdp_supported(intel_dp)) 283 return; 284 285 if (crtc_state->has_psr) 286 return; 287 288 if (!(intel_alpm_aux_wake_supported(intel_dp) || 289 intel_alpm_aux_less_wake_supported(intel_dp))) 290 return; 291 292 if (!intel_alpm_compute_params(intel_dp, crtc_state)) 293 return; 294 295 context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; 296 guardband = adjusted_mode->crtc_vtotal - 297 adjusted_mode->crtc_vdisplay - context_latency; 298 first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start; 299 if (intel_alpm_aux_less_wake_supported(intel_dp)) 300 waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines; 301 else 302 waketime_in_lines = intel_dp->alpm_parameters.aux_less_wake_lines; 303 304 crtc_state->has_lobf = (context_latency + guardband) > 305 (first_sdp_position + waketime_in_lines); 306 } 307 308 static void lnl_alpm_configure(struct intel_dp *intel_dp, 309 const struct intel_crtc_state *crtc_state) 310 { 311 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 312 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 313 enum port port = dp_to_dig_port(intel_dp)->base.port; 314 u32 alpm_ctl; 315 316 if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && 317 !intel_dp_is_edp(intel_dp))) 318 return; 319 320 /* 321 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to 322 * check panel support at this point. 323 */ 324 if ((intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) || 325 (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp))) { 326 alpm_ctl = ALPM_CTL_ALPM_ENABLE | 327 ALPM_CTL_ALPM_AUX_LESS_ENABLE | 328 ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS | 329 ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines); 330 331 intel_de_write(dev_priv, 332 PORT_ALPM_CTL(dev_priv, port), 333 PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | 334 PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | 335 PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | 336 PORT_ALPM_CTL_SILENCE_PERIOD( 337 intel_dp->alpm_parameters.silence_period_sym_clocks)); 338 339 intel_de_write(dev_priv, 340 PORT_ALPM_LFPS_CTL(dev_priv, port), 341 PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | 342 PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( 343 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | 344 PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( 345 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | 346 PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION( 347 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms)); 348 } else { 349 alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE | 350 ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines); 351 } 352 353 if (crtc_state->has_lobf) 354 alpm_ctl |= ALPM_CTL_LOBF_ENABLE; 355 356 alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines); 357 358 intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl); 359 } 360 361 void intel_alpm_configure(struct intel_dp *intel_dp, 362 const struct intel_crtc_state *crtc_state) 363 { 364 lnl_alpm_configure(intel_dp, crtc_state); 365 } 366 367 static int i915_edp_lobf_info_show(struct seq_file *m, void *data) 368 { 369 struct intel_connector *connector = m->private; 370 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 371 struct drm_crtc *crtc; 372 struct intel_crtc_state *crtc_state; 373 enum transcoder cpu_transcoder; 374 u32 alpm_ctl; 375 int ret; 376 377 ret = drm_modeset_lock_single_interruptible(&dev_priv->drm.mode_config.connection_mutex); 378 if (ret) 379 return ret; 380 381 crtc = connector->base.state->crtc; 382 if (connector->base.status != connector_status_connected || !crtc) { 383 ret = -ENODEV; 384 goto out; 385 } 386 387 crtc_state = to_intel_crtc_state(crtc->state); 388 cpu_transcoder = crtc_state->cpu_transcoder; 389 alpm_ctl = intel_de_read(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder)); 390 seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE)); 391 seq_printf(m, "Aux-wake alpm status: %s\n", 392 str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE))); 393 seq_printf(m, "Aux-less alpm status: %s\n", 394 str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)); 395 out: 396 drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex); 397 398 return ret; 399 } 400 401 DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info); 402 403 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector) 404 { 405 struct drm_i915_private *i915 = to_i915(connector->base.dev); 406 struct dentry *root = connector->base.debugfs_entry; 407 408 if (DISPLAY_VER(i915) < 20 || 409 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 410 return; 411 412 debugfs_create_file("i915_edp_lobf_info", 0444, root, 413 connector, &i915_edp_lobf_info_fops); 414 } 415