1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/display/drm_dsc_helper.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_fixed.h> 31 #include <drm/drm_mipi_dsi.h> 32 #include <drm/drm_probe_helper.h> 33 34 #include "i915_reg.h" 35 #include "icl_dsi.h" 36 #include "icl_dsi_regs.h" 37 #include "intel_atomic.h" 38 #include "intel_backlight.h" 39 #include "intel_backlight_regs.h" 40 #include "intel_combo_phy.h" 41 #include "intel_combo_phy_regs.h" 42 #include "intel_connector.h" 43 #include "intel_crtc.h" 44 #include "intel_ddi.h" 45 #include "intel_de.h" 46 #include "intel_dsi.h" 47 #include "intel_dsi_vbt.h" 48 #include "intel_panel.h" 49 #include "intel_pfit.h" 50 #include "intel_vdsc.h" 51 #include "intel_vdsc_regs.h" 52 #include "skl_scaler.h" 53 #include "skl_universal_plane.h" 54 55 static int header_credits_available(struct intel_display *display, 56 enum transcoder dsi_trans) 57 { 58 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 59 >> FREE_HEADER_CREDIT_SHIFT; 60 } 61 62 static int payload_credits_available(struct intel_display *display, 63 enum transcoder dsi_trans) 64 { 65 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 66 >> FREE_PLOAD_CREDIT_SHIFT; 67 } 68 69 static bool wait_for_header_credits(struct intel_display *display, 70 enum transcoder dsi_trans, int hdr_credit) 71 { 72 if (wait_for_us(header_credits_available(display, dsi_trans) >= 73 hdr_credit, 100)) { 74 drm_err(display->drm, "DSI header credits not released\n"); 75 return false; 76 } 77 78 return true; 79 } 80 81 static bool wait_for_payload_credits(struct intel_display *display, 82 enum transcoder dsi_trans, int payld_credit) 83 { 84 if (wait_for_us(payload_credits_available(display, dsi_trans) >= 85 payld_credit, 100)) { 86 drm_err(display->drm, "DSI payload credits not released\n"); 87 return false; 88 } 89 90 return true; 91 } 92 93 static enum transcoder dsi_port_to_transcoder(enum port port) 94 { 95 if (port == PORT_A) 96 return TRANSCODER_DSI_0; 97 else 98 return TRANSCODER_DSI_1; 99 } 100 101 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 102 { 103 struct intel_display *display = to_intel_display(encoder); 104 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 105 struct mipi_dsi_device *dsi; 106 enum port port; 107 enum transcoder dsi_trans; 108 int ret; 109 110 /* wait for header/payload credits to be released */ 111 for_each_dsi_port(port, intel_dsi->ports) { 112 dsi_trans = dsi_port_to_transcoder(port); 113 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT); 114 wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT); 115 } 116 117 /* send nop DCS command */ 118 for_each_dsi_port(port, intel_dsi->ports) { 119 dsi = intel_dsi->dsi_hosts[port]->device; 120 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 121 dsi->channel = 0; 122 ret = mipi_dsi_dcs_nop(dsi); 123 if (ret < 0) 124 drm_err(display->drm, 125 "error sending DCS NOP command\n"); 126 } 127 128 /* wait for header credits to be released */ 129 for_each_dsi_port(port, intel_dsi->ports) { 130 dsi_trans = dsi_port_to_transcoder(port); 131 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT); 132 } 133 134 /* wait for LP TX in progress bit to be cleared */ 135 for_each_dsi_port(port, intel_dsi->ports) { 136 dsi_trans = dsi_port_to_transcoder(port); 137 if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) & 138 LPTX_IN_PROGRESS), 20)) 139 drm_err(display->drm, "LPTX bit not cleared\n"); 140 } 141 } 142 143 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 144 const struct mipi_dsi_packet *packet) 145 { 146 struct intel_dsi *intel_dsi = host->intel_dsi; 147 struct intel_display *display = to_intel_display(&intel_dsi->base); 148 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 149 const u8 *data = packet->payload; 150 u32 len = packet->payload_length; 151 int i, j; 152 153 /* payload queue can accept *256 bytes*, check limit */ 154 if (len > MAX_PLOAD_CREDIT * 4) { 155 drm_err(display->drm, "payload size exceeds max queue limit\n"); 156 return -EINVAL; 157 } 158 159 for (i = 0; i < len; i += 4) { 160 u32 tmp = 0; 161 162 if (!wait_for_payload_credits(display, dsi_trans, 1)) 163 return -EBUSY; 164 165 for (j = 0; j < min_t(u32, len - i, 4); j++) 166 tmp |= *data++ << 8 * j; 167 168 intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp); 169 } 170 171 return 0; 172 } 173 174 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 175 const struct mipi_dsi_packet *packet, 176 bool enable_lpdt) 177 { 178 struct intel_dsi *intel_dsi = host->intel_dsi; 179 struct intel_display *display = to_intel_display(&intel_dsi->base); 180 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 181 u32 tmp; 182 183 if (!wait_for_header_credits(display, dsi_trans, 1)) 184 return -EBUSY; 185 186 tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans)); 187 188 if (packet->payload) 189 tmp |= PAYLOAD_PRESENT; 190 else 191 tmp &= ~PAYLOAD_PRESENT; 192 193 tmp &= ~VBLANK_FENCE; 194 195 if (enable_lpdt) 196 tmp |= LP_DATA_TRANSFER; 197 else 198 tmp &= ~LP_DATA_TRANSFER; 199 200 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 201 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 202 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 203 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 204 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 205 intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp); 206 207 return 0; 208 } 209 210 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 211 { 212 struct intel_display *display = to_intel_display(crtc_state); 213 u32 mode_flags; 214 enum port port; 215 216 mode_flags = crtc_state->mode_flags; 217 218 /* 219 * case 1 also covers dual link 220 * In case of dual link, frame update should be set on 221 * DSI_0 222 */ 223 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 224 port = PORT_A; 225 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 226 port = PORT_B; 227 else 228 return; 229 230 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0, 231 DSI_FRAME_UPDATE_REQUEST); 232 } 233 234 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 235 { 236 struct intel_display *display = to_intel_display(encoder); 237 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 238 enum phy phy; 239 u32 tmp, mask, val; 240 int lane; 241 242 for_each_dsi_phy(phy, intel_dsi->phys) { 243 /* 244 * Program voltage swing and pre-emphasis level values as per 245 * table in BSPEC under DDI buffer programing 246 */ 247 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK; 248 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE | 249 RTERM_SELECT(0x6); 250 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 251 tmp &= ~mask; 252 tmp |= val; 253 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 254 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val); 255 256 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 257 RCOMP_SCALAR_MASK; 258 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) | 259 RCOMP_SCALAR(0x98); 260 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); 261 tmp &= ~mask; 262 tmp |= val; 263 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 264 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val); 265 266 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 267 CURSOR_COEFF_MASK; 268 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) | 269 CURSOR_COEFF(0x3f); 270 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val); 271 272 /* Bspec: must not use GRP register for write */ 273 for (lane = 0; lane <= 3; lane++) 274 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), 275 mask, val); 276 } 277 } 278 279 static void configure_dual_link_mode(struct intel_encoder *encoder, 280 const struct intel_crtc_state *pipe_config) 281 { 282 struct intel_display *display = to_intel_display(encoder); 283 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 284 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 285 u32 dss_ctl1; 286 287 /* FIXME: Move all DSS handling to intel_vdsc.c */ 288 if (DISPLAY_VER(display) >= 12) { 289 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 290 291 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); 292 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); 293 } else { 294 dss_ctl1_reg = DSS_CTL1; 295 dss_ctl2_reg = DSS_CTL2; 296 } 297 298 dss_ctl1 = intel_de_read(display, dss_ctl1_reg); 299 dss_ctl1 |= SPLITTER_ENABLE; 300 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 301 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 302 303 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 304 const struct drm_display_mode *adjusted_mode = 305 &pipe_config->hw.adjusted_mode; 306 u16 hactive = adjusted_mode->crtc_hdisplay; 307 u16 dl_buffer_depth; 308 309 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 310 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 311 312 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 313 drm_err(display->drm, 314 "DL buffer depth exceed max value\n"); 315 316 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 317 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 318 intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, 319 RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth)); 320 } else { 321 /* Interleave */ 322 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 323 } 324 325 intel_de_write(display, dss_ctl1_reg, dss_ctl1); 326 } 327 328 /* aka DSI 8X clock */ 329 static int afe_clk(struct intel_encoder *encoder, 330 const struct intel_crtc_state *crtc_state) 331 { 332 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 333 int bpp; 334 335 if (crtc_state->dsc.compression_enable) 336 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 337 else 338 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 339 340 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 341 } 342 343 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 344 const struct intel_crtc_state *crtc_state) 345 { 346 struct intel_display *display = to_intel_display(encoder); 347 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 348 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 349 enum port port; 350 int afe_clk_khz; 351 int theo_word_clk, act_word_clk; 352 u32 esc_clk_div_m, esc_clk_div_m_phy; 353 354 afe_clk_khz = afe_clk(encoder, crtc_state); 355 356 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 357 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 358 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 359 esc_clk_div_m = act_word_clk * 8; 360 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 361 } else { 362 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 363 } 364 365 for_each_dsi_port(port, intel_dsi->ports) { 366 intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port), 367 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 368 intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port)); 369 } 370 371 for_each_dsi_port(port, intel_dsi->ports) { 372 intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port), 373 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 374 intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port)); 375 } 376 377 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { 378 for_each_dsi_port(port, intel_dsi->ports) { 379 intel_de_write(display, ADL_MIPIO_DW(port, 8), 380 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 381 intel_de_posting_read(display, ADL_MIPIO_DW(port, 8)); 382 } 383 } 384 } 385 386 static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi) 387 { 388 struct intel_display *display = to_intel_display(&intel_dsi->base); 389 struct drm_i915_private *dev_priv = to_i915(display->drm); 390 enum port port; 391 392 for_each_dsi_port(port, intel_dsi->ports) { 393 drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]); 394 intel_dsi->io_wakeref[port] = 395 intel_display_power_get(dev_priv, 396 port == PORT_A ? 397 POWER_DOMAIN_PORT_DDI_IO_A : 398 POWER_DOMAIN_PORT_DDI_IO_B); 399 } 400 } 401 402 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 403 { 404 struct intel_display *display = to_intel_display(encoder); 405 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 406 enum port port; 407 408 for_each_dsi_port(port, intel_dsi->ports) 409 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), 410 0, COMBO_PHY_MODE_DSI); 411 412 get_dsi_io_power_domains(intel_dsi); 413 } 414 415 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 416 { 417 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 418 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 419 enum phy phy; 420 421 for_each_dsi_phy(phy, intel_dsi->phys) 422 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 423 intel_dsi->lane_count, false); 424 } 425 426 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 427 { 428 struct intel_display *display = to_intel_display(encoder); 429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 430 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 431 enum phy phy; 432 u32 tmp; 433 int lane; 434 435 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 436 for_each_dsi_phy(phy, intel_dsi->phys) { 437 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), 438 LOADGEN_SELECT, 0); 439 for (lane = 0; lane <= 3; lane++) 440 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), 441 LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0); 442 } 443 444 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 445 for_each_dsi_phy(phy, intel_dsi->phys) { 446 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), 447 FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5)); 448 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); 449 tmp &= ~FRC_LATENCY_OPTIM_MASK; 450 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 451 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 452 453 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 454 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) || 455 (DISPLAY_VER(display) >= 12)) { 456 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), 457 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0)); 458 459 tmp = intel_de_read(display, 460 ICL_PORT_PCS_DW1_LN(0, phy)); 461 tmp &= ~LATENCY_OPTIM_MASK; 462 tmp |= LATENCY_OPTIM_VAL(0x1); 463 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), 464 tmp); 465 } 466 } 467 468 } 469 470 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 471 { 472 struct intel_display *display = to_intel_display(encoder); 473 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 474 u32 tmp; 475 enum phy phy; 476 477 /* clear common keeper enable bit */ 478 for_each_dsi_phy(phy, intel_dsi->phys) { 479 tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 480 tmp &= ~COMMON_KEEPER_EN; 481 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp); 482 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0); 483 } 484 485 /* 486 * Set SUS Clock Config bitfield to 11b 487 * Note: loadgen select program is done 488 * as part of lane phy sequence configuration 489 */ 490 for_each_dsi_phy(phy, intel_dsi->phys) 491 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0, 492 SUS_CLOCK_CONFIG); 493 494 /* Clear training enable to change swing values */ 495 for_each_dsi_phy(phy, intel_dsi->phys) { 496 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 497 tmp &= ~TX_TRAINING_EN; 498 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 499 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0); 500 } 501 502 /* Program swing and de-emphasis */ 503 dsi_program_swing_and_deemphasis(encoder); 504 505 /* Set training enable to trigger update */ 506 for_each_dsi_phy(phy, intel_dsi->phys) { 507 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 508 tmp |= TX_TRAINING_EN; 509 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 510 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN); 511 } 512 } 513 514 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 515 { 516 struct intel_display *display = to_intel_display(encoder); 517 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 518 enum port port; 519 520 for_each_dsi_port(port, intel_dsi->ports) { 521 intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE); 522 523 if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) & 524 DDI_BUF_IS_IDLE), 525 500)) 526 drm_err(display->drm, "DDI port:%c buffer idle\n", 527 port_name(port)); 528 } 529 } 530 531 static void 532 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 533 const struct intel_crtc_state *crtc_state) 534 { 535 struct intel_display *display = to_intel_display(encoder); 536 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 537 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 538 enum port port; 539 enum phy phy; 540 541 /* Program DPHY clock lanes timings */ 542 for_each_dsi_port(port, intel_dsi->ports) 543 intel_de_write(display, DPHY_CLK_TIMING_PARAM(port), 544 intel_dsi->dphy_reg); 545 546 /* Program DPHY data lanes timings */ 547 for_each_dsi_port(port, intel_dsi->ports) 548 intel_de_write(display, DPHY_DATA_TIMING_PARAM(port), 549 intel_dsi->dphy_data_lane_reg); 550 551 /* 552 * If DSI link operating at or below an 800 MHz, 553 * TA_SURE should be override and programmed to 554 * a value '0' inside TA_PARAM_REGISTERS otherwise 555 * leave all fields at HW default values. 556 */ 557 if (DISPLAY_VER(display) == 11) { 558 if (afe_clk(encoder, crtc_state) <= 800000) { 559 for_each_dsi_port(port, intel_dsi->ports) 560 intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port), 561 TA_SURE_MASK, 562 TA_SURE_OVERRIDE | TA_SURE(0)); 563 } 564 } 565 566 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { 567 for_each_dsi_phy(phy, intel_dsi->phys) 568 intel_de_rmw(display, ICL_DPHY_CHKN(phy), 569 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP); 570 } 571 } 572 573 static void 574 gen11_dsi_setup_timings(struct intel_encoder *encoder, 575 const struct intel_crtc_state *crtc_state) 576 { 577 struct intel_display *display = to_intel_display(encoder); 578 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 579 enum port port; 580 581 /* Program T-INIT master registers */ 582 for_each_dsi_port(port, intel_dsi->ports) 583 intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port), 584 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); 585 586 /* shadow register inside display core */ 587 for_each_dsi_port(port, intel_dsi->ports) 588 intel_de_write(display, DSI_CLK_TIMING_PARAM(port), 589 intel_dsi->dphy_reg); 590 591 /* shadow register inside display core */ 592 for_each_dsi_port(port, intel_dsi->ports) 593 intel_de_write(display, DSI_DATA_TIMING_PARAM(port), 594 intel_dsi->dphy_data_lane_reg); 595 596 /* shadow register inside display core */ 597 if (DISPLAY_VER(display) == 11) { 598 if (afe_clk(encoder, crtc_state) <= 800000) { 599 for_each_dsi_port(port, intel_dsi->ports) { 600 intel_de_rmw(display, DSI_TA_TIMING_PARAM(port), 601 TA_SURE_MASK, 602 TA_SURE_OVERRIDE | TA_SURE(0)); 603 } 604 } 605 } 606 } 607 608 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 609 { 610 struct intel_display *display = to_intel_display(encoder); 611 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 612 u32 tmp; 613 enum phy phy; 614 615 mutex_lock(&display->dpll.lock); 616 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 617 for_each_dsi_phy(phy, intel_dsi->phys) 618 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 619 620 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); 621 mutex_unlock(&display->dpll.lock); 622 } 623 624 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 625 { 626 struct intel_display *display = to_intel_display(encoder); 627 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 628 u32 tmp; 629 enum phy phy; 630 631 mutex_lock(&display->dpll.lock); 632 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 633 for_each_dsi_phy(phy, intel_dsi->phys) 634 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 635 636 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); 637 mutex_unlock(&display->dpll.lock); 638 } 639 640 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 641 { 642 struct intel_display *display = to_intel_display(encoder); 643 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 644 bool clock_enabled = false; 645 enum phy phy; 646 u32 tmp; 647 648 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 649 650 for_each_dsi_phy(phy, intel_dsi->phys) { 651 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 652 clock_enabled = true; 653 } 654 655 return clock_enabled; 656 } 657 658 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 659 const struct intel_crtc_state *crtc_state) 660 { 661 struct intel_display *display = to_intel_display(encoder); 662 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 663 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 664 enum phy phy; 665 u32 val; 666 667 mutex_lock(&display->dpll.lock); 668 669 val = intel_de_read(display, ICL_DPCLKA_CFGCR0); 670 for_each_dsi_phy(phy, intel_dsi->phys) { 671 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 672 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 673 } 674 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); 675 676 for_each_dsi_phy(phy, intel_dsi->phys) { 677 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 678 } 679 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); 680 681 intel_de_posting_read(display, ICL_DPCLKA_CFGCR0); 682 683 mutex_unlock(&display->dpll.lock); 684 } 685 686 static void 687 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 688 const struct intel_crtc_state *pipe_config) 689 { 690 struct intel_display *display = to_intel_display(encoder); 691 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 692 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 693 enum pipe pipe = crtc->pipe; 694 u32 tmp; 695 enum port port; 696 enum transcoder dsi_trans; 697 698 for_each_dsi_port(port, intel_dsi->ports) { 699 dsi_trans = dsi_port_to_transcoder(port); 700 tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 701 702 if (intel_dsi->eotp_pkt) 703 tmp &= ~EOTP_DISABLED; 704 else 705 tmp |= EOTP_DISABLED; 706 707 /* enable link calibration if freq > 1.5Gbps */ 708 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 709 tmp &= ~LINK_CALIBRATION_MASK; 710 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 711 } 712 713 /* configure continuous clock */ 714 tmp &= ~CONTINUOUS_CLK_MASK; 715 if (intel_dsi->clock_stop) 716 tmp |= CLK_ENTER_LP_AFTER_DATA; 717 else 718 tmp |= CLK_HS_CONTINUOUS; 719 720 /* configure buffer threshold limit to minimum */ 721 tmp &= ~PIX_BUF_THRESHOLD_MASK; 722 tmp |= PIX_BUF_THRESHOLD_1_4; 723 724 /* set virtual channel to '0' */ 725 tmp &= ~PIX_VIRT_CHAN_MASK; 726 tmp |= PIX_VIRT_CHAN(0); 727 728 /* program BGR transmission */ 729 if (intel_dsi->bgr_enabled) 730 tmp |= BGR_TRANSMISSION; 731 732 /* select pixel format */ 733 tmp &= ~PIX_FMT_MASK; 734 if (pipe_config->dsc.compression_enable) { 735 tmp |= PIX_FMT_COMPRESSED; 736 } else { 737 switch (intel_dsi->pixel_format) { 738 default: 739 MISSING_CASE(intel_dsi->pixel_format); 740 fallthrough; 741 case MIPI_DSI_FMT_RGB565: 742 tmp |= PIX_FMT_RGB565; 743 break; 744 case MIPI_DSI_FMT_RGB666_PACKED: 745 tmp |= PIX_FMT_RGB666_PACKED; 746 break; 747 case MIPI_DSI_FMT_RGB666: 748 tmp |= PIX_FMT_RGB666_LOOSE; 749 break; 750 case MIPI_DSI_FMT_RGB888: 751 tmp |= PIX_FMT_RGB888; 752 break; 753 } 754 } 755 756 if (DISPLAY_VER(display) >= 12) { 757 if (is_vid_mode(intel_dsi)) 758 tmp |= BLANKING_PACKET_ENABLE; 759 } 760 761 /* program DSI operation mode */ 762 if (is_vid_mode(intel_dsi)) { 763 tmp &= ~OP_MODE_MASK; 764 switch (intel_dsi->video_mode) { 765 default: 766 MISSING_CASE(intel_dsi->video_mode); 767 fallthrough; 768 case NON_BURST_SYNC_EVENTS: 769 tmp |= VIDEO_MODE_SYNC_EVENT; 770 break; 771 case NON_BURST_SYNC_PULSE: 772 tmp |= VIDEO_MODE_SYNC_PULSE; 773 break; 774 } 775 } else { 776 /* 777 * FIXME: Retrieve this info from VBT. 778 * As per the spec when dsi transcoder is operating 779 * in TE GATE mode, TE comes from GPIO 780 * which is UTIL PIN for DSI 0. 781 * Also this GPIO would not be used for other 782 * purposes is an assumption. 783 */ 784 tmp &= ~OP_MODE_MASK; 785 tmp |= CMD_MODE_TE_GATE; 786 tmp |= TE_SOURCE_GPIO; 787 } 788 789 intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 790 } 791 792 /* enable port sync mode if dual link */ 793 if (intel_dsi->dual_link) { 794 for_each_dsi_port(port, intel_dsi->ports) { 795 dsi_trans = dsi_port_to_transcoder(port); 796 intel_de_rmw(display, 797 TRANS_DDI_FUNC_CTL2(display, dsi_trans), 798 0, PORT_SYNC_MODE_ENABLE); 799 } 800 801 /* configure stream splitting */ 802 configure_dual_link_mode(encoder, pipe_config); 803 } 804 805 for_each_dsi_port(port, intel_dsi->ports) { 806 dsi_trans = dsi_port_to_transcoder(port); 807 808 /* select data lane width */ 809 tmp = intel_de_read(display, 810 TRANS_DDI_FUNC_CTL(display, dsi_trans)); 811 tmp &= ~DDI_PORT_WIDTH_MASK; 812 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 813 814 /* select input pipe */ 815 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 816 switch (pipe) { 817 default: 818 MISSING_CASE(pipe); 819 fallthrough; 820 case PIPE_A: 821 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 822 break; 823 case PIPE_B: 824 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 825 break; 826 case PIPE_C: 827 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 828 break; 829 case PIPE_D: 830 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 831 break; 832 } 833 834 /* enable DDI buffer */ 835 tmp |= TRANS_DDI_FUNC_ENABLE; 836 intel_de_write(display, 837 TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp); 838 } 839 840 /* wait for link ready */ 841 for_each_dsi_port(port, intel_dsi->ports) { 842 dsi_trans = dsi_port_to_transcoder(port); 843 if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) & 844 LINK_READY), 2500)) 845 drm_err(display->drm, "DSI link not ready\n"); 846 } 847 } 848 849 static void 850 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 851 const struct intel_crtc_state *crtc_state) 852 { 853 struct intel_display *display = to_intel_display(encoder); 854 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 855 const struct drm_display_mode *adjusted_mode = 856 &crtc_state->hw.adjusted_mode; 857 enum port port; 858 enum transcoder dsi_trans; 859 /* horizontal timings */ 860 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 861 u16 hback_porch; 862 /* vertical timings */ 863 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 864 int mul = 1, div = 1; 865 866 /* 867 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 868 * for slower link speed if DSC is enabled. 869 * 870 * The compression frequency ratio is the ratio between compressed and 871 * non-compressed link speeds, and simplifies down to the ratio between 872 * compressed and non-compressed bpp. 873 */ 874 if (crtc_state->dsc.compression_enable) { 875 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 876 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 877 } 878 879 hactive = adjusted_mode->crtc_hdisplay; 880 881 if (is_vid_mode(intel_dsi)) 882 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 883 else 884 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 885 886 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 887 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 888 hsync_size = hsync_end - hsync_start; 889 hback_porch = (adjusted_mode->crtc_htotal - 890 adjusted_mode->crtc_hsync_end); 891 vactive = adjusted_mode->crtc_vdisplay; 892 893 if (is_vid_mode(intel_dsi)) { 894 vtotal = adjusted_mode->crtc_vtotal; 895 } else { 896 int bpp, line_time_us, byte_clk_period_ns; 897 898 if (crtc_state->dsc.compression_enable) 899 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 900 else 901 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 902 903 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 904 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 905 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 906 } 907 vsync_start = adjusted_mode->crtc_vsync_start; 908 vsync_end = adjusted_mode->crtc_vsync_end; 909 vsync_shift = hsync_start - htotal / 2; 910 911 if (intel_dsi->dual_link) { 912 hactive /= 2; 913 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 914 hactive += intel_dsi->pixel_overlap; 915 htotal /= 2; 916 } 917 918 /* minimum hactive as per bspec: 256 pixels */ 919 if (adjusted_mode->crtc_hdisplay < 256) 920 drm_err(display->drm, "hactive is less then 256 pixels\n"); 921 922 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 923 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 924 drm_err(display->drm, 925 "hactive pixels are not multiple of 4\n"); 926 927 /* program TRANS_HTOTAL register */ 928 for_each_dsi_port(port, intel_dsi->ports) { 929 dsi_trans = dsi_port_to_transcoder(port); 930 intel_de_write(display, TRANS_HTOTAL(display, dsi_trans), 931 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); 932 } 933 934 /* TRANS_HSYNC register to be programmed only for video mode */ 935 if (is_vid_mode(intel_dsi)) { 936 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 937 /* BSPEC: hsync size should be atleast 16 pixels */ 938 if (hsync_size < 16) 939 drm_err(display->drm, 940 "hsync size < 16 pixels\n"); 941 } 942 943 if (hback_porch < 16) 944 drm_err(display->drm, "hback porch < 16 pixels\n"); 945 946 if (intel_dsi->dual_link) { 947 hsync_start /= 2; 948 hsync_end /= 2; 949 } 950 951 for_each_dsi_port(port, intel_dsi->ports) { 952 dsi_trans = dsi_port_to_transcoder(port); 953 intel_de_write(display, 954 TRANS_HSYNC(display, dsi_trans), 955 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); 956 } 957 } 958 959 /* program TRANS_VTOTAL register */ 960 for_each_dsi_port(port, intel_dsi->ports) { 961 dsi_trans = dsi_port_to_transcoder(port); 962 /* 963 * FIXME: Programing this by assuming progressive mode, since 964 * non-interlaced info from VBT is not saved inside 965 * struct drm_display_mode. 966 * For interlace mode: program required pixel minus 2 967 */ 968 intel_de_write(display, TRANS_VTOTAL(display, dsi_trans), 969 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); 970 } 971 972 if (vsync_end < vsync_start || vsync_end > vtotal) 973 drm_err(display->drm, "Invalid vsync_end value\n"); 974 975 if (vsync_start < vactive) 976 drm_err(display->drm, "vsync_start less than vactive\n"); 977 978 /* program TRANS_VSYNC register for video mode only */ 979 if (is_vid_mode(intel_dsi)) { 980 for_each_dsi_port(port, intel_dsi->ports) { 981 dsi_trans = dsi_port_to_transcoder(port); 982 intel_de_write(display, 983 TRANS_VSYNC(display, dsi_trans), 984 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); 985 } 986 } 987 988 /* 989 * FIXME: It has to be programmed only for video modes and interlaced 990 * modes. Put the check condition here once interlaced 991 * info available as described above. 992 * program TRANS_VSYNCSHIFT register 993 */ 994 if (is_vid_mode(intel_dsi)) { 995 for_each_dsi_port(port, intel_dsi->ports) { 996 dsi_trans = dsi_port_to_transcoder(port); 997 intel_de_write(display, 998 TRANS_VSYNCSHIFT(display, dsi_trans), 999 vsync_shift); 1000 } 1001 } 1002 1003 /* 1004 * program TRANS_VBLANK register, should be same as vtotal programmed 1005 * 1006 * FIXME get rid of these local hacks and do it right, 1007 * this will not handle eg. delayed vblank correctly. 1008 */ 1009 if (DISPLAY_VER(display) >= 12) { 1010 for_each_dsi_port(port, intel_dsi->ports) { 1011 dsi_trans = dsi_port_to_transcoder(port); 1012 intel_de_write(display, 1013 TRANS_VBLANK(display, dsi_trans), 1014 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); 1015 } 1016 } 1017 } 1018 1019 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1020 { 1021 struct intel_display *display = to_intel_display(encoder); 1022 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1023 enum port port; 1024 enum transcoder dsi_trans; 1025 1026 for_each_dsi_port(port, intel_dsi->ports) { 1027 dsi_trans = dsi_port_to_transcoder(port); 1028 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0, 1029 TRANSCONF_ENABLE); 1030 1031 /* wait for transcoder to be enabled */ 1032 if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans), 1033 TRANSCONF_STATE_ENABLE, 10)) 1034 drm_err(display->drm, 1035 "DSI transcoder not enabled\n"); 1036 } 1037 } 1038 1039 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1040 const struct intel_crtc_state *crtc_state) 1041 { 1042 struct intel_display *display = to_intel_display(encoder); 1043 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1044 enum port port; 1045 enum transcoder dsi_trans; 1046 u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1047 1048 /* 1049 * escape clock count calculation: 1050 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1051 * UI (nsec) = (10^6)/Bitrate 1052 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1053 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1054 */ 1055 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1056 mul = 8 * 1000000; 1057 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1058 divisor); 1059 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1060 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1061 1062 for_each_dsi_port(port, intel_dsi->ports) { 1063 dsi_trans = dsi_port_to_transcoder(port); 1064 1065 /* program hst_tx_timeout */ 1066 intel_de_rmw(display, DSI_HSTX_TO(dsi_trans), 1067 HSTX_TIMEOUT_VALUE_MASK, 1068 HSTX_TIMEOUT_VALUE(hs_tx_timeout)); 1069 1070 /* FIXME: DSI_CALIB_TO */ 1071 1072 /* program lp_rx_host timeout */ 1073 intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans), 1074 LPRX_TIMEOUT_VALUE_MASK, 1075 LPRX_TIMEOUT_VALUE(lp_rx_timeout)); 1076 1077 /* FIXME: DSI_PWAIT_TO */ 1078 1079 /* program turn around timeout */ 1080 intel_de_rmw(display, DSI_TA_TO(dsi_trans), 1081 TA_TIMEOUT_VALUE_MASK, 1082 TA_TIMEOUT_VALUE(ta_timeout)); 1083 } 1084 } 1085 1086 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1087 bool enable) 1088 { 1089 struct intel_display *display = to_intel_display(encoder); 1090 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1091 u32 tmp; 1092 1093 /* 1094 * used as TE i/p for DSI0, 1095 * for dual link/DSI1 TE is from slave DSI1 1096 * through GPIO. 1097 */ 1098 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1099 return; 1100 1101 tmp = intel_de_read(display, UTIL_PIN_CTL); 1102 1103 if (enable) { 1104 tmp |= UTIL_PIN_DIRECTION_INPUT; 1105 tmp |= UTIL_PIN_ENABLE; 1106 } else { 1107 tmp &= ~UTIL_PIN_ENABLE; 1108 } 1109 intel_de_write(display, UTIL_PIN_CTL, tmp); 1110 } 1111 1112 static void 1113 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1114 const struct intel_crtc_state *crtc_state) 1115 { 1116 /* step 4a: power up all lanes of the DDI used by DSI */ 1117 gen11_dsi_power_up_lanes(encoder); 1118 1119 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1120 gen11_dsi_config_phy_lanes_sequence(encoder); 1121 1122 /* step 4c: configure voltage swing and skew */ 1123 gen11_dsi_voltage_swing_program_seq(encoder); 1124 1125 /* setup D-PHY timings */ 1126 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1127 1128 /* enable DDI buffer */ 1129 gen11_dsi_enable_ddi_buffer(encoder); 1130 1131 gen11_dsi_gate_clocks(encoder); 1132 1133 gen11_dsi_setup_timings(encoder, crtc_state); 1134 1135 /* Since transcoder is configured to take events from GPIO */ 1136 gen11_dsi_config_util_pin(encoder, true); 1137 1138 /* step 4h: setup DSI protocol timeouts */ 1139 gen11_dsi_setup_timeouts(encoder, crtc_state); 1140 1141 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1142 gen11_dsi_configure_transcoder(encoder, crtc_state); 1143 } 1144 1145 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1146 { 1147 struct intel_display *display = to_intel_display(encoder); 1148 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1149 struct mipi_dsi_device *dsi; 1150 enum port port; 1151 enum transcoder dsi_trans; 1152 u32 tmp; 1153 int ret; 1154 1155 /* set maximum return packet size */ 1156 for_each_dsi_port(port, intel_dsi->ports) { 1157 dsi_trans = dsi_port_to_transcoder(port); 1158 1159 /* 1160 * FIXME: This uses the number of DW's currently in the payload 1161 * receive queue. This is probably not what we want here. 1162 */ 1163 tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans)); 1164 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1165 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1166 tmp = tmp * 4; 1167 dsi = intel_dsi->dsi_hosts[port]->device; 1168 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1169 if (ret < 0) 1170 drm_err(display->drm, 1171 "error setting max return pkt size%d\n", tmp); 1172 } 1173 1174 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1175 1176 /* ensure all panel commands dispatched before enabling transcoder */ 1177 wait_for_cmds_dispatched_to_panel(encoder); 1178 } 1179 1180 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1181 struct intel_encoder *encoder, 1182 const struct intel_crtc_state *crtc_state, 1183 const struct drm_connector_state *conn_state) 1184 { 1185 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1186 1187 intel_dsi_wait_panel_power_cycle(intel_dsi); 1188 1189 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1190 msleep(intel_dsi->panel_on_delay); 1191 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1192 1193 /* step2: enable IO power */ 1194 gen11_dsi_enable_io_power(encoder); 1195 1196 /* step3: enable DSI PLL */ 1197 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1198 } 1199 1200 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1201 struct intel_encoder *encoder, 1202 const struct intel_crtc_state *pipe_config, 1203 const struct drm_connector_state *conn_state) 1204 { 1205 /* step3b */ 1206 gen11_dsi_map_pll(encoder, pipe_config); 1207 1208 /* step4: enable DSI port and DPHY */ 1209 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1210 1211 /* step5: program and powerup panel */ 1212 gen11_dsi_powerup_panel(encoder); 1213 1214 intel_dsc_dsi_pps_write(encoder, pipe_config); 1215 1216 /* step6c: configure transcoder timings */ 1217 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1218 } 1219 1220 /* 1221 * Wa_1409054076:icl,jsl,ehl 1222 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1223 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1224 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1225 * it set while DSI is enabled on pipe B 1226 */ 1227 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1228 enum pipe pipe, bool enable) 1229 { 1230 struct intel_display *display = to_intel_display(encoder); 1231 1232 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B) 1233 intel_de_rmw(display, CHICKEN_PAR1_1, 1234 IGNORE_KVMR_PIPE_A, 1235 enable ? IGNORE_KVMR_PIPE_A : 0); 1236 } 1237 1238 /* 1239 * Wa_16012360555:adl-p 1240 * SW will have to program the "LP to HS Wakeup Guardband" 1241 * to account for the repeaters on the HS Request/Ready 1242 * PPI signaling between the Display engine and the DPHY. 1243 */ 1244 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1245 { 1246 struct intel_display *display = to_intel_display(encoder); 1247 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1248 enum port port; 1249 1250 if (DISPLAY_VER(display) == 13) { 1251 for_each_dsi_port(port, intel_dsi->ports) 1252 intel_de_rmw(display, TGL_DSI_CHKN_REG(port), 1253 TGL_DSI_CHKN_LSHS_GB_MASK, 1254 TGL_DSI_CHKN_LSHS_GB(4)); 1255 } 1256 } 1257 1258 static void gen11_dsi_enable(struct intel_atomic_state *state, 1259 struct intel_encoder *encoder, 1260 const struct intel_crtc_state *crtc_state, 1261 const struct drm_connector_state *conn_state) 1262 { 1263 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1264 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1265 1266 /* Wa_1409054076:icl,jsl,ehl */ 1267 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1268 1269 /* Wa_16012360555:adl-p */ 1270 adlp_set_lp_hs_wakeup_gb(encoder); 1271 1272 /* step6d: enable dsi transcoder */ 1273 gen11_dsi_enable_transcoder(encoder); 1274 1275 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1276 1277 /* step7: enable backlight */ 1278 intel_backlight_enable(crtc_state, conn_state); 1279 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1280 1281 intel_crtc_vblank_on(crtc_state); 1282 } 1283 1284 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1285 { 1286 struct intel_display *display = to_intel_display(encoder); 1287 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1288 enum port port; 1289 enum transcoder dsi_trans; 1290 1291 for_each_dsi_port(port, intel_dsi->ports) { 1292 dsi_trans = dsi_port_to_transcoder(port); 1293 1294 /* disable transcoder */ 1295 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 1296 TRANSCONF_ENABLE, 0); 1297 1298 /* wait for transcoder to be disabled */ 1299 if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans), 1300 TRANSCONF_STATE_ENABLE, 50)) 1301 drm_err(display->drm, 1302 "DSI trancoder not disabled\n"); 1303 } 1304 } 1305 1306 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1307 { 1308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1309 1310 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1311 1312 /* ensure cmds dispatched to panel */ 1313 wait_for_cmds_dispatched_to_panel(encoder); 1314 } 1315 1316 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1317 { 1318 struct intel_display *display = to_intel_display(encoder); 1319 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1320 enum port port; 1321 enum transcoder dsi_trans; 1322 u32 tmp; 1323 1324 /* disable periodic update mode */ 1325 if (is_cmd_mode(intel_dsi)) { 1326 for_each_dsi_port(port, intel_dsi->ports) 1327 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 1328 DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0); 1329 } 1330 1331 /* put dsi link in ULPS */ 1332 for_each_dsi_port(port, intel_dsi->ports) { 1333 dsi_trans = dsi_port_to_transcoder(port); 1334 tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans)); 1335 tmp |= LINK_ENTER_ULPS; 1336 tmp &= ~LINK_ULPS_TYPE_LP11; 1337 intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp); 1338 1339 if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) & 1340 LINK_IN_ULPS), 1341 10)) 1342 drm_err(display->drm, "DSI link not in ULPS\n"); 1343 } 1344 1345 /* disable ddi function */ 1346 for_each_dsi_port(port, intel_dsi->ports) { 1347 dsi_trans = dsi_port_to_transcoder(port); 1348 intel_de_rmw(display, 1349 TRANS_DDI_FUNC_CTL(display, dsi_trans), 1350 TRANS_DDI_FUNC_ENABLE, 0); 1351 } 1352 1353 /* disable port sync mode if dual link */ 1354 if (intel_dsi->dual_link) { 1355 for_each_dsi_port(port, intel_dsi->ports) { 1356 dsi_trans = dsi_port_to_transcoder(port); 1357 intel_de_rmw(display, 1358 TRANS_DDI_FUNC_CTL2(display, dsi_trans), 1359 PORT_SYNC_MODE_ENABLE, 0); 1360 } 1361 } 1362 } 1363 1364 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1365 { 1366 struct intel_display *display = to_intel_display(encoder); 1367 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1368 enum port port; 1369 1370 gen11_dsi_ungate_clocks(encoder); 1371 for_each_dsi_port(port, intel_dsi->ports) { 1372 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 1373 1374 if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) & 1375 DDI_BUF_IS_IDLE), 1376 8)) 1377 drm_err(display->drm, 1378 "DDI port:%c buffer not idle\n", 1379 port_name(port)); 1380 } 1381 gen11_dsi_gate_clocks(encoder); 1382 } 1383 1384 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1385 { 1386 struct intel_display *display = to_intel_display(encoder); 1387 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1388 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1389 enum port port; 1390 1391 for_each_dsi_port(port, intel_dsi->ports) { 1392 intel_wakeref_t wakeref; 1393 1394 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1395 intel_display_power_put(dev_priv, 1396 port == PORT_A ? 1397 POWER_DOMAIN_PORT_DDI_IO_A : 1398 POWER_DOMAIN_PORT_DDI_IO_B, 1399 wakeref); 1400 } 1401 1402 /* set mode to DDI */ 1403 for_each_dsi_port(port, intel_dsi->ports) 1404 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), 1405 COMBO_PHY_MODE_DSI, 0); 1406 } 1407 1408 static void gen11_dsi_disable(struct intel_atomic_state *state, 1409 struct intel_encoder *encoder, 1410 const struct intel_crtc_state *old_crtc_state, 1411 const struct drm_connector_state *old_conn_state) 1412 { 1413 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1414 1415 /* step1: turn off backlight */ 1416 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1417 intel_backlight_disable(old_conn_state); 1418 } 1419 1420 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1421 struct intel_encoder *encoder, 1422 const struct intel_crtc_state *old_crtc_state, 1423 const struct drm_connector_state *old_conn_state) 1424 { 1425 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1426 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1427 1428 intel_crtc_vblank_off(old_crtc_state); 1429 1430 /* step2d,e: disable transcoder and wait */ 1431 gen11_dsi_disable_transcoder(encoder); 1432 1433 /* Wa_1409054076:icl,jsl,ehl */ 1434 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1435 1436 /* step2f,g: powerdown panel */ 1437 gen11_dsi_powerdown_panel(encoder); 1438 1439 /* step2h,i,j: deconfig trancoder */ 1440 gen11_dsi_deconfigure_trancoder(encoder); 1441 1442 intel_dsc_disable(old_crtc_state); 1443 skl_scaler_disable(old_crtc_state); 1444 1445 /* step3: disable port */ 1446 gen11_dsi_disable_port(encoder); 1447 1448 gen11_dsi_config_util_pin(encoder, false); 1449 1450 /* step4: disable IO power */ 1451 gen11_dsi_disable_io_power(encoder); 1452 1453 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1454 1455 msleep(intel_dsi->panel_off_delay); 1456 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1457 1458 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1459 } 1460 1461 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1462 struct drm_display_mode *mode) 1463 { 1464 struct drm_i915_private *i915 = to_i915(connector->dev); 1465 enum drm_mode_status status; 1466 1467 status = intel_cpu_transcoder_mode_valid(i915, mode); 1468 if (status != MODE_OK) 1469 return status; 1470 1471 /* FIXME: DSC? */ 1472 return intel_dsi_mode_valid(connector, mode); 1473 } 1474 1475 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1476 struct intel_crtc_state *pipe_config) 1477 { 1478 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1479 struct drm_display_mode *adjusted_mode = 1480 &pipe_config->hw.adjusted_mode; 1481 1482 if (pipe_config->dsc.compressed_bpp_x16) { 1483 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); 1484 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1485 1486 adjusted_mode->crtc_htotal = 1487 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1488 adjusted_mode->crtc_hsync_start = 1489 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1490 adjusted_mode->crtc_hsync_end = 1491 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1492 } 1493 1494 if (intel_dsi->dual_link) { 1495 adjusted_mode->crtc_hdisplay *= 2; 1496 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1497 adjusted_mode->crtc_hdisplay -= 1498 intel_dsi->pixel_overlap; 1499 adjusted_mode->crtc_htotal *= 2; 1500 } 1501 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1502 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1503 1504 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1505 if (intel_dsi->dual_link) { 1506 adjusted_mode->crtc_hsync_start *= 2; 1507 adjusted_mode->crtc_hsync_end *= 2; 1508 } 1509 } 1510 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1511 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1512 } 1513 1514 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1515 { 1516 struct intel_display *display = to_intel_display(&intel_dsi->base); 1517 enum transcoder dsi_trans; 1518 u32 val; 1519 1520 if (intel_dsi->ports == BIT(PORT_B)) 1521 dsi_trans = TRANSCODER_DSI_1; 1522 else 1523 dsi_trans = TRANSCODER_DSI_0; 1524 1525 val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 1526 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1527 } 1528 1529 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1530 struct intel_crtc_state *pipe_config) 1531 { 1532 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1533 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1534 I915_MODE_FLAG_DSI_USE_TE0; 1535 else if (intel_dsi->ports == BIT(PORT_B)) 1536 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1537 else 1538 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1539 } 1540 1541 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1542 struct intel_crtc_state *pipe_config) 1543 { 1544 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1545 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1546 1547 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1548 1549 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1550 if (intel_dsi->dual_link) 1551 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1552 1553 gen11_dsi_get_timings(encoder, pipe_config); 1554 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1555 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1556 1557 /* Get the details on which TE should be enabled */ 1558 if (is_cmd_mode(intel_dsi)) 1559 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1560 1561 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1562 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1563 } 1564 1565 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1566 const struct intel_crtc_state *crtc_state) 1567 { 1568 struct intel_display *display = to_intel_display(encoder); 1569 struct intel_crtc *intel_crtc; 1570 enum pipe pipe; 1571 1572 if (!crtc_state) 1573 return; 1574 1575 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1576 pipe = intel_crtc->pipe; 1577 1578 /* wa verify 1409054076:icl,jsl,ehl */ 1579 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B && 1580 !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1581 drm_dbg_kms(display->drm, 1582 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1583 encoder->base.base.id, 1584 encoder->base.name); 1585 } 1586 1587 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1588 struct intel_crtc_state *crtc_state) 1589 { 1590 struct intel_display *display = to_intel_display(encoder); 1591 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1592 int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10; 1593 bool use_dsc; 1594 int ret; 1595 1596 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1597 if (!use_dsc) 1598 return 0; 1599 1600 if (crtc_state->pipe_bpp < 8 * 3) 1601 return -EINVAL; 1602 1603 /* FIXME: split only when necessary */ 1604 if (crtc_state->dsc.slice_count > 1) 1605 crtc_state->dsc.dsc_split = true; 1606 1607 /* FIXME: initialize from VBT */ 1608 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1609 1610 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1611 1612 ret = intel_dsc_compute_params(crtc_state); 1613 if (ret) 1614 return ret; 1615 1616 /* DSI specific sanity checks on the common code */ 1617 drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable); 1618 drm_WARN_ON(display->drm, vdsc_cfg->simple_422); 1619 drm_WARN_ON(display->drm, 1620 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1621 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8); 1622 drm_WARN_ON(display->drm, 1623 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1624 1625 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1626 if (ret) 1627 return ret; 1628 1629 crtc_state->dsc.compression_enable = true; 1630 1631 return 0; 1632 } 1633 1634 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1635 struct intel_crtc_state *pipe_config, 1636 struct drm_connector_state *conn_state) 1637 { 1638 struct intel_display *display = to_intel_display(encoder); 1639 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1640 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1641 struct drm_display_mode *adjusted_mode = 1642 &pipe_config->hw.adjusted_mode; 1643 int ret; 1644 1645 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1646 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1647 1648 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1649 if (ret) 1650 return ret; 1651 1652 ret = intel_panel_fitting(pipe_config, conn_state); 1653 if (ret) 1654 return ret; 1655 1656 adjusted_mode->flags = 0; 1657 1658 /* Dual link goes to trancoder DSI'0' */ 1659 if (intel_dsi->ports == BIT(PORT_B)) 1660 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1661 else 1662 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1663 1664 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1665 pipe_config->pipe_bpp = 24; 1666 else 1667 pipe_config->pipe_bpp = 18; 1668 1669 pipe_config->clock_set = true; 1670 1671 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1672 drm_dbg_kms(display->drm, "Attempting to use DSC failed\n"); 1673 1674 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1675 1676 /* 1677 * In case of TE GATE cmd mode, we 1678 * receive TE from the slave if 1679 * dual link is enabled 1680 */ 1681 if (is_cmd_mode(intel_dsi)) 1682 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1683 1684 return 0; 1685 } 1686 1687 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1688 struct intel_crtc_state *crtc_state) 1689 { 1690 get_dsi_io_power_domains(enc_to_intel_dsi(encoder)); 1691 } 1692 1693 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1694 enum pipe *pipe) 1695 { 1696 struct intel_display *display = to_intel_display(encoder); 1697 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1698 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1699 enum transcoder dsi_trans; 1700 intel_wakeref_t wakeref; 1701 enum port port; 1702 bool ret = false; 1703 u32 tmp; 1704 1705 wakeref = intel_display_power_get_if_enabled(dev_priv, 1706 encoder->power_domain); 1707 if (!wakeref) 1708 return false; 1709 1710 for_each_dsi_port(port, intel_dsi->ports) { 1711 dsi_trans = dsi_port_to_transcoder(port); 1712 tmp = intel_de_read(display, 1713 TRANS_DDI_FUNC_CTL(display, dsi_trans)); 1714 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1715 case TRANS_DDI_EDP_INPUT_A_ON: 1716 *pipe = PIPE_A; 1717 break; 1718 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1719 *pipe = PIPE_B; 1720 break; 1721 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1722 *pipe = PIPE_C; 1723 break; 1724 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1725 *pipe = PIPE_D; 1726 break; 1727 default: 1728 drm_err(display->drm, "Invalid PIPE input\n"); 1729 goto out; 1730 } 1731 1732 tmp = intel_de_read(display, TRANSCONF(display, dsi_trans)); 1733 ret = tmp & TRANSCONF_ENABLE; 1734 } 1735 out: 1736 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1737 return ret; 1738 } 1739 1740 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1741 struct intel_crtc_state *crtc_state) 1742 { 1743 if (crtc_state->dsc.compression_enable) { 1744 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1745 crtc_state->uapi.mode_changed = true; 1746 1747 return false; 1748 } 1749 1750 return true; 1751 } 1752 1753 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1754 { 1755 intel_encoder_destroy(encoder); 1756 } 1757 1758 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1759 .destroy = gen11_dsi_encoder_destroy, 1760 }; 1761 1762 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1763 .detect = intel_panel_detect, 1764 .late_register = intel_connector_register, 1765 .early_unregister = intel_connector_unregister, 1766 .destroy = intel_connector_destroy, 1767 .fill_modes = drm_helper_probe_single_connector_modes, 1768 .atomic_get_property = intel_digital_connector_atomic_get_property, 1769 .atomic_set_property = intel_digital_connector_atomic_set_property, 1770 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1771 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1772 }; 1773 1774 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1775 .get_modes = intel_dsi_get_modes, 1776 .mode_valid = gen11_dsi_mode_valid, 1777 .atomic_check = intel_digital_connector_atomic_check, 1778 }; 1779 1780 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1781 struct mipi_dsi_device *dsi) 1782 { 1783 return 0; 1784 } 1785 1786 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1787 struct mipi_dsi_device *dsi) 1788 { 1789 return 0; 1790 } 1791 1792 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1793 const struct mipi_dsi_msg *msg) 1794 { 1795 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1796 struct mipi_dsi_packet dsi_pkt; 1797 ssize_t ret; 1798 bool enable_lpdt = false; 1799 1800 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1801 if (ret < 0) 1802 return ret; 1803 1804 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1805 enable_lpdt = true; 1806 1807 /* only long packet contains payload */ 1808 if (mipi_dsi_packet_format_is_long(msg->type)) { 1809 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1810 if (ret < 0) 1811 return ret; 1812 } 1813 1814 /* send packet header */ 1815 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1816 if (ret < 0) 1817 return ret; 1818 1819 //TODO: add payload receive code if needed 1820 1821 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1822 1823 return ret; 1824 } 1825 1826 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1827 .attach = gen11_dsi_host_attach, 1828 .detach = gen11_dsi_host_detach, 1829 .transfer = gen11_dsi_host_transfer, 1830 }; 1831 1832 #define ICL_PREPARE_CNT_MAX 0x7 1833 #define ICL_CLK_ZERO_CNT_MAX 0xf 1834 #define ICL_TRAIL_CNT_MAX 0x7 1835 #define ICL_TCLK_PRE_CNT_MAX 0x3 1836 #define ICL_TCLK_POST_CNT_MAX 0x7 1837 #define ICL_HS_ZERO_CNT_MAX 0xf 1838 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1839 1840 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1841 { 1842 struct intel_display *display = to_intel_display(&intel_dsi->base); 1843 struct intel_connector *connector = intel_dsi->attached_connector; 1844 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1845 u32 tlpx_ns; 1846 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1847 u32 ths_prepare_ns, tclk_trail_ns; 1848 u32 hs_zero_cnt; 1849 u32 tclk_pre_cnt; 1850 1851 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1852 1853 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1854 ths_prepare_ns = max(mipi_config->ths_prepare, 1855 mipi_config->tclk_prepare); 1856 1857 /* 1858 * prepare cnt in escape clocks 1859 * this field represents a hexadecimal value with a precision 1860 * of 1.2 – i.e. the most significant bit is the integer 1861 * and the least significant 2 bits are fraction bits. 1862 * so, the field can represent a range of 0.25 to 1.75 1863 */ 1864 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1865 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1866 drm_dbg_kms(display->drm, "prepare_cnt out of range (%d)\n", 1867 prepare_cnt); 1868 prepare_cnt = ICL_PREPARE_CNT_MAX; 1869 } 1870 1871 /* clk zero count in escape clocks */ 1872 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1873 ths_prepare_ns, tlpx_ns); 1874 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1875 drm_dbg_kms(display->drm, 1876 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1877 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1878 } 1879 1880 /* trail cnt in escape clocks*/ 1881 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1882 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1883 drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n", 1884 trail_cnt); 1885 trail_cnt = ICL_TRAIL_CNT_MAX; 1886 } 1887 1888 /* tclk pre count in escape clocks */ 1889 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1890 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1891 drm_dbg_kms(display->drm, 1892 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1893 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1894 } 1895 1896 /* hs zero cnt in escape clocks */ 1897 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1898 ths_prepare_ns, tlpx_ns); 1899 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1900 drm_dbg_kms(display->drm, "hs_zero_cnt out of range (%d)\n", 1901 hs_zero_cnt); 1902 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1903 } 1904 1905 /* hs exit zero cnt in escape clocks */ 1906 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1907 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1908 drm_dbg_kms(display->drm, 1909 "exit_zero_cnt out of range (%d)\n", 1910 exit_zero_cnt); 1911 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1912 } 1913 1914 /* clock lane dphy timings */ 1915 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1916 CLK_PREPARE(prepare_cnt) | 1917 CLK_ZERO_OVERRIDE | 1918 CLK_ZERO(clk_zero_cnt) | 1919 CLK_PRE_OVERRIDE | 1920 CLK_PRE(tclk_pre_cnt) | 1921 CLK_TRAIL_OVERRIDE | 1922 CLK_TRAIL(trail_cnt)); 1923 1924 /* data lanes dphy timings */ 1925 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1926 HS_PREPARE(prepare_cnt) | 1927 HS_ZERO_OVERRIDE | 1928 HS_ZERO(hs_zero_cnt) | 1929 HS_TRAIL_OVERRIDE | 1930 HS_TRAIL(trail_cnt) | 1931 HS_EXIT_OVERRIDE | 1932 HS_EXIT(exit_zero_cnt)); 1933 1934 intel_dsi_log_params(intel_dsi); 1935 } 1936 1937 static void icl_dsi_add_properties(struct intel_connector *connector) 1938 { 1939 const struct drm_display_mode *fixed_mode = 1940 intel_panel_preferred_fixed_mode(connector); 1941 1942 intel_attach_scaling_mode_property(&connector->base); 1943 1944 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1945 intel_dsi_get_panel_orientation(connector), 1946 fixed_mode->hdisplay, 1947 fixed_mode->vdisplay); 1948 } 1949 1950 void icl_dsi_init(struct intel_display *display, 1951 const struct intel_bios_encoder_data *devdata) 1952 { 1953 struct intel_dsi *intel_dsi; 1954 struct intel_encoder *encoder; 1955 struct intel_connector *intel_connector; 1956 struct drm_connector *connector; 1957 enum port port; 1958 1959 port = intel_bios_encoder_port(devdata); 1960 if (port == PORT_NONE) 1961 return; 1962 1963 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1964 if (!intel_dsi) 1965 return; 1966 1967 intel_connector = intel_connector_alloc(); 1968 if (!intel_connector) { 1969 kfree(intel_dsi); 1970 return; 1971 } 1972 1973 encoder = &intel_dsi->base; 1974 intel_dsi->attached_connector = intel_connector; 1975 connector = &intel_connector->base; 1976 1977 encoder->devdata = devdata; 1978 1979 /* register DSI encoder with DRM subsystem */ 1980 drm_encoder_init(display->drm, &encoder->base, 1981 &gen11_dsi_encoder_funcs, 1982 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1983 1984 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1985 encoder->pre_enable = gen11_dsi_pre_enable; 1986 encoder->enable = gen11_dsi_enable; 1987 encoder->disable = gen11_dsi_disable; 1988 encoder->post_disable = gen11_dsi_post_disable; 1989 encoder->port = port; 1990 encoder->get_config = gen11_dsi_get_config; 1991 encoder->sync_state = gen11_dsi_sync_state; 1992 encoder->update_pipe = intel_backlight_update; 1993 encoder->compute_config = gen11_dsi_compute_config; 1994 encoder->get_hw_state = gen11_dsi_get_hw_state; 1995 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 1996 encoder->type = INTEL_OUTPUT_DSI; 1997 encoder->cloneable = 0; 1998 encoder->pipe_mask = ~0; 1999 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 2000 encoder->get_power_domains = gen11_dsi_get_power_domains; 2001 encoder->disable_clock = gen11_dsi_gate_clocks; 2002 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 2003 encoder->shutdown = intel_dsi_shutdown; 2004 2005 /* register DSI connector with DRM subsystem */ 2006 drm_connector_init(display->drm, connector, 2007 &gen11_dsi_connector_funcs, 2008 DRM_MODE_CONNECTOR_DSI); 2009 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 2010 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 2011 intel_connector->get_hw_state = intel_connector_get_hw_state; 2012 2013 /* attach connector to encoder */ 2014 intel_connector_attach_encoder(intel_connector, encoder); 2015 2016 intel_dsi->panel_power_off_time = ktime_get_boottime(); 2017 2018 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL); 2019 2020 mutex_lock(&display->drm->mode_config.mutex); 2021 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 2022 mutex_unlock(&display->drm->mode_config.mutex); 2023 2024 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2025 drm_err(display->drm, "DSI fixed mode info missing\n"); 2026 goto err; 2027 } 2028 2029 intel_panel_init(intel_connector, NULL); 2030 2031 intel_backlight_setup(intel_connector, INVALID_PIPE); 2032 2033 if (intel_connector->panel.vbt.dsi.config->dual_link) 2034 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2035 else 2036 intel_dsi->ports = BIT(port); 2037 2038 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 2039 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 2040 2041 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 2042 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 2043 2044 for_each_dsi_port(port, intel_dsi->ports) { 2045 struct intel_dsi_host *host; 2046 2047 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2048 if (!host) 2049 goto err; 2050 2051 intel_dsi->dsi_hosts[port] = host; 2052 } 2053 2054 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2055 drm_dbg_kms(display->drm, "no device found\n"); 2056 goto err; 2057 } 2058 2059 icl_dphy_param_init(intel_dsi); 2060 2061 icl_dsi_add_properties(intel_connector); 2062 return; 2063 2064 err: 2065 drm_connector_cleanup(connector); 2066 drm_encoder_cleanup(&encoder->base); 2067 kfree(intel_dsi); 2068 kfree(intel_connector); 2069 } 2070