1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/display/drm_dsc_helper.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_fixed.h> 31 #include <drm/drm_mipi_dsi.h> 32 #include <drm/drm_print.h> 33 #include <drm/drm_probe_helper.h> 34 35 #include "i915_reg.h" 36 #include "i915_utils.h" 37 #include "icl_dsi.h" 38 #include "icl_dsi_regs.h" 39 #include "intel_atomic.h" 40 #include "intel_backlight.h" 41 #include "intel_backlight_regs.h" 42 #include "intel_combo_phy.h" 43 #include "intel_combo_phy_regs.h" 44 #include "intel_connector.h" 45 #include "intel_crtc.h" 46 #include "intel_ddi.h" 47 #include "intel_de.h" 48 #include "intel_display_regs.h" 49 #include "intel_dsi.h" 50 #include "intel_dsi_vbt.h" 51 #include "intel_panel.h" 52 #include "intel_pfit.h" 53 #include "intel_vdsc.h" 54 #include "intel_vdsc_regs.h" 55 #include "skl_scaler.h" 56 #include "skl_universal_plane.h" 57 58 static int header_credits_available(struct intel_display *display, 59 enum transcoder dsi_trans) 60 { 61 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 62 >> FREE_HEADER_CREDIT_SHIFT; 63 } 64 65 static int payload_credits_available(struct intel_display *display, 66 enum transcoder dsi_trans) 67 { 68 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 69 >> FREE_PLOAD_CREDIT_SHIFT; 70 } 71 72 static bool wait_for_header_credits(struct intel_display *display, 73 enum transcoder dsi_trans, int hdr_credit) 74 { 75 if (wait_for_us(header_credits_available(display, dsi_trans) >= 76 hdr_credit, 100)) { 77 drm_err(display->drm, "DSI header credits not released\n"); 78 return false; 79 } 80 81 return true; 82 } 83 84 static bool wait_for_payload_credits(struct intel_display *display, 85 enum transcoder dsi_trans, int payld_credit) 86 { 87 if (wait_for_us(payload_credits_available(display, dsi_trans) >= 88 payld_credit, 100)) { 89 drm_err(display->drm, "DSI payload credits not released\n"); 90 return false; 91 } 92 93 return true; 94 } 95 96 static enum transcoder dsi_port_to_transcoder(enum port port) 97 { 98 if (port == PORT_A) 99 return TRANSCODER_DSI_0; 100 else 101 return TRANSCODER_DSI_1; 102 } 103 104 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 105 { 106 struct intel_display *display = to_intel_display(encoder); 107 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 108 struct mipi_dsi_device *dsi; 109 enum port port; 110 enum transcoder dsi_trans; 111 int ret; 112 113 /* wait for header/payload credits to be released */ 114 for_each_dsi_port(port, intel_dsi->ports) { 115 dsi_trans = dsi_port_to_transcoder(port); 116 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT); 117 wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT); 118 } 119 120 /* send nop DCS command */ 121 for_each_dsi_port(port, intel_dsi->ports) { 122 dsi = intel_dsi->dsi_hosts[port]->device; 123 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 124 dsi->channel = 0; 125 ret = mipi_dsi_dcs_nop(dsi); 126 if (ret < 0) 127 drm_err(display->drm, 128 "error sending DCS NOP command\n"); 129 } 130 131 /* wait for header credits to be released */ 132 for_each_dsi_port(port, intel_dsi->ports) { 133 dsi_trans = dsi_port_to_transcoder(port); 134 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT); 135 } 136 137 /* wait for LP TX in progress bit to be cleared */ 138 for_each_dsi_port(port, intel_dsi->ports) { 139 dsi_trans = dsi_port_to_transcoder(port); 140 if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) & 141 LPTX_IN_PROGRESS), 20)) 142 drm_err(display->drm, "LPTX bit not cleared\n"); 143 } 144 } 145 146 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 147 const struct mipi_dsi_packet *packet) 148 { 149 struct intel_dsi *intel_dsi = host->intel_dsi; 150 struct intel_display *display = to_intel_display(&intel_dsi->base); 151 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 152 const u8 *data = packet->payload; 153 u32 len = packet->payload_length; 154 int i, j; 155 156 /* payload queue can accept *256 bytes*, check limit */ 157 if (len > MAX_PLOAD_CREDIT * 4) { 158 drm_err(display->drm, "payload size exceeds max queue limit\n"); 159 return -EINVAL; 160 } 161 162 for (i = 0; i < len; i += 4) { 163 u32 tmp = 0; 164 165 if (!wait_for_payload_credits(display, dsi_trans, 1)) 166 return -EBUSY; 167 168 for (j = 0; j < min_t(u32, len - i, 4); j++) 169 tmp |= *data++ << 8 * j; 170 171 intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp); 172 } 173 174 return 0; 175 } 176 177 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 178 const struct mipi_dsi_packet *packet, 179 bool enable_lpdt) 180 { 181 struct intel_dsi *intel_dsi = host->intel_dsi; 182 struct intel_display *display = to_intel_display(&intel_dsi->base); 183 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 184 u32 tmp; 185 186 if (!wait_for_header_credits(display, dsi_trans, 1)) 187 return -EBUSY; 188 189 tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans)); 190 191 if (packet->payload) 192 tmp |= PAYLOAD_PRESENT; 193 else 194 tmp &= ~PAYLOAD_PRESENT; 195 196 tmp &= ~(VBLANK_FENCE | LP_DATA_TRANSFER | PIPELINE_FLUSH); 197 198 if (enable_lpdt) 199 tmp |= LP_DATA_TRANSFER; 200 else 201 tmp |= PIPELINE_FLUSH; 202 203 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 204 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 205 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 206 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 207 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 208 intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp); 209 210 return 0; 211 } 212 213 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 214 { 215 struct intel_display *display = to_intel_display(crtc_state); 216 u32 mode_flags; 217 enum port port; 218 219 mode_flags = crtc_state->mode_flags; 220 221 /* 222 * case 1 also covers dual link 223 * In case of dual link, frame update should be set on 224 * DSI_0 225 */ 226 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 227 port = PORT_A; 228 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 229 port = PORT_B; 230 else 231 return; 232 233 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0, 234 DSI_FRAME_UPDATE_REQUEST); 235 } 236 237 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 238 { 239 struct intel_display *display = to_intel_display(encoder); 240 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 241 enum phy phy; 242 u32 tmp, mask, val; 243 int lane; 244 245 for_each_dsi_phy(phy, intel_dsi->phys) { 246 /* 247 * Program voltage swing and pre-emphasis level values as per 248 * table in BSPEC under DDI buffer programming. 249 */ 250 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK; 251 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE | 252 RTERM_SELECT(0x6); 253 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 254 tmp &= ~mask; 255 tmp |= val; 256 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 257 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val); 258 259 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 260 RCOMP_SCALAR_MASK; 261 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) | 262 RCOMP_SCALAR(0x98); 263 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); 264 tmp &= ~mask; 265 tmp |= val; 266 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 267 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val); 268 269 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 270 CURSOR_COEFF_MASK; 271 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) | 272 CURSOR_COEFF(0x3f); 273 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val); 274 275 /* Bspec: must not use GRP register for write */ 276 for (lane = 0; lane <= 3; lane++) 277 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), 278 mask, val); 279 } 280 } 281 282 static void configure_dual_link_mode(struct intel_encoder *encoder, 283 const struct intel_crtc_state *pipe_config) 284 { 285 struct intel_display *display = to_intel_display(encoder); 286 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 287 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 288 u32 dss_ctl1; 289 290 /* FIXME: Move all DSS handling to intel_vdsc.c */ 291 if (DISPLAY_VER(display) >= 12) { 292 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 293 294 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); 295 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); 296 } else { 297 dss_ctl1_reg = DSS_CTL1; 298 dss_ctl2_reg = DSS_CTL2; 299 } 300 301 dss_ctl1 = intel_de_read(display, dss_ctl1_reg); 302 dss_ctl1 |= SPLITTER_ENABLE; 303 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 304 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 305 306 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 307 const struct drm_display_mode *adjusted_mode = 308 &pipe_config->hw.adjusted_mode; 309 u16 hactive = adjusted_mode->crtc_hdisplay; 310 u16 dl_buffer_depth; 311 312 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 313 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 314 315 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 316 drm_err(display->drm, 317 "DL buffer depth exceed max value\n"); 318 319 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 320 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 321 intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, 322 RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth)); 323 } else { 324 /* Interleave */ 325 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 326 } 327 328 intel_de_write(display, dss_ctl1_reg, dss_ctl1); 329 } 330 331 /* aka DSI 8X clock */ 332 static int afe_clk(struct intel_encoder *encoder, 333 const struct intel_crtc_state *crtc_state) 334 { 335 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 336 int bpp; 337 338 if (crtc_state->dsc.compression_enable) 339 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 340 else 341 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 342 343 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 344 } 345 346 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 347 const struct intel_crtc_state *crtc_state) 348 { 349 struct intel_display *display = to_intel_display(encoder); 350 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 351 enum port port; 352 int afe_clk_khz; 353 int theo_word_clk, act_word_clk; 354 u32 esc_clk_div_m, esc_clk_div_m_phy; 355 356 afe_clk_khz = afe_clk(encoder, crtc_state); 357 358 if (display->platform.alderlake_s || display->platform.alderlake_p) { 359 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 360 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 361 esc_clk_div_m = act_word_clk * 8; 362 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 363 } else { 364 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 365 } 366 367 for_each_dsi_port(port, intel_dsi->ports) { 368 intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port), 369 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 370 intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port)); 371 } 372 373 for_each_dsi_port(port, intel_dsi->ports) { 374 intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port), 375 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 376 intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port)); 377 } 378 379 if (display->platform.alderlake_s || display->platform.alderlake_p) { 380 for_each_dsi_port(port, intel_dsi->ports) { 381 intel_de_write(display, ADL_MIPIO_DW(port, 8), 382 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 383 intel_de_posting_read(display, ADL_MIPIO_DW(port, 8)); 384 } 385 } 386 } 387 388 static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi) 389 { 390 struct intel_display *display = to_intel_display(&intel_dsi->base); 391 enum port port; 392 393 for_each_dsi_port(port, intel_dsi->ports) { 394 drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]); 395 intel_dsi->io_wakeref[port] = 396 intel_display_power_get(display, 397 port == PORT_A ? 398 POWER_DOMAIN_PORT_DDI_IO_A : 399 POWER_DOMAIN_PORT_DDI_IO_B); 400 } 401 } 402 403 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 404 { 405 struct intel_display *display = to_intel_display(encoder); 406 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 407 enum port port; 408 409 for_each_dsi_port(port, intel_dsi->ports) 410 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), 411 0, COMBO_PHY_MODE_DSI); 412 413 get_dsi_io_power_domains(intel_dsi); 414 } 415 416 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 417 { 418 struct intel_display *display = to_intel_display(encoder); 419 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 420 enum phy phy; 421 422 for_each_dsi_phy(phy, intel_dsi->phys) 423 intel_combo_phy_power_up_lanes(display, phy, true, 424 intel_dsi->lane_count, false); 425 } 426 427 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 428 { 429 struct intel_display *display = to_intel_display(encoder); 430 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 431 enum phy phy; 432 u32 tmp; 433 int lane; 434 435 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 436 for_each_dsi_phy(phy, intel_dsi->phys) { 437 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), 438 LOADGEN_SELECT, 0); 439 for (lane = 0; lane <= 3; lane++) 440 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), 441 LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0); 442 } 443 444 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 445 for_each_dsi_phy(phy, intel_dsi->phys) { 446 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), 447 FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5)); 448 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); 449 tmp &= ~FRC_LATENCY_OPTIM_MASK; 450 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 451 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 452 453 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 454 if (display->platform.jasperlake || display->platform.elkhartlake || 455 (DISPLAY_VER(display) >= 12)) { 456 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), 457 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0)); 458 459 tmp = intel_de_read(display, 460 ICL_PORT_PCS_DW1_LN(0, phy)); 461 tmp &= ~LATENCY_OPTIM_MASK; 462 tmp |= LATENCY_OPTIM_VAL(0x1); 463 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), 464 tmp); 465 } 466 } 467 468 } 469 470 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 471 { 472 struct intel_display *display = to_intel_display(encoder); 473 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 474 u32 tmp; 475 enum phy phy; 476 477 /* clear common keeper enable bit */ 478 for_each_dsi_phy(phy, intel_dsi->phys) { 479 tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 480 tmp &= ~COMMON_KEEPER_EN; 481 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp); 482 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0); 483 } 484 485 /* 486 * Set SUS Clock Config bitfield to 11b 487 * Note: loadgen select program is done 488 * as part of lane phy sequence configuration 489 */ 490 for_each_dsi_phy(phy, intel_dsi->phys) 491 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0, 492 SUS_CLOCK_CONFIG); 493 494 /* Clear training enable to change swing values */ 495 for_each_dsi_phy(phy, intel_dsi->phys) { 496 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 497 tmp &= ~TX_TRAINING_EN; 498 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 499 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0); 500 } 501 502 /* Program swing and de-emphasis */ 503 dsi_program_swing_and_deemphasis(encoder); 504 505 /* Set training enable to trigger update */ 506 for_each_dsi_phy(phy, intel_dsi->phys) { 507 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 508 tmp |= TX_TRAINING_EN; 509 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 510 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN); 511 } 512 } 513 514 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 515 { 516 struct intel_display *display = to_intel_display(encoder); 517 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 518 enum port port; 519 520 for_each_dsi_port(port, intel_dsi->ports) { 521 intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE); 522 523 if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) & 524 DDI_BUF_IS_IDLE), 525 500)) 526 drm_err(display->drm, "DDI port:%c buffer idle\n", 527 port_name(port)); 528 } 529 } 530 531 static void 532 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 533 const struct intel_crtc_state *crtc_state) 534 { 535 struct intel_display *display = to_intel_display(encoder); 536 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 537 enum port port; 538 enum phy phy; 539 540 /* Program DPHY clock lanes timings */ 541 for_each_dsi_port(port, intel_dsi->ports) 542 intel_de_write(display, DPHY_CLK_TIMING_PARAM(port), 543 intel_dsi->dphy_reg); 544 545 /* Program DPHY data lanes timings */ 546 for_each_dsi_port(port, intel_dsi->ports) 547 intel_de_write(display, DPHY_DATA_TIMING_PARAM(port), 548 intel_dsi->dphy_data_lane_reg); 549 550 /* 551 * If DSI link operating at or below an 800 MHz, 552 * TA_SURE should be override and programmed to 553 * a value '0' inside TA_PARAM_REGISTERS otherwise 554 * leave all fields at HW default values. 555 */ 556 if (DISPLAY_VER(display) == 11) { 557 if (afe_clk(encoder, crtc_state) <= 800000) { 558 for_each_dsi_port(port, intel_dsi->ports) 559 intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port), 560 TA_SURE_MASK, 561 TA_SURE_OVERRIDE | TA_SURE(0)); 562 } 563 } 564 565 if (display->platform.jasperlake || display->platform.elkhartlake) { 566 for_each_dsi_phy(phy, intel_dsi->phys) 567 intel_de_rmw(display, ICL_DPHY_CHKN(phy), 568 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP); 569 } 570 } 571 572 static void 573 gen11_dsi_setup_timings(struct intel_encoder *encoder, 574 const struct intel_crtc_state *crtc_state) 575 { 576 struct intel_display *display = to_intel_display(encoder); 577 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 578 enum port port; 579 580 /* Program T-INIT master registers */ 581 for_each_dsi_port(port, intel_dsi->ports) 582 intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port), 583 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); 584 585 /* shadow register inside display core */ 586 for_each_dsi_port(port, intel_dsi->ports) 587 intel_de_write(display, DSI_CLK_TIMING_PARAM(port), 588 intel_dsi->dphy_reg); 589 590 /* shadow register inside display core */ 591 for_each_dsi_port(port, intel_dsi->ports) 592 intel_de_write(display, DSI_DATA_TIMING_PARAM(port), 593 intel_dsi->dphy_data_lane_reg); 594 595 /* shadow register inside display core */ 596 if (DISPLAY_VER(display) == 11) { 597 if (afe_clk(encoder, crtc_state) <= 800000) { 598 for_each_dsi_port(port, intel_dsi->ports) { 599 intel_de_rmw(display, DSI_TA_TIMING_PARAM(port), 600 TA_SURE_MASK, 601 TA_SURE_OVERRIDE | TA_SURE(0)); 602 } 603 } 604 } 605 } 606 607 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 608 { 609 struct intel_display *display = to_intel_display(encoder); 610 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 611 u32 tmp; 612 enum phy phy; 613 614 mutex_lock(&display->dpll.lock); 615 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 616 for_each_dsi_phy(phy, intel_dsi->phys) 617 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 618 619 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); 620 mutex_unlock(&display->dpll.lock); 621 } 622 623 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 624 { 625 struct intel_display *display = to_intel_display(encoder); 626 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 627 u32 tmp; 628 enum phy phy; 629 630 mutex_lock(&display->dpll.lock); 631 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 632 for_each_dsi_phy(phy, intel_dsi->phys) 633 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 634 635 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); 636 mutex_unlock(&display->dpll.lock); 637 } 638 639 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 640 { 641 struct intel_display *display = to_intel_display(encoder); 642 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 643 bool clock_enabled = false; 644 enum phy phy; 645 u32 tmp; 646 647 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 648 649 for_each_dsi_phy(phy, intel_dsi->phys) { 650 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 651 clock_enabled = true; 652 } 653 654 return clock_enabled; 655 } 656 657 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 658 const struct intel_crtc_state *crtc_state) 659 { 660 struct intel_display *display = to_intel_display(encoder); 661 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 662 struct intel_dpll *pll = crtc_state->intel_dpll; 663 enum phy phy; 664 u32 val; 665 666 mutex_lock(&display->dpll.lock); 667 668 val = intel_de_read(display, ICL_DPCLKA_CFGCR0); 669 for_each_dsi_phy(phy, intel_dsi->phys) { 670 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 671 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 672 } 673 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); 674 675 for_each_dsi_phy(phy, intel_dsi->phys) { 676 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 677 } 678 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); 679 680 intel_de_posting_read(display, ICL_DPCLKA_CFGCR0); 681 682 mutex_unlock(&display->dpll.lock); 683 } 684 685 static void 686 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 687 const struct intel_crtc_state *pipe_config) 688 { 689 struct intel_display *display = to_intel_display(encoder); 690 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 691 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 692 enum pipe pipe = crtc->pipe; 693 u32 tmp; 694 enum port port; 695 enum transcoder dsi_trans; 696 697 for_each_dsi_port(port, intel_dsi->ports) { 698 dsi_trans = dsi_port_to_transcoder(port); 699 tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 700 701 if (intel_dsi->eotp_pkt) 702 tmp &= ~EOTP_DISABLED; 703 else 704 tmp |= EOTP_DISABLED; 705 706 /* enable link calibration if freq > 1.5Gbps */ 707 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 708 tmp &= ~LINK_CALIBRATION_MASK; 709 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 710 } 711 712 /* configure continuous clock */ 713 tmp &= ~CONTINUOUS_CLK_MASK; 714 if (intel_dsi->clock_stop) 715 tmp |= CLK_ENTER_LP_AFTER_DATA; 716 else 717 tmp |= CLK_HS_CONTINUOUS; 718 719 /* configure buffer threshold limit to minimum */ 720 tmp &= ~PIX_BUF_THRESHOLD_MASK; 721 tmp |= PIX_BUF_THRESHOLD_1_4; 722 723 /* set virtual channel to '0' */ 724 tmp &= ~PIX_VIRT_CHAN_MASK; 725 tmp |= PIX_VIRT_CHAN(0); 726 727 /* program BGR transmission */ 728 if (intel_dsi->bgr_enabled) 729 tmp |= BGR_TRANSMISSION; 730 731 /* select pixel format */ 732 tmp &= ~PIX_FMT_MASK; 733 if (pipe_config->dsc.compression_enable) { 734 tmp |= PIX_FMT_COMPRESSED; 735 } else { 736 switch (intel_dsi->pixel_format) { 737 default: 738 MISSING_CASE(intel_dsi->pixel_format); 739 fallthrough; 740 case MIPI_DSI_FMT_RGB565: 741 tmp |= PIX_FMT_RGB565; 742 break; 743 case MIPI_DSI_FMT_RGB666_PACKED: 744 tmp |= PIX_FMT_RGB666_PACKED; 745 break; 746 case MIPI_DSI_FMT_RGB666: 747 tmp |= PIX_FMT_RGB666_LOOSE; 748 break; 749 case MIPI_DSI_FMT_RGB888: 750 tmp |= PIX_FMT_RGB888; 751 break; 752 } 753 } 754 755 if (DISPLAY_VER(display) >= 12) { 756 if (is_vid_mode(intel_dsi)) 757 tmp |= BLANKING_PACKET_ENABLE; 758 } 759 760 /* program DSI operation mode */ 761 if (is_vid_mode(intel_dsi)) { 762 tmp &= ~OP_MODE_MASK; 763 switch (intel_dsi->video_mode) { 764 default: 765 MISSING_CASE(intel_dsi->video_mode); 766 fallthrough; 767 case NON_BURST_SYNC_EVENTS: 768 tmp |= VIDEO_MODE_SYNC_EVENT; 769 break; 770 case NON_BURST_SYNC_PULSE: 771 tmp |= VIDEO_MODE_SYNC_PULSE; 772 break; 773 } 774 } else { 775 /* 776 * FIXME: Retrieve this info from VBT. 777 * As per the spec when dsi transcoder is operating 778 * in TE GATE mode, TE comes from GPIO 779 * which is UTIL PIN for DSI 0. 780 * Also this GPIO would not be used for other 781 * purposes is an assumption. 782 */ 783 tmp &= ~OP_MODE_MASK; 784 tmp |= CMD_MODE_TE_GATE; 785 tmp |= TE_SOURCE_GPIO; 786 } 787 788 intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 789 } 790 791 /* enable port sync mode if dual link */ 792 if (intel_dsi->dual_link) { 793 for_each_dsi_port(port, intel_dsi->ports) { 794 dsi_trans = dsi_port_to_transcoder(port); 795 intel_de_rmw(display, 796 TRANS_DDI_FUNC_CTL2(display, dsi_trans), 797 0, PORT_SYNC_MODE_ENABLE); 798 } 799 800 /* configure stream splitting */ 801 configure_dual_link_mode(encoder, pipe_config); 802 } 803 804 for_each_dsi_port(port, intel_dsi->ports) { 805 dsi_trans = dsi_port_to_transcoder(port); 806 807 /* select data lane width */ 808 tmp = intel_de_read(display, 809 TRANS_DDI_FUNC_CTL(display, dsi_trans)); 810 tmp &= ~TRANS_DDI_PORT_WIDTH_MASK; 811 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); 812 813 /* select input pipe */ 814 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 815 switch (pipe) { 816 default: 817 MISSING_CASE(pipe); 818 fallthrough; 819 case PIPE_A: 820 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 821 break; 822 case PIPE_B: 823 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 824 break; 825 case PIPE_C: 826 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 827 break; 828 case PIPE_D: 829 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 830 break; 831 } 832 833 /* enable DDI buffer */ 834 tmp |= TRANS_DDI_FUNC_ENABLE; 835 intel_de_write(display, 836 TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp); 837 } 838 839 /* wait for link ready */ 840 for_each_dsi_port(port, intel_dsi->ports) { 841 dsi_trans = dsi_port_to_transcoder(port); 842 if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) & 843 LINK_READY), 2500)) 844 drm_err(display->drm, "DSI link not ready\n"); 845 } 846 } 847 848 static void 849 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 850 const struct intel_crtc_state *crtc_state) 851 { 852 struct intel_display *display = to_intel_display(encoder); 853 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 854 const struct drm_display_mode *adjusted_mode = 855 &crtc_state->hw.adjusted_mode; 856 enum port port; 857 enum transcoder dsi_trans; 858 /* horizontal timings */ 859 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 860 u16 hback_porch; 861 /* vertical timings */ 862 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 863 int mul = 1, div = 1; 864 865 /* 866 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 867 * for slower link speed if DSC is enabled. 868 * 869 * The compression frequency ratio is the ratio between compressed and 870 * non-compressed link speeds, and simplifies down to the ratio between 871 * compressed and non-compressed bpp. 872 */ 873 if (crtc_state->dsc.compression_enable) { 874 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 875 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 876 } 877 878 hactive = adjusted_mode->crtc_hdisplay; 879 880 if (is_vid_mode(intel_dsi)) 881 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 882 else 883 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 884 885 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 886 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 887 hsync_size = hsync_end - hsync_start; 888 hback_porch = (adjusted_mode->crtc_htotal - 889 adjusted_mode->crtc_hsync_end); 890 vactive = adjusted_mode->crtc_vdisplay; 891 892 if (is_vid_mode(intel_dsi)) { 893 vtotal = adjusted_mode->crtc_vtotal; 894 } else { 895 int bpp, line_time_us, byte_clk_period_ns; 896 897 if (crtc_state->dsc.compression_enable) 898 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 899 else 900 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 901 902 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 903 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 904 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 905 } 906 vsync_start = adjusted_mode->crtc_vsync_start; 907 vsync_end = adjusted_mode->crtc_vsync_end; 908 vsync_shift = hsync_start - htotal / 2; 909 910 if (intel_dsi->dual_link) { 911 hactive /= 2; 912 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 913 hactive += intel_dsi->pixel_overlap; 914 htotal /= 2; 915 } 916 917 /* minimum hactive as per bspec: 256 pixels */ 918 if (adjusted_mode->crtc_hdisplay < 256) 919 drm_err(display->drm, "hactive is less then 256 pixels\n"); 920 921 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 922 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 923 drm_err(display->drm, 924 "hactive pixels are not multiple of 4\n"); 925 926 /* program TRANS_HTOTAL register */ 927 for_each_dsi_port(port, intel_dsi->ports) { 928 dsi_trans = dsi_port_to_transcoder(port); 929 intel_de_write(display, TRANS_HTOTAL(display, dsi_trans), 930 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); 931 } 932 933 /* TRANS_HSYNC register to be programmed only for video mode */ 934 if (is_vid_mode(intel_dsi)) { 935 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 936 /* BSPEC: hsync size should be atleast 16 pixels */ 937 if (hsync_size < 16) 938 drm_err(display->drm, 939 "hsync size < 16 pixels\n"); 940 } 941 942 if (hback_porch < 16) 943 drm_err(display->drm, "hback porch < 16 pixels\n"); 944 945 if (intel_dsi->dual_link) { 946 hsync_start /= 2; 947 hsync_end /= 2; 948 } 949 950 for_each_dsi_port(port, intel_dsi->ports) { 951 dsi_trans = dsi_port_to_transcoder(port); 952 intel_de_write(display, 953 TRANS_HSYNC(display, dsi_trans), 954 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); 955 } 956 } 957 958 /* program TRANS_VTOTAL register */ 959 for_each_dsi_port(port, intel_dsi->ports) { 960 dsi_trans = dsi_port_to_transcoder(port); 961 /* 962 * FIXME: Programming this by assuming progressive mode, since 963 * non-interlaced info from VBT is not saved inside 964 * struct drm_display_mode. 965 * For interlace mode: program required pixel minus 2 966 */ 967 intel_de_write(display, TRANS_VTOTAL(display, dsi_trans), 968 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); 969 } 970 971 if (vsync_end < vsync_start || vsync_end > vtotal) 972 drm_err(display->drm, "Invalid vsync_end value\n"); 973 974 if (vsync_start < vactive) 975 drm_err(display->drm, "vsync_start less than vactive\n"); 976 977 /* program TRANS_VSYNC register for video mode only */ 978 if (is_vid_mode(intel_dsi)) { 979 for_each_dsi_port(port, intel_dsi->ports) { 980 dsi_trans = dsi_port_to_transcoder(port); 981 intel_de_write(display, 982 TRANS_VSYNC(display, dsi_trans), 983 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); 984 } 985 } 986 987 /* 988 * FIXME: It has to be programmed only for video modes and interlaced 989 * modes. Put the check condition here once interlaced 990 * info available as described above. 991 * program TRANS_VSYNCSHIFT register 992 */ 993 if (is_vid_mode(intel_dsi)) { 994 for_each_dsi_port(port, intel_dsi->ports) { 995 dsi_trans = dsi_port_to_transcoder(port); 996 intel_de_write(display, 997 TRANS_VSYNCSHIFT(display, dsi_trans), 998 vsync_shift); 999 } 1000 } 1001 1002 /* 1003 * program TRANS_VBLANK register, should be same as vtotal programmed 1004 * 1005 * FIXME get rid of these local hacks and do it right, 1006 * this will not handle eg. delayed vblank correctly. 1007 */ 1008 if (DISPLAY_VER(display) >= 12) { 1009 for_each_dsi_port(port, intel_dsi->ports) { 1010 dsi_trans = dsi_port_to_transcoder(port); 1011 intel_de_write(display, 1012 TRANS_VBLANK(display, dsi_trans), 1013 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); 1014 } 1015 } 1016 } 1017 1018 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1019 { 1020 struct intel_display *display = to_intel_display(encoder); 1021 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1022 enum port port; 1023 enum transcoder dsi_trans; 1024 1025 for_each_dsi_port(port, intel_dsi->ports) { 1026 dsi_trans = dsi_port_to_transcoder(port); 1027 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0, 1028 TRANSCONF_ENABLE); 1029 1030 /* wait for transcoder to be enabled */ 1031 if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans), 1032 TRANSCONF_STATE_ENABLE, 10)) 1033 drm_err(display->drm, 1034 "DSI transcoder not enabled\n"); 1035 } 1036 } 1037 1038 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1039 const struct intel_crtc_state *crtc_state) 1040 { 1041 struct intel_display *display = to_intel_display(encoder); 1042 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1043 enum port port; 1044 enum transcoder dsi_trans; 1045 u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1046 1047 /* 1048 * escape clock count calculation: 1049 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1050 * UI (nsec) = (10^6)/Bitrate 1051 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1052 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1053 */ 1054 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1055 mul = 8 * 1000000; 1056 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1057 divisor); 1058 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1059 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1060 1061 for_each_dsi_port(port, intel_dsi->ports) { 1062 dsi_trans = dsi_port_to_transcoder(port); 1063 1064 /* program hst_tx_timeout */ 1065 intel_de_rmw(display, DSI_HSTX_TO(dsi_trans), 1066 HSTX_TIMEOUT_VALUE_MASK, 1067 HSTX_TIMEOUT_VALUE(hs_tx_timeout)); 1068 1069 /* FIXME: DSI_CALIB_TO */ 1070 1071 /* program lp_rx_host timeout */ 1072 intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans), 1073 LPRX_TIMEOUT_VALUE_MASK, 1074 LPRX_TIMEOUT_VALUE(lp_rx_timeout)); 1075 1076 /* FIXME: DSI_PWAIT_TO */ 1077 1078 /* program turn around timeout */ 1079 intel_de_rmw(display, DSI_TA_TO(dsi_trans), 1080 TA_TIMEOUT_VALUE_MASK, 1081 TA_TIMEOUT_VALUE(ta_timeout)); 1082 } 1083 } 1084 1085 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1086 bool enable) 1087 { 1088 struct intel_display *display = to_intel_display(encoder); 1089 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1090 u32 tmp; 1091 1092 /* 1093 * used as TE i/p for DSI0, 1094 * for dual link/DSI1 TE is from slave DSI1 1095 * through GPIO. 1096 */ 1097 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1098 return; 1099 1100 tmp = intel_de_read(display, UTIL_PIN_CTL); 1101 1102 if (enable) { 1103 tmp |= UTIL_PIN_DIRECTION_INPUT; 1104 tmp |= UTIL_PIN_ENABLE; 1105 } else { 1106 tmp &= ~UTIL_PIN_ENABLE; 1107 } 1108 intel_de_write(display, UTIL_PIN_CTL, tmp); 1109 } 1110 1111 static void 1112 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1113 const struct intel_crtc_state *crtc_state) 1114 { 1115 /* step 4a: power up all lanes of the DDI used by DSI */ 1116 gen11_dsi_power_up_lanes(encoder); 1117 1118 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1119 gen11_dsi_config_phy_lanes_sequence(encoder); 1120 1121 /* step 4c: configure voltage swing and skew */ 1122 gen11_dsi_voltage_swing_program_seq(encoder); 1123 1124 /* setup D-PHY timings */ 1125 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1126 1127 /* enable DDI buffer */ 1128 gen11_dsi_enable_ddi_buffer(encoder); 1129 1130 gen11_dsi_gate_clocks(encoder); 1131 1132 gen11_dsi_setup_timings(encoder, crtc_state); 1133 1134 /* Since transcoder is configured to take events from GPIO */ 1135 gen11_dsi_config_util_pin(encoder, true); 1136 1137 /* step 4h: setup DSI protocol timeouts */ 1138 gen11_dsi_setup_timeouts(encoder, crtc_state); 1139 1140 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1141 gen11_dsi_configure_transcoder(encoder, crtc_state); 1142 } 1143 1144 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1145 { 1146 struct intel_display *display = to_intel_display(encoder); 1147 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1148 struct mipi_dsi_device *dsi; 1149 enum port port; 1150 enum transcoder dsi_trans; 1151 u32 tmp; 1152 int ret; 1153 1154 /* set maximum return packet size */ 1155 for_each_dsi_port(port, intel_dsi->ports) { 1156 dsi_trans = dsi_port_to_transcoder(port); 1157 1158 /* 1159 * FIXME: This uses the number of DW's currently in the payload 1160 * receive queue. This is probably not what we want here. 1161 */ 1162 tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans)); 1163 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1164 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1165 tmp = tmp * 4; 1166 dsi = intel_dsi->dsi_hosts[port]->device; 1167 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1168 if (ret < 0) 1169 drm_err(display->drm, 1170 "error setting max return pkt size%d\n", tmp); 1171 } 1172 1173 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1174 1175 /* ensure all panel commands dispatched before enabling transcoder */ 1176 wait_for_cmds_dispatched_to_panel(encoder); 1177 } 1178 1179 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1180 struct intel_encoder *encoder, 1181 const struct intel_crtc_state *crtc_state, 1182 const struct drm_connector_state *conn_state) 1183 { 1184 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1185 1186 intel_dsi_wait_panel_power_cycle(intel_dsi); 1187 1188 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1189 msleep(intel_dsi->panel_on_delay); 1190 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1191 1192 /* step2: enable IO power */ 1193 gen11_dsi_enable_io_power(encoder); 1194 1195 /* step3: enable DSI PLL */ 1196 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1197 } 1198 1199 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1200 struct intel_encoder *encoder, 1201 const struct intel_crtc_state *pipe_config, 1202 const struct drm_connector_state *conn_state) 1203 { 1204 /* step3b */ 1205 gen11_dsi_map_pll(encoder, pipe_config); 1206 1207 /* step4: enable DSI port and DPHY */ 1208 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1209 1210 /* step5: program and powerup panel */ 1211 gen11_dsi_powerup_panel(encoder); 1212 1213 intel_dsc_dsi_pps_write(encoder, pipe_config); 1214 1215 /* step6c: configure transcoder timings */ 1216 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1217 } 1218 1219 /* 1220 * Wa_1409054076:icl,jsl,ehl 1221 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1222 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1223 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1224 * it set while DSI is enabled on pipe B 1225 */ 1226 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1227 enum pipe pipe, bool enable) 1228 { 1229 struct intel_display *display = to_intel_display(encoder); 1230 1231 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B) 1232 intel_de_rmw(display, CHICKEN_PAR1_1, 1233 IGNORE_KVMR_PIPE_A, 1234 enable ? IGNORE_KVMR_PIPE_A : 0); 1235 } 1236 1237 /* 1238 * Wa_16012360555:adl-p 1239 * SW will have to program the "LP to HS Wakeup Guardband" 1240 * to account for the repeaters on the HS Request/Ready 1241 * PPI signaling between the Display engine and the DPHY. 1242 */ 1243 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1244 { 1245 struct intel_display *display = to_intel_display(encoder); 1246 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1247 enum port port; 1248 1249 if (DISPLAY_VER(display) == 13) { 1250 for_each_dsi_port(port, intel_dsi->ports) 1251 intel_de_rmw(display, TGL_DSI_CHKN_REG(port), 1252 TGL_DSI_CHKN_LSHS_GB_MASK, 1253 TGL_DSI_CHKN_LSHS_GB(4)); 1254 } 1255 } 1256 1257 static void gen11_dsi_enable(struct intel_atomic_state *state, 1258 struct intel_encoder *encoder, 1259 const struct intel_crtc_state *crtc_state, 1260 const struct drm_connector_state *conn_state) 1261 { 1262 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1263 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1264 1265 /* Wa_1409054076:icl,jsl,ehl */ 1266 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1267 1268 /* Wa_16012360555:adl-p */ 1269 adlp_set_lp_hs_wakeup_gb(encoder); 1270 1271 /* step6d: enable dsi transcoder */ 1272 gen11_dsi_enable_transcoder(encoder); 1273 1274 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1275 1276 /* step7: enable backlight */ 1277 intel_backlight_enable(crtc_state, conn_state); 1278 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1279 1280 intel_panel_prepare(crtc_state, conn_state); 1281 1282 intel_crtc_vblank_on(crtc_state); 1283 } 1284 1285 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1286 { 1287 struct intel_display *display = to_intel_display(encoder); 1288 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1289 enum port port; 1290 enum transcoder dsi_trans; 1291 1292 for_each_dsi_port(port, intel_dsi->ports) { 1293 dsi_trans = dsi_port_to_transcoder(port); 1294 1295 /* disable transcoder */ 1296 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 1297 TRANSCONF_ENABLE, 0); 1298 1299 /* wait for transcoder to be disabled */ 1300 if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans), 1301 TRANSCONF_STATE_ENABLE, 50)) 1302 drm_err(display->drm, 1303 "DSI trancoder not disabled\n"); 1304 } 1305 } 1306 1307 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1308 { 1309 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1310 1311 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1312 1313 /* ensure cmds dispatched to panel */ 1314 wait_for_cmds_dispatched_to_panel(encoder); 1315 } 1316 1317 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1318 { 1319 struct intel_display *display = to_intel_display(encoder); 1320 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1321 enum port port; 1322 enum transcoder dsi_trans; 1323 u32 tmp; 1324 1325 /* disable periodic update mode */ 1326 if (is_cmd_mode(intel_dsi)) { 1327 for_each_dsi_port(port, intel_dsi->ports) 1328 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 1329 DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0); 1330 } 1331 1332 /* put dsi link in ULPS */ 1333 for_each_dsi_port(port, intel_dsi->ports) { 1334 dsi_trans = dsi_port_to_transcoder(port); 1335 tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans)); 1336 tmp |= LINK_ENTER_ULPS; 1337 tmp &= ~LINK_ULPS_TYPE_LP11; 1338 intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp); 1339 1340 if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) & 1341 LINK_IN_ULPS), 1342 10)) 1343 drm_err(display->drm, "DSI link not in ULPS\n"); 1344 } 1345 1346 /* disable ddi function */ 1347 for_each_dsi_port(port, intel_dsi->ports) { 1348 dsi_trans = dsi_port_to_transcoder(port); 1349 intel_de_rmw(display, 1350 TRANS_DDI_FUNC_CTL(display, dsi_trans), 1351 TRANS_DDI_FUNC_ENABLE, 0); 1352 } 1353 1354 /* disable port sync mode if dual link */ 1355 if (intel_dsi->dual_link) { 1356 for_each_dsi_port(port, intel_dsi->ports) { 1357 dsi_trans = dsi_port_to_transcoder(port); 1358 intel_de_rmw(display, 1359 TRANS_DDI_FUNC_CTL2(display, dsi_trans), 1360 PORT_SYNC_MODE_ENABLE, 0); 1361 } 1362 } 1363 } 1364 1365 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1366 { 1367 struct intel_display *display = to_intel_display(encoder); 1368 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1369 enum port port; 1370 1371 gen11_dsi_ungate_clocks(encoder); 1372 for_each_dsi_port(port, intel_dsi->ports) { 1373 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 1374 1375 if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) & 1376 DDI_BUF_IS_IDLE), 1377 8)) 1378 drm_err(display->drm, 1379 "DDI port:%c buffer not idle\n", 1380 port_name(port)); 1381 } 1382 gen11_dsi_gate_clocks(encoder); 1383 } 1384 1385 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1386 { 1387 struct intel_display *display = to_intel_display(encoder); 1388 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1389 enum port port; 1390 1391 for_each_dsi_port(port, intel_dsi->ports) { 1392 intel_wakeref_t wakeref; 1393 1394 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1395 intel_display_power_put(display, 1396 port == PORT_A ? 1397 POWER_DOMAIN_PORT_DDI_IO_A : 1398 POWER_DOMAIN_PORT_DDI_IO_B, 1399 wakeref); 1400 } 1401 1402 /* set mode to DDI */ 1403 for_each_dsi_port(port, intel_dsi->ports) 1404 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), 1405 COMBO_PHY_MODE_DSI, 0); 1406 } 1407 1408 static void gen11_dsi_disable(struct intel_atomic_state *state, 1409 struct intel_encoder *encoder, 1410 const struct intel_crtc_state *old_crtc_state, 1411 const struct drm_connector_state *old_conn_state) 1412 { 1413 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1414 1415 intel_panel_unprepare(old_conn_state); 1416 1417 /* step1: turn off backlight */ 1418 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1419 intel_backlight_disable(old_conn_state); 1420 } 1421 1422 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1423 struct intel_encoder *encoder, 1424 const struct intel_crtc_state *old_crtc_state, 1425 const struct drm_connector_state *old_conn_state) 1426 { 1427 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1428 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1429 1430 intel_crtc_vblank_off(old_crtc_state); 1431 1432 /* step2d,e: disable transcoder and wait */ 1433 gen11_dsi_disable_transcoder(encoder); 1434 1435 /* Wa_1409054076:icl,jsl,ehl */ 1436 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1437 1438 /* step2f,g: powerdown panel */ 1439 gen11_dsi_powerdown_panel(encoder); 1440 1441 /* step2h,i,j: deconfig trancoder */ 1442 gen11_dsi_deconfigure_trancoder(encoder); 1443 1444 intel_dsc_disable(old_crtc_state); 1445 skl_scaler_disable(old_crtc_state); 1446 1447 /* step3: disable port */ 1448 gen11_dsi_disable_port(encoder); 1449 1450 gen11_dsi_config_util_pin(encoder, false); 1451 1452 /* step4: disable IO power */ 1453 gen11_dsi_disable_io_power(encoder); 1454 1455 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1456 1457 msleep(intel_dsi->panel_off_delay); 1458 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1459 1460 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1461 } 1462 1463 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1464 const struct drm_display_mode *mode) 1465 { 1466 struct intel_display *display = to_intel_display(connector->dev); 1467 enum drm_mode_status status; 1468 1469 status = intel_cpu_transcoder_mode_valid(display, mode); 1470 if (status != MODE_OK) 1471 return status; 1472 1473 /* FIXME: DSC? */ 1474 return intel_dsi_mode_valid(connector, mode); 1475 } 1476 1477 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1478 struct intel_crtc_state *pipe_config) 1479 { 1480 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1481 struct drm_display_mode *adjusted_mode = 1482 &pipe_config->hw.adjusted_mode; 1483 1484 if (pipe_config->dsc.compressed_bpp_x16) { 1485 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); 1486 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1487 1488 adjusted_mode->crtc_htotal = 1489 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1490 adjusted_mode->crtc_hsync_start = 1491 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1492 adjusted_mode->crtc_hsync_end = 1493 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1494 } 1495 1496 if (intel_dsi->dual_link) { 1497 adjusted_mode->crtc_hdisplay *= 2; 1498 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1499 adjusted_mode->crtc_hdisplay -= 1500 intel_dsi->pixel_overlap; 1501 adjusted_mode->crtc_htotal *= 2; 1502 } 1503 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1504 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1505 1506 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1507 if (intel_dsi->dual_link) { 1508 adjusted_mode->crtc_hsync_start *= 2; 1509 adjusted_mode->crtc_hsync_end *= 2; 1510 } 1511 } 1512 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1513 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1514 } 1515 1516 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1517 { 1518 struct intel_display *display = to_intel_display(&intel_dsi->base); 1519 enum transcoder dsi_trans; 1520 u32 val; 1521 1522 if (intel_dsi->ports == BIT(PORT_B)) 1523 dsi_trans = TRANSCODER_DSI_1; 1524 else 1525 dsi_trans = TRANSCODER_DSI_0; 1526 1527 val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 1528 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1529 } 1530 1531 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1532 struct intel_crtc_state *pipe_config) 1533 { 1534 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1535 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1536 I915_MODE_FLAG_DSI_USE_TE0; 1537 else if (intel_dsi->ports == BIT(PORT_B)) 1538 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1539 else 1540 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1541 } 1542 1543 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1544 struct intel_crtc_state *pipe_config) 1545 { 1546 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1547 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1548 1549 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1550 1551 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1552 if (intel_dsi->dual_link) 1553 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1554 1555 gen11_dsi_get_timings(encoder, pipe_config); 1556 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1557 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1558 1559 /* Get the details on which TE should be enabled */ 1560 if (is_cmd_mode(intel_dsi)) 1561 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1562 1563 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1564 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1565 } 1566 1567 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1568 const struct intel_crtc_state *crtc_state) 1569 { 1570 struct intel_display *display = to_intel_display(encoder); 1571 struct intel_crtc *intel_crtc; 1572 enum pipe pipe; 1573 1574 if (!crtc_state) 1575 return; 1576 1577 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1578 pipe = intel_crtc->pipe; 1579 1580 /* wa verify 1409054076:icl,jsl,ehl */ 1581 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B && 1582 !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1583 drm_dbg_kms(display->drm, 1584 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1585 encoder->base.base.id, 1586 encoder->base.name); 1587 } 1588 1589 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1590 struct intel_crtc_state *crtc_state) 1591 { 1592 struct intel_display *display = to_intel_display(encoder); 1593 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1594 int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10; 1595 bool use_dsc; 1596 int ret; 1597 1598 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1599 if (!use_dsc) 1600 return 0; 1601 1602 if (crtc_state->pipe_bpp < 8 * 3) 1603 return -EINVAL; 1604 1605 /* FIXME: split only when necessary */ 1606 if (crtc_state->dsc.slice_count > 1) 1607 crtc_state->dsc.num_streams = 2; 1608 else 1609 crtc_state->dsc.num_streams = 1; 1610 1611 /* FIXME: initialize from VBT */ 1612 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1613 1614 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1615 1616 ret = intel_dsc_compute_params(crtc_state); 1617 if (ret) 1618 return ret; 1619 1620 /* DSI specific sanity checks on the common code */ 1621 drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable); 1622 drm_WARN_ON(display->drm, vdsc_cfg->simple_422); 1623 drm_WARN_ON(display->drm, 1624 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1625 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8); 1626 drm_WARN_ON(display->drm, 1627 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1628 1629 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1630 if (ret) 1631 return ret; 1632 1633 crtc_state->dsc.compression_enable = true; 1634 1635 return 0; 1636 } 1637 1638 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1639 struct intel_crtc_state *pipe_config, 1640 struct drm_connector_state *conn_state) 1641 { 1642 struct intel_display *display = to_intel_display(encoder); 1643 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1644 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1645 struct drm_display_mode *adjusted_mode = 1646 &pipe_config->hw.adjusted_mode; 1647 int ret; 1648 1649 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1650 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1651 1652 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1653 if (ret) 1654 return ret; 1655 1656 ret = intel_pfit_compute_config(pipe_config, conn_state); 1657 if (ret) 1658 return ret; 1659 1660 adjusted_mode->flags = 0; 1661 1662 /* Dual link goes to trancoder DSI'0' */ 1663 if (intel_dsi->ports == BIT(PORT_B)) 1664 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1665 else 1666 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1667 1668 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1669 pipe_config->pipe_bpp = 24; 1670 else 1671 pipe_config->pipe_bpp = 18; 1672 1673 pipe_config->clock_set = true; 1674 1675 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1676 drm_dbg_kms(display->drm, "Attempting to use DSC failed\n"); 1677 1678 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1679 1680 /* 1681 * In case of TE GATE cmd mode, we 1682 * receive TE from the slave if 1683 * dual link is enabled 1684 */ 1685 if (is_cmd_mode(intel_dsi)) 1686 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1687 1688 return 0; 1689 } 1690 1691 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1692 struct intel_crtc_state *crtc_state) 1693 { 1694 get_dsi_io_power_domains(enc_to_intel_dsi(encoder)); 1695 } 1696 1697 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1698 enum pipe *pipe) 1699 { 1700 struct intel_display *display = to_intel_display(encoder); 1701 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1702 enum transcoder dsi_trans; 1703 intel_wakeref_t wakeref; 1704 enum port port; 1705 bool ret = false; 1706 u32 tmp; 1707 1708 wakeref = intel_display_power_get_if_enabled(display, 1709 encoder->power_domain); 1710 if (!wakeref) 1711 return false; 1712 1713 for_each_dsi_port(port, intel_dsi->ports) { 1714 dsi_trans = dsi_port_to_transcoder(port); 1715 tmp = intel_de_read(display, 1716 TRANS_DDI_FUNC_CTL(display, dsi_trans)); 1717 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1718 case TRANS_DDI_EDP_INPUT_A_ON: 1719 *pipe = PIPE_A; 1720 break; 1721 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1722 *pipe = PIPE_B; 1723 break; 1724 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1725 *pipe = PIPE_C; 1726 break; 1727 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1728 *pipe = PIPE_D; 1729 break; 1730 default: 1731 drm_err(display->drm, "Invalid PIPE input\n"); 1732 goto out; 1733 } 1734 1735 tmp = intel_de_read(display, TRANSCONF(display, dsi_trans)); 1736 ret = tmp & TRANSCONF_ENABLE; 1737 } 1738 out: 1739 intel_display_power_put(display, encoder->power_domain, wakeref); 1740 return ret; 1741 } 1742 1743 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1744 struct intel_crtc_state *crtc_state) 1745 { 1746 if (crtc_state->dsc.compression_enable) { 1747 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1748 crtc_state->uapi.mode_changed = true; 1749 1750 return false; 1751 } 1752 1753 return true; 1754 } 1755 1756 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1757 { 1758 intel_encoder_destroy(encoder); 1759 } 1760 1761 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1762 .destroy = gen11_dsi_encoder_destroy, 1763 }; 1764 1765 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1766 .detect = intel_panel_detect, 1767 .late_register = intel_connector_register, 1768 .early_unregister = intel_connector_unregister, 1769 .destroy = intel_connector_destroy, 1770 .fill_modes = drm_helper_probe_single_connector_modes, 1771 .atomic_get_property = intel_digital_connector_atomic_get_property, 1772 .atomic_set_property = intel_digital_connector_atomic_set_property, 1773 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1774 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1775 }; 1776 1777 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1778 .get_modes = intel_dsi_get_modes, 1779 .mode_valid = gen11_dsi_mode_valid, 1780 .atomic_check = intel_digital_connector_atomic_check, 1781 }; 1782 1783 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1784 struct mipi_dsi_device *dsi) 1785 { 1786 return 0; 1787 } 1788 1789 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1790 struct mipi_dsi_device *dsi) 1791 { 1792 return 0; 1793 } 1794 1795 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1796 const struct mipi_dsi_msg *msg) 1797 { 1798 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1799 struct mipi_dsi_packet dsi_pkt; 1800 ssize_t ret; 1801 bool enable_lpdt = false; 1802 1803 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1804 if (ret < 0) 1805 return ret; 1806 1807 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1808 enable_lpdt = true; 1809 1810 /* only long packet contains payload */ 1811 if (mipi_dsi_packet_format_is_long(msg->type)) { 1812 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1813 if (ret < 0) 1814 return ret; 1815 } 1816 1817 /* send packet header */ 1818 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1819 if (ret < 0) 1820 return ret; 1821 1822 //TODO: add payload receive code if needed 1823 1824 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1825 1826 return ret; 1827 } 1828 1829 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1830 .attach = gen11_dsi_host_attach, 1831 .detach = gen11_dsi_host_detach, 1832 .transfer = gen11_dsi_host_transfer, 1833 }; 1834 1835 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1836 { 1837 struct intel_connector *connector = intel_dsi->attached_connector; 1838 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1839 u32 tlpx_ns; 1840 u32 tclk_prepare_esc_clk, tclk_zero_esc_clk, tclk_pre_esc_clk; 1841 u32 ths_prepare_esc_clk, ths_zero_esc_clk, ths_exit_esc_clk; 1842 1843 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1844 1845 /* 1846 * The clock and data lane prepare timing parameters are in expressed in 1847 * units of 1/4 escape clocks, and all the other timings parameters in 1848 * escape clocks. 1849 */ 1850 tclk_prepare_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare * 4, tlpx_ns); 1851 tclk_prepare_esc_clk = min(tclk_prepare_esc_clk, 7); 1852 1853 tclk_zero_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1854 mipi_config->tclk_prepare, tlpx_ns); 1855 tclk_zero_esc_clk = min(tclk_zero_esc_clk, 15); 1856 1857 tclk_pre_esc_clk = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1858 tclk_pre_esc_clk = min(tclk_pre_esc_clk, 3); 1859 1860 ths_prepare_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare * 4, tlpx_ns); 1861 ths_prepare_esc_clk = min(ths_prepare_esc_clk, 7); 1862 1863 ths_zero_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1864 mipi_config->ths_prepare, tlpx_ns); 1865 ths_zero_esc_clk = min(ths_zero_esc_clk, 15); 1866 1867 ths_exit_esc_clk = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1868 ths_exit_esc_clk = min(ths_exit_esc_clk, 7); 1869 1870 /* clock lane dphy timings */ 1871 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1872 CLK_PREPARE(tclk_prepare_esc_clk) | 1873 CLK_ZERO_OVERRIDE | 1874 CLK_ZERO(tclk_zero_esc_clk) | 1875 CLK_PRE_OVERRIDE | 1876 CLK_PRE(tclk_pre_esc_clk)); 1877 1878 /* data lanes dphy timings */ 1879 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1880 HS_PREPARE(ths_prepare_esc_clk) | 1881 HS_ZERO_OVERRIDE | 1882 HS_ZERO(ths_zero_esc_clk) | 1883 HS_EXIT_OVERRIDE | 1884 HS_EXIT(ths_exit_esc_clk)); 1885 1886 intel_dsi_log_params(intel_dsi); 1887 } 1888 1889 static void icl_dsi_add_properties(struct intel_connector *connector) 1890 { 1891 const struct drm_display_mode *fixed_mode = 1892 intel_panel_preferred_fixed_mode(connector); 1893 1894 intel_attach_scaling_mode_property(&connector->base); 1895 1896 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1897 intel_dsi_get_panel_orientation(connector), 1898 fixed_mode->hdisplay, 1899 fixed_mode->vdisplay); 1900 } 1901 1902 void icl_dsi_init(struct intel_display *display, 1903 const struct intel_bios_encoder_data *devdata) 1904 { 1905 struct intel_dsi *intel_dsi; 1906 struct intel_encoder *encoder; 1907 struct intel_connector *intel_connector; 1908 struct drm_connector *connector; 1909 enum port port; 1910 1911 port = intel_bios_encoder_port(devdata); 1912 if (port == PORT_NONE) 1913 return; 1914 1915 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1916 if (!intel_dsi) 1917 return; 1918 1919 intel_connector = intel_connector_alloc(); 1920 if (!intel_connector) { 1921 kfree(intel_dsi); 1922 return; 1923 } 1924 1925 encoder = &intel_dsi->base; 1926 intel_dsi->attached_connector = intel_connector; 1927 connector = &intel_connector->base; 1928 1929 encoder->devdata = devdata; 1930 1931 /* register DSI encoder with DRM subsystem */ 1932 drm_encoder_init(display->drm, &encoder->base, 1933 &gen11_dsi_encoder_funcs, 1934 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1935 1936 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1937 encoder->pre_enable = gen11_dsi_pre_enable; 1938 encoder->enable = gen11_dsi_enable; 1939 encoder->disable = gen11_dsi_disable; 1940 encoder->post_disable = gen11_dsi_post_disable; 1941 encoder->port = port; 1942 encoder->get_config = gen11_dsi_get_config; 1943 encoder->sync_state = gen11_dsi_sync_state; 1944 encoder->update_pipe = intel_backlight_update; 1945 encoder->compute_config = gen11_dsi_compute_config; 1946 encoder->get_hw_state = gen11_dsi_get_hw_state; 1947 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 1948 encoder->type = INTEL_OUTPUT_DSI; 1949 encoder->cloneable = 0; 1950 encoder->pipe_mask = ~0; 1951 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1952 encoder->get_power_domains = gen11_dsi_get_power_domains; 1953 encoder->disable_clock = gen11_dsi_gate_clocks; 1954 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 1955 encoder->shutdown = intel_dsi_shutdown; 1956 1957 /* register DSI connector with DRM subsystem */ 1958 drm_connector_init(display->drm, connector, 1959 &gen11_dsi_connector_funcs, 1960 DRM_MODE_CONNECTOR_DSI); 1961 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 1962 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1963 intel_connector->get_hw_state = intel_connector_get_hw_state; 1964 1965 /* attach connector to encoder */ 1966 intel_connector_attach_encoder(intel_connector, encoder); 1967 1968 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1969 1970 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL); 1971 1972 mutex_lock(&display->drm->mode_config.mutex); 1973 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 1974 mutex_unlock(&display->drm->mode_config.mutex); 1975 1976 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 1977 drm_err(display->drm, "DSI fixed mode info missing\n"); 1978 goto err; 1979 } 1980 1981 intel_panel_init(intel_connector, NULL); 1982 1983 intel_backlight_setup(intel_connector, INVALID_PIPE); 1984 1985 if (intel_connector->panel.vbt.dsi.config->dual_link) 1986 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 1987 else 1988 intel_dsi->ports = BIT(port); 1989 1990 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 1991 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 1992 1993 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 1994 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 1995 1996 for_each_dsi_port(port, intel_dsi->ports) { 1997 struct intel_dsi_host *host; 1998 1999 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2000 if (!host) 2001 goto err; 2002 2003 intel_dsi->dsi_hosts[port] = host; 2004 } 2005 2006 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2007 drm_dbg_kms(display->drm, "no device found\n"); 2008 goto err; 2009 } 2010 2011 icl_dphy_param_init(intel_dsi); 2012 2013 icl_dsi_add_properties(intel_connector); 2014 return; 2015 2016 err: 2017 drm_connector_cleanup(connector); 2018 drm_encoder_cleanup(&encoder->base); 2019 kfree(intel_dsi); 2020 kfree(intel_connector); 2021 } 2022