1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <linux/iopoll.h> 29 30 #include <drm/display/drm_dsc_helper.h> 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_fixed.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include "i915_reg.h" 38 #include "i915_utils.h" 39 #include "icl_dsi.h" 40 #include "icl_dsi_regs.h" 41 #include "intel_atomic.h" 42 #include "intel_backlight.h" 43 #include "intel_backlight_regs.h" 44 #include "intel_combo_phy.h" 45 #include "intel_combo_phy_regs.h" 46 #include "intel_connector.h" 47 #include "intel_crtc.h" 48 #include "intel_ddi.h" 49 #include "intel_de.h" 50 #include "intel_display_regs.h" 51 #include "intel_dsi.h" 52 #include "intel_dsi_vbt.h" 53 #include "intel_panel.h" 54 #include "intel_pfit.h" 55 #include "intel_vdsc.h" 56 #include "intel_vdsc_regs.h" 57 #include "skl_scaler.h" 58 #include "skl_universal_plane.h" 59 60 static int header_credits_available(struct intel_display *display, 61 enum transcoder dsi_trans) 62 { 63 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 64 >> FREE_HEADER_CREDIT_SHIFT; 65 } 66 67 static int payload_credits_available(struct intel_display *display, 68 enum transcoder dsi_trans) 69 { 70 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 71 >> FREE_PLOAD_CREDIT_SHIFT; 72 } 73 74 static bool wait_for_header_credits(struct intel_display *display, 75 enum transcoder dsi_trans, int hdr_credit) 76 { 77 int ret, available; 78 79 ret = poll_timeout_us(available = header_credits_available(display, dsi_trans), 80 available >= hdr_credit, 81 10, 100, false); 82 if (ret) { 83 drm_err(display->drm, "DSI header credits not released\n"); 84 return false; 85 } 86 87 return true; 88 } 89 90 static bool wait_for_payload_credits(struct intel_display *display, 91 enum transcoder dsi_trans, int payld_credit) 92 { 93 int ret, available; 94 95 ret = poll_timeout_us(available = payload_credits_available(display, dsi_trans), 96 available >= payld_credit, 97 10, 100, false); 98 if (ret) { 99 drm_err(display->drm, "DSI payload credits not released\n"); 100 return false; 101 } 102 103 return true; 104 } 105 106 static enum transcoder dsi_port_to_transcoder(enum port port) 107 { 108 if (port == PORT_A) 109 return TRANSCODER_DSI_0; 110 else 111 return TRANSCODER_DSI_1; 112 } 113 114 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 115 { 116 struct intel_display *display = to_intel_display(encoder); 117 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 118 struct mipi_dsi_device *dsi; 119 enum port port; 120 enum transcoder dsi_trans; 121 int ret; 122 123 /* wait for header/payload credits to be released */ 124 for_each_dsi_port(port, intel_dsi->ports) { 125 dsi_trans = dsi_port_to_transcoder(port); 126 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT); 127 wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT); 128 } 129 130 /* send nop DCS command */ 131 for_each_dsi_port(port, intel_dsi->ports) { 132 dsi = intel_dsi->dsi_hosts[port]->device; 133 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 134 dsi->channel = 0; 135 ret = mipi_dsi_dcs_nop(dsi); 136 if (ret < 0) 137 drm_err(display->drm, 138 "error sending DCS NOP command\n"); 139 } 140 141 /* wait for header credits to be released */ 142 for_each_dsi_port(port, intel_dsi->ports) { 143 dsi_trans = dsi_port_to_transcoder(port); 144 wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT); 145 } 146 147 /* wait for LP TX in progress bit to be cleared */ 148 for_each_dsi_port(port, intel_dsi->ports) { 149 dsi_trans = dsi_port_to_transcoder(port); 150 151 ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans), 152 LPTX_IN_PROGRESS, 0, 153 20, 0, NULL); 154 if (ret) 155 drm_err(display->drm, "LPTX bit not cleared\n"); 156 } 157 } 158 159 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 160 const struct mipi_dsi_packet *packet) 161 { 162 struct intel_dsi *intel_dsi = host->intel_dsi; 163 struct intel_display *display = to_intel_display(&intel_dsi->base); 164 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 165 const u8 *data = packet->payload; 166 u32 len = packet->payload_length; 167 int i, j; 168 169 /* payload queue can accept *256 bytes*, check limit */ 170 if (len > MAX_PLOAD_CREDIT * 4) { 171 drm_err(display->drm, "payload size exceeds max queue limit\n"); 172 return -EINVAL; 173 } 174 175 for (i = 0; i < len; i += 4) { 176 u32 tmp = 0; 177 178 if (!wait_for_payload_credits(display, dsi_trans, 1)) 179 return -EBUSY; 180 181 for (j = 0; j < min_t(u32, len - i, 4); j++) 182 tmp |= *data++ << 8 * j; 183 184 intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp); 185 } 186 187 return 0; 188 } 189 190 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 191 const struct mipi_dsi_packet *packet, 192 bool enable_lpdt) 193 { 194 struct intel_dsi *intel_dsi = host->intel_dsi; 195 struct intel_display *display = to_intel_display(&intel_dsi->base); 196 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 197 u32 tmp; 198 199 if (!wait_for_header_credits(display, dsi_trans, 1)) 200 return -EBUSY; 201 202 tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans)); 203 204 if (packet->payload) 205 tmp |= PAYLOAD_PRESENT; 206 else 207 tmp &= ~PAYLOAD_PRESENT; 208 209 tmp &= ~(VBLANK_FENCE | LP_DATA_TRANSFER | PIPELINE_FLUSH); 210 211 if (enable_lpdt) 212 tmp |= LP_DATA_TRANSFER; 213 else 214 tmp |= PIPELINE_FLUSH; 215 216 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 217 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); 218 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); 219 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); 220 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); 221 intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp); 222 223 return 0; 224 } 225 226 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state) 227 { 228 struct intel_display *display = to_intel_display(crtc_state); 229 u32 mode_flags; 230 enum port port; 231 232 mode_flags = crtc_state->mode_flags; 233 234 /* 235 * case 1 also covers dual link 236 * In case of dual link, frame update should be set on 237 * DSI_0 238 */ 239 if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0) 240 port = PORT_A; 241 else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1) 242 port = PORT_B; 243 else 244 return; 245 246 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0, 247 DSI_FRAME_UPDATE_REQUEST); 248 } 249 250 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 251 { 252 struct intel_display *display = to_intel_display(encoder); 253 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 254 enum phy phy; 255 u32 tmp, mask, val; 256 int lane; 257 258 for_each_dsi_phy(phy, intel_dsi->phys) { 259 /* 260 * Program voltage swing and pre-emphasis level values as per 261 * table in BSPEC under DDI buffer programming. 262 */ 263 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK; 264 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE | 265 RTERM_SELECT(0x6); 266 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 267 tmp &= ~mask; 268 tmp |= val; 269 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 270 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val); 271 272 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 273 RCOMP_SCALAR_MASK; 274 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) | 275 RCOMP_SCALAR(0x98); 276 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); 277 tmp &= ~mask; 278 tmp |= val; 279 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 280 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val); 281 282 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 283 CURSOR_COEFF_MASK; 284 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) | 285 CURSOR_COEFF(0x3f); 286 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val); 287 288 /* Bspec: must not use GRP register for write */ 289 for (lane = 0; lane <= 3; lane++) 290 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), 291 mask, val); 292 } 293 } 294 295 static void configure_dual_link_mode(struct intel_encoder *encoder, 296 const struct intel_crtc_state *pipe_config) 297 { 298 struct intel_display *display = to_intel_display(encoder); 299 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 300 i915_reg_t dss_ctl1_reg, dss_ctl2_reg; 301 u32 dss_ctl1; 302 303 /* FIXME: Move all DSS handling to intel_vdsc.c */ 304 if (DISPLAY_VER(display) >= 12) { 305 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 306 307 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); 308 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); 309 } else { 310 dss_ctl1_reg = DSS_CTL1; 311 dss_ctl2_reg = DSS_CTL2; 312 } 313 314 dss_ctl1 = intel_de_read(display, dss_ctl1_reg); 315 dss_ctl1 |= SPLITTER_ENABLE; 316 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 317 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 318 319 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 320 const struct drm_display_mode *adjusted_mode = 321 &pipe_config->hw.adjusted_mode; 322 u16 hactive = adjusted_mode->crtc_hdisplay; 323 u16 dl_buffer_depth; 324 325 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 326 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 327 328 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 329 drm_err(display->drm, 330 "DL buffer depth exceed max value\n"); 331 332 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 333 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 334 intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, 335 RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth)); 336 } else { 337 /* Interleave */ 338 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 339 } 340 341 intel_de_write(display, dss_ctl1_reg, dss_ctl1); 342 } 343 344 /* aka DSI 8X clock */ 345 static int afe_clk(struct intel_encoder *encoder, 346 const struct intel_crtc_state *crtc_state) 347 { 348 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 349 int bpp; 350 351 if (crtc_state->dsc.compression_enable) 352 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 353 else 354 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 355 356 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 357 } 358 359 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 360 const struct intel_crtc_state *crtc_state) 361 { 362 struct intel_display *display = to_intel_display(encoder); 363 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 364 enum port port; 365 int afe_clk_khz; 366 int theo_word_clk, act_word_clk; 367 u32 esc_clk_div_m, esc_clk_div_m_phy; 368 369 afe_clk_khz = afe_clk(encoder, crtc_state); 370 371 if (display->platform.alderlake_s || display->platform.alderlake_p) { 372 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); 373 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); 374 esc_clk_div_m = act_word_clk * 8; 375 esc_clk_div_m_phy = (act_word_clk - 1) / 2; 376 } else { 377 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 378 } 379 380 for_each_dsi_port(port, intel_dsi->ports) { 381 intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port), 382 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 383 intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port)); 384 } 385 386 for_each_dsi_port(port, intel_dsi->ports) { 387 intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port), 388 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 389 intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port)); 390 } 391 392 if (display->platform.alderlake_s || display->platform.alderlake_p) { 393 for_each_dsi_port(port, intel_dsi->ports) { 394 intel_de_write(display, ADL_MIPIO_DW(port, 8), 395 esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); 396 intel_de_posting_read(display, ADL_MIPIO_DW(port, 8)); 397 } 398 } 399 } 400 401 static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi) 402 { 403 struct intel_display *display = to_intel_display(&intel_dsi->base); 404 enum port port; 405 406 for_each_dsi_port(port, intel_dsi->ports) { 407 drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]); 408 intel_dsi->io_wakeref[port] = 409 intel_display_power_get(display, 410 port == PORT_A ? 411 POWER_DOMAIN_PORT_DDI_IO_A : 412 POWER_DOMAIN_PORT_DDI_IO_B); 413 } 414 } 415 416 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 417 { 418 struct intel_display *display = to_intel_display(encoder); 419 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 420 enum port port; 421 422 for_each_dsi_port(port, intel_dsi->ports) 423 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), 424 0, COMBO_PHY_MODE_DSI); 425 426 get_dsi_io_power_domains(intel_dsi); 427 } 428 429 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 430 { 431 struct intel_display *display = to_intel_display(encoder); 432 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 433 enum phy phy; 434 435 for_each_dsi_phy(phy, intel_dsi->phys) 436 intel_combo_phy_power_up_lanes(display, phy, true, 437 intel_dsi->lane_count, false); 438 } 439 440 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 441 { 442 struct intel_display *display = to_intel_display(encoder); 443 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 444 enum phy phy; 445 u32 tmp; 446 int lane; 447 448 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 449 for_each_dsi_phy(phy, intel_dsi->phys) { 450 intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), 451 LOADGEN_SELECT, 0); 452 for (lane = 0; lane <= 3; lane++) 453 intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy), 454 LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0); 455 } 456 457 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 458 for_each_dsi_phy(phy, intel_dsi->phys) { 459 intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), 460 FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5)); 461 tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy)); 462 tmp &= ~FRC_LATENCY_OPTIM_MASK; 463 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 464 intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); 465 466 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 467 if (display->platform.jasperlake || display->platform.elkhartlake || 468 (DISPLAY_VER(display) >= 12)) { 469 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), 470 LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0)); 471 472 tmp = intel_de_read(display, 473 ICL_PORT_PCS_DW1_LN(0, phy)); 474 tmp &= ~LATENCY_OPTIM_MASK; 475 tmp |= LATENCY_OPTIM_VAL(0x1); 476 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), 477 tmp); 478 } 479 } 480 481 } 482 483 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 484 { 485 struct intel_display *display = to_intel_display(encoder); 486 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 487 u32 tmp; 488 enum phy phy; 489 490 /* clear common keeper enable bit */ 491 for_each_dsi_phy(phy, intel_dsi->phys) { 492 tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); 493 tmp &= ~COMMON_KEEPER_EN; 494 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp); 495 intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0); 496 } 497 498 /* 499 * Set SUS Clock Config bitfield to 11b 500 * Note: loadgen select program is done 501 * as part of lane phy sequence configuration 502 */ 503 for_each_dsi_phy(phy, intel_dsi->phys) 504 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0, 505 SUS_CLOCK_CONFIG); 506 507 /* Clear training enable to change swing values */ 508 for_each_dsi_phy(phy, intel_dsi->phys) { 509 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 510 tmp &= ~TX_TRAINING_EN; 511 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 512 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0); 513 } 514 515 /* Program swing and de-emphasis */ 516 dsi_program_swing_and_deemphasis(encoder); 517 518 /* Set training enable to trigger update */ 519 for_each_dsi_phy(phy, intel_dsi->phys) { 520 tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy)); 521 tmp |= TX_TRAINING_EN; 522 intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp); 523 intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN); 524 } 525 } 526 527 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 528 { 529 struct intel_display *display = to_intel_display(encoder); 530 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 531 enum port port; 532 int ret; 533 534 for_each_dsi_port(port, intel_dsi->ports) { 535 intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE); 536 537 ret = intel_de_wait_custom(display, DDI_BUF_CTL(port), 538 DDI_BUF_IS_IDLE, 0, 539 500, 0, NULL); 540 if (ret) 541 drm_err(display->drm, "DDI port:%c buffer idle\n", 542 port_name(port)); 543 } 544 } 545 546 static void 547 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 548 const struct intel_crtc_state *crtc_state) 549 { 550 struct intel_display *display = to_intel_display(encoder); 551 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 552 enum port port; 553 enum phy phy; 554 555 /* Program DPHY clock lanes timings */ 556 for_each_dsi_port(port, intel_dsi->ports) 557 intel_de_write(display, DPHY_CLK_TIMING_PARAM(port), 558 intel_dsi->dphy_reg); 559 560 /* Program DPHY data lanes timings */ 561 for_each_dsi_port(port, intel_dsi->ports) 562 intel_de_write(display, DPHY_DATA_TIMING_PARAM(port), 563 intel_dsi->dphy_data_lane_reg); 564 565 /* 566 * If DSI link operating at or below an 800 MHz, 567 * TA_SURE should be override and programmed to 568 * a value '0' inside TA_PARAM_REGISTERS otherwise 569 * leave all fields at HW default values. 570 */ 571 if (DISPLAY_VER(display) == 11) { 572 if (afe_clk(encoder, crtc_state) <= 800000) { 573 for_each_dsi_port(port, intel_dsi->ports) 574 intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port), 575 TA_SURE_MASK, 576 TA_SURE_OVERRIDE | TA_SURE(0)); 577 } 578 } 579 580 if (display->platform.jasperlake || display->platform.elkhartlake) { 581 for_each_dsi_phy(phy, intel_dsi->phys) 582 intel_de_rmw(display, ICL_DPHY_CHKN(phy), 583 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP); 584 } 585 } 586 587 static void 588 gen11_dsi_setup_timings(struct intel_encoder *encoder, 589 const struct intel_crtc_state *crtc_state) 590 { 591 struct intel_display *display = to_intel_display(encoder); 592 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 593 enum port port; 594 595 /* Program T-INIT master registers */ 596 for_each_dsi_port(port, intel_dsi->ports) 597 intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port), 598 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); 599 600 /* shadow register inside display core */ 601 for_each_dsi_port(port, intel_dsi->ports) 602 intel_de_write(display, DSI_CLK_TIMING_PARAM(port), 603 intel_dsi->dphy_reg); 604 605 /* shadow register inside display core */ 606 for_each_dsi_port(port, intel_dsi->ports) 607 intel_de_write(display, DSI_DATA_TIMING_PARAM(port), 608 intel_dsi->dphy_data_lane_reg); 609 610 /* shadow register inside display core */ 611 if (DISPLAY_VER(display) == 11) { 612 if (afe_clk(encoder, crtc_state) <= 800000) { 613 for_each_dsi_port(port, intel_dsi->ports) { 614 intel_de_rmw(display, DSI_TA_TIMING_PARAM(port), 615 TA_SURE_MASK, 616 TA_SURE_OVERRIDE | TA_SURE(0)); 617 } 618 } 619 } 620 } 621 622 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 623 { 624 struct intel_display *display = to_intel_display(encoder); 625 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 626 u32 tmp; 627 enum phy phy; 628 629 mutex_lock(&display->dpll.lock); 630 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 631 for_each_dsi_phy(phy, intel_dsi->phys) 632 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 633 634 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); 635 mutex_unlock(&display->dpll.lock); 636 } 637 638 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 639 { 640 struct intel_display *display = to_intel_display(encoder); 641 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 642 u32 tmp; 643 enum phy phy; 644 645 mutex_lock(&display->dpll.lock); 646 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 647 for_each_dsi_phy(phy, intel_dsi->phys) 648 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 649 650 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); 651 mutex_unlock(&display->dpll.lock); 652 } 653 654 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder) 655 { 656 struct intel_display *display = to_intel_display(encoder); 657 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 658 bool clock_enabled = false; 659 enum phy phy; 660 u32 tmp; 661 662 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); 663 664 for_each_dsi_phy(phy, intel_dsi->phys) { 665 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy))) 666 clock_enabled = true; 667 } 668 669 return clock_enabled; 670 } 671 672 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 673 const struct intel_crtc_state *crtc_state) 674 { 675 struct intel_display *display = to_intel_display(encoder); 676 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 677 struct intel_dpll *pll = crtc_state->intel_dpll; 678 enum phy phy; 679 u32 val; 680 681 mutex_lock(&display->dpll.lock); 682 683 val = intel_de_read(display, ICL_DPCLKA_CFGCR0); 684 for_each_dsi_phy(phy, intel_dsi->phys) { 685 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 686 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 687 } 688 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); 689 690 for_each_dsi_phy(phy, intel_dsi->phys) { 691 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 692 } 693 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); 694 695 intel_de_posting_read(display, ICL_DPCLKA_CFGCR0); 696 697 mutex_unlock(&display->dpll.lock); 698 } 699 700 static void 701 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 702 const struct intel_crtc_state *pipe_config) 703 { 704 struct intel_display *display = to_intel_display(encoder); 705 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 706 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 707 enum pipe pipe = crtc->pipe; 708 u32 tmp; 709 enum port port; 710 enum transcoder dsi_trans; 711 712 for_each_dsi_port(port, intel_dsi->ports) { 713 dsi_trans = dsi_port_to_transcoder(port); 714 tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 715 716 if (intel_dsi->eotp_pkt) 717 tmp &= ~EOTP_DISABLED; 718 else 719 tmp |= EOTP_DISABLED; 720 721 /* enable link calibration if freq > 1.5Gbps */ 722 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 723 tmp &= ~LINK_CALIBRATION_MASK; 724 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 725 } 726 727 /* configure continuous clock */ 728 tmp &= ~CONTINUOUS_CLK_MASK; 729 if (intel_dsi->clock_stop) 730 tmp |= CLK_ENTER_LP_AFTER_DATA; 731 else 732 tmp |= CLK_HS_CONTINUOUS; 733 734 /* configure buffer threshold limit to minimum */ 735 tmp &= ~PIX_BUF_THRESHOLD_MASK; 736 tmp |= PIX_BUF_THRESHOLD_1_4; 737 738 /* set virtual channel to '0' */ 739 tmp &= ~PIX_VIRT_CHAN_MASK; 740 tmp |= PIX_VIRT_CHAN(0); 741 742 /* program BGR transmission */ 743 if (intel_dsi->bgr_enabled) 744 tmp |= BGR_TRANSMISSION; 745 746 /* select pixel format */ 747 tmp &= ~PIX_FMT_MASK; 748 if (pipe_config->dsc.compression_enable) { 749 tmp |= PIX_FMT_COMPRESSED; 750 } else { 751 switch (intel_dsi->pixel_format) { 752 default: 753 MISSING_CASE(intel_dsi->pixel_format); 754 fallthrough; 755 case MIPI_DSI_FMT_RGB565: 756 tmp |= PIX_FMT_RGB565; 757 break; 758 case MIPI_DSI_FMT_RGB666_PACKED: 759 tmp |= PIX_FMT_RGB666_PACKED; 760 break; 761 case MIPI_DSI_FMT_RGB666: 762 tmp |= PIX_FMT_RGB666_LOOSE; 763 break; 764 case MIPI_DSI_FMT_RGB888: 765 tmp |= PIX_FMT_RGB888; 766 break; 767 } 768 } 769 770 if (DISPLAY_VER(display) >= 12) { 771 if (is_vid_mode(intel_dsi)) 772 tmp |= BLANKING_PACKET_ENABLE; 773 } 774 775 /* program DSI operation mode */ 776 if (is_vid_mode(intel_dsi)) { 777 tmp &= ~OP_MODE_MASK; 778 switch (intel_dsi->video_mode) { 779 default: 780 MISSING_CASE(intel_dsi->video_mode); 781 fallthrough; 782 case NON_BURST_SYNC_EVENTS: 783 tmp |= VIDEO_MODE_SYNC_EVENT; 784 break; 785 case NON_BURST_SYNC_PULSE: 786 tmp |= VIDEO_MODE_SYNC_PULSE; 787 break; 788 } 789 } else { 790 /* 791 * FIXME: Retrieve this info from VBT. 792 * As per the spec when dsi transcoder is operating 793 * in TE GATE mode, TE comes from GPIO 794 * which is UTIL PIN for DSI 0. 795 * Also this GPIO would not be used for other 796 * purposes is an assumption. 797 */ 798 tmp &= ~OP_MODE_MASK; 799 tmp |= CMD_MODE_TE_GATE; 800 tmp |= TE_SOURCE_GPIO; 801 } 802 803 intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 804 } 805 806 /* enable port sync mode if dual link */ 807 if (intel_dsi->dual_link) { 808 for_each_dsi_port(port, intel_dsi->ports) { 809 dsi_trans = dsi_port_to_transcoder(port); 810 intel_de_rmw(display, 811 TRANS_DDI_FUNC_CTL2(display, dsi_trans), 812 0, PORT_SYNC_MODE_ENABLE); 813 } 814 815 /* configure stream splitting */ 816 configure_dual_link_mode(encoder, pipe_config); 817 } 818 819 for_each_dsi_port(port, intel_dsi->ports) { 820 dsi_trans = dsi_port_to_transcoder(port); 821 822 /* select data lane width */ 823 tmp = intel_de_read(display, 824 TRANS_DDI_FUNC_CTL(display, dsi_trans)); 825 tmp &= ~TRANS_DDI_PORT_WIDTH_MASK; 826 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); 827 828 /* select input pipe */ 829 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 830 switch (pipe) { 831 default: 832 MISSING_CASE(pipe); 833 fallthrough; 834 case PIPE_A: 835 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 836 break; 837 case PIPE_B: 838 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 839 break; 840 case PIPE_C: 841 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 842 break; 843 case PIPE_D: 844 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 845 break; 846 } 847 848 /* enable DDI buffer */ 849 tmp |= TRANS_DDI_FUNC_ENABLE; 850 intel_de_write(display, 851 TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp); 852 } 853 854 /* wait for link ready */ 855 for_each_dsi_port(port, intel_dsi->ports) { 856 int ret; 857 858 dsi_trans = dsi_port_to_transcoder(port); 859 860 ret = intel_de_wait_custom(display, DSI_TRANS_FUNC_CONF(dsi_trans), 861 LINK_READY, LINK_READY, 862 2500, 0, NULL); 863 if (ret) 864 drm_err(display->drm, "DSI link not ready\n"); 865 } 866 } 867 868 static void 869 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 870 const struct intel_crtc_state *crtc_state) 871 { 872 struct intel_display *display = to_intel_display(encoder); 873 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 874 const struct drm_display_mode *adjusted_mode = 875 &crtc_state->hw.adjusted_mode; 876 enum port port; 877 enum transcoder dsi_trans; 878 /* horizontal timings */ 879 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 880 u16 hback_porch; 881 /* vertical timings */ 882 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 883 int mul = 1, div = 1; 884 885 /* 886 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 887 * for slower link speed if DSC is enabled. 888 * 889 * The compression frequency ratio is the ratio between compressed and 890 * non-compressed link speeds, and simplifies down to the ratio between 891 * compressed and non-compressed bpp. 892 */ 893 if (crtc_state->dsc.compression_enable) { 894 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 895 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 896 } 897 898 hactive = adjusted_mode->crtc_hdisplay; 899 900 if (is_vid_mode(intel_dsi)) 901 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 902 else 903 htotal = DIV_ROUND_UP((hactive + 160) * mul, div); 904 905 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 906 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 907 hsync_size = hsync_end - hsync_start; 908 hback_porch = (adjusted_mode->crtc_htotal - 909 adjusted_mode->crtc_hsync_end); 910 vactive = adjusted_mode->crtc_vdisplay; 911 912 if (is_vid_mode(intel_dsi)) { 913 vtotal = adjusted_mode->crtc_vtotal; 914 } else { 915 int bpp, line_time_us, byte_clk_period_ns; 916 917 if (crtc_state->dsc.compression_enable) 918 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); 919 else 920 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 921 922 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state); 923 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); 924 vtotal = vactive + DIV_ROUND_UP(400, line_time_us); 925 } 926 vsync_start = adjusted_mode->crtc_vsync_start; 927 vsync_end = adjusted_mode->crtc_vsync_end; 928 vsync_shift = hsync_start - htotal / 2; 929 930 if (intel_dsi->dual_link) { 931 hactive /= 2; 932 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 933 hactive += intel_dsi->pixel_overlap; 934 htotal /= 2; 935 } 936 937 /* minimum hactive as per bspec: 256 pixels */ 938 if (adjusted_mode->crtc_hdisplay < 256) 939 drm_err(display->drm, "hactive is less then 256 pixels\n"); 940 941 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 942 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 943 drm_err(display->drm, 944 "hactive pixels are not multiple of 4\n"); 945 946 /* program TRANS_HTOTAL register */ 947 for_each_dsi_port(port, intel_dsi->ports) { 948 dsi_trans = dsi_port_to_transcoder(port); 949 intel_de_write(display, TRANS_HTOTAL(display, dsi_trans), 950 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); 951 } 952 953 /* TRANS_HSYNC register to be programmed only for video mode */ 954 if (is_vid_mode(intel_dsi)) { 955 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { 956 /* BSPEC: hsync size should be atleast 16 pixels */ 957 if (hsync_size < 16) 958 drm_err(display->drm, 959 "hsync size < 16 pixels\n"); 960 } 961 962 if (hback_porch < 16) 963 drm_err(display->drm, "hback porch < 16 pixels\n"); 964 965 if (intel_dsi->dual_link) { 966 hsync_start /= 2; 967 hsync_end /= 2; 968 } 969 970 for_each_dsi_port(port, intel_dsi->ports) { 971 dsi_trans = dsi_port_to_transcoder(port); 972 intel_de_write(display, 973 TRANS_HSYNC(display, dsi_trans), 974 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); 975 } 976 } 977 978 /* program TRANS_VTOTAL register */ 979 for_each_dsi_port(port, intel_dsi->ports) { 980 dsi_trans = dsi_port_to_transcoder(port); 981 /* 982 * FIXME: Programming this by assuming progressive mode, since 983 * non-interlaced info from VBT is not saved inside 984 * struct drm_display_mode. 985 * For interlace mode: program required pixel minus 2 986 */ 987 intel_de_write(display, TRANS_VTOTAL(display, dsi_trans), 988 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); 989 } 990 991 if (vsync_end < vsync_start || vsync_end > vtotal) 992 drm_err(display->drm, "Invalid vsync_end value\n"); 993 994 if (vsync_start < vactive) 995 drm_err(display->drm, "vsync_start less than vactive\n"); 996 997 /* program TRANS_VSYNC register for video mode only */ 998 if (is_vid_mode(intel_dsi)) { 999 for_each_dsi_port(port, intel_dsi->ports) { 1000 dsi_trans = dsi_port_to_transcoder(port); 1001 intel_de_write(display, 1002 TRANS_VSYNC(display, dsi_trans), 1003 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); 1004 } 1005 } 1006 1007 /* 1008 * FIXME: It has to be programmed only for video modes and interlaced 1009 * modes. Put the check condition here once interlaced 1010 * info available as described above. 1011 * program TRANS_VSYNCSHIFT register 1012 */ 1013 if (is_vid_mode(intel_dsi)) { 1014 for_each_dsi_port(port, intel_dsi->ports) { 1015 dsi_trans = dsi_port_to_transcoder(port); 1016 intel_de_write(display, 1017 TRANS_VSYNCSHIFT(display, dsi_trans), 1018 vsync_shift); 1019 } 1020 } 1021 1022 /* 1023 * program TRANS_VBLANK register, should be same as vtotal programmed 1024 * 1025 * FIXME get rid of these local hacks and do it right, 1026 * this will not handle eg. delayed vblank correctly. 1027 */ 1028 if (DISPLAY_VER(display) >= 12) { 1029 for_each_dsi_port(port, intel_dsi->ports) { 1030 dsi_trans = dsi_port_to_transcoder(port); 1031 intel_de_write(display, 1032 TRANS_VBLANK(display, dsi_trans), 1033 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); 1034 } 1035 } 1036 } 1037 1038 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 1039 { 1040 struct intel_display *display = to_intel_display(encoder); 1041 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1042 enum port port; 1043 enum transcoder dsi_trans; 1044 1045 for_each_dsi_port(port, intel_dsi->ports) { 1046 dsi_trans = dsi_port_to_transcoder(port); 1047 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0, 1048 TRANSCONF_ENABLE); 1049 1050 /* wait for transcoder to be enabled */ 1051 if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans), 1052 TRANSCONF_STATE_ENABLE, 10)) 1053 drm_err(display->drm, 1054 "DSI transcoder not enabled\n"); 1055 } 1056 } 1057 1058 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 1059 const struct intel_crtc_state *crtc_state) 1060 { 1061 struct intel_display *display = to_intel_display(encoder); 1062 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1063 enum port port; 1064 enum transcoder dsi_trans; 1065 u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 1066 1067 /* 1068 * escape clock count calculation: 1069 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 1070 * UI (nsec) = (10^6)/Bitrate 1071 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 1072 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 1073 */ 1074 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 1075 mul = 8 * 1000000; 1076 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 1077 divisor); 1078 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 1079 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 1080 1081 for_each_dsi_port(port, intel_dsi->ports) { 1082 dsi_trans = dsi_port_to_transcoder(port); 1083 1084 /* program hst_tx_timeout */ 1085 intel_de_rmw(display, DSI_HSTX_TO(dsi_trans), 1086 HSTX_TIMEOUT_VALUE_MASK, 1087 HSTX_TIMEOUT_VALUE(hs_tx_timeout)); 1088 1089 /* FIXME: DSI_CALIB_TO */ 1090 1091 /* program lp_rx_host timeout */ 1092 intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans), 1093 LPRX_TIMEOUT_VALUE_MASK, 1094 LPRX_TIMEOUT_VALUE(lp_rx_timeout)); 1095 1096 /* FIXME: DSI_PWAIT_TO */ 1097 1098 /* program turn around timeout */ 1099 intel_de_rmw(display, DSI_TA_TO(dsi_trans), 1100 TA_TIMEOUT_VALUE_MASK, 1101 TA_TIMEOUT_VALUE(ta_timeout)); 1102 } 1103 } 1104 1105 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder, 1106 bool enable) 1107 { 1108 struct intel_display *display = to_intel_display(encoder); 1109 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1110 u32 tmp; 1111 1112 /* 1113 * used as TE i/p for DSI0, 1114 * for dual link/DSI1 TE is from slave DSI1 1115 * through GPIO. 1116 */ 1117 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) 1118 return; 1119 1120 tmp = intel_de_read(display, UTIL_PIN_CTL); 1121 1122 if (enable) { 1123 tmp |= UTIL_PIN_DIRECTION_INPUT; 1124 tmp |= UTIL_PIN_ENABLE; 1125 } else { 1126 tmp &= ~UTIL_PIN_ENABLE; 1127 } 1128 intel_de_write(display, UTIL_PIN_CTL, tmp); 1129 } 1130 1131 static void 1132 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1133 const struct intel_crtc_state *crtc_state) 1134 { 1135 /* step 4a: power up all lanes of the DDI used by DSI */ 1136 gen11_dsi_power_up_lanes(encoder); 1137 1138 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1139 gen11_dsi_config_phy_lanes_sequence(encoder); 1140 1141 /* step 4c: configure voltage swing and skew */ 1142 gen11_dsi_voltage_swing_program_seq(encoder); 1143 1144 /* setup D-PHY timings */ 1145 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1146 1147 /* enable DDI buffer */ 1148 gen11_dsi_enable_ddi_buffer(encoder); 1149 1150 gen11_dsi_gate_clocks(encoder); 1151 1152 gen11_dsi_setup_timings(encoder, crtc_state); 1153 1154 /* Since transcoder is configured to take events from GPIO */ 1155 gen11_dsi_config_util_pin(encoder, true); 1156 1157 /* step 4h: setup DSI protocol timeouts */ 1158 gen11_dsi_setup_timeouts(encoder, crtc_state); 1159 1160 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1161 gen11_dsi_configure_transcoder(encoder, crtc_state); 1162 } 1163 1164 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1165 { 1166 struct intel_display *display = to_intel_display(encoder); 1167 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1168 struct mipi_dsi_device *dsi; 1169 enum port port; 1170 enum transcoder dsi_trans; 1171 u32 tmp; 1172 int ret; 1173 1174 /* set maximum return packet size */ 1175 for_each_dsi_port(port, intel_dsi->ports) { 1176 dsi_trans = dsi_port_to_transcoder(port); 1177 1178 /* 1179 * FIXME: This uses the number of DW's currently in the payload 1180 * receive queue. This is probably not what we want here. 1181 */ 1182 tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans)); 1183 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1184 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1185 tmp = tmp * 4; 1186 dsi = intel_dsi->dsi_hosts[port]->device; 1187 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1188 if (ret < 0) 1189 drm_err(display->drm, 1190 "error setting max return pkt size%d\n", tmp); 1191 } 1192 1193 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1194 1195 /* ensure all panel commands dispatched before enabling transcoder */ 1196 wait_for_cmds_dispatched_to_panel(encoder); 1197 } 1198 1199 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state, 1200 struct intel_encoder *encoder, 1201 const struct intel_crtc_state *crtc_state, 1202 const struct drm_connector_state *conn_state) 1203 { 1204 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1205 1206 intel_dsi_wait_panel_power_cycle(intel_dsi); 1207 1208 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1209 msleep(intel_dsi->panel_on_delay); 1210 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1211 1212 /* step2: enable IO power */ 1213 gen11_dsi_enable_io_power(encoder); 1214 1215 /* step3: enable DSI PLL */ 1216 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1217 } 1218 1219 static void gen11_dsi_pre_enable(struct intel_atomic_state *state, 1220 struct intel_encoder *encoder, 1221 const struct intel_crtc_state *pipe_config, 1222 const struct drm_connector_state *conn_state) 1223 { 1224 /* step3b */ 1225 gen11_dsi_map_pll(encoder, pipe_config); 1226 1227 /* step4: enable DSI port and DPHY */ 1228 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1229 1230 /* step5: program and powerup panel */ 1231 gen11_dsi_powerup_panel(encoder); 1232 1233 intel_dsc_dsi_pps_write(encoder, pipe_config); 1234 1235 /* step6c: configure transcoder timings */ 1236 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1237 } 1238 1239 /* 1240 * Wa_1409054076:icl,jsl,ehl 1241 * When pipe A is disabled and MIPI DSI is enabled on pipe B, 1242 * the AMT KVMR feature will incorrectly see pipe A as enabled. 1243 * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave 1244 * it set while DSI is enabled on pipe B 1245 */ 1246 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 1247 enum pipe pipe, bool enable) 1248 { 1249 struct intel_display *display = to_intel_display(encoder); 1250 1251 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B) 1252 intel_de_rmw(display, CHICKEN_PAR1_1, 1253 IGNORE_KVMR_PIPE_A, 1254 enable ? IGNORE_KVMR_PIPE_A : 0); 1255 } 1256 1257 /* 1258 * Wa_16012360555:adl-p 1259 * SW will have to program the "LP to HS Wakeup Guardband" 1260 * to account for the repeaters on the HS Request/Ready 1261 * PPI signaling between the Display engine and the DPHY. 1262 */ 1263 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 1264 { 1265 struct intel_display *display = to_intel_display(encoder); 1266 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1267 enum port port; 1268 1269 if (DISPLAY_VER(display) == 13) { 1270 for_each_dsi_port(port, intel_dsi->ports) 1271 intel_de_rmw(display, TGL_DSI_CHKN_REG(port), 1272 TGL_DSI_CHKN_LSHS_GB_MASK, 1273 TGL_DSI_CHKN_LSHS_GB(4)); 1274 } 1275 } 1276 1277 static void gen11_dsi_enable(struct intel_atomic_state *state, 1278 struct intel_encoder *encoder, 1279 const struct intel_crtc_state *crtc_state, 1280 const struct drm_connector_state *conn_state) 1281 { 1282 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1283 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1284 1285 /* Wa_1409054076:icl,jsl,ehl */ 1286 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); 1287 1288 /* Wa_16012360555:adl-p */ 1289 adlp_set_lp_hs_wakeup_gb(encoder); 1290 1291 /* step6d: enable dsi transcoder */ 1292 gen11_dsi_enable_transcoder(encoder); 1293 1294 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1295 1296 /* step7: enable backlight */ 1297 intel_backlight_enable(crtc_state, conn_state); 1298 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1299 1300 intel_panel_prepare(crtc_state, conn_state); 1301 1302 intel_crtc_vblank_on(crtc_state); 1303 } 1304 1305 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1306 { 1307 struct intel_display *display = to_intel_display(encoder); 1308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1309 enum port port; 1310 enum transcoder dsi_trans; 1311 1312 for_each_dsi_port(port, intel_dsi->ports) { 1313 dsi_trans = dsi_port_to_transcoder(port); 1314 1315 /* disable transcoder */ 1316 intel_de_rmw(display, TRANSCONF(display, dsi_trans), 1317 TRANSCONF_ENABLE, 0); 1318 1319 /* wait for transcoder to be disabled */ 1320 if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans), 1321 TRANSCONF_STATE_ENABLE, 50)) 1322 drm_err(display->drm, 1323 "DSI trancoder not disabled\n"); 1324 } 1325 } 1326 1327 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1328 { 1329 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1330 1331 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1332 1333 /* ensure cmds dispatched to panel */ 1334 wait_for_cmds_dispatched_to_panel(encoder); 1335 } 1336 1337 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1338 { 1339 struct intel_display *display = to_intel_display(encoder); 1340 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1341 enum port port; 1342 enum transcoder dsi_trans; 1343 u32 tmp; 1344 int ret; 1345 1346 /* disable periodic update mode */ 1347 if (is_cmd_mode(intel_dsi)) { 1348 for_each_dsi_port(port, intel_dsi->ports) 1349 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 1350 DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0); 1351 } 1352 1353 /* put dsi link in ULPS */ 1354 for_each_dsi_port(port, intel_dsi->ports) { 1355 dsi_trans = dsi_port_to_transcoder(port); 1356 tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans)); 1357 tmp |= LINK_ENTER_ULPS; 1358 tmp &= ~LINK_ULPS_TYPE_LP11; 1359 intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp); 1360 1361 ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans), 1362 LINK_IN_ULPS, LINK_IN_ULPS, 1363 10, 0, NULL); 1364 if (ret) 1365 drm_err(display->drm, "DSI link not in ULPS\n"); 1366 } 1367 1368 /* disable ddi function */ 1369 for_each_dsi_port(port, intel_dsi->ports) { 1370 dsi_trans = dsi_port_to_transcoder(port); 1371 intel_de_rmw(display, 1372 TRANS_DDI_FUNC_CTL(display, dsi_trans), 1373 TRANS_DDI_FUNC_ENABLE, 0); 1374 } 1375 1376 /* disable port sync mode if dual link */ 1377 if (intel_dsi->dual_link) { 1378 for_each_dsi_port(port, intel_dsi->ports) { 1379 dsi_trans = dsi_port_to_transcoder(port); 1380 intel_de_rmw(display, 1381 TRANS_DDI_FUNC_CTL2(display, dsi_trans), 1382 PORT_SYNC_MODE_ENABLE, 0); 1383 } 1384 } 1385 } 1386 1387 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1388 { 1389 struct intel_display *display = to_intel_display(encoder); 1390 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1391 enum port port; 1392 int ret; 1393 1394 gen11_dsi_ungate_clocks(encoder); 1395 for_each_dsi_port(port, intel_dsi->ports) { 1396 intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); 1397 1398 ret = intel_de_wait_custom(display, DDI_BUF_CTL(port), 1399 DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE, 1400 8, 0, NULL); 1401 1402 if (ret) 1403 drm_err(display->drm, 1404 "DDI port:%c buffer not idle\n", 1405 port_name(port)); 1406 } 1407 gen11_dsi_gate_clocks(encoder); 1408 } 1409 1410 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1411 { 1412 struct intel_display *display = to_intel_display(encoder); 1413 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1414 enum port port; 1415 1416 for_each_dsi_port(port, intel_dsi->ports) { 1417 intel_wakeref_t wakeref; 1418 1419 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1420 intel_display_power_put(display, 1421 port == PORT_A ? 1422 POWER_DOMAIN_PORT_DDI_IO_A : 1423 POWER_DOMAIN_PORT_DDI_IO_B, 1424 wakeref); 1425 } 1426 1427 /* set mode to DDI */ 1428 for_each_dsi_port(port, intel_dsi->ports) 1429 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), 1430 COMBO_PHY_MODE_DSI, 0); 1431 } 1432 1433 static void gen11_dsi_disable(struct intel_atomic_state *state, 1434 struct intel_encoder *encoder, 1435 const struct intel_crtc_state *old_crtc_state, 1436 const struct drm_connector_state *old_conn_state) 1437 { 1438 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1439 1440 intel_panel_unprepare(old_conn_state); 1441 1442 /* step1: turn off backlight */ 1443 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1444 intel_backlight_disable(old_conn_state); 1445 } 1446 1447 static void gen11_dsi_post_disable(struct intel_atomic_state *state, 1448 struct intel_encoder *encoder, 1449 const struct intel_crtc_state *old_crtc_state, 1450 const struct drm_connector_state *old_conn_state) 1451 { 1452 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1453 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1454 1455 intel_crtc_vblank_off(old_crtc_state); 1456 1457 /* step2d,e: disable transcoder and wait */ 1458 gen11_dsi_disable_transcoder(encoder); 1459 1460 /* Wa_1409054076:icl,jsl,ehl */ 1461 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); 1462 1463 /* step2f,g: powerdown panel */ 1464 gen11_dsi_powerdown_panel(encoder); 1465 1466 /* step2h,i,j: deconfig trancoder */ 1467 gen11_dsi_deconfigure_trancoder(encoder); 1468 1469 intel_dsc_disable(old_crtc_state); 1470 skl_scaler_disable(old_crtc_state); 1471 1472 /* step3: disable port */ 1473 gen11_dsi_disable_port(encoder); 1474 1475 gen11_dsi_config_util_pin(encoder, false); 1476 1477 /* step4: disable IO power */ 1478 gen11_dsi_disable_io_power(encoder); 1479 1480 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1481 1482 msleep(intel_dsi->panel_off_delay); 1483 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1484 1485 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1486 } 1487 1488 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1489 const struct drm_display_mode *mode) 1490 { 1491 struct intel_display *display = to_intel_display(connector->dev); 1492 enum drm_mode_status status; 1493 1494 status = intel_cpu_transcoder_mode_valid(display, mode); 1495 if (status != MODE_OK) 1496 return status; 1497 1498 /* FIXME: DSC? */ 1499 return intel_dsi_mode_valid(connector, mode); 1500 } 1501 1502 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1503 struct intel_crtc_state *pipe_config) 1504 { 1505 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1506 struct drm_display_mode *adjusted_mode = 1507 &pipe_config->hw.adjusted_mode; 1508 1509 if (pipe_config->dsc.compressed_bpp_x16) { 1510 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); 1511 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1512 1513 adjusted_mode->crtc_htotal = 1514 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1515 adjusted_mode->crtc_hsync_start = 1516 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1517 adjusted_mode->crtc_hsync_end = 1518 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1519 } 1520 1521 if (intel_dsi->dual_link) { 1522 adjusted_mode->crtc_hdisplay *= 2; 1523 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1524 adjusted_mode->crtc_hdisplay -= 1525 intel_dsi->pixel_overlap; 1526 adjusted_mode->crtc_htotal *= 2; 1527 } 1528 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1529 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1530 1531 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1532 if (intel_dsi->dual_link) { 1533 adjusted_mode->crtc_hsync_start *= 2; 1534 adjusted_mode->crtc_hsync_end *= 2; 1535 } 1536 } 1537 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1538 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1539 } 1540 1541 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi) 1542 { 1543 struct intel_display *display = to_intel_display(&intel_dsi->base); 1544 enum transcoder dsi_trans; 1545 u32 val; 1546 1547 if (intel_dsi->ports == BIT(PORT_B)) 1548 dsi_trans = TRANSCODER_DSI_1; 1549 else 1550 dsi_trans = TRANSCODER_DSI_0; 1551 1552 val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); 1553 return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE); 1554 } 1555 1556 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 1557 struct intel_crtc_state *pipe_config) 1558 { 1559 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) 1560 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | 1561 I915_MODE_FLAG_DSI_USE_TE0; 1562 else if (intel_dsi->ports == BIT(PORT_B)) 1563 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; 1564 else 1565 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; 1566 } 1567 1568 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1569 struct intel_crtc_state *pipe_config) 1570 { 1571 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1572 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1573 1574 intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder)); 1575 1576 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1577 if (intel_dsi->dual_link) 1578 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1579 1580 gen11_dsi_get_timings(encoder, pipe_config); 1581 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1582 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); 1583 1584 /* Get the details on which TE should be enabled */ 1585 if (is_cmd_mode(intel_dsi)) 1586 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1587 1588 if (gen11_dsi_is_periodic_cmd_mode(intel_dsi)) 1589 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; 1590 } 1591 1592 static void gen11_dsi_sync_state(struct intel_encoder *encoder, 1593 const struct intel_crtc_state *crtc_state) 1594 { 1595 struct intel_display *display = to_intel_display(encoder); 1596 struct intel_crtc *intel_crtc; 1597 enum pipe pipe; 1598 1599 if (!crtc_state) 1600 return; 1601 1602 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1603 pipe = intel_crtc->pipe; 1604 1605 /* wa verify 1409054076:icl,jsl,ehl */ 1606 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B && 1607 !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A)) 1608 drm_dbg_kms(display->drm, 1609 "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n", 1610 encoder->base.base.id, 1611 encoder->base.name); 1612 } 1613 1614 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1615 struct intel_crtc_state *crtc_state) 1616 { 1617 struct intel_display *display = to_intel_display(encoder); 1618 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1619 int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10; 1620 bool use_dsc; 1621 int ret; 1622 1623 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1624 if (!use_dsc) 1625 return 0; 1626 1627 if (crtc_state->pipe_bpp < 8 * 3) 1628 return -EINVAL; 1629 1630 /* FIXME: split only when necessary */ 1631 if (crtc_state->dsc.slice_count > 1) 1632 crtc_state->dsc.num_streams = 2; 1633 else 1634 crtc_state->dsc.num_streams = 1; 1635 1636 /* FIXME: initialize from VBT */ 1637 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1638 1639 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1640 1641 ret = intel_dsc_compute_params(crtc_state); 1642 if (ret) 1643 return ret; 1644 1645 /* DSI specific sanity checks on the common code */ 1646 drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable); 1647 drm_WARN_ON(display->drm, vdsc_cfg->simple_422); 1648 drm_WARN_ON(display->drm, 1649 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1650 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8); 1651 drm_WARN_ON(display->drm, 1652 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1653 1654 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1655 if (ret) 1656 return ret; 1657 1658 crtc_state->dsc.compression_enable = true; 1659 1660 return 0; 1661 } 1662 1663 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1664 struct intel_crtc_state *pipe_config, 1665 struct drm_connector_state *conn_state) 1666 { 1667 struct intel_display *display = to_intel_display(encoder); 1668 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1669 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1670 struct drm_display_mode *adjusted_mode = 1671 &pipe_config->hw.adjusted_mode; 1672 int ret; 1673 1674 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1675 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1676 1677 ret = intel_panel_compute_config(intel_connector, adjusted_mode); 1678 if (ret) 1679 return ret; 1680 1681 ret = intel_pfit_compute_config(pipe_config, conn_state); 1682 if (ret) 1683 return ret; 1684 1685 adjusted_mode->flags = 0; 1686 1687 /* Dual link goes to trancoder DSI'0' */ 1688 if (intel_dsi->ports == BIT(PORT_B)) 1689 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1690 else 1691 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1692 1693 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1694 pipe_config->pipe_bpp = 24; 1695 else 1696 pipe_config->pipe_bpp = 18; 1697 1698 pipe_config->clock_set = true; 1699 1700 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1701 drm_dbg_kms(display->drm, "Attempting to use DSC failed\n"); 1702 1703 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1704 1705 /* 1706 * In case of TE GATE cmd mode, we 1707 * receive TE from the slave if 1708 * dual link is enabled 1709 */ 1710 if (is_cmd_mode(intel_dsi)) 1711 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config); 1712 1713 return 0; 1714 } 1715 1716 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1717 struct intel_crtc_state *crtc_state) 1718 { 1719 get_dsi_io_power_domains(enc_to_intel_dsi(encoder)); 1720 } 1721 1722 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1723 enum pipe *pipe) 1724 { 1725 struct intel_display *display = to_intel_display(encoder); 1726 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1727 enum transcoder dsi_trans; 1728 intel_wakeref_t wakeref; 1729 enum port port; 1730 bool ret = false; 1731 u32 tmp; 1732 1733 wakeref = intel_display_power_get_if_enabled(display, 1734 encoder->power_domain); 1735 if (!wakeref) 1736 return false; 1737 1738 for_each_dsi_port(port, intel_dsi->ports) { 1739 dsi_trans = dsi_port_to_transcoder(port); 1740 tmp = intel_de_read(display, 1741 TRANS_DDI_FUNC_CTL(display, dsi_trans)); 1742 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1743 case TRANS_DDI_EDP_INPUT_A_ON: 1744 *pipe = PIPE_A; 1745 break; 1746 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1747 *pipe = PIPE_B; 1748 break; 1749 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1750 *pipe = PIPE_C; 1751 break; 1752 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1753 *pipe = PIPE_D; 1754 break; 1755 default: 1756 drm_err(display->drm, "Invalid PIPE input\n"); 1757 goto out; 1758 } 1759 1760 tmp = intel_de_read(display, TRANSCONF(display, dsi_trans)); 1761 ret = tmp & TRANSCONF_ENABLE; 1762 } 1763 out: 1764 intel_display_power_put(display, encoder->power_domain, wakeref); 1765 return ret; 1766 } 1767 1768 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder, 1769 struct intel_crtc_state *crtc_state) 1770 { 1771 if (crtc_state->dsc.compression_enable) { 1772 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); 1773 crtc_state->uapi.mode_changed = true; 1774 1775 return false; 1776 } 1777 1778 return true; 1779 } 1780 1781 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1782 { 1783 intel_encoder_destroy(encoder); 1784 } 1785 1786 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1787 .destroy = gen11_dsi_encoder_destroy, 1788 }; 1789 1790 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1791 .detect = intel_panel_detect, 1792 .late_register = intel_connector_register, 1793 .early_unregister = intel_connector_unregister, 1794 .destroy = intel_connector_destroy, 1795 .fill_modes = drm_helper_probe_single_connector_modes, 1796 .atomic_get_property = intel_digital_connector_atomic_get_property, 1797 .atomic_set_property = intel_digital_connector_atomic_set_property, 1798 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1799 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1800 }; 1801 1802 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1803 .get_modes = intel_dsi_get_modes, 1804 .mode_valid = gen11_dsi_mode_valid, 1805 .atomic_check = intel_digital_connector_atomic_check, 1806 }; 1807 1808 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1809 struct mipi_dsi_device *dsi) 1810 { 1811 return 0; 1812 } 1813 1814 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1815 struct mipi_dsi_device *dsi) 1816 { 1817 return 0; 1818 } 1819 1820 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1821 const struct mipi_dsi_msg *msg) 1822 { 1823 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1824 struct mipi_dsi_packet dsi_pkt; 1825 ssize_t ret; 1826 bool enable_lpdt = false; 1827 1828 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1829 if (ret < 0) 1830 return ret; 1831 1832 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1833 enable_lpdt = true; 1834 1835 /* only long packet contains payload */ 1836 if (mipi_dsi_packet_format_is_long(msg->type)) { 1837 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt); 1838 if (ret < 0) 1839 return ret; 1840 } 1841 1842 /* send packet header */ 1843 ret = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt); 1844 if (ret < 0) 1845 return ret; 1846 1847 //TODO: add payload receive code if needed 1848 1849 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1850 1851 return ret; 1852 } 1853 1854 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1855 .attach = gen11_dsi_host_attach, 1856 .detach = gen11_dsi_host_detach, 1857 .transfer = gen11_dsi_host_transfer, 1858 }; 1859 1860 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1861 { 1862 struct intel_connector *connector = intel_dsi->attached_connector; 1863 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1864 u32 tlpx_ns; 1865 u32 tclk_prepare_esc_clk, tclk_zero_esc_clk, tclk_pre_esc_clk; 1866 u32 ths_prepare_esc_clk, ths_zero_esc_clk, ths_exit_esc_clk; 1867 1868 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1869 1870 /* 1871 * The clock and data lane prepare timing parameters are in expressed in 1872 * units of 1/4 escape clocks, and all the other timings parameters in 1873 * escape clocks. 1874 */ 1875 tclk_prepare_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare * 4, tlpx_ns); 1876 tclk_prepare_esc_clk = min(tclk_prepare_esc_clk, 7); 1877 1878 tclk_zero_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1879 mipi_config->tclk_prepare, tlpx_ns); 1880 tclk_zero_esc_clk = min(tclk_zero_esc_clk, 15); 1881 1882 tclk_pre_esc_clk = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1883 tclk_pre_esc_clk = min(tclk_pre_esc_clk, 3); 1884 1885 ths_prepare_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare * 4, tlpx_ns); 1886 ths_prepare_esc_clk = min(ths_prepare_esc_clk, 7); 1887 1888 ths_zero_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1889 mipi_config->ths_prepare, tlpx_ns); 1890 ths_zero_esc_clk = min(ths_zero_esc_clk, 15); 1891 1892 ths_exit_esc_clk = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1893 ths_exit_esc_clk = min(ths_exit_esc_clk, 7); 1894 1895 /* clock lane dphy timings */ 1896 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1897 CLK_PREPARE(tclk_prepare_esc_clk) | 1898 CLK_ZERO_OVERRIDE | 1899 CLK_ZERO(tclk_zero_esc_clk) | 1900 CLK_PRE_OVERRIDE | 1901 CLK_PRE(tclk_pre_esc_clk)); 1902 1903 /* data lanes dphy timings */ 1904 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1905 HS_PREPARE(ths_prepare_esc_clk) | 1906 HS_ZERO_OVERRIDE | 1907 HS_ZERO(ths_zero_esc_clk) | 1908 HS_EXIT_OVERRIDE | 1909 HS_EXIT(ths_exit_esc_clk)); 1910 1911 intel_dsi_log_params(intel_dsi); 1912 } 1913 1914 static void icl_dsi_add_properties(struct intel_connector *connector) 1915 { 1916 const struct drm_display_mode *fixed_mode = 1917 intel_panel_preferred_fixed_mode(connector); 1918 1919 intel_attach_scaling_mode_property(&connector->base); 1920 1921 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1922 intel_dsi_get_panel_orientation(connector), 1923 fixed_mode->hdisplay, 1924 fixed_mode->vdisplay); 1925 } 1926 1927 void icl_dsi_init(struct intel_display *display, 1928 const struct intel_bios_encoder_data *devdata) 1929 { 1930 struct intel_dsi *intel_dsi; 1931 struct intel_encoder *encoder; 1932 struct intel_connector *intel_connector; 1933 struct drm_connector *connector; 1934 enum port port; 1935 1936 port = intel_bios_encoder_port(devdata); 1937 if (port == PORT_NONE) 1938 return; 1939 1940 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1941 if (!intel_dsi) 1942 return; 1943 1944 intel_connector = intel_connector_alloc(); 1945 if (!intel_connector) { 1946 kfree(intel_dsi); 1947 return; 1948 } 1949 1950 encoder = &intel_dsi->base; 1951 intel_dsi->attached_connector = intel_connector; 1952 connector = &intel_connector->base; 1953 1954 encoder->devdata = devdata; 1955 1956 /* register DSI encoder with DRM subsystem */ 1957 drm_encoder_init(display->drm, &encoder->base, 1958 &gen11_dsi_encoder_funcs, 1959 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1960 1961 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1962 encoder->pre_enable = gen11_dsi_pre_enable; 1963 encoder->enable = gen11_dsi_enable; 1964 encoder->disable = gen11_dsi_disable; 1965 encoder->post_disable = gen11_dsi_post_disable; 1966 encoder->port = port; 1967 encoder->get_config = gen11_dsi_get_config; 1968 encoder->sync_state = gen11_dsi_sync_state; 1969 encoder->update_pipe = intel_backlight_update; 1970 encoder->compute_config = gen11_dsi_compute_config; 1971 encoder->get_hw_state = gen11_dsi_get_hw_state; 1972 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; 1973 encoder->type = INTEL_OUTPUT_DSI; 1974 encoder->cloneable = 0; 1975 encoder->pipe_mask = ~0; 1976 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1977 encoder->get_power_domains = gen11_dsi_get_power_domains; 1978 encoder->disable_clock = gen11_dsi_gate_clocks; 1979 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; 1980 encoder->shutdown = intel_dsi_shutdown; 1981 1982 /* register DSI connector with DRM subsystem */ 1983 drm_connector_init(display->drm, connector, 1984 &gen11_dsi_connector_funcs, 1985 DRM_MODE_CONNECTOR_DSI); 1986 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 1987 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1988 intel_connector->get_hw_state = intel_connector_get_hw_state; 1989 1990 /* attach connector to encoder */ 1991 intel_connector_attach_encoder(intel_connector, encoder); 1992 1993 intel_dsi->panel_power_off_time = ktime_get_boottime(); 1994 1995 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL); 1996 1997 mutex_lock(&display->drm->mode_config.mutex); 1998 intel_panel_add_vbt_lfp_fixed_mode(intel_connector); 1999 mutex_unlock(&display->drm->mode_config.mutex); 2000 2001 if (!intel_panel_preferred_fixed_mode(intel_connector)) { 2002 drm_err(display->drm, "DSI fixed mode info missing\n"); 2003 goto err; 2004 } 2005 2006 intel_panel_init(intel_connector, NULL); 2007 2008 intel_backlight_setup(intel_connector, INVALID_PIPE); 2009 2010 if (intel_connector->panel.vbt.dsi.config->dual_link) 2011 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 2012 else 2013 intel_dsi->ports = BIT(port); 2014 2015 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) 2016 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; 2017 2018 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) 2019 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; 2020 2021 for_each_dsi_port(port, intel_dsi->ports) { 2022 struct intel_dsi_host *host; 2023 2024 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 2025 if (!host) 2026 goto err; 2027 2028 intel_dsi->dsi_hosts[port] = host; 2029 } 2030 2031 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 2032 drm_dbg_kms(display->drm, "no device found\n"); 2033 goto err; 2034 } 2035 2036 icl_dphy_param_init(intel_dsi); 2037 2038 icl_dsi_add_properties(intel_connector); 2039 return; 2040 2041 err: 2042 drm_connector_cleanup(connector); 2043 drm_encoder_cleanup(&encoder->base); 2044 kfree(intel_dsi); 2045 kfree(intel_connector); 2046 } 2047