1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 7 #include <drm/drm_atomic_helper.h> 8 #include <drm/drm_blend.h> 9 #include <drm/drm_fourcc.h> 10 11 #include "i915_drv.h" 12 #include "i915_reg.h" 13 #include "i9xx_plane.h" 14 #include "i9xx_plane_regs.h" 15 #include "intel_atomic.h" 16 #include "intel_atomic_plane.h" 17 #include "intel_de.h" 18 #include "intel_display_irq.h" 19 #include "intel_display_types.h" 20 #include "intel_fb.h" 21 #include "intel_fbc.h" 22 #include "intel_frontbuffer.h" 23 #include "intel_sprite.h" 24 25 /* Primary plane formats for gen <= 3 */ 26 static const u32 i8xx_primary_formats[] = { 27 DRM_FORMAT_C8, 28 DRM_FORMAT_XRGB1555, 29 DRM_FORMAT_RGB565, 30 DRM_FORMAT_XRGB8888, 31 }; 32 33 /* Primary plane formats for ivb (no fp16 due to hw issue) */ 34 static const u32 ivb_primary_formats[] = { 35 DRM_FORMAT_C8, 36 DRM_FORMAT_RGB565, 37 DRM_FORMAT_XRGB8888, 38 DRM_FORMAT_XBGR8888, 39 DRM_FORMAT_XRGB2101010, 40 DRM_FORMAT_XBGR2101010, 41 }; 42 43 /* Primary plane formats for gen >= 4, except ivb */ 44 static const u32 i965_primary_formats[] = { 45 DRM_FORMAT_C8, 46 DRM_FORMAT_RGB565, 47 DRM_FORMAT_XRGB8888, 48 DRM_FORMAT_XBGR8888, 49 DRM_FORMAT_XRGB2101010, 50 DRM_FORMAT_XBGR2101010, 51 DRM_FORMAT_XBGR16161616F, 52 }; 53 54 /* Primary plane formats for vlv/chv */ 55 static const u32 vlv_primary_formats[] = { 56 DRM_FORMAT_C8, 57 DRM_FORMAT_RGB565, 58 DRM_FORMAT_XRGB8888, 59 DRM_FORMAT_XBGR8888, 60 DRM_FORMAT_ARGB8888, 61 DRM_FORMAT_ABGR8888, 62 DRM_FORMAT_XRGB2101010, 63 DRM_FORMAT_XBGR2101010, 64 DRM_FORMAT_ARGB2101010, 65 DRM_FORMAT_ABGR2101010, 66 DRM_FORMAT_XBGR16161616F, 67 }; 68 69 static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, 70 u32 format, u64 modifier) 71 { 72 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 73 return false; 74 75 switch (format) { 76 case DRM_FORMAT_C8: 77 case DRM_FORMAT_RGB565: 78 case DRM_FORMAT_XRGB1555: 79 case DRM_FORMAT_XRGB8888: 80 return modifier == DRM_FORMAT_MOD_LINEAR || 81 modifier == I915_FORMAT_MOD_X_TILED; 82 default: 83 return false; 84 } 85 } 86 87 static bool i965_plane_format_mod_supported(struct drm_plane *_plane, 88 u32 format, u64 modifier) 89 { 90 if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) 91 return false; 92 93 switch (format) { 94 case DRM_FORMAT_C8: 95 case DRM_FORMAT_RGB565: 96 case DRM_FORMAT_XRGB8888: 97 case DRM_FORMAT_XBGR8888: 98 case DRM_FORMAT_ARGB8888: 99 case DRM_FORMAT_ABGR8888: 100 case DRM_FORMAT_XRGB2101010: 101 case DRM_FORMAT_XBGR2101010: 102 case DRM_FORMAT_ARGB2101010: 103 case DRM_FORMAT_ABGR2101010: 104 case DRM_FORMAT_XBGR16161616F: 105 return modifier == DRM_FORMAT_MOD_LINEAR || 106 modifier == I915_FORMAT_MOD_X_TILED; 107 default: 108 return false; 109 } 110 } 111 112 static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, 113 enum i9xx_plane_id i9xx_plane) 114 { 115 if (!HAS_FBC(dev_priv)) 116 return false; 117 118 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 119 return i9xx_plane == PLANE_A; /* tied to pipe A */ 120 else if (IS_IVYBRIDGE(dev_priv)) 121 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || 122 i9xx_plane == PLANE_C; 123 else if (DISPLAY_VER(dev_priv) >= 4) 124 return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; 125 else 126 return i9xx_plane == PLANE_A; 127 } 128 129 static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv, 130 enum i9xx_plane_id i9xx_plane) 131 { 132 if (i9xx_plane_has_fbc(dev_priv, i9xx_plane)) 133 return dev_priv->display.fbc[INTEL_FBC_A]; 134 else 135 return NULL; 136 } 137 138 static bool i9xx_plane_has_windowing(struct intel_plane *plane) 139 { 140 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 141 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 142 143 if (IS_CHERRYVIEW(dev_priv)) 144 return i9xx_plane == PLANE_B; 145 else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 146 return false; 147 else if (DISPLAY_VER(dev_priv) == 4) 148 return i9xx_plane == PLANE_C; 149 else 150 return i9xx_plane == PLANE_B || 151 i9xx_plane == PLANE_C; 152 } 153 154 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, 155 const struct intel_plane_state *plane_state) 156 { 157 struct drm_i915_private *dev_priv = 158 to_i915(plane_state->uapi.plane->dev); 159 const struct drm_framebuffer *fb = plane_state->hw.fb; 160 unsigned int rotation = plane_state->hw.rotation; 161 u32 dspcntr; 162 163 dspcntr = DISP_ENABLE; 164 165 if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) || 166 IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) 167 dspcntr |= DISP_TRICKLE_FEED_DISABLE; 168 169 switch (fb->format->format) { 170 case DRM_FORMAT_C8: 171 dspcntr |= DISP_FORMAT_8BPP; 172 break; 173 case DRM_FORMAT_XRGB1555: 174 dspcntr |= DISP_FORMAT_BGRX555; 175 break; 176 case DRM_FORMAT_ARGB1555: 177 dspcntr |= DISP_FORMAT_BGRA555; 178 break; 179 case DRM_FORMAT_RGB565: 180 dspcntr |= DISP_FORMAT_BGRX565; 181 break; 182 case DRM_FORMAT_XRGB8888: 183 dspcntr |= DISP_FORMAT_BGRX888; 184 break; 185 case DRM_FORMAT_XBGR8888: 186 dspcntr |= DISP_FORMAT_RGBX888; 187 break; 188 case DRM_FORMAT_ARGB8888: 189 dspcntr |= DISP_FORMAT_BGRA888; 190 break; 191 case DRM_FORMAT_ABGR8888: 192 dspcntr |= DISP_FORMAT_RGBA888; 193 break; 194 case DRM_FORMAT_XRGB2101010: 195 dspcntr |= DISP_FORMAT_BGRX101010; 196 break; 197 case DRM_FORMAT_XBGR2101010: 198 dspcntr |= DISP_FORMAT_RGBX101010; 199 break; 200 case DRM_FORMAT_ARGB2101010: 201 dspcntr |= DISP_FORMAT_BGRA101010; 202 break; 203 case DRM_FORMAT_ABGR2101010: 204 dspcntr |= DISP_FORMAT_RGBA101010; 205 break; 206 case DRM_FORMAT_XBGR16161616F: 207 dspcntr |= DISP_FORMAT_RGBX161616; 208 break; 209 default: 210 MISSING_CASE(fb->format->format); 211 return 0; 212 } 213 214 if (DISPLAY_VER(dev_priv) >= 4 && 215 fb->modifier == I915_FORMAT_MOD_X_TILED) 216 dspcntr |= DISP_TILED; 217 218 if (rotation & DRM_MODE_ROTATE_180) 219 dspcntr |= DISP_ROTATE_180; 220 221 if (rotation & DRM_MODE_REFLECT_X) 222 dspcntr |= DISP_MIRROR; 223 224 return dspcntr; 225 } 226 227 int i9xx_check_plane_surface(struct intel_plane_state *plane_state) 228 { 229 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 230 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 231 const struct drm_framebuffer *fb = plane_state->hw.fb; 232 int src_x, src_y, src_w; 233 u32 offset; 234 int ret; 235 236 ret = intel_plane_compute_gtt(plane_state); 237 if (ret) 238 return ret; 239 240 if (!plane_state->uapi.visible) 241 return 0; 242 243 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 244 src_x = plane_state->uapi.src.x1 >> 16; 245 src_y = plane_state->uapi.src.y1 >> 16; 246 247 /* Undocumented hardware limit on i965/g4x/vlv/chv */ 248 if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) 249 return -EINVAL; 250 251 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); 252 253 if (DISPLAY_VER(dev_priv) >= 4) 254 offset = intel_plane_compute_aligned_offset(&src_x, &src_y, 255 plane_state, 0); 256 else 257 offset = 0; 258 259 /* 260 * When using an X-tiled surface the plane starts to 261 * misbehave if the x offset + width exceeds the stride. 262 * hsw/bdw: underrun galore 263 * ilk/snb/ivb: wrap to the next tile row mid scanout 264 * i965/g4x: so far appear immune to this 265 * vlv/chv: TODO check 266 * 267 * Linear surfaces seem to work just fine, even on hsw/bdw 268 * despite them not using the linear offset anymore. 269 */ 270 if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { 271 unsigned int alignment = plane->min_alignment(plane, fb, 0); 272 int cpp = fb->format->cpp[0]; 273 274 while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { 275 if (offset == 0) { 276 drm_dbg_kms(&dev_priv->drm, 277 "Unable to find suitable display surface offset due to X-tiling\n"); 278 return -EINVAL; 279 } 280 281 offset = intel_plane_adjust_aligned_offset(&src_x, &src_y, plane_state, 0, 282 offset, offset - alignment); 283 } 284 } 285 286 /* 287 * Put the final coordinates back so that the src 288 * coordinate checks will see the right values. 289 */ 290 drm_rect_translate_to(&plane_state->uapi.src, 291 src_x << 16, src_y << 16); 292 293 /* HSW/BDW do this automagically in hardware */ 294 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { 295 unsigned int rotation = plane_state->hw.rotation; 296 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 297 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 298 299 if (rotation & DRM_MODE_ROTATE_180) { 300 src_x += src_w - 1; 301 src_y += src_h - 1; 302 } else if (rotation & DRM_MODE_REFLECT_X) { 303 src_x += src_w - 1; 304 } 305 } 306 307 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 308 drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095); 309 } else if (DISPLAY_VER(dev_priv) >= 4 && 310 fb->modifier == I915_FORMAT_MOD_X_TILED) { 311 drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095); 312 } 313 314 plane_state->view.color_plane[0].offset = offset; 315 plane_state->view.color_plane[0].x = src_x; 316 plane_state->view.color_plane[0].y = src_y; 317 318 return 0; 319 } 320 321 static int 322 i9xx_plane_check(struct intel_crtc_state *crtc_state, 323 struct intel_plane_state *plane_state) 324 { 325 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 326 int ret; 327 328 ret = chv_plane_check_rotation(plane_state); 329 if (ret) 330 return ret; 331 332 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, 333 DRM_PLANE_NO_SCALING, 334 DRM_PLANE_NO_SCALING, 335 i9xx_plane_has_windowing(plane)); 336 if (ret) 337 return ret; 338 339 ret = i9xx_check_plane_surface(plane_state); 340 if (ret) 341 return ret; 342 343 if (!plane_state->uapi.visible) 344 return 0; 345 346 ret = intel_plane_check_src_coordinates(plane_state); 347 if (ret) 348 return ret; 349 350 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); 351 352 return 0; 353 } 354 355 static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) 356 { 357 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 358 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 359 u32 dspcntr = 0; 360 361 if (crtc_state->gamma_enable) 362 dspcntr |= DISP_PIPE_GAMMA_ENABLE; 363 364 if (crtc_state->csc_enable) 365 dspcntr |= DISP_PIPE_CSC_ENABLE; 366 367 if (DISPLAY_VER(dev_priv) < 5) 368 dspcntr |= DISP_PIPE_SEL(crtc->pipe); 369 370 return dspcntr; 371 } 372 373 static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, 374 const struct intel_plane_state *plane_state, 375 unsigned int *num, unsigned int *den) 376 { 377 const struct drm_framebuffer *fb = plane_state->hw.fb; 378 unsigned int cpp = fb->format->cpp[0]; 379 380 /* 381 * g4x bspec says 64bpp pixel rate can't exceed 80% 382 * of cdclk when the sprite plane is enabled on the 383 * same pipe. ilk/snb bspec says 64bpp pixel rate is 384 * never allowed to exceed 80% of cdclk. Let's just go 385 * with the ilk/snb limit always. 386 */ 387 if (cpp == 8) { 388 *num = 10; 389 *den = 8; 390 } else { 391 *num = 1; 392 *den = 1; 393 } 394 } 395 396 static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 397 const struct intel_plane_state *plane_state) 398 { 399 unsigned int pixel_rate; 400 unsigned int num, den; 401 402 /* 403 * Note that crtc_state->pixel_rate accounts for both 404 * horizontal and vertical panel fitter downscaling factors. 405 * Pre-HSW bspec tells us to only consider the horizontal 406 * downscaling factor here. We ignore that and just consider 407 * both for simplicity. 408 */ 409 pixel_rate = crtc_state->pixel_rate; 410 411 i9xx_plane_ratio(crtc_state, plane_state, &num, &den); 412 413 /* two pixels per clock with double wide pipe */ 414 if (crtc_state->double_wide) 415 den *= 2; 416 417 return DIV_ROUND_UP(pixel_rate * num, den); 418 } 419 420 static void i9xx_plane_update_noarm(struct intel_dsb *dsb, 421 struct intel_plane *plane, 422 const struct intel_crtc_state *crtc_state, 423 const struct intel_plane_state *plane_state) 424 { 425 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 426 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 427 428 intel_de_write_fw(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane), 429 plane_state->view.color_plane[0].mapping_stride); 430 431 if (DISPLAY_VER(dev_priv) < 4) { 432 int crtc_x = plane_state->uapi.dst.x1; 433 int crtc_y = plane_state->uapi.dst.y1; 434 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 435 int crtc_h = drm_rect_height(&plane_state->uapi.dst); 436 437 /* 438 * PLANE_A doesn't actually have a full window 439 * generator but let's assume we still need to 440 * program whatever is there. 441 */ 442 intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), 443 DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); 444 intel_de_write_fw(dev_priv, DSPSIZE(dev_priv, i9xx_plane), 445 DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); 446 } 447 } 448 449 static void i9xx_plane_update_arm(struct intel_dsb *dsb, 450 struct intel_plane *plane, 451 const struct intel_crtc_state *crtc_state, 452 const struct intel_plane_state *plane_state) 453 { 454 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 455 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 456 int x = plane_state->view.color_plane[0].x; 457 int y = plane_state->view.color_plane[0].y; 458 u32 dspcntr, dspaddr_offset, linear_offset; 459 460 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 461 462 /* see intel_plane_atomic_calc_changes() */ 463 if (plane->need_async_flip_toggle_wa && 464 crtc_state->async_flip_planes & BIT(plane->id)) 465 dspcntr |= DISP_ASYNC_FLIP; 466 467 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 468 469 if (DISPLAY_VER(dev_priv) >= 4) 470 dspaddr_offset = plane_state->view.color_plane[0].offset; 471 else 472 dspaddr_offset = linear_offset; 473 474 if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { 475 int crtc_x = plane_state->uapi.dst.x1; 476 int crtc_y = plane_state->uapi.dst.y1; 477 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 478 int crtc_h = drm_rect_height(&plane_state->uapi.dst); 479 480 intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), 481 PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); 482 intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane), 483 PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); 484 intel_de_write_fw(dev_priv, 485 PRIMCNSTALPHA(dev_priv, i9xx_plane), 0); 486 } 487 488 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 489 intel_de_write_fw(dev_priv, DSPOFFSET(dev_priv, i9xx_plane), 490 DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); 491 } else if (DISPLAY_VER(dev_priv) >= 4) { 492 intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane), 493 linear_offset); 494 intel_de_write_fw(dev_priv, DSPTILEOFF(dev_priv, i9xx_plane), 495 DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); 496 } 497 498 /* 499 * The control register self-arms if the plane was previously 500 * disabled. Try to make the plane enable atomic by writing 501 * the control register just before the surface register. 502 */ 503 intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); 504 505 if (DISPLAY_VER(dev_priv) >= 4) 506 intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 507 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 508 else 509 intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 510 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 511 } 512 513 static void i830_plane_update_arm(struct intel_dsb *dsb, 514 struct intel_plane *plane, 515 const struct intel_crtc_state *crtc_state, 516 const struct intel_plane_state *plane_state) 517 { 518 /* 519 * On i830/i845 all registers are self-arming [ALM040]. 520 * 521 * Additional breakage on i830 causes register reads to return 522 * the last latched value instead of the last written value [ALM026]. 523 */ 524 i9xx_plane_update_noarm(dsb, plane, crtc_state, plane_state); 525 i9xx_plane_update_arm(dsb, plane, crtc_state, plane_state); 526 } 527 528 static void i9xx_plane_disable_arm(struct intel_dsb *dsb, 529 struct intel_plane *plane, 530 const struct intel_crtc_state *crtc_state) 531 { 532 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 533 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 534 u32 dspcntr; 535 536 /* 537 * DSPCNTR pipe gamma enable on g4x+ and pipe csc 538 * enable on ilk+ affect the pipe bottom color as 539 * well, so we must configure them even if the plane 540 * is disabled. 541 * 542 * On pre-g4x there is no way to gamma correct the 543 * pipe bottom color but we'll keep on doing this 544 * anyway so that the crtc state readout works correctly. 545 */ 546 dspcntr = i9xx_plane_ctl_crtc(crtc_state); 547 548 intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); 549 550 if (DISPLAY_VER(dev_priv) >= 4) 551 intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 0); 552 else 553 intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0); 554 } 555 556 static void 557 g4x_primary_async_flip(struct intel_dsb *dsb, 558 struct intel_plane *plane, 559 const struct intel_crtc_state *crtc_state, 560 const struct intel_plane_state *plane_state, 561 bool async_flip) 562 { 563 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 564 u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); 565 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; 566 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 567 568 if (async_flip) 569 dspcntr |= DISP_ASYNC_FLIP; 570 571 intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); 572 573 intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 574 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 575 } 576 577 static void 578 vlv_primary_async_flip(struct intel_dsb *dsb, 579 struct intel_plane *plane, 580 const struct intel_crtc_state *crtc_state, 581 const struct intel_plane_state *plane_state, 582 bool async_flip) 583 { 584 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 585 u32 dspaddr_offset = plane_state->view.color_plane[0].offset; 586 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 587 588 intel_de_write_fw(dev_priv, DSPADDR_VLV(dev_priv, i9xx_plane), 589 intel_plane_ggtt_offset(plane_state) + dspaddr_offset); 590 } 591 592 static void 593 bdw_primary_enable_flip_done(struct intel_plane *plane) 594 { 595 struct drm_i915_private *i915 = to_i915(plane->base.dev); 596 enum pipe pipe = plane->pipe; 597 598 spin_lock_irq(&i915->irq_lock); 599 bdw_enable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); 600 spin_unlock_irq(&i915->irq_lock); 601 } 602 603 static void 604 bdw_primary_disable_flip_done(struct intel_plane *plane) 605 { 606 struct drm_i915_private *i915 = to_i915(plane->base.dev); 607 enum pipe pipe = plane->pipe; 608 609 spin_lock_irq(&i915->irq_lock); 610 bdw_disable_pipe_irq(i915, pipe, GEN8_PIPE_PRIMARY_FLIP_DONE); 611 spin_unlock_irq(&i915->irq_lock); 612 } 613 614 static void 615 ivb_primary_enable_flip_done(struct intel_plane *plane) 616 { 617 struct drm_i915_private *i915 = to_i915(plane->base.dev); 618 619 spin_lock_irq(&i915->irq_lock); 620 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); 621 spin_unlock_irq(&i915->irq_lock); 622 } 623 624 static void 625 ivb_primary_disable_flip_done(struct intel_plane *plane) 626 { 627 struct drm_i915_private *i915 = to_i915(plane->base.dev); 628 629 spin_lock_irq(&i915->irq_lock); 630 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE_IVB(plane->i9xx_plane)); 631 spin_unlock_irq(&i915->irq_lock); 632 } 633 634 static void 635 ilk_primary_enable_flip_done(struct intel_plane *plane) 636 { 637 struct drm_i915_private *i915 = to_i915(plane->base.dev); 638 639 spin_lock_irq(&i915->irq_lock); 640 ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); 641 spin_unlock_irq(&i915->irq_lock); 642 } 643 644 static void 645 ilk_primary_disable_flip_done(struct intel_plane *plane) 646 { 647 struct drm_i915_private *i915 = to_i915(plane->base.dev); 648 649 spin_lock_irq(&i915->irq_lock); 650 ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane)); 651 spin_unlock_irq(&i915->irq_lock); 652 } 653 654 static void 655 vlv_primary_enable_flip_done(struct intel_plane *plane) 656 { 657 struct drm_i915_private *i915 = to_i915(plane->base.dev); 658 enum pipe pipe = plane->pipe; 659 660 spin_lock_irq(&i915->irq_lock); 661 i915_enable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); 662 spin_unlock_irq(&i915->irq_lock); 663 } 664 665 static void 666 vlv_primary_disable_flip_done(struct intel_plane *plane) 667 { 668 struct drm_i915_private *i915 = to_i915(plane->base.dev); 669 enum pipe pipe = plane->pipe; 670 671 spin_lock_irq(&i915->irq_lock); 672 i915_disable_pipestat(i915, pipe, PLANE_FLIP_DONE_INT_STATUS_VLV); 673 spin_unlock_irq(&i915->irq_lock); 674 } 675 676 static bool i9xx_plane_can_async_flip(u64 modifier) 677 { 678 return modifier == I915_FORMAT_MOD_X_TILED; 679 } 680 681 static bool i9xx_plane_get_hw_state(struct intel_plane *plane, 682 enum pipe *pipe) 683 { 684 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 685 enum intel_display_power_domain power_domain; 686 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 687 intel_wakeref_t wakeref; 688 bool ret; 689 u32 val; 690 691 /* 692 * Not 100% correct for planes that can move between pipes, 693 * but that's only the case for gen2-4 which don't have any 694 * display power wells. 695 */ 696 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 697 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 698 if (!wakeref) 699 return false; 700 701 val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); 702 703 ret = val & DISP_ENABLE; 704 705 if (DISPLAY_VER(dev_priv) >= 5) 706 *pipe = plane->pipe; 707 else 708 *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val); 709 710 intel_display_power_put(dev_priv, power_domain, wakeref); 711 712 return ret; 713 } 714 715 static unsigned int 716 hsw_primary_max_stride(struct intel_plane *plane, 717 u32 pixel_format, u64 modifier, 718 unsigned int rotation) 719 { 720 const struct drm_format_info *info = drm_format_info(pixel_format); 721 int cpp = info->cpp[0]; 722 723 /* Limit to 8k pixels to guarantee OFFSET.x doesn't get too big. */ 724 return min(8192 * cpp, 32 * 1024); 725 } 726 727 static unsigned int 728 ilk_primary_max_stride(struct intel_plane *plane, 729 u32 pixel_format, u64 modifier, 730 unsigned int rotation) 731 { 732 const struct drm_format_info *info = drm_format_info(pixel_format); 733 int cpp = info->cpp[0]; 734 735 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 736 if (modifier == I915_FORMAT_MOD_X_TILED) 737 return min(4096 * cpp, 32 * 1024); 738 else 739 return 32 * 1024; 740 } 741 742 unsigned int 743 i965_plane_max_stride(struct intel_plane *plane, 744 u32 pixel_format, u64 modifier, 745 unsigned int rotation) 746 { 747 const struct drm_format_info *info = drm_format_info(pixel_format); 748 int cpp = info->cpp[0]; 749 750 /* Limit to 4k pixels to guarantee TILEOFF.x doesn't get too big. */ 751 if (modifier == I915_FORMAT_MOD_X_TILED) 752 return min(4096 * cpp, 16 * 1024); 753 else 754 return 32 * 1024; 755 } 756 757 static unsigned int 758 i915_plane_max_stride(struct intel_plane *plane, 759 u32 pixel_format, u64 modifier, 760 unsigned int rotation) 761 { 762 if (modifier == I915_FORMAT_MOD_X_TILED) 763 return 8 * 1024; 764 else 765 return 16 * 1024; 766 } 767 768 static unsigned int 769 i8xx_plane_max_stride(struct intel_plane *plane, 770 u32 pixel_format, u64 modifier, 771 unsigned int rotation) 772 { 773 if (plane->i9xx_plane == PLANE_C) 774 return 4 * 1024; 775 else 776 return 8 * 1024; 777 } 778 779 unsigned int vlv_plane_min_alignment(struct intel_plane *plane, 780 const struct drm_framebuffer *fb, 781 int color_plane) 782 { 783 if (intel_plane_can_async_flip(plane, fb->modifier)) 784 return 256 * 1024; 785 786 switch (fb->modifier) { 787 case I915_FORMAT_MOD_X_TILED: 788 return 4 * 1024; 789 case DRM_FORMAT_MOD_LINEAR: 790 return 128 * 1024; 791 default: 792 MISSING_CASE(fb->modifier); 793 return 0; 794 } 795 } 796 797 static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, 798 const struct drm_framebuffer *fb, 799 int color_plane) 800 { 801 if (intel_plane_can_async_flip(plane, fb->modifier)) 802 return 256 * 1024; 803 804 switch (fb->modifier) { 805 case I915_FORMAT_MOD_X_TILED: 806 case DRM_FORMAT_MOD_LINEAR: 807 return 4 * 1024; 808 default: 809 MISSING_CASE(fb->modifier); 810 return 0; 811 } 812 } 813 814 static unsigned int i965_plane_min_alignment(struct intel_plane *plane, 815 const struct drm_framebuffer *fb, 816 int color_plane) 817 { 818 switch (fb->modifier) { 819 case I915_FORMAT_MOD_X_TILED: 820 return 4 * 1024; 821 case DRM_FORMAT_MOD_LINEAR: 822 return 128 * 1024; 823 default: 824 MISSING_CASE(fb->modifier); 825 return 0; 826 } 827 } 828 829 static unsigned int i9xx_plane_min_alignment(struct intel_plane *plane, 830 const struct drm_framebuffer *fb, 831 int color_plane) 832 { 833 return 0; 834 } 835 836 static const struct drm_plane_funcs i965_plane_funcs = { 837 .update_plane = drm_atomic_helper_update_plane, 838 .disable_plane = drm_atomic_helper_disable_plane, 839 .destroy = intel_plane_destroy, 840 .atomic_duplicate_state = intel_plane_duplicate_state, 841 .atomic_destroy_state = intel_plane_destroy_state, 842 .format_mod_supported = i965_plane_format_mod_supported, 843 }; 844 845 static const struct drm_plane_funcs i8xx_plane_funcs = { 846 .update_plane = drm_atomic_helper_update_plane, 847 .disable_plane = drm_atomic_helper_disable_plane, 848 .destroy = intel_plane_destroy, 849 .atomic_duplicate_state = intel_plane_duplicate_state, 850 .atomic_destroy_state = intel_plane_destroy_state, 851 .format_mod_supported = i8xx_plane_format_mod_supported, 852 }; 853 854 struct intel_plane * 855 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 856 { 857 struct intel_plane *plane; 858 const struct drm_plane_funcs *plane_funcs; 859 unsigned int supported_rotations; 860 const u64 *modifiers; 861 const u32 *formats; 862 int num_formats; 863 int ret, zpos; 864 865 plane = intel_plane_alloc(); 866 if (IS_ERR(plane)) 867 return plane; 868 869 plane->pipe = pipe; 870 /* 871 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS 872 * port is hooked to pipe B. Hence we want plane A feeding pipe B. 873 */ 874 if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 && 875 INTEL_NUM_PIPES(dev_priv) == 2) 876 plane->i9xx_plane = (enum i9xx_plane_id) !pipe; 877 else 878 plane->i9xx_plane = (enum i9xx_plane_id) pipe; 879 plane->id = PLANE_PRIMARY; 880 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); 881 882 intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane); 883 884 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 885 formats = vlv_primary_formats; 886 num_formats = ARRAY_SIZE(vlv_primary_formats); 887 } else if (DISPLAY_VER(dev_priv) >= 4) { 888 /* 889 * WaFP16GammaEnabling:ivb 890 * "Workaround : When using the 64-bit format, the plane 891 * output on each color channel has one quarter amplitude. 892 * It can be brought up to full amplitude by using pipe 893 * gamma correction or pipe color space conversion to 894 * multiply the plane output by four." 895 * 896 * There is no dedicated plane gamma for the primary plane, 897 * and using the pipe gamma/csc could conflict with other 898 * planes, so we choose not to expose fp16 on IVB primary 899 * planes. HSW primary planes no longer have this problem. 900 */ 901 if (IS_IVYBRIDGE(dev_priv)) { 902 formats = ivb_primary_formats; 903 num_formats = ARRAY_SIZE(ivb_primary_formats); 904 } else { 905 formats = i965_primary_formats; 906 num_formats = ARRAY_SIZE(i965_primary_formats); 907 } 908 } else { 909 formats = i8xx_primary_formats; 910 num_formats = ARRAY_SIZE(i8xx_primary_formats); 911 } 912 913 if (DISPLAY_VER(dev_priv) >= 4) 914 plane_funcs = &i965_plane_funcs; 915 else 916 plane_funcs = &i8xx_plane_funcs; 917 918 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 919 plane->min_cdclk = vlv_plane_min_cdclk; 920 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 921 plane->min_cdclk = hsw_plane_min_cdclk; 922 else if (IS_IVYBRIDGE(dev_priv)) 923 plane->min_cdclk = ivb_plane_min_cdclk; 924 else 925 plane->min_cdclk = i9xx_plane_min_cdclk; 926 927 if (HAS_GMCH(dev_priv)) { 928 if (DISPLAY_VER(dev_priv) >= 4) 929 plane->max_stride = i965_plane_max_stride; 930 else if (DISPLAY_VER(dev_priv) == 3) 931 plane->max_stride = i915_plane_max_stride; 932 else 933 plane->max_stride = i8xx_plane_max_stride; 934 } else { 935 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 936 plane->max_stride = hsw_primary_max_stride; 937 else 938 plane->max_stride = ilk_primary_max_stride; 939 } 940 941 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 942 plane->min_alignment = vlv_plane_min_alignment; 943 else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 944 plane->min_alignment = g4x_primary_min_alignment; 945 else if (DISPLAY_VER(dev_priv) == 4) 946 plane->min_alignment = i965_plane_min_alignment; 947 else 948 plane->min_alignment = i9xx_plane_min_alignment; 949 950 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { 951 plane->update_arm = i830_plane_update_arm; 952 } else { 953 plane->update_noarm = i9xx_plane_update_noarm; 954 plane->update_arm = i9xx_plane_update_arm; 955 } 956 plane->disable_arm = i9xx_plane_disable_arm; 957 plane->get_hw_state = i9xx_plane_get_hw_state; 958 plane->check_plane = i9xx_plane_check; 959 960 if (HAS_ASYNC_FLIPS(dev_priv)) { 961 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 962 plane->async_flip = vlv_primary_async_flip; 963 plane->enable_flip_done = vlv_primary_enable_flip_done; 964 plane->disable_flip_done = vlv_primary_disable_flip_done; 965 plane->can_async_flip = i9xx_plane_can_async_flip; 966 } else if (IS_BROADWELL(dev_priv)) { 967 plane->need_async_flip_toggle_wa = true; 968 plane->async_flip = g4x_primary_async_flip; 969 plane->enable_flip_done = bdw_primary_enable_flip_done; 970 plane->disable_flip_done = bdw_primary_disable_flip_done; 971 plane->can_async_flip = i9xx_plane_can_async_flip; 972 } else if (DISPLAY_VER(dev_priv) >= 7) { 973 plane->async_flip = g4x_primary_async_flip; 974 plane->enable_flip_done = ivb_primary_enable_flip_done; 975 plane->disable_flip_done = ivb_primary_disable_flip_done; 976 plane->can_async_flip = i9xx_plane_can_async_flip; 977 } else if (DISPLAY_VER(dev_priv) >= 5) { 978 plane->async_flip = g4x_primary_async_flip; 979 plane->enable_flip_done = ilk_primary_enable_flip_done; 980 plane->disable_flip_done = ilk_primary_disable_flip_done; 981 plane->can_async_flip = i9xx_plane_can_async_flip; 982 } 983 } 984 985 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); 986 987 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) 988 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 989 0, plane_funcs, 990 formats, num_formats, 991 modifiers, 992 DRM_PLANE_TYPE_PRIMARY, 993 "primary %c", pipe_name(pipe)); 994 else 995 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 996 0, plane_funcs, 997 formats, num_formats, 998 modifiers, 999 DRM_PLANE_TYPE_PRIMARY, 1000 "plane %c", 1001 plane_name(plane->i9xx_plane)); 1002 1003 kfree(modifiers); 1004 1005 if (ret) 1006 goto fail; 1007 1008 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 1009 supported_rotations = 1010 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 1011 DRM_MODE_REFLECT_X; 1012 } else if (DISPLAY_VER(dev_priv) >= 4) { 1013 supported_rotations = 1014 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 1015 } else { 1016 supported_rotations = DRM_MODE_ROTATE_0; 1017 } 1018 1019 if (DISPLAY_VER(dev_priv) >= 4) 1020 drm_plane_create_rotation_property(&plane->base, 1021 DRM_MODE_ROTATE_0, 1022 supported_rotations); 1023 1024 zpos = 0; 1025 drm_plane_create_zpos_immutable_property(&plane->base, zpos); 1026 1027 intel_plane_helper_add(plane); 1028 1029 return plane; 1030 1031 fail: 1032 intel_plane_free(plane); 1033 1034 return ERR_PTR(ret); 1035 } 1036 1037 static int i9xx_format_to_fourcc(int format) 1038 { 1039 switch (format) { 1040 case DISP_FORMAT_8BPP: 1041 return DRM_FORMAT_C8; 1042 case DISP_FORMAT_BGRA555: 1043 return DRM_FORMAT_ARGB1555; 1044 case DISP_FORMAT_BGRX555: 1045 return DRM_FORMAT_XRGB1555; 1046 case DISP_FORMAT_BGRX565: 1047 return DRM_FORMAT_RGB565; 1048 default: 1049 case DISP_FORMAT_BGRX888: 1050 return DRM_FORMAT_XRGB8888; 1051 case DISP_FORMAT_RGBX888: 1052 return DRM_FORMAT_XBGR8888; 1053 case DISP_FORMAT_BGRA888: 1054 return DRM_FORMAT_ARGB8888; 1055 case DISP_FORMAT_RGBA888: 1056 return DRM_FORMAT_ABGR8888; 1057 case DISP_FORMAT_BGRX101010: 1058 return DRM_FORMAT_XRGB2101010; 1059 case DISP_FORMAT_RGBX101010: 1060 return DRM_FORMAT_XBGR2101010; 1061 case DISP_FORMAT_BGRA101010: 1062 return DRM_FORMAT_ARGB2101010; 1063 case DISP_FORMAT_RGBA101010: 1064 return DRM_FORMAT_ABGR2101010; 1065 case DISP_FORMAT_RGBX161616: 1066 return DRM_FORMAT_XBGR16161616F; 1067 } 1068 } 1069 1070 void 1071 i9xx_get_initial_plane_config(struct intel_crtc *crtc, 1072 struct intel_initial_plane_config *plane_config) 1073 { 1074 struct drm_device *dev = crtc->base.dev; 1075 struct drm_i915_private *dev_priv = to_i915(dev); 1076 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1077 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 1078 enum pipe pipe; 1079 u32 val, base, offset; 1080 int fourcc, pixel_format; 1081 unsigned int aligned_height; 1082 struct drm_framebuffer *fb; 1083 struct intel_framebuffer *intel_fb; 1084 1085 if (!plane->get_hw_state(plane, &pipe)) 1086 return; 1087 1088 drm_WARN_ON(dev, pipe != crtc->pipe); 1089 1090 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 1091 if (!intel_fb) { 1092 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); 1093 return; 1094 } 1095 1096 fb = &intel_fb->base; 1097 1098 fb->dev = dev; 1099 1100 val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); 1101 1102 if (DISPLAY_VER(dev_priv) >= 4) { 1103 if (val & DISP_TILED) { 1104 plane_config->tiling = I915_TILING_X; 1105 fb->modifier = I915_FORMAT_MOD_X_TILED; 1106 } 1107 1108 if (val & DISP_ROTATE_180) 1109 plane_config->rotation = DRM_MODE_ROTATE_180; 1110 } 1111 1112 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && 1113 val & DISP_MIRROR) 1114 plane_config->rotation |= DRM_MODE_REFLECT_X; 1115 1116 pixel_format = val & DISP_FORMAT_MASK; 1117 fourcc = i9xx_format_to_fourcc(pixel_format); 1118 fb->format = drm_format_info(fourcc); 1119 1120 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1121 offset = intel_de_read(dev_priv, 1122 DSPOFFSET(dev_priv, i9xx_plane)); 1123 base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; 1124 } else if (DISPLAY_VER(dev_priv) >= 4) { 1125 if (plane_config->tiling) 1126 offset = intel_de_read(dev_priv, 1127 DSPTILEOFF(dev_priv, i9xx_plane)); 1128 else 1129 offset = intel_de_read(dev_priv, 1130 DSPLINOFF(dev_priv, i9xx_plane)); 1131 base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; 1132 } else { 1133 offset = 0; 1134 base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane)); 1135 } 1136 plane_config->base = base; 1137 1138 drm_WARN_ON(&dev_priv->drm, offset != 0); 1139 1140 val = intel_de_read(dev_priv, PIPESRC(dev_priv, pipe)); 1141 fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; 1142 fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; 1143 1144 val = intel_de_read(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane)); 1145 fb->pitches[0] = val & 0xffffffc0; 1146 1147 aligned_height = intel_fb_align_height(fb, 0, fb->height); 1148 1149 plane_config->size = fb->pitches[0] * aligned_height; 1150 1151 drm_dbg_kms(&dev_priv->drm, 1152 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 1153 crtc->base.name, plane->base.name, fb->width, fb->height, 1154 fb->format->cpp[0] * 8, base, fb->pitches[0], 1155 plane_config->size); 1156 1157 plane_config->fb = intel_fb; 1158 } 1159 1160 bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, 1161 const struct intel_initial_plane_config *plane_config) 1162 { 1163 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1164 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1165 const struct intel_plane_state *plane_state = 1166 to_intel_plane_state(plane->base.state); 1167 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 1168 u32 base; 1169 1170 if (!plane_state->uapi.visible) 1171 return false; 1172 1173 base = intel_plane_ggtt_offset(plane_state); 1174 1175 /* 1176 * We may have moved the surface to a different 1177 * part of ggtt, make the plane aware of that. 1178 */ 1179 if (plane_config->base == base) 1180 return false; 1181 1182 if (DISPLAY_VER(dev_priv) >= 4) 1183 intel_de_write(dev_priv, DSPSURF(dev_priv, i9xx_plane), base); 1184 else 1185 intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base); 1186 1187 return true; 1188 } 1189