1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include "g4x_hdmi.h" 9 #include "i915_reg.h" 10 #include "intel_atomic.h" 11 #include "intel_audio.h" 12 #include "intel_connector.h" 13 #include "intel_crtc.h" 14 #include "intel_de.h" 15 #include "intel_display_power.h" 16 #include "intel_display_types.h" 17 #include "intel_dp_aux.h" 18 #include "intel_dpio_phy.h" 19 #include "intel_fdi.h" 20 #include "intel_fifo_underrun.h" 21 #include "intel_hdmi.h" 22 #include "intel_hotplug.h" 23 #include "intel_sdvo.h" 24 #include "vlv_sideband.h" 25 26 static void intel_hdmi_prepare(struct intel_encoder *encoder, 27 const struct intel_crtc_state *crtc_state) 28 { 29 struct drm_device *dev = encoder->base.dev; 30 struct drm_i915_private *dev_priv = to_i915(dev); 31 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 32 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 33 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 34 u32 hdmi_val; 35 36 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 37 38 hdmi_val = SDVO_ENCODING_HDMI; 39 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 40 hdmi_val |= HDMI_COLOR_RANGE_16_235; 41 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 42 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 43 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 44 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 45 46 if (crtc_state->pipe_bpp > 24) 47 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 48 else 49 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 50 51 if (crtc_state->has_hdmi_sink) 52 hdmi_val |= HDMI_MODE_SELECT_HDMI; 53 54 if (HAS_PCH_CPT(dev_priv)) 55 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 56 else if (IS_CHERRYVIEW(dev_priv)) 57 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 58 else 59 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 60 61 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 62 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 63 } 64 65 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 66 enum pipe *pipe) 67 { 68 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 69 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 70 intel_wakeref_t wakeref; 71 bool ret; 72 73 wakeref = intel_display_power_get_if_enabled(dev_priv, 74 encoder->power_domain); 75 if (!wakeref) 76 return false; 77 78 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 79 80 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 81 82 return ret; 83 } 84 85 static bool connector_is_hdmi(struct drm_connector *connector) 86 { 87 struct intel_encoder *encoder = 88 intel_attached_encoder(to_intel_connector(connector)); 89 90 return encoder && encoder->type == INTEL_OUTPUT_HDMI; 91 } 92 93 static bool g4x_compute_has_hdmi_sink(struct intel_atomic_state *state, 94 struct intel_crtc *this_crtc) 95 { 96 const struct drm_connector_state *conn_state; 97 struct drm_connector *connector; 98 int i; 99 100 /* 101 * On g4x only one HDMI port can transmit infoframes/audio at 102 * any given time. Select the first suitable port for this duty. 103 * 104 * See also g4x_hdmi_connector_atomic_check(). 105 */ 106 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 107 struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder); 108 const struct intel_crtc_state *crtc_state; 109 struct intel_crtc *crtc; 110 111 if (!connector_is_hdmi(connector)) 112 continue; 113 114 crtc = to_intel_crtc(conn_state->crtc); 115 if (!crtc) 116 continue; 117 118 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 119 120 if (!intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state)) 121 continue; 122 123 return crtc == this_crtc; 124 } 125 126 return false; 127 } 128 129 static int g4x_hdmi_compute_config(struct intel_encoder *encoder, 130 struct intel_crtc_state *crtc_state, 131 struct drm_connector_state *conn_state) 132 { 133 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 134 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 135 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 136 137 if (HAS_PCH_SPLIT(i915)) { 138 crtc_state->has_pch_encoder = true; 139 if (!intel_fdi_compute_pipe_bpp(crtc_state)) 140 return -EINVAL; 141 } 142 143 if (IS_G4X(i915)) 144 crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc); 145 else 146 crtc_state->has_hdmi_sink = 147 intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state); 148 149 return intel_hdmi_compute_config(encoder, crtc_state, conn_state); 150 } 151 152 static void intel_hdmi_get_config(struct intel_encoder *encoder, 153 struct intel_crtc_state *pipe_config) 154 { 155 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 156 struct drm_device *dev = encoder->base.dev; 157 struct drm_i915_private *dev_priv = to_i915(dev); 158 u32 tmp, flags = 0; 159 int dotclock; 160 161 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 162 163 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 164 165 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 166 flags |= DRM_MODE_FLAG_PHSYNC; 167 else 168 flags |= DRM_MODE_FLAG_NHSYNC; 169 170 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 171 flags |= DRM_MODE_FLAG_PVSYNC; 172 else 173 flags |= DRM_MODE_FLAG_NVSYNC; 174 175 if (tmp & HDMI_MODE_SELECT_HDMI) 176 pipe_config->has_hdmi_sink = true; 177 178 pipe_config->infoframes.enable |= 179 intel_hdmi_infoframes_enabled(encoder, pipe_config); 180 181 if (pipe_config->infoframes.enable) 182 pipe_config->has_infoframe = true; 183 184 if (tmp & HDMI_AUDIO_ENABLE) 185 pipe_config->has_audio = true; 186 187 if (!HAS_PCH_SPLIT(dev_priv) && 188 tmp & HDMI_COLOR_RANGE_16_235) 189 pipe_config->limited_color_range = true; 190 191 pipe_config->hw.adjusted_mode.flags |= flags; 192 193 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 194 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); 195 else 196 dotclock = pipe_config->port_clock; 197 198 if (pipe_config->pixel_multiplier) 199 dotclock /= pipe_config->pixel_multiplier; 200 201 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 202 203 pipe_config->lane_count = 4; 204 205 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 206 207 intel_read_infoframe(encoder, pipe_config, 208 HDMI_INFOFRAME_TYPE_AVI, 209 &pipe_config->infoframes.avi); 210 intel_read_infoframe(encoder, pipe_config, 211 HDMI_INFOFRAME_TYPE_SPD, 212 &pipe_config->infoframes.spd); 213 intel_read_infoframe(encoder, pipe_config, 214 HDMI_INFOFRAME_TYPE_VENDOR, 215 &pipe_config->infoframes.hdmi); 216 217 intel_audio_codec_get_config(encoder, pipe_config); 218 } 219 220 static void g4x_hdmi_enable_port(struct intel_encoder *encoder, 221 const struct intel_crtc_state *pipe_config) 222 { 223 struct drm_device *dev = encoder->base.dev; 224 struct drm_i915_private *dev_priv = to_i915(dev); 225 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 226 u32 temp; 227 228 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 229 230 temp |= SDVO_ENABLE; 231 if (pipe_config->has_audio) 232 temp |= HDMI_AUDIO_ENABLE; 233 234 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 235 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 236 } 237 238 static void g4x_enable_hdmi(struct intel_atomic_state *state, 239 struct intel_encoder *encoder, 240 const struct intel_crtc_state *pipe_config, 241 const struct drm_connector_state *conn_state) 242 { 243 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 244 245 g4x_hdmi_enable_port(encoder, pipe_config); 246 247 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 248 !pipe_config->has_hdmi_sink); 249 intel_audio_codec_enable(encoder, pipe_config, conn_state); 250 } 251 252 static void ibx_enable_hdmi(struct intel_atomic_state *state, 253 struct intel_encoder *encoder, 254 const struct intel_crtc_state *pipe_config, 255 const struct drm_connector_state *conn_state) 256 { 257 struct drm_device *dev = encoder->base.dev; 258 struct drm_i915_private *dev_priv = to_i915(dev); 259 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 260 u32 temp; 261 262 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 263 264 temp |= SDVO_ENABLE; 265 if (pipe_config->has_audio) 266 temp |= HDMI_AUDIO_ENABLE; 267 268 /* 269 * HW workaround, need to write this twice for issue 270 * that may result in first write getting masked. 271 */ 272 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 273 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 274 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 275 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 276 277 /* 278 * HW workaround, need to toggle enable bit off and on 279 * for 12bpc with pixel repeat. 280 * 281 * FIXME: BSpec says this should be done at the end of 282 * the modeset sequence, so not sure if this isn't too soon. 283 */ 284 if (pipe_config->pipe_bpp > 24 && 285 pipe_config->pixel_multiplier > 1) { 286 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 287 temp & ~SDVO_ENABLE); 288 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 289 290 /* 291 * HW workaround, need to write this twice for issue 292 * that may result in first write getting masked. 293 */ 294 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 295 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 296 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 297 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 298 } 299 300 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 301 !pipe_config->has_hdmi_sink); 302 intel_audio_codec_enable(encoder, pipe_config, conn_state); 303 } 304 305 static void cpt_enable_hdmi(struct intel_atomic_state *state, 306 struct intel_encoder *encoder, 307 const struct intel_crtc_state *pipe_config, 308 const struct drm_connector_state *conn_state) 309 { 310 struct drm_device *dev = encoder->base.dev; 311 struct drm_i915_private *dev_priv = to_i915(dev); 312 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 313 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 314 enum pipe pipe = crtc->pipe; 315 u32 temp; 316 317 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 318 319 temp |= SDVO_ENABLE; 320 if (pipe_config->has_audio) 321 temp |= HDMI_AUDIO_ENABLE; 322 323 /* 324 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 325 * 326 * The procedure for 12bpc is as follows: 327 * 1. disable HDMI clock gating 328 * 2. enable HDMI with 8bpc 329 * 3. enable HDMI with 12bpc 330 * 4. enable HDMI clock gating 331 */ 332 333 if (pipe_config->pipe_bpp > 24) { 334 intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), 335 0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 336 337 temp &= ~SDVO_COLOR_FORMAT_MASK; 338 temp |= SDVO_COLOR_FORMAT_8bpc; 339 } 340 341 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 342 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 343 344 if (pipe_config->pipe_bpp > 24) { 345 temp &= ~SDVO_COLOR_FORMAT_MASK; 346 temp |= HDMI_COLOR_FORMAT_12bpc; 347 348 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 349 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 350 351 intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), 352 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0); 353 } 354 355 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 356 !pipe_config->has_hdmi_sink); 357 intel_audio_codec_enable(encoder, pipe_config, conn_state); 358 } 359 360 static void vlv_enable_hdmi(struct intel_atomic_state *state, 361 struct intel_encoder *encoder, 362 const struct intel_crtc_state *pipe_config, 363 const struct drm_connector_state *conn_state) 364 { 365 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 366 367 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 368 !pipe_config->has_hdmi_sink); 369 intel_audio_codec_enable(encoder, pipe_config, conn_state); 370 } 371 372 static void intel_disable_hdmi(struct intel_atomic_state *state, 373 struct intel_encoder *encoder, 374 const struct intel_crtc_state *old_crtc_state, 375 const struct drm_connector_state *old_conn_state) 376 { 377 struct drm_device *dev = encoder->base.dev; 378 struct drm_i915_private *dev_priv = to_i915(dev); 379 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 380 struct intel_digital_port *dig_port = 381 hdmi_to_dig_port(intel_hdmi); 382 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 383 u32 temp; 384 385 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 386 387 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 388 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 389 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 390 391 /* 392 * HW workaround for IBX, we need to move the port 393 * to transcoder A after disabling it to allow the 394 * matching DP port to be enabled on transcoder A. 395 */ 396 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 397 /* 398 * We get CPU/PCH FIFO underruns on the other pipe when 399 * doing the workaround. Sweep them under the rug. 400 */ 401 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 402 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 403 404 temp &= ~SDVO_PIPE_SEL_MASK; 405 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 406 /* 407 * HW workaround, need to write this twice for issue 408 * that may result in first write getting masked. 409 */ 410 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 411 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 412 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 413 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 414 415 temp &= ~SDVO_ENABLE; 416 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 417 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 418 419 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 420 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 421 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 422 } 423 424 dig_port->set_infoframes(encoder, 425 false, 426 old_crtc_state, old_conn_state); 427 428 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 429 } 430 431 static void g4x_disable_hdmi(struct intel_atomic_state *state, 432 struct intel_encoder *encoder, 433 const struct intel_crtc_state *old_crtc_state, 434 const struct drm_connector_state *old_conn_state) 435 { 436 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 437 438 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 439 } 440 441 static void pch_disable_hdmi(struct intel_atomic_state *state, 442 struct intel_encoder *encoder, 443 const struct intel_crtc_state *old_crtc_state, 444 const struct drm_connector_state *old_conn_state) 445 { 446 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 447 } 448 449 static void pch_post_disable_hdmi(struct intel_atomic_state *state, 450 struct intel_encoder *encoder, 451 const struct intel_crtc_state *old_crtc_state, 452 const struct drm_connector_state *old_conn_state) 453 { 454 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 455 } 456 457 static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 458 struct intel_encoder *encoder, 459 const struct intel_crtc_state *pipe_config, 460 const struct drm_connector_state *conn_state) 461 { 462 struct intel_digital_port *dig_port = 463 enc_to_dig_port(encoder); 464 465 intel_hdmi_prepare(encoder, pipe_config); 466 467 dig_port->set_infoframes(encoder, 468 pipe_config->has_infoframe, 469 pipe_config, conn_state); 470 } 471 472 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 473 struct intel_encoder *encoder, 474 const struct intel_crtc_state *pipe_config, 475 const struct drm_connector_state *conn_state) 476 { 477 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 479 480 vlv_phy_pre_encoder_enable(encoder, pipe_config); 481 482 /* HDMI 1.0V-2dB */ 483 vlv_set_phy_signal_level(encoder, pipe_config, 484 0x2b245f5f, 0x00002000, 485 0x5578b83a, 0x2b247878); 486 487 dig_port->set_infoframes(encoder, 488 pipe_config->has_infoframe, 489 pipe_config, conn_state); 490 491 g4x_hdmi_enable_port(encoder, pipe_config); 492 493 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 494 } 495 496 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 497 struct intel_encoder *encoder, 498 const struct intel_crtc_state *pipe_config, 499 const struct drm_connector_state *conn_state) 500 { 501 intel_hdmi_prepare(encoder, pipe_config); 502 503 vlv_phy_pre_pll_enable(encoder, pipe_config); 504 } 505 506 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 507 struct intel_encoder *encoder, 508 const struct intel_crtc_state *pipe_config, 509 const struct drm_connector_state *conn_state) 510 { 511 intel_hdmi_prepare(encoder, pipe_config); 512 513 chv_phy_pre_pll_enable(encoder, pipe_config); 514 } 515 516 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 517 struct intel_encoder *encoder, 518 const struct intel_crtc_state *old_crtc_state, 519 const struct drm_connector_state *old_conn_state) 520 { 521 chv_phy_post_pll_disable(encoder, old_crtc_state); 522 } 523 524 static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 525 struct intel_encoder *encoder, 526 const struct intel_crtc_state *old_crtc_state, 527 const struct drm_connector_state *old_conn_state) 528 { 529 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 530 vlv_phy_reset_lanes(encoder, old_crtc_state); 531 } 532 533 static void chv_hdmi_post_disable(struct intel_atomic_state *state, 534 struct intel_encoder *encoder, 535 const struct intel_crtc_state *old_crtc_state, 536 const struct drm_connector_state *old_conn_state) 537 { 538 struct drm_device *dev = encoder->base.dev; 539 struct drm_i915_private *dev_priv = to_i915(dev); 540 541 vlv_dpio_get(dev_priv); 542 543 /* Assert data lane reset */ 544 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 545 546 vlv_dpio_put(dev_priv); 547 } 548 549 static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 550 struct intel_encoder *encoder, 551 const struct intel_crtc_state *pipe_config, 552 const struct drm_connector_state *conn_state) 553 { 554 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 555 struct drm_device *dev = encoder->base.dev; 556 struct drm_i915_private *dev_priv = to_i915(dev); 557 558 chv_phy_pre_encoder_enable(encoder, pipe_config); 559 560 /* FIXME: Program the support xxx V-dB */ 561 /* Use 800mV-0dB */ 562 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); 563 564 dig_port->set_infoframes(encoder, 565 pipe_config->has_infoframe, 566 pipe_config, conn_state); 567 568 g4x_hdmi_enable_port(encoder, pipe_config); 569 570 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 571 572 /* Second common lane will stay alive on its own now */ 573 chv_phy_release_cl2_override(encoder); 574 } 575 576 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 577 .destroy = intel_encoder_destroy, 578 }; 579 580 static enum intel_hotplug_state 581 intel_hdmi_hotplug(struct intel_encoder *encoder, 582 struct intel_connector *connector) 583 { 584 enum intel_hotplug_state state; 585 586 state = intel_encoder_hotplug(encoder, connector); 587 588 /* 589 * On many platforms the HDMI live state signal is known to be 590 * unreliable, so we can't use it to detect if a sink is connected or 591 * not. Instead we detect if it's connected based on whether we can 592 * read the EDID or not. That in turn has a problem during disconnect, 593 * since the HPD interrupt may be raised before the DDC lines get 594 * disconnected (due to how the required length of DDC vs. HPD 595 * connector pins are specified) and so we'll still be able to get a 596 * valid EDID. To solve this schedule another detection cycle if this 597 * time around we didn't detect any change in the sink's connection 598 * status. 599 */ 600 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 601 state = INTEL_HOTPLUG_RETRY; 602 603 return state; 604 } 605 606 int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, 607 struct drm_atomic_state *state) 608 { 609 struct drm_i915_private *i915 = to_i915(state->dev); 610 struct drm_connector_list_iter conn_iter; 611 struct drm_connector *conn; 612 int ret; 613 614 ret = intel_digital_connector_atomic_check(connector, state); 615 if (ret) 616 return ret; 617 618 if (!IS_G4X(i915)) 619 return 0; 620 621 if (!intel_connector_needs_modeset(to_intel_atomic_state(state), connector)) 622 return 0; 623 624 /* 625 * On g4x only one HDMI port can transmit infoframes/audio 626 * at any given time. Make sure all enabled HDMI ports are 627 * included in the state so that it's possible to select 628 * one of them for this duty. 629 * 630 * See also g4x_compute_has_hdmi_sink(). 631 */ 632 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 633 drm_for_each_connector_iter(conn, &conn_iter) { 634 struct drm_connector_state *conn_state; 635 struct drm_crtc_state *crtc_state; 636 struct drm_crtc *crtc; 637 638 if (!connector_is_hdmi(conn)) 639 continue; 640 641 drm_dbg_kms(&i915->drm, "Adding [CONNECTOR:%d:%s]\n", 642 conn->base.id, conn->name); 643 644 conn_state = drm_atomic_get_connector_state(state, conn); 645 if (IS_ERR(conn_state)) { 646 ret = PTR_ERR(conn_state); 647 break; 648 } 649 650 crtc = conn_state->crtc; 651 if (!crtc) 652 continue; 653 654 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 655 crtc_state->mode_changed = true; 656 657 ret = drm_atomic_add_affected_planes(state, crtc); 658 if (ret) 659 break; 660 } 661 drm_connector_list_iter_end(&conn_iter); 662 663 return ret; 664 } 665 666 static bool is_hdmi_port_valid(struct drm_i915_private *i915, enum port port) 667 { 668 if (IS_G4X(i915) || IS_VALLEYVIEW(i915)) 669 return port == PORT_B || port == PORT_C; 670 else 671 return port == PORT_B || port == PORT_C || port == PORT_D; 672 } 673 674 static bool assert_hdmi_port_valid(struct drm_i915_private *i915, enum port port) 675 { 676 return !drm_WARN(&i915->drm, !is_hdmi_port_valid(i915, port), 677 "Platform does not support HDMI %c\n", port_name(port)); 678 } 679 680 void g4x_hdmi_init(struct drm_i915_private *dev_priv, 681 i915_reg_t hdmi_reg, enum port port) 682 { 683 const struct intel_bios_encoder_data *devdata; 684 struct intel_digital_port *dig_port; 685 struct intel_encoder *intel_encoder; 686 struct intel_connector *intel_connector; 687 688 if (!assert_port_valid(dev_priv, port)) 689 return; 690 691 if (!assert_hdmi_port_valid(dev_priv, port)) 692 return; 693 694 devdata = intel_bios_encoder_data_lookup(dev_priv, port); 695 696 /* FIXME bail? */ 697 if (!devdata) 698 drm_dbg_kms(&dev_priv->drm, "No VBT child device for HDMI-%c\n", 699 port_name(port)); 700 701 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 702 if (!dig_port) 703 return; 704 705 dig_port->aux_ch = AUX_CH_NONE; 706 707 intel_connector = intel_connector_alloc(); 708 if (!intel_connector) { 709 kfree(dig_port); 710 return; 711 } 712 713 intel_encoder = &dig_port->base; 714 715 intel_encoder->devdata = devdata; 716 717 mutex_init(&dig_port->hdcp_mutex); 718 719 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 720 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 721 "HDMI %c", port_name(port)); 722 723 intel_encoder->hotplug = intel_hdmi_hotplug; 724 intel_encoder->compute_config = g4x_hdmi_compute_config; 725 if (HAS_PCH_SPLIT(dev_priv)) { 726 intel_encoder->disable = pch_disable_hdmi; 727 intel_encoder->post_disable = pch_post_disable_hdmi; 728 } else { 729 intel_encoder->disable = g4x_disable_hdmi; 730 } 731 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 732 intel_encoder->get_config = intel_hdmi_get_config; 733 if (IS_CHERRYVIEW(dev_priv)) { 734 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 735 intel_encoder->pre_enable = chv_hdmi_pre_enable; 736 intel_encoder->enable = vlv_enable_hdmi; 737 intel_encoder->post_disable = chv_hdmi_post_disable; 738 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 739 } else if (IS_VALLEYVIEW(dev_priv)) { 740 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 741 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 742 intel_encoder->enable = vlv_enable_hdmi; 743 intel_encoder->post_disable = vlv_hdmi_post_disable; 744 } else { 745 intel_encoder->pre_enable = intel_hdmi_pre_enable; 746 if (HAS_PCH_CPT(dev_priv)) 747 intel_encoder->enable = cpt_enable_hdmi; 748 else if (HAS_PCH_IBX(dev_priv)) 749 intel_encoder->enable = ibx_enable_hdmi; 750 else 751 intel_encoder->enable = g4x_enable_hdmi; 752 } 753 intel_encoder->shutdown = intel_hdmi_encoder_shutdown; 754 755 intel_encoder->type = INTEL_OUTPUT_HDMI; 756 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 757 intel_encoder->port = port; 758 if (IS_CHERRYVIEW(dev_priv)) { 759 if (port == PORT_D) 760 intel_encoder->pipe_mask = BIT(PIPE_C); 761 else 762 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 763 } else { 764 intel_encoder->pipe_mask = ~0; 765 } 766 intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG); 767 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 768 /* 769 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 770 * to work on real hardware. And since g4x can send infoframes to 771 * only one port anyway, nothing is lost by allowing it. 772 */ 773 if (IS_G4X(dev_priv)) 774 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); 775 776 dig_port->hdmi.hdmi_reg = hdmi_reg; 777 dig_port->dp.output_reg = INVALID_MMIO_REG; 778 dig_port->max_lanes = 4; 779 780 intel_infoframe_init(dig_port); 781 782 intel_hdmi_init_connector(dig_port, intel_connector); 783 } 784