1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include "g4x_hdmi.h" 9 #include "i915_reg.h" 10 #include "intel_audio.h" 11 #include "intel_connector.h" 12 #include "intel_crtc.h" 13 #include "intel_de.h" 14 #include "intel_display_power.h" 15 #include "intel_display_types.h" 16 #include "intel_dpio_phy.h" 17 #include "intel_fifo_underrun.h" 18 #include "intel_hdmi.h" 19 #include "intel_hotplug.h" 20 #include "intel_sdvo.h" 21 #include "vlv_sideband.h" 22 23 static void intel_hdmi_prepare(struct intel_encoder *encoder, 24 const struct intel_crtc_state *crtc_state) 25 { 26 struct drm_device *dev = encoder->base.dev; 27 struct drm_i915_private *dev_priv = to_i915(dev); 28 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 29 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 30 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 31 u32 hdmi_val; 32 33 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 34 35 hdmi_val = SDVO_ENCODING_HDMI; 36 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 37 hdmi_val |= HDMI_COLOR_RANGE_16_235; 38 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 39 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 40 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 41 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 42 43 if (crtc_state->pipe_bpp > 24) 44 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 45 else 46 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 47 48 if (crtc_state->has_hdmi_sink) 49 hdmi_val |= HDMI_MODE_SELECT_HDMI; 50 51 if (HAS_PCH_CPT(dev_priv)) 52 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 53 else if (IS_CHERRYVIEW(dev_priv)) 54 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 55 else 56 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 57 58 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 59 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 60 } 61 62 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 63 enum pipe *pipe) 64 { 65 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 66 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 67 intel_wakeref_t wakeref; 68 bool ret; 69 70 wakeref = intel_display_power_get_if_enabled(dev_priv, 71 encoder->power_domain); 72 if (!wakeref) 73 return false; 74 75 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 76 77 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 78 79 return ret; 80 } 81 82 static int g4x_hdmi_compute_config(struct intel_encoder *encoder, 83 struct intel_crtc_state *crtc_state, 84 struct drm_connector_state *conn_state) 85 { 86 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 87 88 if (HAS_PCH_SPLIT(i915)) 89 crtc_state->has_pch_encoder = true; 90 91 return intel_hdmi_compute_config(encoder, crtc_state, conn_state); 92 } 93 94 static void intel_hdmi_get_config(struct intel_encoder *encoder, 95 struct intel_crtc_state *pipe_config) 96 { 97 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 98 struct drm_device *dev = encoder->base.dev; 99 struct drm_i915_private *dev_priv = to_i915(dev); 100 u32 tmp, flags = 0; 101 int dotclock; 102 103 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 104 105 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 106 107 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 108 flags |= DRM_MODE_FLAG_PHSYNC; 109 else 110 flags |= DRM_MODE_FLAG_NHSYNC; 111 112 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 113 flags |= DRM_MODE_FLAG_PVSYNC; 114 else 115 flags |= DRM_MODE_FLAG_NVSYNC; 116 117 if (tmp & HDMI_MODE_SELECT_HDMI) 118 pipe_config->has_hdmi_sink = true; 119 120 pipe_config->infoframes.enable |= 121 intel_hdmi_infoframes_enabled(encoder, pipe_config); 122 123 if (pipe_config->infoframes.enable) 124 pipe_config->has_infoframe = true; 125 126 if (tmp & HDMI_AUDIO_ENABLE) 127 pipe_config->has_audio = true; 128 129 if (!HAS_PCH_SPLIT(dev_priv) && 130 tmp & HDMI_COLOR_RANGE_16_235) 131 pipe_config->limited_color_range = true; 132 133 pipe_config->hw.adjusted_mode.flags |= flags; 134 135 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 136 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); 137 else 138 dotclock = pipe_config->port_clock; 139 140 if (pipe_config->pixel_multiplier) 141 dotclock /= pipe_config->pixel_multiplier; 142 143 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 144 145 pipe_config->lane_count = 4; 146 147 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 148 149 intel_read_infoframe(encoder, pipe_config, 150 HDMI_INFOFRAME_TYPE_AVI, 151 &pipe_config->infoframes.avi); 152 intel_read_infoframe(encoder, pipe_config, 153 HDMI_INFOFRAME_TYPE_SPD, 154 &pipe_config->infoframes.spd); 155 intel_read_infoframe(encoder, pipe_config, 156 HDMI_INFOFRAME_TYPE_VENDOR, 157 &pipe_config->infoframes.hdmi); 158 } 159 160 static void g4x_hdmi_enable_port(struct intel_encoder *encoder, 161 const struct intel_crtc_state *pipe_config) 162 { 163 struct drm_device *dev = encoder->base.dev; 164 struct drm_i915_private *dev_priv = to_i915(dev); 165 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 166 u32 temp; 167 168 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 169 170 temp |= SDVO_ENABLE; 171 if (pipe_config->has_audio) 172 temp |= HDMI_AUDIO_ENABLE; 173 174 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 175 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 176 } 177 178 static void g4x_enable_hdmi(struct intel_atomic_state *state, 179 struct intel_encoder *encoder, 180 const struct intel_crtc_state *pipe_config, 181 const struct drm_connector_state *conn_state) 182 { 183 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 184 185 g4x_hdmi_enable_port(encoder, pipe_config); 186 187 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 188 !pipe_config->has_hdmi_sink); 189 intel_audio_codec_enable(encoder, pipe_config, conn_state); 190 } 191 192 static void ibx_enable_hdmi(struct intel_atomic_state *state, 193 struct intel_encoder *encoder, 194 const struct intel_crtc_state *pipe_config, 195 const struct drm_connector_state *conn_state) 196 { 197 struct drm_device *dev = encoder->base.dev; 198 struct drm_i915_private *dev_priv = to_i915(dev); 199 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 200 u32 temp; 201 202 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 203 204 temp |= SDVO_ENABLE; 205 if (pipe_config->has_audio) 206 temp |= HDMI_AUDIO_ENABLE; 207 208 /* 209 * HW workaround, need to write this twice for issue 210 * that may result in first write getting masked. 211 */ 212 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 213 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 214 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 215 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 216 217 /* 218 * HW workaround, need to toggle enable bit off and on 219 * for 12bpc with pixel repeat. 220 * 221 * FIXME: BSpec says this should be done at the end of 222 * the modeset sequence, so not sure if this isn't too soon. 223 */ 224 if (pipe_config->pipe_bpp > 24 && 225 pipe_config->pixel_multiplier > 1) { 226 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 227 temp & ~SDVO_ENABLE); 228 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 229 230 /* 231 * HW workaround, need to write this twice for issue 232 * that may result in first write getting masked. 233 */ 234 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 235 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 236 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 237 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 238 } 239 240 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 241 !pipe_config->has_hdmi_sink); 242 intel_audio_codec_enable(encoder, pipe_config, conn_state); 243 } 244 245 static void cpt_enable_hdmi(struct intel_atomic_state *state, 246 struct intel_encoder *encoder, 247 const struct intel_crtc_state *pipe_config, 248 const struct drm_connector_state *conn_state) 249 { 250 struct drm_device *dev = encoder->base.dev; 251 struct drm_i915_private *dev_priv = to_i915(dev); 252 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 253 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 254 enum pipe pipe = crtc->pipe; 255 u32 temp; 256 257 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 258 259 temp |= SDVO_ENABLE; 260 if (pipe_config->has_audio) 261 temp |= HDMI_AUDIO_ENABLE; 262 263 /* 264 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 265 * 266 * The procedure for 12bpc is as follows: 267 * 1. disable HDMI clock gating 268 * 2. enable HDMI with 8bpc 269 * 3. enable HDMI with 12bpc 270 * 4. enable HDMI clock gating 271 */ 272 273 if (pipe_config->pipe_bpp > 24) { 274 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 275 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 276 277 temp &= ~SDVO_COLOR_FORMAT_MASK; 278 temp |= SDVO_COLOR_FORMAT_8bpc; 279 } 280 281 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 282 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 283 284 if (pipe_config->pipe_bpp > 24) { 285 temp &= ~SDVO_COLOR_FORMAT_MASK; 286 temp |= HDMI_COLOR_FORMAT_12bpc; 287 288 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 289 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 290 291 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 292 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 293 } 294 295 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 296 !pipe_config->has_hdmi_sink); 297 intel_audio_codec_enable(encoder, pipe_config, conn_state); 298 } 299 300 static void vlv_enable_hdmi(struct intel_atomic_state *state, 301 struct intel_encoder *encoder, 302 const struct intel_crtc_state *pipe_config, 303 const struct drm_connector_state *conn_state) 304 { 305 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 306 307 drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio && 308 !pipe_config->has_hdmi_sink); 309 intel_audio_codec_enable(encoder, pipe_config, conn_state); 310 } 311 312 static void intel_disable_hdmi(struct intel_atomic_state *state, 313 struct intel_encoder *encoder, 314 const struct intel_crtc_state *old_crtc_state, 315 const struct drm_connector_state *old_conn_state) 316 { 317 struct drm_device *dev = encoder->base.dev; 318 struct drm_i915_private *dev_priv = to_i915(dev); 319 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 320 struct intel_digital_port *dig_port = 321 hdmi_to_dig_port(intel_hdmi); 322 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 323 u32 temp; 324 325 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 326 327 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 328 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 329 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 330 331 /* 332 * HW workaround for IBX, we need to move the port 333 * to transcoder A after disabling it to allow the 334 * matching DP port to be enabled on transcoder A. 335 */ 336 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 337 /* 338 * We get CPU/PCH FIFO underruns on the other pipe when 339 * doing the workaround. Sweep them under the rug. 340 */ 341 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 342 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 343 344 temp &= ~SDVO_PIPE_SEL_MASK; 345 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 346 /* 347 * HW workaround, need to write this twice for issue 348 * that may result in first write getting masked. 349 */ 350 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 351 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 352 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 353 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 354 355 temp &= ~SDVO_ENABLE; 356 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 357 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 358 359 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 360 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 361 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 362 } 363 364 dig_port->set_infoframes(encoder, 365 false, 366 old_crtc_state, old_conn_state); 367 368 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 369 } 370 371 static void g4x_disable_hdmi(struct intel_atomic_state *state, 372 struct intel_encoder *encoder, 373 const struct intel_crtc_state *old_crtc_state, 374 const struct drm_connector_state *old_conn_state) 375 { 376 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 377 378 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 379 } 380 381 static void pch_disable_hdmi(struct intel_atomic_state *state, 382 struct intel_encoder *encoder, 383 const struct intel_crtc_state *old_crtc_state, 384 const struct drm_connector_state *old_conn_state) 385 { 386 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 387 } 388 389 static void pch_post_disable_hdmi(struct intel_atomic_state *state, 390 struct intel_encoder *encoder, 391 const struct intel_crtc_state *old_crtc_state, 392 const struct drm_connector_state *old_conn_state) 393 { 394 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 395 } 396 397 static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 398 struct intel_encoder *encoder, 399 const struct intel_crtc_state *pipe_config, 400 const struct drm_connector_state *conn_state) 401 { 402 struct intel_digital_port *dig_port = 403 enc_to_dig_port(encoder); 404 405 intel_hdmi_prepare(encoder, pipe_config); 406 407 dig_port->set_infoframes(encoder, 408 pipe_config->has_infoframe, 409 pipe_config, conn_state); 410 } 411 412 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 413 struct intel_encoder *encoder, 414 const struct intel_crtc_state *pipe_config, 415 const struct drm_connector_state *conn_state) 416 { 417 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 419 420 vlv_phy_pre_encoder_enable(encoder, pipe_config); 421 422 /* HDMI 1.0V-2dB */ 423 vlv_set_phy_signal_level(encoder, pipe_config, 424 0x2b245f5f, 0x00002000, 425 0x5578b83a, 0x2b247878); 426 427 dig_port->set_infoframes(encoder, 428 pipe_config->has_infoframe, 429 pipe_config, conn_state); 430 431 g4x_hdmi_enable_port(encoder, pipe_config); 432 433 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 434 } 435 436 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 437 struct intel_encoder *encoder, 438 const struct intel_crtc_state *pipe_config, 439 const struct drm_connector_state *conn_state) 440 { 441 intel_hdmi_prepare(encoder, pipe_config); 442 443 vlv_phy_pre_pll_enable(encoder, pipe_config); 444 } 445 446 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 447 struct intel_encoder *encoder, 448 const struct intel_crtc_state *pipe_config, 449 const struct drm_connector_state *conn_state) 450 { 451 intel_hdmi_prepare(encoder, pipe_config); 452 453 chv_phy_pre_pll_enable(encoder, pipe_config); 454 } 455 456 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 457 struct intel_encoder *encoder, 458 const struct intel_crtc_state *old_crtc_state, 459 const struct drm_connector_state *old_conn_state) 460 { 461 chv_phy_post_pll_disable(encoder, old_crtc_state); 462 } 463 464 static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 465 struct intel_encoder *encoder, 466 const struct intel_crtc_state *old_crtc_state, 467 const struct drm_connector_state *old_conn_state) 468 { 469 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 470 vlv_phy_reset_lanes(encoder, old_crtc_state); 471 } 472 473 static void chv_hdmi_post_disable(struct intel_atomic_state *state, 474 struct intel_encoder *encoder, 475 const struct intel_crtc_state *old_crtc_state, 476 const struct drm_connector_state *old_conn_state) 477 { 478 struct drm_device *dev = encoder->base.dev; 479 struct drm_i915_private *dev_priv = to_i915(dev); 480 481 vlv_dpio_get(dev_priv); 482 483 /* Assert data lane reset */ 484 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 485 486 vlv_dpio_put(dev_priv); 487 } 488 489 static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 490 struct intel_encoder *encoder, 491 const struct intel_crtc_state *pipe_config, 492 const struct drm_connector_state *conn_state) 493 { 494 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 495 struct drm_device *dev = encoder->base.dev; 496 struct drm_i915_private *dev_priv = to_i915(dev); 497 498 chv_phy_pre_encoder_enable(encoder, pipe_config); 499 500 /* FIXME: Program the support xxx V-dB */ 501 /* Use 800mV-0dB */ 502 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); 503 504 dig_port->set_infoframes(encoder, 505 pipe_config->has_infoframe, 506 pipe_config, conn_state); 507 508 g4x_hdmi_enable_port(encoder, pipe_config); 509 510 vlv_wait_port_ready(dev_priv, dig_port, 0x0); 511 512 /* Second common lane will stay alive on its own now */ 513 chv_phy_release_cl2_override(encoder); 514 } 515 516 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 517 .destroy = intel_encoder_destroy, 518 }; 519 520 static enum intel_hotplug_state 521 intel_hdmi_hotplug(struct intel_encoder *encoder, 522 struct intel_connector *connector) 523 { 524 enum intel_hotplug_state state; 525 526 state = intel_encoder_hotplug(encoder, connector); 527 528 /* 529 * On many platforms the HDMI live state signal is known to be 530 * unreliable, so we can't use it to detect if a sink is connected or 531 * not. Instead we detect if it's connected based on whether we can 532 * read the EDID or not. That in turn has a problem during disconnect, 533 * since the HPD interrupt may be raised before the DDC lines get 534 * disconnected (due to how the required length of DDC vs. HPD 535 * connector pins are specified) and so we'll still be able to get a 536 * valid EDID. To solve this schedule another detection cycle if this 537 * time around we didn't detect any change in the sink's connection 538 * status. 539 */ 540 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 541 state = INTEL_HOTPLUG_RETRY; 542 543 return state; 544 } 545 546 void g4x_hdmi_init(struct drm_i915_private *dev_priv, 547 i915_reg_t hdmi_reg, enum port port) 548 { 549 struct intel_digital_port *dig_port; 550 struct intel_encoder *intel_encoder; 551 struct intel_connector *intel_connector; 552 553 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 554 if (!dig_port) 555 return; 556 557 intel_connector = intel_connector_alloc(); 558 if (!intel_connector) { 559 kfree(dig_port); 560 return; 561 } 562 563 intel_encoder = &dig_port->base; 564 565 mutex_init(&dig_port->hdcp_mutex); 566 567 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 568 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 569 "HDMI %c", port_name(port)); 570 571 intel_encoder->hotplug = intel_hdmi_hotplug; 572 intel_encoder->compute_config = g4x_hdmi_compute_config; 573 if (HAS_PCH_SPLIT(dev_priv)) { 574 intel_encoder->disable = pch_disable_hdmi; 575 intel_encoder->post_disable = pch_post_disable_hdmi; 576 } else { 577 intel_encoder->disable = g4x_disable_hdmi; 578 } 579 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 580 intel_encoder->get_config = intel_hdmi_get_config; 581 if (IS_CHERRYVIEW(dev_priv)) { 582 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 583 intel_encoder->pre_enable = chv_hdmi_pre_enable; 584 intel_encoder->enable = vlv_enable_hdmi; 585 intel_encoder->post_disable = chv_hdmi_post_disable; 586 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 587 } else if (IS_VALLEYVIEW(dev_priv)) { 588 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 589 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 590 intel_encoder->enable = vlv_enable_hdmi; 591 intel_encoder->post_disable = vlv_hdmi_post_disable; 592 } else { 593 intel_encoder->pre_enable = intel_hdmi_pre_enable; 594 if (HAS_PCH_CPT(dev_priv)) 595 intel_encoder->enable = cpt_enable_hdmi; 596 else if (HAS_PCH_IBX(dev_priv)) 597 intel_encoder->enable = ibx_enable_hdmi; 598 else 599 intel_encoder->enable = g4x_enable_hdmi; 600 } 601 intel_encoder->shutdown = intel_hdmi_encoder_shutdown; 602 603 intel_encoder->type = INTEL_OUTPUT_HDMI; 604 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); 605 intel_encoder->port = port; 606 if (IS_CHERRYVIEW(dev_priv)) { 607 if (port == PORT_D) 608 intel_encoder->pipe_mask = BIT(PIPE_C); 609 else 610 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 611 } else { 612 intel_encoder->pipe_mask = ~0; 613 } 614 intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG); 615 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 616 /* 617 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 618 * to work on real hardware. And since g4x can send infoframes to 619 * only one port anyway, nothing is lost by allowing it. 620 */ 621 if (IS_G4X(dev_priv)) 622 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); 623 624 dig_port->hdmi.hdmi_reg = hdmi_reg; 625 dig_port->dp.output_reg = INVALID_MMIO_REG; 626 dig_port->max_lanes = 4; 627 628 intel_infoframe_init(dig_port); 629 630 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 631 intel_hdmi_init_connector(dig_port, intel_connector); 632 } 633