1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 * 5 * HDMI support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code). 6 */ 7 8 #include <drm/drm_print.h> 9 10 #include "g4x_hdmi.h" 11 #include "i915_reg.h" 12 #include "intel_atomic.h" 13 #include "intel_audio.h" 14 #include "intel_connector.h" 15 #include "intel_crtc.h" 16 #include "intel_de.h" 17 #include "intel_display_power.h" 18 #include "intel_display_types.h" 19 #include "intel_dp_aux.h" 20 #include "intel_dpio_phy.h" 21 #include "intel_fdi.h" 22 #include "intel_fifo_underrun.h" 23 #include "intel_hdmi.h" 24 #include "intel_hotplug.h" 25 #include "intel_sdvo.h" 26 27 static void intel_hdmi_prepare(struct intel_encoder *encoder, 28 const struct intel_crtc_state *crtc_state) 29 { 30 struct intel_display *display = to_intel_display(encoder); 31 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 32 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 33 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 34 u32 hdmi_val; 35 36 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 37 38 hdmi_val = SDVO_ENCODING_HDMI; 39 if (!HAS_PCH_SPLIT(display) && crtc_state->limited_color_range) 40 hdmi_val |= HDMI_COLOR_RANGE_16_235; 41 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 42 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 43 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 44 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 45 46 if (crtc_state->pipe_bpp > 24) 47 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 48 else 49 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 50 51 if (crtc_state->has_hdmi_sink) 52 hdmi_val |= HDMI_MODE_SELECT_HDMI; 53 54 if (HAS_PCH_CPT(display)) 55 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 56 else if (display->platform.cherryview) 57 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 58 else 59 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 60 61 intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val); 62 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 63 } 64 65 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 66 enum pipe *pipe) 67 { 68 struct intel_display *display = to_intel_display(encoder); 69 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 70 intel_wakeref_t wakeref; 71 bool ret; 72 73 wakeref = intel_display_power_get_if_enabled(display, 74 encoder->power_domain); 75 if (!wakeref) 76 return false; 77 78 ret = intel_sdvo_port_enabled(display, intel_hdmi->hdmi_reg, pipe); 79 80 intel_display_power_put(display, encoder->power_domain, wakeref); 81 82 return ret; 83 } 84 85 static bool connector_is_hdmi(struct drm_connector *connector) 86 { 87 struct intel_encoder *encoder = 88 intel_attached_encoder(to_intel_connector(connector)); 89 90 return encoder && encoder->type == INTEL_OUTPUT_HDMI; 91 } 92 93 static bool g4x_compute_has_hdmi_sink(struct intel_atomic_state *state, 94 struct intel_crtc *this_crtc) 95 { 96 const struct drm_connector_state *conn_state; 97 struct drm_connector *connector; 98 int i; 99 100 /* 101 * On g4x only one HDMI port can transmit infoframes/audio at 102 * any given time. Select the first suitable port for this duty. 103 * 104 * See also g4x_hdmi_connector_atomic_check(). 105 */ 106 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { 107 struct intel_encoder *encoder = to_intel_encoder(conn_state->best_encoder); 108 const struct intel_crtc_state *crtc_state; 109 struct intel_crtc *crtc; 110 111 if (!connector_is_hdmi(connector)) 112 continue; 113 114 crtc = to_intel_crtc(conn_state->crtc); 115 if (!crtc) 116 continue; 117 118 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 119 120 if (!intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state)) 121 continue; 122 123 return crtc == this_crtc; 124 } 125 126 return false; 127 } 128 129 static int g4x_hdmi_compute_config(struct intel_encoder *encoder, 130 struct intel_crtc_state *crtc_state, 131 struct drm_connector_state *conn_state) 132 { 133 struct intel_display *display = to_intel_display(encoder); 134 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 135 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 136 137 if (HAS_PCH_SPLIT(display)) { 138 crtc_state->has_pch_encoder = true; 139 if (!intel_fdi_compute_pipe_bpp(crtc_state)) 140 return -EINVAL; 141 } 142 143 if (display->platform.g4x) 144 crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc); 145 else 146 crtc_state->has_hdmi_sink = 147 intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state, conn_state); 148 149 return intel_hdmi_compute_config(encoder, crtc_state, conn_state); 150 } 151 152 static void intel_hdmi_get_config(struct intel_encoder *encoder, 153 struct intel_crtc_state *pipe_config) 154 { 155 struct intel_display *display = to_intel_display(encoder); 156 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 157 u32 tmp, flags = 0; 158 int dotclock; 159 160 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 161 162 tmp = intel_de_read(display, intel_hdmi->hdmi_reg); 163 164 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 165 flags |= DRM_MODE_FLAG_PHSYNC; 166 else 167 flags |= DRM_MODE_FLAG_NHSYNC; 168 169 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 170 flags |= DRM_MODE_FLAG_PVSYNC; 171 else 172 flags |= DRM_MODE_FLAG_NVSYNC; 173 174 if (tmp & HDMI_MODE_SELECT_HDMI) 175 pipe_config->has_hdmi_sink = true; 176 177 pipe_config->infoframes.enable |= 178 intel_hdmi_infoframes_enabled(encoder, pipe_config); 179 180 if (pipe_config->infoframes.enable) 181 pipe_config->has_infoframe = true; 182 183 if (tmp & HDMI_AUDIO_ENABLE) 184 pipe_config->has_audio = true; 185 186 if (!HAS_PCH_SPLIT(display) && 187 tmp & HDMI_COLOR_RANGE_16_235) 188 pipe_config->limited_color_range = true; 189 190 pipe_config->hw.adjusted_mode.flags |= flags; 191 192 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 193 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); 194 else 195 dotclock = pipe_config->port_clock; 196 197 if (pipe_config->pixel_multiplier) 198 dotclock /= pipe_config->pixel_multiplier; 199 200 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 201 202 pipe_config->lane_count = 4; 203 204 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 205 206 intel_read_infoframe(encoder, pipe_config, 207 HDMI_INFOFRAME_TYPE_AVI, 208 &pipe_config->infoframes.avi); 209 intel_read_infoframe(encoder, pipe_config, 210 HDMI_INFOFRAME_TYPE_SPD, 211 &pipe_config->infoframes.spd); 212 intel_read_infoframe(encoder, pipe_config, 213 HDMI_INFOFRAME_TYPE_VENDOR, 214 &pipe_config->infoframes.hdmi); 215 216 intel_audio_codec_get_config(encoder, pipe_config); 217 } 218 219 static void g4x_hdmi_enable_port(struct intel_encoder *encoder, 220 const struct intel_crtc_state *pipe_config) 221 { 222 struct intel_display *display = to_intel_display(encoder); 223 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 224 u32 temp; 225 226 temp = intel_de_read(display, intel_hdmi->hdmi_reg); 227 228 temp |= SDVO_ENABLE; 229 230 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 231 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 232 } 233 234 static void g4x_hdmi_audio_enable(struct intel_encoder *encoder, 235 const struct intel_crtc_state *crtc_state, 236 const struct drm_connector_state *conn_state) 237 { 238 struct intel_display *display = to_intel_display(encoder); 239 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 240 241 if (!crtc_state->has_audio) 242 return; 243 244 drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink); 245 246 /* Enable audio presence detect */ 247 intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE); 248 249 intel_audio_codec_enable(encoder, crtc_state, conn_state); 250 } 251 252 static void g4x_hdmi_audio_disable(struct intel_encoder *encoder, 253 const struct intel_crtc_state *old_crtc_state, 254 const struct drm_connector_state *old_conn_state) 255 { 256 struct intel_display *display = to_intel_display(encoder); 257 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 258 259 if (!old_crtc_state->has_audio) 260 return; 261 262 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 263 264 /* Disable audio presence detect */ 265 intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0); 266 } 267 268 static void g4x_enable_hdmi(struct intel_atomic_state *state, 269 struct intel_encoder *encoder, 270 const struct intel_crtc_state *pipe_config, 271 const struct drm_connector_state *conn_state) 272 { 273 g4x_hdmi_enable_port(encoder, pipe_config); 274 } 275 276 static void ibx_enable_hdmi(struct intel_atomic_state *state, 277 struct intel_encoder *encoder, 278 const struct intel_crtc_state *pipe_config, 279 const struct drm_connector_state *conn_state) 280 { 281 struct intel_display *display = to_intel_display(encoder); 282 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 283 u32 temp; 284 285 temp = intel_de_read(display, intel_hdmi->hdmi_reg); 286 287 temp |= SDVO_ENABLE; 288 289 /* 290 * HW workaround, need to write this twice for issue 291 * that may result in first write getting masked. 292 */ 293 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 294 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 295 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 296 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 297 298 /* 299 * HW workaround, need to toggle enable bit off and on 300 * for 12bpc with pixel repeat. 301 * 302 * FIXME: BSpec says this should be done at the end of 303 * the modeset sequence, so not sure if this isn't too soon. 304 */ 305 if (pipe_config->pipe_bpp > 24 && 306 pipe_config->pixel_multiplier > 1) { 307 intel_de_write(display, intel_hdmi->hdmi_reg, 308 temp & ~SDVO_ENABLE); 309 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 310 311 /* 312 * HW workaround, need to write this twice for issue 313 * that may result in first write getting masked. 314 */ 315 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 316 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 317 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 318 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 319 } 320 } 321 322 static void cpt_enable_hdmi(struct intel_atomic_state *state, 323 struct intel_encoder *encoder, 324 const struct intel_crtc_state *pipe_config, 325 const struct drm_connector_state *conn_state) 326 { 327 struct intel_display *display = to_intel_display(encoder); 328 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 329 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 330 enum pipe pipe = crtc->pipe; 331 u32 temp; 332 333 temp = intel_de_read(display, intel_hdmi->hdmi_reg); 334 335 temp |= SDVO_ENABLE; 336 337 /* 338 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 339 * 340 * The procedure for 12bpc is as follows: 341 * 1. disable HDMI clock gating 342 * 2. enable HDMI with 8bpc 343 * 3. enable HDMI with 12bpc 344 * 4. enable HDMI clock gating 345 */ 346 347 if (pipe_config->pipe_bpp > 24) { 348 intel_de_rmw(display, TRANS_CHICKEN1(pipe), 349 0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 350 351 temp &= ~SDVO_COLOR_FORMAT_MASK; 352 temp |= SDVO_COLOR_FORMAT_8bpc; 353 } 354 355 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 356 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 357 358 if (pipe_config->pipe_bpp > 24) { 359 temp &= ~SDVO_COLOR_FORMAT_MASK; 360 temp |= HDMI_COLOR_FORMAT_12bpc; 361 362 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 363 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 364 365 intel_de_rmw(display, TRANS_CHICKEN1(pipe), 366 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0); 367 } 368 } 369 370 static void vlv_enable_hdmi(struct intel_atomic_state *state, 371 struct intel_encoder *encoder, 372 const struct intel_crtc_state *pipe_config, 373 const struct drm_connector_state *conn_state) 374 { 375 } 376 377 static void intel_disable_hdmi(struct intel_atomic_state *state, 378 struct intel_encoder *encoder, 379 const struct intel_crtc_state *old_crtc_state, 380 const struct drm_connector_state *old_conn_state) 381 { 382 struct intel_display *display = to_intel_display(encoder); 383 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 384 struct intel_digital_port *dig_port = 385 hdmi_to_dig_port(intel_hdmi); 386 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 387 u32 temp; 388 389 temp = intel_de_read(display, intel_hdmi->hdmi_reg); 390 391 temp &= ~SDVO_ENABLE; 392 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 393 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 394 395 /* 396 * HW workaround for IBX, we need to move the port 397 * to transcoder A after disabling it to allow the 398 * matching DP port to be enabled on transcoder A. 399 */ 400 if (HAS_PCH_IBX(display) && crtc->pipe == PIPE_B) { 401 /* 402 * We get CPU/PCH FIFO underruns on the other pipe when 403 * doing the workaround. Sweep them under the rug. 404 */ 405 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); 406 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); 407 408 temp &= ~SDVO_PIPE_SEL_MASK; 409 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 410 /* 411 * HW workaround, need to write this twice for issue 412 * that may result in first write getting masked. 413 */ 414 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 415 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 416 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 417 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 418 419 temp &= ~SDVO_ENABLE; 420 intel_de_write(display, intel_hdmi->hdmi_reg, temp); 421 intel_de_posting_read(display, intel_hdmi->hdmi_reg); 422 423 intel_wait_for_vblank_if_active(display, PIPE_A); 424 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); 425 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); 426 } 427 428 dig_port->set_infoframes(encoder, 429 false, 430 old_crtc_state, old_conn_state); 431 432 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 433 } 434 435 static void g4x_disable_hdmi(struct intel_atomic_state *state, 436 struct intel_encoder *encoder, 437 const struct intel_crtc_state *old_crtc_state, 438 const struct drm_connector_state *old_conn_state) 439 { 440 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 441 } 442 443 static void pch_disable_hdmi(struct intel_atomic_state *state, 444 struct intel_encoder *encoder, 445 const struct intel_crtc_state *old_crtc_state, 446 const struct drm_connector_state *old_conn_state) 447 { 448 } 449 450 static void pch_post_disable_hdmi(struct intel_atomic_state *state, 451 struct intel_encoder *encoder, 452 const struct intel_crtc_state *old_crtc_state, 453 const struct drm_connector_state *old_conn_state) 454 { 455 intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state); 456 } 457 458 static void intel_hdmi_pre_enable(struct intel_atomic_state *state, 459 struct intel_encoder *encoder, 460 const struct intel_crtc_state *pipe_config, 461 const struct drm_connector_state *conn_state) 462 { 463 struct intel_digital_port *dig_port = 464 enc_to_dig_port(encoder); 465 466 intel_hdmi_prepare(encoder, pipe_config); 467 468 dig_port->set_infoframes(encoder, 469 pipe_config->has_infoframe, 470 pipe_config, conn_state); 471 } 472 473 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 474 struct intel_encoder *encoder, 475 const struct intel_crtc_state *pipe_config, 476 const struct drm_connector_state *conn_state) 477 { 478 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 479 480 vlv_phy_pre_encoder_enable(encoder, pipe_config); 481 482 /* HDMI 1.0V-2dB */ 483 vlv_set_phy_signal_level(encoder, pipe_config, 484 0x2b245f5f, 0x00002000, 485 0x5578b83a, 0x2b247878); 486 487 dig_port->set_infoframes(encoder, 488 pipe_config->has_infoframe, 489 pipe_config, conn_state); 490 491 g4x_hdmi_enable_port(encoder, pipe_config); 492 493 vlv_wait_port_ready(encoder, 0x0); 494 } 495 496 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 497 struct intel_encoder *encoder, 498 const struct intel_crtc_state *pipe_config, 499 const struct drm_connector_state *conn_state) 500 { 501 intel_hdmi_prepare(encoder, pipe_config); 502 503 vlv_phy_pre_pll_enable(encoder, pipe_config); 504 } 505 506 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state, 507 struct intel_encoder *encoder, 508 const struct intel_crtc_state *pipe_config, 509 const struct drm_connector_state *conn_state) 510 { 511 intel_hdmi_prepare(encoder, pipe_config); 512 513 chv_phy_pre_pll_enable(encoder, pipe_config); 514 } 515 516 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state, 517 struct intel_encoder *encoder, 518 const struct intel_crtc_state *old_crtc_state, 519 const struct drm_connector_state *old_conn_state) 520 { 521 chv_phy_post_pll_disable(encoder, old_crtc_state); 522 } 523 524 static void vlv_hdmi_post_disable(struct intel_atomic_state *state, 525 struct intel_encoder *encoder, 526 const struct intel_crtc_state *old_crtc_state, 527 const struct drm_connector_state *old_conn_state) 528 { 529 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 530 vlv_phy_reset_lanes(encoder, old_crtc_state); 531 } 532 533 static void chv_hdmi_post_disable(struct intel_atomic_state *state, 534 struct intel_encoder *encoder, 535 const struct intel_crtc_state *old_crtc_state, 536 const struct drm_connector_state *old_conn_state) 537 { 538 /* Assert data lane reset */ 539 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 540 } 541 542 static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 543 struct intel_encoder *encoder, 544 const struct intel_crtc_state *pipe_config, 545 const struct drm_connector_state *conn_state) 546 { 547 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 548 549 chv_phy_pre_encoder_enable(encoder, pipe_config); 550 551 /* FIXME: Program the support xxx V-dB */ 552 /* Use 800mV-0dB */ 553 chv_set_phy_signal_level(encoder, pipe_config, 128, 102, false); 554 555 dig_port->set_infoframes(encoder, 556 pipe_config->has_infoframe, 557 pipe_config, conn_state); 558 559 g4x_hdmi_enable_port(encoder, pipe_config); 560 561 vlv_wait_port_ready(encoder, 0x0); 562 563 /* Second common lane will stay alive on its own now */ 564 chv_phy_release_cl2_override(encoder); 565 } 566 567 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 568 .destroy = intel_encoder_destroy, 569 }; 570 571 static enum intel_hotplug_state 572 intel_hdmi_hotplug(struct intel_encoder *encoder, 573 struct intel_connector *connector) 574 { 575 enum intel_hotplug_state state; 576 577 state = intel_encoder_hotplug(encoder, connector); 578 579 /* 580 * On many platforms the HDMI live state signal is known to be 581 * unreliable, so we can't use it to detect if a sink is connected or 582 * not. Instead we detect if it's connected based on whether we can 583 * read the EDID or not. That in turn has a problem during disconnect, 584 * since the HPD interrupt may be raised before the DDC lines get 585 * disconnected (due to how the required length of DDC vs. HPD 586 * connector pins are specified) and so we'll still be able to get a 587 * valid EDID. To solve this schedule another detection cycle if this 588 * time around we didn't detect any change in the sink's connection 589 * status. 590 */ 591 if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries) 592 state = INTEL_HOTPLUG_RETRY; 593 594 return state; 595 } 596 597 int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, 598 struct drm_atomic_state *state) 599 { 600 struct intel_display *display = to_intel_display(connector->dev); 601 struct drm_connector_list_iter conn_iter; 602 struct drm_connector *conn; 603 int ret; 604 605 ret = intel_digital_connector_atomic_check(connector, state); 606 if (ret) 607 return ret; 608 609 if (!display->platform.g4x) 610 return 0; 611 612 if (!intel_connector_needs_modeset(to_intel_atomic_state(state), connector)) 613 return 0; 614 615 /* 616 * On g4x only one HDMI port can transmit infoframes/audio 617 * at any given time. Make sure all enabled HDMI ports are 618 * included in the state so that it's possible to select 619 * one of them for this duty. 620 * 621 * See also g4x_compute_has_hdmi_sink(). 622 */ 623 drm_connector_list_iter_begin(display->drm, &conn_iter); 624 drm_for_each_connector_iter(conn, &conn_iter) { 625 struct drm_connector_state *conn_state; 626 struct drm_crtc_state *crtc_state; 627 struct drm_crtc *crtc; 628 629 if (!connector_is_hdmi(conn)) 630 continue; 631 632 drm_dbg_kms(display->drm, "Adding [CONNECTOR:%d:%s]\n", 633 conn->base.id, conn->name); 634 635 conn_state = drm_atomic_get_connector_state(state, conn); 636 if (IS_ERR(conn_state)) { 637 ret = PTR_ERR(conn_state); 638 break; 639 } 640 641 crtc = conn_state->crtc; 642 if (!crtc) 643 continue; 644 645 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 646 crtc_state->mode_changed = true; 647 648 ret = drm_atomic_add_affected_planes(state, crtc); 649 if (ret) 650 break; 651 } 652 drm_connector_list_iter_end(&conn_iter); 653 654 return ret; 655 } 656 657 static bool is_hdmi_port_valid(struct intel_display *display, enum port port) 658 { 659 if (display->platform.g4x || display->platform.valleyview) 660 return port == PORT_B || port == PORT_C; 661 else 662 return port == PORT_B || port == PORT_C || port == PORT_D; 663 } 664 665 static bool assert_hdmi_port_valid(struct intel_display *display, enum port port) 666 { 667 return !drm_WARN(display->drm, !is_hdmi_port_valid(display, port), 668 "Platform does not support HDMI %c\n", port_name(port)); 669 } 670 671 bool g4x_hdmi_init(struct intel_display *display, 672 i915_reg_t hdmi_reg, enum port port) 673 { 674 const struct intel_bios_encoder_data *devdata; 675 struct intel_digital_port *dig_port; 676 struct intel_encoder *intel_encoder; 677 struct intel_connector *intel_connector; 678 679 if (!assert_port_valid(display, port)) 680 return false; 681 682 if (!assert_hdmi_port_valid(display, port)) 683 return false; 684 685 devdata = intel_bios_encoder_data_lookup(display, port); 686 687 /* FIXME bail? */ 688 if (!devdata) 689 drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n", 690 port_name(port)); 691 692 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); 693 if (!dig_port) 694 return false; 695 696 dig_port->aux_ch = AUX_CH_NONE; 697 698 intel_connector = intel_connector_alloc(); 699 if (!intel_connector) 700 goto err_connector_alloc; 701 702 intel_encoder = &dig_port->base; 703 704 intel_encoder->devdata = devdata; 705 706 mutex_init(&dig_port->hdcp.mutex); 707 708 if (drm_encoder_init(display->drm, &intel_encoder->base, 709 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 710 "HDMI %c", port_name(port))) 711 goto err_encoder_init; 712 713 intel_encoder->hotplug = intel_hdmi_hotplug; 714 intel_encoder->compute_config = g4x_hdmi_compute_config; 715 if (HAS_PCH_SPLIT(display)) { 716 intel_encoder->disable = pch_disable_hdmi; 717 intel_encoder->post_disable = pch_post_disable_hdmi; 718 } else { 719 intel_encoder->disable = g4x_disable_hdmi; 720 } 721 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 722 intel_encoder->get_config = intel_hdmi_get_config; 723 if (display->platform.cherryview) { 724 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 725 intel_encoder->pre_enable = chv_hdmi_pre_enable; 726 intel_encoder->enable = vlv_enable_hdmi; 727 intel_encoder->post_disable = chv_hdmi_post_disable; 728 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 729 } else if (display->platform.valleyview) { 730 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 731 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 732 intel_encoder->enable = vlv_enable_hdmi; 733 intel_encoder->post_disable = vlv_hdmi_post_disable; 734 } else { 735 intel_encoder->pre_enable = intel_hdmi_pre_enable; 736 if (HAS_PCH_CPT(display)) 737 intel_encoder->enable = cpt_enable_hdmi; 738 else if (HAS_PCH_IBX(display)) 739 intel_encoder->enable = ibx_enable_hdmi; 740 else 741 intel_encoder->enable = g4x_enable_hdmi; 742 } 743 intel_encoder->audio_enable = g4x_hdmi_audio_enable; 744 intel_encoder->audio_disable = g4x_hdmi_audio_disable; 745 intel_encoder->shutdown = intel_hdmi_encoder_shutdown; 746 747 intel_encoder->type = INTEL_OUTPUT_HDMI; 748 intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); 749 intel_encoder->port = port; 750 if (display->platform.cherryview) { 751 if (port == PORT_D) 752 intel_encoder->pipe_mask = BIT(PIPE_C); 753 else 754 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 755 } else { 756 intel_encoder->pipe_mask = ~0; 757 } 758 intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG); 759 intel_encoder->hpd_pin = intel_hpd_pin_default(port); 760 /* 761 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 762 * to work on real hardware. And since g4x can send infoframes to 763 * only one port anyway, nothing is lost by allowing it. 764 */ 765 if (display->platform.g4x) 766 intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); 767 768 dig_port->hdmi.hdmi_reg = hdmi_reg; 769 dig_port->dp.output_reg = INVALID_MMIO_REG; 770 dig_port->max_lanes = 4; 771 772 intel_infoframe_init(dig_port); 773 774 if (!intel_hdmi_init_connector(dig_port, intel_connector)) 775 goto err_init_connector; 776 777 return true; 778 779 err_init_connector: 780 drm_encoder_cleanup(&intel_encoder->base); 781 err_encoder_init: 782 kfree(intel_connector); 783 err_connector_alloc: 784 kfree(dig_port); 785 786 return false; 787 } 788